1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 // 9 // This pass performs peephole optimizations to clean up ugly code 10 // sequences at the MachineInstruction layer. It runs at the end of 11 // the SSA phases, following VSX swap removal. A pass of dead code 12 // elimination follows this one for quick clean-up of any dead 13 // instructions introduced here. Although we could do this as callbacks 14 // from the generic peephole pass, this would have a couple of bad 15 // effects: it might remove optimization opportunities for VSX swap 16 // removal, and it would miss cleanups made possible following VSX 17 // swap removal. 18 // 19 //===---------------------------------------------------------------------===// 20 21 #include "MCTargetDesc/PPCMCTargetDesc.h" 22 #include "MCTargetDesc/PPCPredicates.h" 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCMachineFunctionInfo.h" 27 #include "PPCTargetMachine.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 30 #include "llvm/CodeGen/MachineDominators.h" 31 #include "llvm/CodeGen/MachineFrameInfo.h" 32 #include "llvm/CodeGen/MachineFunctionPass.h" 33 #include "llvm/CodeGen/MachineInstrBuilder.h" 34 #include "llvm/CodeGen/MachinePostDominators.h" 35 #include "llvm/CodeGen/MachineRegisterInfo.h" 36 #include "llvm/InitializePasses.h" 37 #include "llvm/Support/Debug.h" 38 39 using namespace llvm; 40 41 #define DEBUG_TYPE "ppc-mi-peepholes" 42 43 STATISTIC(RemoveTOCSave, "Number of TOC saves removed"); 44 STATISTIC(MultiTOCSaves, 45 "Number of functions with multiple TOC saves that must be kept"); 46 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue"); 47 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions"); 48 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions"); 49 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI"); 50 STATISTIC(NumConvertedToImmediateForm, 51 "Number of instructions converted to their immediate form"); 52 STATISTIC(NumFunctionsEnteredInMIPeephole, 53 "Number of functions entered in PPC MI Peepholes"); 54 STATISTIC(NumFixedPointIterations, 55 "Number of fixed-point iterations converting reg-reg instructions " 56 "to reg-imm ones"); 57 STATISTIC(NumRotatesCollapsed, 58 "Number of pairs of rotate left, clear left/right collapsed"); 59 STATISTIC(NumEXTSWAndSLDICombined, 60 "Number of pairs of EXTSW and SLDI combined as EXTSWSLI"); 61 STATISTIC(NumLoadImmZeroFoldedAndRemoved, 62 "Number of LI(8) reg, 0 that are folded to r0 and removed"); 63 64 static cl::opt<bool> 65 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), 66 cl::desc("Iterate to a fixed point when attempting to " 67 "convert reg-reg instructions to reg-imm")); 68 69 static cl::opt<bool> 70 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), 71 cl::desc("Convert eligible reg+reg instructions to reg+imm")); 72 73 static cl::opt<bool> 74 EnableSExtElimination("ppc-eliminate-signext", 75 cl::desc("enable elimination of sign-extensions"), 76 cl::init(false), cl::Hidden); 77 78 static cl::opt<bool> 79 EnableZExtElimination("ppc-eliminate-zeroext", 80 cl::desc("enable elimination of zero-extensions"), 81 cl::init(false), cl::Hidden); 82 83 static cl::opt<bool> 84 EnableTrapOptimization("ppc-opt-conditional-trap", 85 cl::desc("enable optimization of conditional traps"), 86 cl::init(false), cl::Hidden); 87 88 namespace { 89 90 struct PPCMIPeephole : public MachineFunctionPass { 91 92 static char ID; 93 const PPCInstrInfo *TII; 94 MachineFunction *MF; 95 MachineRegisterInfo *MRI; 96 97 PPCMIPeephole() : MachineFunctionPass(ID) { 98 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry()); 99 } 100 101 private: 102 MachineDominatorTree *MDT; 103 MachinePostDominatorTree *MPDT; 104 MachineBlockFrequencyInfo *MBFI; 105 uint64_t EntryFreq; 106 107 // Initialize class variables. 108 void initialize(MachineFunction &MFParm); 109 110 // Perform peepholes. 111 bool simplifyCode(); 112 113 // Perform peepholes. 114 bool eliminateRedundantCompare(); 115 bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves); 116 bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase); 117 bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI); 118 void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves, 119 MachineInstr *MI); 120 121 public: 122 123 void getAnalysisUsage(AnalysisUsage &AU) const override { 124 AU.addRequired<MachineDominatorTree>(); 125 AU.addRequired<MachinePostDominatorTree>(); 126 AU.addRequired<MachineBlockFrequencyInfo>(); 127 AU.addPreserved<MachineDominatorTree>(); 128 AU.addPreserved<MachinePostDominatorTree>(); 129 AU.addPreserved<MachineBlockFrequencyInfo>(); 130 MachineFunctionPass::getAnalysisUsage(AU); 131 } 132 133 // Main entry point for this pass. 134 bool runOnMachineFunction(MachineFunction &MF) override { 135 initialize(MF); 136 // At this point, TOC pointer should not be used in a function that uses 137 // PC-Relative addressing. 138 assert((MF.getRegInfo().use_empty(PPC::X2) || 139 !MF.getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) && 140 "TOC pointer used in a function using PC-Relative addressing!"); 141 if (skipFunction(MF.getFunction())) 142 return false; 143 return simplifyCode(); 144 } 145 }; 146 147 // Initialize class variables. 148 void PPCMIPeephole::initialize(MachineFunction &MFParm) { 149 MF = &MFParm; 150 MRI = &MF->getRegInfo(); 151 MDT = &getAnalysis<MachineDominatorTree>(); 152 MPDT = &getAnalysis<MachinePostDominatorTree>(); 153 MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); 154 EntryFreq = MBFI->getEntryFreq(); 155 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 156 LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 157 LLVM_DEBUG(MF->dump()); 158 } 159 160 static MachineInstr *getVRegDefOrNull(MachineOperand *Op, 161 MachineRegisterInfo *MRI) { 162 assert(Op && "Invalid Operand!"); 163 if (!Op->isReg()) 164 return nullptr; 165 166 Register Reg = Op->getReg(); 167 if (!Register::isVirtualRegister(Reg)) 168 return nullptr; 169 170 return MRI->getVRegDef(Reg); 171 } 172 173 // This function returns number of known zero bits in output of MI 174 // starting from the most significant bit. 175 static unsigned 176 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) { 177 unsigned Opcode = MI->getOpcode(); 178 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || 179 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) 180 return MI->getOperand(3).getImm(); 181 182 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && 183 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) 184 return MI->getOperand(3).getImm(); 185 186 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || 187 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || 188 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && 189 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) 190 return 32 + MI->getOperand(3).getImm(); 191 192 if (Opcode == PPC::ANDI_rec) { 193 uint16_t Imm = MI->getOperand(2).getImm(); 194 return 48 + countLeadingZeros(Imm); 195 } 196 197 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || 198 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || 199 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) 200 // The result ranges from 0 to 32. 201 return 58; 202 203 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec || 204 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec) 205 // The result ranges from 0 to 64. 206 return 57; 207 208 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || 209 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || 210 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || 211 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) 212 return 48; 213 214 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || 215 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || 216 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || 217 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) 218 return 56; 219 220 if (TII->isZeroExtended(*MI)) 221 return 32; 222 223 return 0; 224 } 225 226 // This function maintains a map for the pairs <TOC Save Instr, Keep> 227 // Each time a new TOC save is encountered, it checks if any of the existing 228 // ones are dominated by the new one. If so, it marks the existing one as 229 // redundant by setting it's entry in the map as false. It then adds the new 230 // instruction to the map with either true or false depending on if any 231 // existing instructions dominated the new one. 232 void PPCMIPeephole::UpdateTOCSaves( 233 std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) { 234 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here"); 235 // FIXME: Saving TOC in prologue hasn't been implemented well in AIX ABI part, 236 // here only support it under ELFv2. 237 if (MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) { 238 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 239 240 MachineBasicBlock *Entry = &MF->front(); 241 uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency(); 242 243 // If the block in which the TOC save resides is in a block that 244 // post-dominates Entry, or a block that is hotter than entry (keep in mind 245 // that early MachineLICM has already run so the TOC save won't be hoisted) 246 // we can just do the save in the prologue. 247 if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry)) 248 FI->setMustSaveTOC(true); 249 250 // If we are saving the TOC in the prologue, all the TOC saves can be 251 // removed from the code. 252 if (FI->mustSaveTOC()) { 253 for (auto &TOCSave : TOCSaves) 254 TOCSave.second = false; 255 // Add new instruction to map. 256 TOCSaves[MI] = false; 257 return; 258 } 259 } 260 261 bool Keep = true; 262 for (auto &I : TOCSaves) { 263 MachineInstr *CurrInst = I.first; 264 // If new instruction dominates an existing one, mark existing one as 265 // redundant. 266 if (I.second && MDT->dominates(MI, CurrInst)) 267 I.second = false; 268 // Check if the new instruction is redundant. 269 if (MDT->dominates(CurrInst, MI)) { 270 Keep = false; 271 break; 272 } 273 } 274 // Add new instruction to map. 275 TOCSaves[MI] = Keep; 276 } 277 278 // This function returns a list of all PHI nodes in the tree starting from 279 // the RootPHI node. We perform a BFS traversal to get an ordered list of nodes. 280 // The list initially only contains the root PHI. When we visit a PHI node, we 281 // add it to the list. We continue to look for other PHI node operands while 282 // there are nodes to visit in the list. The function returns false if the 283 // optimization cannot be applied on this tree. 284 static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI, 285 MachineInstr *RootPHI, 286 SmallVectorImpl<MachineInstr *> &PHIs) { 287 PHIs.push_back(RootPHI); 288 unsigned VisitedIndex = 0; 289 while (VisitedIndex < PHIs.size()) { 290 MachineInstr *VisitedPHI = PHIs[VisitedIndex]; 291 for (unsigned PHIOp = 1, NumOps = VisitedPHI->getNumOperands(); 292 PHIOp != NumOps; PHIOp += 2) { 293 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); 294 if (!Register::isVirtualRegister(RegOp)) 295 return false; 296 MachineInstr *Instr = MRI->getVRegDef(RegOp); 297 // While collecting the PHI nodes, we check if they can be converted (i.e. 298 // all the operands are either copies, implicit defs or PHI nodes). 299 unsigned Opcode = Instr->getOpcode(); 300 if (Opcode == PPC::COPY) { 301 Register Reg = Instr->getOperand(1).getReg(); 302 if (!Register::isVirtualRegister(Reg) || 303 MRI->getRegClass(Reg) != &PPC::ACCRCRegClass) 304 return false; 305 } else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI) 306 return false; 307 // If we detect a cycle in the PHI nodes, we exit. It would be 308 // possible to change cycles as well, but that would add a lot 309 // of complexity for a case that is unlikely to occur with MMA 310 // code. 311 if (Opcode != PPC::PHI) 312 continue; 313 if (llvm::is_contained(PHIs, Instr)) 314 return false; 315 PHIs.push_back(Instr); 316 } 317 VisitedIndex++; 318 } 319 return true; 320 } 321 322 // This function changes the unprimed accumulator PHI nodes in the PHIs list to 323 // primed accumulator PHI nodes. The list is traversed in reverse order to 324 // change all the PHI operands of a PHI node before changing the node itself. 325 // We keep a map to associate each changed PHI node to its non-changed form. 326 static void convertUnprimedAccPHIs(const PPCInstrInfo *TII, 327 MachineRegisterInfo *MRI, 328 SmallVectorImpl<MachineInstr *> &PHIs, 329 Register Dst) { 330 DenseMap<MachineInstr *, MachineInstr *> ChangedPHIMap; 331 for (MachineInstr *PHI : llvm::reverse(PHIs)) { 332 SmallVector<std::pair<MachineOperand, MachineOperand>, 4> PHIOps; 333 // We check if the current PHI node can be changed by looking at its 334 // operands. If all the operands are either copies from primed 335 // accumulators, implicit definitions or other unprimed accumulator 336 // PHI nodes, we change it. 337 for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps; 338 PHIOp += 2) { 339 Register RegOp = PHI->getOperand(PHIOp).getReg(); 340 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); 341 unsigned Opcode = PHIInput->getOpcode(); 342 assert((Opcode == PPC::COPY || Opcode == PPC::IMPLICIT_DEF || 343 Opcode == PPC::PHI) && 344 "Unexpected instruction"); 345 if (Opcode == PPC::COPY) { 346 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == 347 &PPC::ACCRCRegClass && 348 "Unexpected register class"); 349 PHIOps.push_back({PHIInput->getOperand(1), PHI->getOperand(PHIOp + 1)}); 350 } else if (Opcode == PPC::IMPLICIT_DEF) { 351 Register AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass); 352 BuildMI(*PHIInput->getParent(), PHIInput, PHIInput->getDebugLoc(), 353 TII->get(PPC::IMPLICIT_DEF), AccReg); 354 PHIOps.push_back({MachineOperand::CreateReg(AccReg, false), 355 PHI->getOperand(PHIOp + 1)}); 356 } else if (Opcode == PPC::PHI) { 357 // We found a PHI operand. At this point we know this operand 358 // has already been changed so we get its associated changed form 359 // from the map. 360 assert(ChangedPHIMap.count(PHIInput) == 1 && 361 "This PHI node should have already been changed."); 362 MachineInstr *PrimedAccPHI = ChangedPHIMap.lookup(PHIInput); 363 PHIOps.push_back({MachineOperand::CreateReg( 364 PrimedAccPHI->getOperand(0).getReg(), false), 365 PHI->getOperand(PHIOp + 1)}); 366 } 367 } 368 Register AccReg = Dst; 369 // If the PHI node we are changing is the root node, the register it defines 370 // will be the destination register of the original copy (of the PHI def). 371 // For all other PHI's in the list, we need to create another primed 372 // accumulator virtual register as the PHI will no longer define the 373 // unprimed accumulator. 374 if (PHI != PHIs[0]) 375 AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass); 376 MachineInstrBuilder NewPHI = BuildMI( 377 *PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg); 378 for (auto RegMBB : PHIOps) 379 NewPHI.add(RegMBB.first).add(RegMBB.second); 380 ChangedPHIMap[PHI] = NewPHI.getInstr(); 381 } 382 } 383 384 // Perform peephole optimizations. 385 bool PPCMIPeephole::simplifyCode() { 386 bool Simplified = false; 387 bool TrapOpt = false; 388 MachineInstr* ToErase = nullptr; 389 std::map<MachineInstr *, bool> TOCSaves; 390 const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); 391 NumFunctionsEnteredInMIPeephole++; 392 if (ConvertRegReg) { 393 // Fixed-point conversion of reg/reg instructions fed by load-immediate 394 // into reg/imm instructions. FIXME: This is expensive, control it with 395 // an option. 396 bool SomethingChanged = false; 397 do { 398 NumFixedPointIterations++; 399 SomethingChanged = false; 400 for (MachineBasicBlock &MBB : *MF) { 401 for (MachineInstr &MI : MBB) { 402 if (MI.isDebugInstr()) 403 continue; 404 405 if (TII->convertToImmediateForm(MI)) { 406 // We don't erase anything in case the def has other uses. Let DCE 407 // remove it if it can be removed. 408 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 409 LLVM_DEBUG(MI.dump()); 410 NumConvertedToImmediateForm++; 411 SomethingChanged = true; 412 Simplified = true; 413 continue; 414 } 415 } 416 } 417 } while (SomethingChanged && FixedPointRegToImm); 418 } 419 420 for (MachineBasicBlock &MBB : *MF) { 421 for (MachineInstr &MI : MBB) { 422 423 // If the previous instruction was marked for elimination, 424 // remove it now. 425 if (ToErase) { 426 ToErase->eraseFromParent(); 427 ToErase = nullptr; 428 } 429 // If a conditional trap instruction got optimized to an 430 // unconditional trap, eliminate all the instructions after 431 // the trap. 432 if (EnableTrapOptimization && TrapOpt) { 433 ToErase = &MI; 434 continue; 435 } 436 437 // Ignore debug instructions. 438 if (MI.isDebugInstr()) 439 continue; 440 441 // Per-opcode peepholes. 442 switch (MI.getOpcode()) { 443 444 default: 445 break; 446 case PPC::COPY: { 447 Register Src = MI.getOperand(1).getReg(); 448 Register Dst = MI.getOperand(0).getReg(); 449 if (!Register::isVirtualRegister(Src) || 450 !Register::isVirtualRegister(Dst)) 451 break; 452 if (MRI->getRegClass(Src) != &PPC::UACCRCRegClass || 453 MRI->getRegClass(Dst) != &PPC::ACCRCRegClass) 454 break; 455 456 // We are copying an unprimed accumulator to a primed accumulator. 457 // If the input to the copy is a PHI that is fed only by (i) copies in 458 // the other direction (ii) implicitly defined unprimed accumulators or 459 // (iii) other PHI nodes satisfying (i) and (ii), we can change 460 // the PHI to a PHI on primed accumulators (as long as we also change 461 // its operands). To detect and change such copies, we first get a list 462 // of all the PHI nodes starting from the root PHI node in BFS order. 463 // We then visit all these PHI nodes to check if they can be changed to 464 // primed accumulator PHI nodes and if so, we change them. 465 MachineInstr *RootPHI = MRI->getVRegDef(Src); 466 if (RootPHI->getOpcode() != PPC::PHI) 467 break; 468 469 SmallVector<MachineInstr *, 4> PHIs; 470 if (!collectUnprimedAccPHIs(MRI, RootPHI, PHIs)) 471 break; 472 473 convertUnprimedAccPHIs(TII, MRI, PHIs, Dst); 474 475 ToErase = &MI; 476 break; 477 } 478 case PPC::LI: 479 case PPC::LI8: { 480 // If we are materializing a zero, look for any use operands for which 481 // zero means immediate zero. All such operands can be replaced with 482 // PPC::ZERO. 483 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0) 484 break; 485 Register MIDestReg = MI.getOperand(0).getReg(); 486 for (MachineInstr& UseMI : MRI->use_instructions(MIDestReg)) 487 Simplified |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg); 488 if (MRI->use_nodbg_empty(MIDestReg)) { 489 ++NumLoadImmZeroFoldedAndRemoved; 490 ToErase = &MI; 491 } 492 break; 493 } 494 case PPC::STW: 495 case PPC::STD: { 496 MachineFrameInfo &MFI = MF->getFrameInfo(); 497 if (MFI.hasVarSizedObjects() || 498 (!MF->getSubtarget<PPCSubtarget>().isELFv2ABI() && 499 !MF->getSubtarget<PPCSubtarget>().isAIXABI())) 500 break; 501 // When encountering a TOC save instruction, call UpdateTOCSaves 502 // to add it to the TOCSaves map and mark any existing TOC saves 503 // it dominates as redundant. 504 if (TII->isTOCSaveMI(MI)) 505 UpdateTOCSaves(TOCSaves, &MI); 506 break; 507 } 508 case PPC::XXPERMDI: { 509 // Perform simplifications of 2x64 vector swaps and splats. 510 // A swap is identified by an immediate value of 2, and a splat 511 // is identified by an immediate value of 0 or 3. 512 int Immed = MI.getOperand(3).getImm(); 513 514 if (Immed == 1) 515 break; 516 517 // For each of these simplifications, we need the two source 518 // regs to match. Unfortunately, MachineCSE ignores COPY and 519 // SUBREG_TO_REG, so for example we can see 520 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed. 521 // We have to look through chains of COPY and SUBREG_TO_REG 522 // to find the real source values for comparison. 523 Register TrueReg1 = 524 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 525 Register TrueReg2 = 526 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); 527 528 if (!(TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1))) 529 break; 530 531 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 532 533 if (!DefMI) 534 break; 535 536 unsigned DefOpc = DefMI->getOpcode(); 537 538 // If this is a splat fed by a splatting load, the splat is 539 // redundant. Replace with a copy. This doesn't happen directly due 540 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting 541 // a load of a double to a vector of 64-bit integers. 542 auto isConversionOfLoadAndSplat = [=]() -> bool { 543 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) 544 return false; 545 Register FeedReg1 = 546 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 547 if (Register::isVirtualRegister(FeedReg1)) { 548 MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1); 549 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) 550 return true; 551 } 552 return false; 553 }; 554 if ((Immed == 0 || Immed == 3) && 555 (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) { 556 LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat " 557 "to load-and-splat/copy: "); 558 LLVM_DEBUG(MI.dump()); 559 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 560 MI.getOperand(0).getReg()) 561 .add(MI.getOperand(1)); 562 ToErase = &MI; 563 Simplified = true; 564 } 565 566 // If this is a splat or a swap fed by another splat, we 567 // can replace it with a copy. 568 if (DefOpc == PPC::XXPERMDI) { 569 Register DefReg1 = DefMI->getOperand(1).getReg(); 570 Register DefReg2 = DefMI->getOperand(2).getReg(); 571 unsigned DefImmed = DefMI->getOperand(3).getImm(); 572 573 // If the two inputs are not the same register, check to see if 574 // they originate from the same virtual register after only 575 // copy-like instructions. 576 if (DefReg1 != DefReg2) { 577 Register FeedReg1 = TRI->lookThruCopyLike(DefReg1, MRI); 578 Register FeedReg2 = TRI->lookThruCopyLike(DefReg2, MRI); 579 580 if (!(FeedReg1 == FeedReg2 && 581 Register::isVirtualRegister(FeedReg1))) 582 break; 583 } 584 585 if (DefImmed == 0 || DefImmed == 3) { 586 LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat " 587 "to splat/copy: "); 588 LLVM_DEBUG(MI.dump()); 589 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 590 MI.getOperand(0).getReg()) 591 .add(MI.getOperand(1)); 592 ToErase = &MI; 593 Simplified = true; 594 } 595 596 // If this is a splat fed by a swap, we can simplify modify 597 // the splat to splat the other value from the swap's input 598 // parameter. 599 else if ((Immed == 0 || Immed == 3) && DefImmed == 2) { 600 LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: "); 601 LLVM_DEBUG(MI.dump()); 602 MI.getOperand(1).setReg(DefReg1); 603 MI.getOperand(2).setReg(DefReg2); 604 MI.getOperand(3).setImm(3 - Immed); 605 Simplified = true; 606 } 607 608 // If this is a swap fed by a swap, we can replace it 609 // with a copy from the first swap's input. 610 else if (Immed == 2 && DefImmed == 2) { 611 LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: "); 612 LLVM_DEBUG(MI.dump()); 613 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 614 MI.getOperand(0).getReg()) 615 .add(DefMI->getOperand(1)); 616 ToErase = &MI; 617 Simplified = true; 618 } 619 } else if ((Immed == 0 || Immed == 3 || Immed == 2) && 620 DefOpc == PPC::XXPERMDIs && 621 (DefMI->getOperand(2).getImm() == 0 || 622 DefMI->getOperand(2).getImm() == 3)) { 623 ToErase = &MI; 624 Simplified = true; 625 // Swap of a splat, convert to copy. 626 if (Immed == 2) { 627 LLVM_DEBUG(dbgs() << "Optimizing swap(splat) => copy(splat): "); 628 LLVM_DEBUG(MI.dump()); 629 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 630 MI.getOperand(0).getReg()) 631 .add(MI.getOperand(1)); 632 break; 633 } 634 // Splat fed by another splat - switch the output of the first 635 // and remove the second. 636 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 637 LLVM_DEBUG(dbgs() << "Removing redundant splat: "); 638 LLVM_DEBUG(MI.dump()); 639 } 640 break; 641 } 642 case PPC::VSPLTB: 643 case PPC::VSPLTH: 644 case PPC::XXSPLTW: { 645 unsigned MyOpcode = MI.getOpcode(); 646 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; 647 Register TrueReg = 648 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI); 649 if (!Register::isVirtualRegister(TrueReg)) 650 break; 651 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 652 if (!DefMI) 653 break; 654 unsigned DefOpcode = DefMI->getOpcode(); 655 auto isConvertOfSplat = [=]() -> bool { 656 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) 657 return false; 658 Register ConvReg = DefMI->getOperand(1).getReg(); 659 if (!Register::isVirtualRegister(ConvReg)) 660 return false; 661 MachineInstr *Splt = MRI->getVRegDef(ConvReg); 662 return Splt && (Splt->getOpcode() == PPC::LXVWSX || 663 Splt->getOpcode() == PPC::XXSPLTW); 664 }; 665 bool AlreadySplat = (MyOpcode == DefOpcode) || 666 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || 667 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || 668 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || 669 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || 670 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| 671 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); 672 // If the instruction[s] that feed this splat have already splat 673 // the value, this splat is redundant. 674 if (AlreadySplat) { 675 LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: "); 676 LLVM_DEBUG(MI.dump()); 677 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 678 MI.getOperand(0).getReg()) 679 .add(MI.getOperand(OpNo)); 680 ToErase = &MI; 681 Simplified = true; 682 } 683 // Splat fed by a shift. Usually when we align value to splat into 684 // vector element zero. 685 if (DefOpcode == PPC::XXSLDWI) { 686 Register ShiftRes = DefMI->getOperand(0).getReg(); 687 Register ShiftOp1 = DefMI->getOperand(1).getReg(); 688 Register ShiftOp2 = DefMI->getOperand(2).getReg(); 689 unsigned ShiftImm = DefMI->getOperand(3).getImm(); 690 unsigned SplatImm = 691 MI.getOperand(MyOpcode == PPC::XXSPLTW ? 2 : 1).getImm(); 692 if (ShiftOp1 == ShiftOp2) { 693 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; 694 if (MRI->hasOneNonDBGUse(ShiftRes)) { 695 LLVM_DEBUG(dbgs() << "Removing redundant shift: "); 696 LLVM_DEBUG(DefMI->dump()); 697 ToErase = DefMI; 698 } 699 Simplified = true; 700 LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm 701 << " to " << NewElem << " in instruction: "); 702 LLVM_DEBUG(MI.dump()); 703 MI.getOperand(1).setReg(ShiftOp1); 704 MI.getOperand(2).setImm(NewElem); 705 } 706 } 707 break; 708 } 709 case PPC::XVCVDPSP: { 710 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant. 711 Register TrueReg = 712 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 713 if (!Register::isVirtualRegister(TrueReg)) 714 break; 715 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 716 717 // This can occur when building a vector of single precision or integer 718 // values. 719 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 720 Register DefsReg1 = 721 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 722 Register DefsReg2 = 723 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 724 if (!Register::isVirtualRegister(DefsReg1) || 725 !Register::isVirtualRegister(DefsReg2)) 726 break; 727 MachineInstr *P1 = MRI->getVRegDef(DefsReg1); 728 MachineInstr *P2 = MRI->getVRegDef(DefsReg2); 729 730 if (!P1 || !P2) 731 break; 732 733 // Remove the passed FRSP/XSRSP instruction if it only feeds this MI 734 // and set any uses of that FRSP/XSRSP (in this MI) to the source of 735 // the FRSP/XSRSP. 736 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) { 737 unsigned Opc = RoundInstr->getOpcode(); 738 if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) && 739 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) { 740 Simplified = true; 741 Register ConvReg1 = RoundInstr->getOperand(1).getReg(); 742 Register FRSPDefines = RoundInstr->getOperand(0).getReg(); 743 MachineInstr &Use = *(MRI->use_instr_nodbg_begin(FRSPDefines)); 744 for (int i = 0, e = Use.getNumOperands(); i < e; ++i) 745 if (Use.getOperand(i).isReg() && 746 Use.getOperand(i).getReg() == FRSPDefines) 747 Use.getOperand(i).setReg(ConvReg1); 748 LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n"); 749 LLVM_DEBUG(RoundInstr->dump()); 750 LLVM_DEBUG(dbgs() << "As it feeds instruction:\n"); 751 LLVM_DEBUG(MI.dump()); 752 LLVM_DEBUG(dbgs() << "Through instruction:\n"); 753 LLVM_DEBUG(DefMI->dump()); 754 RoundInstr->eraseFromParent(); 755 } 756 }; 757 758 // If the input to XVCVDPSP is a vector that was built (even 759 // partially) out of FRSP's, the FRSP(s) can safely be removed 760 // since this instruction performs the same operation. 761 if (P1 != P2) { 762 removeFRSPIfPossible(P1); 763 removeFRSPIfPossible(P2); 764 break; 765 } 766 removeFRSPIfPossible(P1); 767 } 768 break; 769 } 770 case PPC::EXTSH: 771 case PPC::EXTSH8: 772 case PPC::EXTSH8_32_64: { 773 if (!EnableSExtElimination) break; 774 Register NarrowReg = MI.getOperand(1).getReg(); 775 if (!Register::isVirtualRegister(NarrowReg)) 776 break; 777 778 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 779 // If we've used a zero-extending load that we will sign-extend, 780 // just do a sign-extending load. 781 if (SrcMI->getOpcode() == PPC::LHZ || 782 SrcMI->getOpcode() == PPC::LHZX) { 783 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 784 break; 785 auto is64Bit = [] (unsigned Opcode) { 786 return Opcode == PPC::EXTSH8; 787 }; 788 auto isXForm = [] (unsigned Opcode) { 789 return Opcode == PPC::LHZX; 790 }; 791 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 792 if (is64Bit) 793 if (isXForm) return PPC::LHAX8; 794 else return PPC::LHA8; 795 else 796 if (isXForm) return PPC::LHAX; 797 else return PPC::LHA; 798 }; 799 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 800 isXForm(SrcMI->getOpcode())); 801 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 802 LLVM_DEBUG(SrcMI->dump()); 803 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 804 LLVM_DEBUG(MI.dump()); 805 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 806 SrcMI->setDesc(TII->get(Opc)); 807 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 808 ToErase = &MI; 809 Simplified = true; 810 NumEliminatedSExt++; 811 } 812 break; 813 } 814 case PPC::EXTSW: 815 case PPC::EXTSW_32: 816 case PPC::EXTSW_32_64: { 817 if (!EnableSExtElimination) break; 818 Register NarrowReg = MI.getOperand(1).getReg(); 819 if (!Register::isVirtualRegister(NarrowReg)) 820 break; 821 822 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 823 // If we've used a zero-extending load that we will sign-extend, 824 // just do a sign-extending load. 825 if (SrcMI->getOpcode() == PPC::LWZ || 826 SrcMI->getOpcode() == PPC::LWZX) { 827 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 828 break; 829 auto is64Bit = [] (unsigned Opcode) { 830 return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64; 831 }; 832 auto isXForm = [] (unsigned Opcode) { 833 return Opcode == PPC::LWZX; 834 }; 835 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 836 if (is64Bit) 837 if (isXForm) return PPC::LWAX; 838 else return PPC::LWA; 839 else 840 if (isXForm) return PPC::LWAX_32; 841 else return PPC::LWA_32; 842 }; 843 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 844 isXForm(SrcMI->getOpcode())); 845 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 846 LLVM_DEBUG(SrcMI->dump()); 847 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 848 LLVM_DEBUG(MI.dump()); 849 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 850 SrcMI->setDesc(TII->get(Opc)); 851 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 852 ToErase = &MI; 853 Simplified = true; 854 NumEliminatedSExt++; 855 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && 856 TII->isSignExtended(*SrcMI)) { 857 // We can eliminate EXTSW if the input is known to be already 858 // sign-extended. 859 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n"); 860 Register TmpReg = 861 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); 862 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 863 TmpReg); 864 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 865 MI.getOperand(0).getReg()) 866 .addReg(TmpReg) 867 .addReg(NarrowReg) 868 .addImm(PPC::sub_32); 869 ToErase = &MI; 870 Simplified = true; 871 NumEliminatedSExt++; 872 } 873 break; 874 } 875 case PPC::RLDICL: { 876 // We can eliminate RLDICL (e.g. for zero-extension) 877 // if all bits to clear are already zero in the input. 878 // This code assume following code sequence for zero-extension. 879 // %6 = COPY %5:sub_32; (optional) 880 // %8 = IMPLICIT_DEF; 881 // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32; 882 if (!EnableZExtElimination) break; 883 884 if (MI.getOperand(2).getImm() != 0) 885 break; 886 887 Register SrcReg = MI.getOperand(1).getReg(); 888 if (!Register::isVirtualRegister(SrcReg)) 889 break; 890 891 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 892 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && 893 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) 894 break; 895 896 MachineInstr *ImpDefMI, *SubRegMI; 897 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 898 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg()); 899 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; 900 901 SrcMI = SubRegMI; 902 if (SubRegMI->getOpcode() == PPC::COPY) { 903 Register CopyReg = SubRegMI->getOperand(1).getReg(); 904 if (Register::isVirtualRegister(CopyReg)) 905 SrcMI = MRI->getVRegDef(CopyReg); 906 } 907 908 unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII); 909 if (MI.getOperand(3).getImm() <= KnownZeroCount) { 910 LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n"); 911 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 912 MI.getOperand(0).getReg()) 913 .addReg(SrcReg); 914 ToErase = &MI; 915 Simplified = true; 916 NumEliminatedZExt++; 917 } 918 break; 919 } 920 921 // TODO: Any instruction that has an immediate form fed only by a PHI 922 // whose operands are all load immediate can be folded away. We currently 923 // do this for ADD instructions, but should expand it to arithmetic and 924 // binary instructions with immediate forms in the future. 925 case PPC::ADD4: 926 case PPC::ADD8: { 927 auto isSingleUsePHI = [&](MachineOperand *PhiOp) { 928 assert(PhiOp && "Invalid Operand!"); 929 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 930 931 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && 932 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg()); 933 }; 934 935 auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp, 936 MachineOperand *PhiOp) { 937 assert(PhiOp && "Invalid Operand!"); 938 assert(DominatorOp && "Invalid Operand!"); 939 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 940 MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI); 941 942 // Note: the vregs only show up at odd indices position of PHI Node, 943 // the even indices position save the BB info. 944 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 945 MachineInstr *LiMI = 946 getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 947 if (!LiMI || 948 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) 949 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) || 950 !MDT->dominates(DefDomMI, LiMI)) 951 return false; 952 } 953 954 return true; 955 }; 956 957 MachineOperand Op1 = MI.getOperand(1); 958 MachineOperand Op2 = MI.getOperand(2); 959 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2)) 960 std::swap(Op1, Op2); 961 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1)) 962 break; // We don't have an ADD fed by LI's that can be transformed 963 964 // Now we know that Op1 is the PHI node and Op2 is the dominator 965 Register DominatorReg = Op2.getReg(); 966 967 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 968 ? &PPC::G8RC_and_G8RC_NOX0RegClass 969 : &PPC::GPRC_and_GPRC_NOR0RegClass; 970 MRI->setRegClass(DominatorReg, TRC); 971 972 // replace LIs with ADDIs 973 MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); 974 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 975 MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 976 LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: "); 977 LLVM_DEBUG(LiMI->dump()); 978 979 // There could be repeated registers in the PHI, e.g: %1 = 980 // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've 981 // already replaced the def instruction, skip. 982 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) 983 continue; 984 985 assert((LiMI->getOpcode() == PPC::LI || 986 LiMI->getOpcode() == PPC::LI8) && 987 "Invalid Opcode!"); 988 auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI 989 LiMI->removeOperand(1); // remove the imm of LI 990 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI 991 : PPC::ADDI8)); 992 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI) 993 .addReg(DominatorReg) 994 .addImm(LiImm); // restore the imm of LI 995 LLVM_DEBUG(LiMI->dump()); 996 } 997 998 // Replace ADD with COPY 999 LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: "); 1000 LLVM_DEBUG(MI.dump()); 1001 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 1002 MI.getOperand(0).getReg()) 1003 .add(Op1); 1004 ToErase = &MI; 1005 Simplified = true; 1006 NumOptADDLIs++; 1007 break; 1008 } 1009 case PPC::RLDICR: { 1010 Simplified |= emitRLDICWhenLoweringJumpTables(MI) || 1011 combineSEXTAndSHL(MI, ToErase); 1012 break; 1013 } 1014 case PPC::RLWINM: 1015 case PPC::RLWINM_rec: 1016 case PPC::RLWINM8: 1017 case PPC::RLWINM8_rec: { 1018 Simplified = TII->combineRLWINM(MI, &ToErase); 1019 if (Simplified) 1020 ++NumRotatesCollapsed; 1021 break; 1022 } 1023 // We will replace TD/TW/TDI/TWI with an unconditional trap if it will 1024 // always trap, we will delete the node if it will never trap. 1025 case PPC::TDI: 1026 case PPC::TWI: 1027 case PPC::TD: 1028 case PPC::TW: { 1029 if (!EnableTrapOptimization) break; 1030 MachineInstr *LiMI1 = getVRegDefOrNull(&MI.getOperand(1), MRI); 1031 MachineInstr *LiMI2 = getVRegDefOrNull(&MI.getOperand(2), MRI); 1032 bool IsOperand2Immediate = MI.getOperand(2).isImm(); 1033 // We can only do the optimization if we can get immediates 1034 // from both operands 1035 if (!(LiMI1 && (LiMI1->getOpcode() == PPC::LI || 1036 LiMI1->getOpcode() == PPC::LI8))) 1037 break; 1038 if (!IsOperand2Immediate && 1039 !(LiMI2 && (LiMI2->getOpcode() == PPC::LI || 1040 LiMI2->getOpcode() == PPC::LI8))) 1041 break; 1042 1043 auto ImmOperand0 = MI.getOperand(0).getImm(); 1044 auto ImmOperand1 = LiMI1->getOperand(1).getImm(); 1045 auto ImmOperand2 = IsOperand2Immediate ? MI.getOperand(2).getImm() 1046 : LiMI2->getOperand(1).getImm(); 1047 1048 // We will replace the MI with an unconditional trap if it will always 1049 // trap. 1050 if ((ImmOperand0 == 31) || 1051 ((ImmOperand0 & 0x10) && 1052 ((int64_t)ImmOperand1 < (int64_t)ImmOperand2)) || 1053 ((ImmOperand0 & 0x8) && 1054 ((int64_t)ImmOperand1 > (int64_t)ImmOperand2)) || 1055 ((ImmOperand0 & 0x2) && 1056 ((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) || 1057 ((ImmOperand0 & 0x1) && 1058 ((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) || 1059 ((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) { 1060 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP)); 1061 TrapOpt = true; 1062 } 1063 // We will delete the MI if it will never trap. 1064 ToErase = &MI; 1065 Simplified = true; 1066 break; 1067 } 1068 } 1069 } 1070 1071 // If the last instruction was marked for elimination, 1072 // remove it now. 1073 if (ToErase) { 1074 ToErase->eraseFromParent(); 1075 ToErase = nullptr; 1076 } 1077 // Reset TrapOpt to false at the end of the basic block. 1078 if (EnableTrapOptimization) 1079 TrapOpt = false; 1080 } 1081 1082 // Eliminate all the TOC save instructions which are redundant. 1083 Simplified |= eliminateRedundantTOCSaves(TOCSaves); 1084 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 1085 if (FI->mustSaveTOC()) 1086 NumTOCSavesInPrologue++; 1087 1088 // We try to eliminate redundant compare instruction. 1089 Simplified |= eliminateRedundantCompare(); 1090 1091 return Simplified; 1092 } 1093 1094 // helper functions for eliminateRedundantCompare 1095 static bool isEqOrNe(MachineInstr *BI) { 1096 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1097 unsigned PredCond = PPC::getPredicateCondition(Pred); 1098 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); 1099 } 1100 1101 static bool isSupportedCmpOp(unsigned opCode) { 1102 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 1103 opCode == PPC::CMPLW || opCode == PPC::CMPW || 1104 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || 1105 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); 1106 } 1107 1108 static bool is64bitCmpOp(unsigned opCode) { 1109 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 1110 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); 1111 } 1112 1113 static bool isSignedCmpOp(unsigned opCode) { 1114 return (opCode == PPC::CMPD || opCode == PPC::CMPW || 1115 opCode == PPC::CMPDI || opCode == PPC::CMPWI); 1116 } 1117 1118 static unsigned getSignedCmpOpCode(unsigned opCode) { 1119 if (opCode == PPC::CMPLD) return PPC::CMPD; 1120 if (opCode == PPC::CMPLW) return PPC::CMPW; 1121 if (opCode == PPC::CMPLDI) return PPC::CMPDI; 1122 if (opCode == PPC::CMPLWI) return PPC::CMPWI; 1123 return opCode; 1124 } 1125 1126 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or 1127 // (LT x) to (LE x-1) 1128 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) { 1129 uint64_t Imm = CMPI->getOperand(2).getImm(); 1130 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1131 if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000)) 1132 return 0; 1133 1134 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1135 unsigned PredCond = PPC::getPredicateCondition(Pred); 1136 unsigned PredHint = PPC::getPredicateHint(Pred); 1137 if (PredCond == PPC::PRED_GE) 1138 return PPC::getPredicate(PPC::PRED_GT, PredHint); 1139 if (PredCond == PPC::PRED_LT) 1140 return PPC::getPredicate(PPC::PRED_LE, PredHint); 1141 1142 return 0; 1143 } 1144 1145 // We can increment immediate x in (GT x) by changing it to (GE x+1) or 1146 // (LE x) to (LT x+1) 1147 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) { 1148 uint64_t Imm = CMPI->getOperand(2).getImm(); 1149 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1150 if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF)) 1151 return 0; 1152 1153 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1154 unsigned PredCond = PPC::getPredicateCondition(Pred); 1155 unsigned PredHint = PPC::getPredicateHint(Pred); 1156 if (PredCond == PPC::PRED_GT) 1157 return PPC::getPredicate(PPC::PRED_GE, PredHint); 1158 if (PredCond == PPC::PRED_LE) 1159 return PPC::getPredicate(PPC::PRED_LT, PredHint); 1160 1161 return 0; 1162 } 1163 1164 // This takes a Phi node and returns a register value for the specified BB. 1165 static unsigned getIncomingRegForBlock(MachineInstr *Phi, 1166 MachineBasicBlock *MBB) { 1167 for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) { 1168 MachineOperand &MO = Phi->getOperand(I); 1169 if (MO.getMBB() == MBB) 1170 return Phi->getOperand(I-1).getReg(); 1171 } 1172 llvm_unreachable("invalid src basic block for this Phi node\n"); 1173 return 0; 1174 } 1175 1176 // This function tracks the source of the register through register copy. 1177 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2 1178 // assuming that the control comes from BB1 into BB2. 1179 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1, 1180 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) { 1181 unsigned SrcReg = Reg; 1182 while (true) { 1183 unsigned NextReg = SrcReg; 1184 MachineInstr *Inst = MRI->getVRegDef(SrcReg); 1185 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { 1186 NextReg = getIncomingRegForBlock(Inst, BB1); 1187 // We track through PHI only once to avoid infinite loop. 1188 BB1 = nullptr; 1189 } 1190 else if (Inst->isFullCopy()) 1191 NextReg = Inst->getOperand(1).getReg(); 1192 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) 1193 break; 1194 SrcReg = NextReg; 1195 } 1196 return SrcReg; 1197 } 1198 1199 static bool eligibleForCompareElimination(MachineBasicBlock &MBB, 1200 MachineBasicBlock *&PredMBB, 1201 MachineBasicBlock *&MBBtoMoveCmp, 1202 MachineRegisterInfo *MRI) { 1203 1204 auto isEligibleBB = [&](MachineBasicBlock &BB) { 1205 auto BII = BB.getFirstInstrTerminator(); 1206 // We optimize BBs ending with a conditional branch. 1207 // We check only for BCC here, not BCCLR, because BCCLR 1208 // will be formed only later in the pipeline. 1209 if (BB.succ_size() == 2 && 1210 BII != BB.instr_end() && 1211 (*BII).getOpcode() == PPC::BCC && 1212 (*BII).getOperand(1).isReg()) { 1213 // We optimize only if the condition code is used only by one BCC. 1214 Register CndReg = (*BII).getOperand(1).getReg(); 1215 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg)) 1216 return false; 1217 1218 MachineInstr *CMPI = MRI->getVRegDef(CndReg); 1219 // We assume compare and branch are in the same BB for ease of analysis. 1220 if (CMPI->getParent() != &BB) 1221 return false; 1222 1223 // We skip this BB if a physical register is used in comparison. 1224 for (MachineOperand &MO : CMPI->operands()) 1225 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg())) 1226 return false; 1227 1228 return true; 1229 } 1230 return false; 1231 }; 1232 1233 // If this BB has more than one successor, we can create a new BB and 1234 // move the compare instruction in the new BB. 1235 // So far, we do not move compare instruction to a BB having multiple 1236 // successors to avoid potentially increasing code size. 1237 auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) { 1238 return BB.succ_size() == 1; 1239 }; 1240 1241 if (!isEligibleBB(MBB)) 1242 return false; 1243 1244 unsigned NumPredBBs = MBB.pred_size(); 1245 if (NumPredBBs == 1) { 1246 MachineBasicBlock *TmpMBB = *MBB.pred_begin(); 1247 if (isEligibleBB(*TmpMBB)) { 1248 PredMBB = TmpMBB; 1249 MBBtoMoveCmp = nullptr; 1250 return true; 1251 } 1252 } 1253 else if (NumPredBBs == 2) { 1254 // We check for partially redundant case. 1255 // So far, we support cases with only two predecessors 1256 // to avoid increasing the number of instructions. 1257 MachineBasicBlock::pred_iterator PI = MBB.pred_begin(); 1258 MachineBasicBlock *Pred1MBB = *PI; 1259 MachineBasicBlock *Pred2MBB = *(PI+1); 1260 1261 if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) { 1262 // We assume Pred1MBB is the BB containing the compare to be merged and 1263 // Pred2MBB is the BB to which we will append a compare instruction. 1264 // Hence we can proceed as is. 1265 } 1266 else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) { 1267 // We need to swap Pred1MBB and Pred2MBB to canonicalize. 1268 std::swap(Pred1MBB, Pred2MBB); 1269 } 1270 else return false; 1271 1272 // Here, Pred2MBB is the BB to which we need to append a compare inst. 1273 // We cannot move the compare instruction if operands are not available 1274 // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI). 1275 MachineInstr *BI = &*MBB.getFirstInstrTerminator(); 1276 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg()); 1277 for (int I = 1; I <= 2; I++) 1278 if (CMPI->getOperand(I).isReg()) { 1279 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg()); 1280 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) 1281 return false; 1282 } 1283 1284 PredMBB = Pred1MBB; 1285 MBBtoMoveCmp = Pred2MBB; 1286 return true; 1287 } 1288 1289 return false; 1290 } 1291 1292 // This function will iterate over the input map containing a pair of TOC save 1293 // instruction and a flag. The flag will be set to false if the TOC save is 1294 // proven redundant. This function will erase from the basic block all the TOC 1295 // saves marked as redundant. 1296 bool PPCMIPeephole::eliminateRedundantTOCSaves( 1297 std::map<MachineInstr *, bool> &TOCSaves) { 1298 bool Simplified = false; 1299 int NumKept = 0; 1300 for (auto TOCSave : TOCSaves) { 1301 if (!TOCSave.second) { 1302 TOCSave.first->eraseFromParent(); 1303 RemoveTOCSave++; 1304 Simplified = true; 1305 } else { 1306 NumKept++; 1307 } 1308 } 1309 1310 if (NumKept > 1) 1311 MultiTOCSaves++; 1312 1313 return Simplified; 1314 } 1315 1316 // If multiple conditional branches are executed based on the (essentially) 1317 // same comparison, we merge compare instructions into one and make multiple 1318 // conditional branches on this comparison. 1319 // For example, 1320 // if (a == 0) { ... } 1321 // else if (a < 0) { ... } 1322 // can be executed by one compare and two conditional branches instead of 1323 // two pairs of a compare and a conditional branch. 1324 // 1325 // This method merges two compare instructions in two MBBs and modifies the 1326 // compare and conditional branch instructions if needed. 1327 // For the above example, the input for this pass looks like: 1328 // cmplwi r3, 0 1329 // beq 0, .LBB0_3 1330 // cmpwi r3, -1 1331 // bgt 0, .LBB0_4 1332 // So, before merging two compares, we need to modify these instructions as 1333 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq 1334 // beq 0, .LBB0_3 1335 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0 1336 // bge 0, .LBB0_4 1337 1338 bool PPCMIPeephole::eliminateRedundantCompare() { 1339 bool Simplified = false; 1340 1341 for (MachineBasicBlock &MBB2 : *MF) { 1342 MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr; 1343 1344 // For fully redundant case, we select two basic blocks MBB1 and MBB2 1345 // as an optimization target if 1346 // - both MBBs end with a conditional branch, 1347 // - MBB1 is the only predecessor of MBB2, and 1348 // - compare does not take a physical register as a operand in both MBBs. 1349 // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr. 1350 // 1351 // As partially redundant case, we additionally handle if MBB2 has one 1352 // additional predecessor, which has only one successor (MBB2). 1353 // In this case, we move the compare instruction originally in MBB2 into 1354 // MBBtoMoveCmp. This partially redundant case is typically appear by 1355 // compiling a while loop; here, MBBtoMoveCmp is the loop preheader. 1356 // 1357 // Overview of CFG of related basic blocks 1358 // Fully redundant case Partially redundant case 1359 // -------- ---------------- -------- 1360 // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ) 1361 // -------- ---------------- -------- 1362 // | \ (w/ 1 succ) \ | \ 1363 // | \ \ | \ 1364 // | \ | 1365 // -------- -------- 1366 // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred 1367 // -------- and 2 succ) -------- and 2 succ) 1368 // | \ | \ 1369 // | \ | \ 1370 // 1371 if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI)) 1372 continue; 1373 1374 MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator(); 1375 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg()); 1376 1377 MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator(); 1378 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg()); 1379 bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr); 1380 1381 // We cannot optimize an unsupported compare opcode or 1382 // a mix of 32-bit and 64-bit comaprisons 1383 if (!isSupportedCmpOp(CMPI1->getOpcode()) || 1384 !isSupportedCmpOp(CMPI2->getOpcode()) || 1385 is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode())) 1386 continue; 1387 1388 unsigned NewOpCode = 0; 1389 unsigned NewPredicate1 = 0, NewPredicate2 = 0; 1390 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; 1391 bool SwapOperands = false; 1392 1393 if (CMPI1->getOpcode() != CMPI2->getOpcode()) { 1394 // Typically, unsigned comparison is used for equality check, but 1395 // we replace it with a signed comparison if the comparison 1396 // to be merged is a signed comparison. 1397 // In other cases of opcode mismatch, we cannot optimize this. 1398 1399 // We cannot change opcode when comparing against an immediate 1400 // if the most significant bit of the immediate is one 1401 // due to the difference in sign extension. 1402 auto CmpAgainstImmWithSignBit = [](MachineInstr *I) { 1403 if (!I->getOperand(2).isImm()) 1404 return false; 1405 int16_t Imm = (int16_t)I->getOperand(2).getImm(); 1406 return Imm < 0; 1407 }; 1408 1409 if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) && 1410 CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode())) 1411 NewOpCode = CMPI1->getOpcode(); 1412 else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) && 1413 getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode()) 1414 NewOpCode = CMPI2->getOpcode(); 1415 else continue; 1416 } 1417 1418 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { 1419 // In case of comparisons between two registers, these two registers 1420 // must be same to merge two comparisons. 1421 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1422 nullptr, nullptr, MRI); 1423 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(), 1424 nullptr, nullptr, MRI); 1425 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1426 MBB1, &MBB2, MRI); 1427 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(), 1428 MBB1, &MBB2, MRI); 1429 1430 if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) { 1431 // Same pair of registers in the same order; ready to merge as is. 1432 } 1433 else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) { 1434 // Same pair of registers in different order. 1435 // We reverse the predicate to merge compare instructions. 1436 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); 1437 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); 1438 // In case of partial redundancy, we need to swap operands 1439 // in another compare instruction. 1440 SwapOperands = true; 1441 } 1442 else continue; 1443 } 1444 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { 1445 // In case of comparisons between a register and an immediate, 1446 // the operand register must be same for two compare instructions. 1447 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1448 nullptr, nullptr, MRI); 1449 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1450 MBB1, &MBB2, MRI); 1451 if (Cmp1Operand1 != Cmp2Operand1) 1452 continue; 1453 1454 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); 1455 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm(); 1456 1457 // If immediate are not same, we try to adjust by changing predicate; 1458 // e.g. GT imm means GE (imm+1). 1459 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { 1460 int Diff = Imm1 - Imm2; 1461 if (Diff < -2 || Diff > 2) 1462 continue; 1463 1464 unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1); 1465 unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1); 1466 unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2); 1467 unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2); 1468 if (Diff == 2) { 1469 if (PredToInc2 && PredToDec1) { 1470 NewPredicate2 = PredToInc2; 1471 NewPredicate1 = PredToDec1; 1472 NewImm2++; 1473 NewImm1--; 1474 } 1475 } 1476 else if (Diff == 1) { 1477 if (PredToInc2) { 1478 NewImm2++; 1479 NewPredicate2 = PredToInc2; 1480 } 1481 else if (PredToDec1) { 1482 NewImm1--; 1483 NewPredicate1 = PredToDec1; 1484 } 1485 } 1486 else if (Diff == -1) { 1487 if (PredToDec2) { 1488 NewImm2--; 1489 NewPredicate2 = PredToDec2; 1490 } 1491 else if (PredToInc1) { 1492 NewImm1++; 1493 NewPredicate1 = PredToInc1; 1494 } 1495 } 1496 else if (Diff == -2) { 1497 if (PredToDec2 && PredToInc1) { 1498 NewPredicate2 = PredToDec2; 1499 NewPredicate1 = PredToInc1; 1500 NewImm2--; 1501 NewImm1++; 1502 } 1503 } 1504 } 1505 1506 // We cannot merge two compares if the immediates are not same. 1507 if (NewImm2 != NewImm1) 1508 continue; 1509 } 1510 1511 LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); 1512 LLVM_DEBUG(CMPI1->dump()); 1513 LLVM_DEBUG(BI1->dump()); 1514 LLVM_DEBUG(CMPI2->dump()); 1515 LLVM_DEBUG(BI2->dump()); 1516 1517 // We adjust opcode, predicates and immediate as we determined above. 1518 if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) { 1519 CMPI1->setDesc(TII->get(NewOpCode)); 1520 } 1521 if (NewPredicate1) { 1522 BI1->getOperand(0).setImm(NewPredicate1); 1523 } 1524 if (NewPredicate2) { 1525 BI2->getOperand(0).setImm(NewPredicate2); 1526 } 1527 if (NewImm1 != Imm1) { 1528 CMPI1->getOperand(2).setImm(NewImm1); 1529 } 1530 1531 if (IsPartiallyRedundant) { 1532 // We touch up the compare instruction in MBB2 and move it to 1533 // a previous BB to handle partially redundant case. 1534 if (SwapOperands) { 1535 Register Op1 = CMPI2->getOperand(1).getReg(); 1536 Register Op2 = CMPI2->getOperand(2).getReg(); 1537 CMPI2->getOperand(1).setReg(Op2); 1538 CMPI2->getOperand(2).setReg(Op1); 1539 } 1540 if (NewImm2 != Imm2) 1541 CMPI2->getOperand(2).setImm(NewImm2); 1542 1543 for (int I = 1; I <= 2; I++) { 1544 if (CMPI2->getOperand(I).isReg()) { 1545 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg()); 1546 if (Inst->getParent() != &MBB2) 1547 continue; 1548 1549 assert(Inst->getOpcode() == PPC::PHI && 1550 "We cannot support if an operand comes from this BB."); 1551 unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp); 1552 CMPI2->getOperand(I).setReg(SrcReg); 1553 } 1554 } 1555 auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator()); 1556 MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2)); 1557 1558 DebugLoc DL = CMPI2->getDebugLoc(); 1559 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); 1560 BuildMI(MBB2, MBB2.begin(), DL, 1561 TII->get(PPC::PHI), NewVReg) 1562 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1) 1563 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp); 1564 BI2->getOperand(1).setReg(NewVReg); 1565 } 1566 else { 1567 // We finally eliminate compare instruction in MBB2. 1568 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); 1569 CMPI2->eraseFromParent(); 1570 } 1571 BI2->getOperand(1).setIsKill(true); 1572 BI1->getOperand(1).setIsKill(false); 1573 1574 LLVM_DEBUG(dbgs() << "into a compare and two branches:\n"); 1575 LLVM_DEBUG(CMPI1->dump()); 1576 LLVM_DEBUG(BI1->dump()); 1577 LLVM_DEBUG(BI2->dump()); 1578 if (IsPartiallyRedundant) { 1579 LLVM_DEBUG(dbgs() << "The following compare is moved into " 1580 << printMBBReference(*MBBtoMoveCmp) 1581 << " to handle partial redundancy.\n"); 1582 LLVM_DEBUG(CMPI2->dump()); 1583 } 1584 1585 Simplified = true; 1586 } 1587 1588 return Simplified; 1589 } 1590 1591 // We miss the opportunity to emit an RLDIC when lowering jump tables 1592 // since ISEL sees only a single basic block. When selecting, the clear 1593 // and shift left will be in different blocks. 1594 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) { 1595 if (MI.getOpcode() != PPC::RLDICR) 1596 return false; 1597 1598 Register SrcReg = MI.getOperand(1).getReg(); 1599 if (!Register::isVirtualRegister(SrcReg)) 1600 return false; 1601 1602 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1603 if (SrcMI->getOpcode() != PPC::RLDICL) 1604 return false; 1605 1606 MachineOperand MOpSHSrc = SrcMI->getOperand(2); 1607 MachineOperand MOpMBSrc = SrcMI->getOperand(3); 1608 MachineOperand MOpSHMI = MI.getOperand(2); 1609 MachineOperand MOpMEMI = MI.getOperand(3); 1610 if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() && 1611 MOpMEMI.isImm())) 1612 return false; 1613 1614 uint64_t SHSrc = MOpSHSrc.getImm(); 1615 uint64_t MBSrc = MOpMBSrc.getImm(); 1616 uint64_t SHMI = MOpSHMI.getImm(); 1617 uint64_t MEMI = MOpMEMI.getImm(); 1618 uint64_t NewSH = SHSrc + SHMI; 1619 uint64_t NewMB = MBSrc - SHMI; 1620 if (NewMB > 63 || NewSH > 63) 1621 return false; 1622 1623 // The bits cleared with RLDICL are [0, MBSrc). 1624 // The bits cleared with RLDICR are (MEMI, 63]. 1625 // After the sequence, the bits cleared are: 1626 // [0, MBSrc-SHMI) and (MEMI, 63). 1627 // 1628 // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63]. 1629 if ((63 - NewSH) != MEMI) 1630 return false; 1631 1632 LLVM_DEBUG(dbgs() << "Converting pair: "); 1633 LLVM_DEBUG(SrcMI->dump()); 1634 LLVM_DEBUG(MI.dump()); 1635 1636 MI.setDesc(TII->get(PPC::RLDIC)); 1637 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 1638 MI.getOperand(2).setImm(NewSH); 1639 MI.getOperand(3).setImm(NewMB); 1640 MI.getOperand(1).setIsKill(SrcMI->getOperand(1).isKill()); 1641 SrcMI->getOperand(1).setIsKill(false); 1642 1643 LLVM_DEBUG(dbgs() << "To: "); 1644 LLVM_DEBUG(MI.dump()); 1645 NumRotatesCollapsed++; 1646 // If SrcReg has no non-debug use it's safe to delete its def SrcMI. 1647 if (MRI->use_nodbg_empty(SrcReg)) { 1648 assert(!SrcMI->hasImplicitDef() && 1649 "Not expecting an implicit def with this instr."); 1650 SrcMI->eraseFromParent(); 1651 } 1652 return true; 1653 } 1654 1655 // For case in LLVM IR 1656 // entry: 1657 // %iconv = sext i32 %index to i64 1658 // br i1 undef label %true, label %false 1659 // true: 1660 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv 1661 // ... 1662 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in 1663 // different BBs when conducting instruction selection. We can do a peephole 1664 // optimization to combine these two instructions into extswsli after 1665 // instruction selection. 1666 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI, 1667 MachineInstr *&ToErase) { 1668 if (MI.getOpcode() != PPC::RLDICR) 1669 return false; 1670 1671 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0()) 1672 return false; 1673 1674 assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands"); 1675 1676 MachineOperand MOpSHMI = MI.getOperand(2); 1677 MachineOperand MOpMEMI = MI.getOperand(3); 1678 if (!(MOpSHMI.isImm() && MOpMEMI.isImm())) 1679 return false; 1680 1681 uint64_t SHMI = MOpSHMI.getImm(); 1682 uint64_t MEMI = MOpMEMI.getImm(); 1683 if (SHMI + MEMI != 63) 1684 return false; 1685 1686 Register SrcReg = MI.getOperand(1).getReg(); 1687 if (!Register::isVirtualRegister(SrcReg)) 1688 return false; 1689 1690 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1691 if (SrcMI->getOpcode() != PPC::EXTSW && 1692 SrcMI->getOpcode() != PPC::EXTSW_32_64) 1693 return false; 1694 1695 // If the register defined by extsw has more than one use, combination is not 1696 // needed. 1697 if (!MRI->hasOneNonDBGUse(SrcReg)) 1698 return false; 1699 1700 assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands"); 1701 assert(SrcMI->getOperand(1).isReg() && 1702 "EXTSW's second operand should be a register"); 1703 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) 1704 return false; 1705 1706 LLVM_DEBUG(dbgs() << "Combining pair: "); 1707 LLVM_DEBUG(SrcMI->dump()); 1708 LLVM_DEBUG(MI.dump()); 1709 1710 MachineInstr *NewInstr = 1711 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), 1712 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) 1713 : TII->get(PPC::EXTSWSLI_32_64), 1714 MI.getOperand(0).getReg()) 1715 .add(SrcMI->getOperand(1)) 1716 .add(MOpSHMI); 1717 (void)NewInstr; 1718 1719 LLVM_DEBUG(dbgs() << "TO: "); 1720 LLVM_DEBUG(NewInstr->dump()); 1721 ++NumEXTSWAndSLDICombined; 1722 ToErase = &MI; 1723 // SrcMI, which is extsw, is of no use now, erase it. 1724 SrcMI->eraseFromParent(); 1725 return true; 1726 } 1727 1728 } // end default namespace 1729 1730 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, 1731 "PowerPC MI Peephole Optimization", false, false) 1732 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) 1733 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 1734 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) 1735 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE, 1736 "PowerPC MI Peephole Optimization", false, false) 1737 1738 char PPCMIPeephole::ID = 0; 1739 FunctionPass* 1740 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); } 1741