1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 // 9 // This pass performs peephole optimizations to clean up ugly code 10 // sequences at the MachineInstruction layer. It runs at the end of 11 // the SSA phases, following VSX swap removal. A pass of dead code 12 // elimination follows this one for quick clean-up of any dead 13 // instructions introduced here. Although we could do this as callbacks 14 // from the generic peephole pass, this would have a couple of bad 15 // effects: it might remove optimization opportunities for VSX swap 16 // removal, and it would miss cleanups made possible following VSX 17 // swap removal. 18 // 19 //===---------------------------------------------------------------------===// 20 21 #include "PPC.h" 22 #include "PPCInstrBuilder.h" 23 #include "PPCInstrInfo.h" 24 #include "PPCMachineFunctionInfo.h" 25 #include "PPCTargetMachine.h" 26 #include "llvm/ADT/Statistic.h" 27 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 28 #include "llvm/CodeGen/MachineDominators.h" 29 #include "llvm/CodeGen/MachinePostDominators.h" 30 #include "llvm/CodeGen/MachineFunctionPass.h" 31 #include "llvm/CodeGen/MachineInstrBuilder.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/Support/Debug.h" 34 #include "MCTargetDesc/PPCPredicates.h" 35 36 using namespace llvm; 37 38 #define DEBUG_TYPE "ppc-mi-peepholes" 39 40 STATISTIC(RemoveTOCSave, "Number of TOC saves removed"); 41 STATISTIC(MultiTOCSaves, 42 "Number of functions with multiple TOC saves that must be kept"); 43 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue"); 44 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions"); 45 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions"); 46 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI"); 47 STATISTIC(NumConvertedToImmediateForm, 48 "Number of instructions converted to their immediate form"); 49 STATISTIC(NumFunctionsEnteredInMIPeephole, 50 "Number of functions entered in PPC MI Peepholes"); 51 STATISTIC(NumFixedPointIterations, 52 "Number of fixed-point iterations converting reg-reg instructions " 53 "to reg-imm ones"); 54 STATISTIC(NumRotatesCollapsed, 55 "Number of pairs of rotate left, clear left/right collapsed"); 56 STATISTIC(NumEXTSWAndSLDICombined, 57 "Number of pairs of EXTSW and SLDI combined as EXTSWSLI"); 58 59 static cl::opt<bool> 60 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), 61 cl::desc("Iterate to a fixed point when attempting to " 62 "convert reg-reg instructions to reg-imm")); 63 64 static cl::opt<bool> 65 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), 66 cl::desc("Convert eligible reg+reg instructions to reg+imm")); 67 68 static cl::opt<bool> 69 EnableSExtElimination("ppc-eliminate-signext", 70 cl::desc("enable elimination of sign-extensions"), 71 cl::init(false), cl::Hidden); 72 73 static cl::opt<bool> 74 EnableZExtElimination("ppc-eliminate-zeroext", 75 cl::desc("enable elimination of zero-extensions"), 76 cl::init(false), cl::Hidden); 77 78 namespace { 79 80 struct PPCMIPeephole : public MachineFunctionPass { 81 82 static char ID; 83 const PPCInstrInfo *TII; 84 MachineFunction *MF; 85 MachineRegisterInfo *MRI; 86 87 PPCMIPeephole() : MachineFunctionPass(ID) { 88 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry()); 89 } 90 91 private: 92 MachineDominatorTree *MDT; 93 MachinePostDominatorTree *MPDT; 94 MachineBlockFrequencyInfo *MBFI; 95 uint64_t EntryFreq; 96 97 // Initialize class variables. 98 void initialize(MachineFunction &MFParm); 99 100 // Perform peepholes. 101 bool simplifyCode(void); 102 103 // Perform peepholes. 104 bool eliminateRedundantCompare(void); 105 bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves); 106 bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase); 107 bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI); 108 void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves, 109 MachineInstr *MI); 110 111 public: 112 113 void getAnalysisUsage(AnalysisUsage &AU) const override { 114 AU.addRequired<MachineDominatorTree>(); 115 AU.addRequired<MachinePostDominatorTree>(); 116 AU.addRequired<MachineBlockFrequencyInfo>(); 117 AU.addPreserved<MachineDominatorTree>(); 118 AU.addPreserved<MachinePostDominatorTree>(); 119 AU.addPreserved<MachineBlockFrequencyInfo>(); 120 MachineFunctionPass::getAnalysisUsage(AU); 121 } 122 123 // Main entry point for this pass. 124 bool runOnMachineFunction(MachineFunction &MF) override { 125 if (skipFunction(MF.getFunction())) 126 return false; 127 initialize(MF); 128 return simplifyCode(); 129 } 130 }; 131 132 // Initialize class variables. 133 void PPCMIPeephole::initialize(MachineFunction &MFParm) { 134 MF = &MFParm; 135 MRI = &MF->getRegInfo(); 136 MDT = &getAnalysis<MachineDominatorTree>(); 137 MPDT = &getAnalysis<MachinePostDominatorTree>(); 138 MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); 139 EntryFreq = MBFI->getEntryFreq(); 140 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 141 LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 142 LLVM_DEBUG(MF->dump()); 143 } 144 145 static MachineInstr *getVRegDefOrNull(MachineOperand *Op, 146 MachineRegisterInfo *MRI) { 147 assert(Op && "Invalid Operand!"); 148 if (!Op->isReg()) 149 return nullptr; 150 151 Register Reg = Op->getReg(); 152 if (!Register::isVirtualRegister(Reg)) 153 return nullptr; 154 155 return MRI->getVRegDef(Reg); 156 } 157 158 // This function returns number of known zero bits in output of MI 159 // starting from the most significant bit. 160 static unsigned 161 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) { 162 unsigned Opcode = MI->getOpcode(); 163 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || 164 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo) 165 return MI->getOperand(3).getImm(); 166 167 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) && 168 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) 169 return MI->getOperand(3).getImm(); 170 171 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo || 172 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo || 173 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && 174 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) 175 return 32 + MI->getOperand(3).getImm(); 176 177 if (Opcode == PPC::ANDIo) { 178 uint16_t Imm = MI->getOperand(2).getImm(); 179 return 48 + countLeadingZeros(Imm); 180 } 181 182 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo || 183 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo || 184 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) 185 // The result ranges from 0 to 32. 186 return 58; 187 188 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo || 189 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo) 190 // The result ranges from 0 to 64. 191 return 57; 192 193 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || 194 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || 195 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || 196 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) 197 return 48; 198 199 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || 200 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || 201 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || 202 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) 203 return 56; 204 205 if (TII->isZeroExtended(*MI)) 206 return 32; 207 208 return 0; 209 } 210 211 // This function maintains a map for the pairs <TOC Save Instr, Keep> 212 // Each time a new TOC save is encountered, it checks if any of the existing 213 // ones are dominated by the new one. If so, it marks the existing one as 214 // redundant by setting it's entry in the map as false. It then adds the new 215 // instruction to the map with either true or false depending on if any 216 // existing instructions dominated the new one. 217 void PPCMIPeephole::UpdateTOCSaves( 218 std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) { 219 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here"); 220 assert(MF->getSubtarget<PPCSubtarget>().isELFv2ABI() && 221 "TOC-save removal only supported on ELFv2"); 222 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 223 224 MachineBasicBlock *Entry = &MF->front(); 225 uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency(); 226 227 // If the block in which the TOC save resides is in a block that 228 // post-dominates Entry, or a block that is hotter than entry (keep in mind 229 // that early MachineLICM has already run so the TOC save won't be hoisted) 230 // we can just do the save in the prologue. 231 if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry)) 232 FI->setMustSaveTOC(true); 233 234 // If we are saving the TOC in the prologue, all the TOC saves can be removed 235 // from the code. 236 if (FI->mustSaveTOC()) { 237 for (auto &TOCSave : TOCSaves) 238 TOCSave.second = false; 239 // Add new instruction to map. 240 TOCSaves[MI] = false; 241 return; 242 } 243 244 bool Keep = true; 245 for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) { 246 MachineInstr *CurrInst = It->first; 247 // If new instruction dominates an existing one, mark existing one as 248 // redundant. 249 if (It->second && MDT->dominates(MI, CurrInst)) 250 It->second = false; 251 // Check if the new instruction is redundant. 252 if (MDT->dominates(CurrInst, MI)) { 253 Keep = false; 254 break; 255 } 256 } 257 // Add new instruction to map. 258 TOCSaves[MI] = Keep; 259 } 260 261 // Perform peephole optimizations. 262 bool PPCMIPeephole::simplifyCode(void) { 263 bool Simplified = false; 264 MachineInstr* ToErase = nullptr; 265 std::map<MachineInstr *, bool> TOCSaves; 266 const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); 267 NumFunctionsEnteredInMIPeephole++; 268 if (ConvertRegReg) { 269 // Fixed-point conversion of reg/reg instructions fed by load-immediate 270 // into reg/imm instructions. FIXME: This is expensive, control it with 271 // an option. 272 bool SomethingChanged = false; 273 do { 274 NumFixedPointIterations++; 275 SomethingChanged = false; 276 for (MachineBasicBlock &MBB : *MF) { 277 for (MachineInstr &MI : MBB) { 278 if (MI.isDebugInstr()) 279 continue; 280 281 if (TII->convertToImmediateForm(MI)) { 282 // We don't erase anything in case the def has other uses. Let DCE 283 // remove it if it can be removed. 284 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 285 LLVM_DEBUG(MI.dump()); 286 NumConvertedToImmediateForm++; 287 SomethingChanged = true; 288 Simplified = true; 289 continue; 290 } 291 } 292 } 293 } while (SomethingChanged && FixedPointRegToImm); 294 } 295 296 for (MachineBasicBlock &MBB : *MF) { 297 for (MachineInstr &MI : MBB) { 298 299 // If the previous instruction was marked for elimination, 300 // remove it now. 301 if (ToErase) { 302 ToErase->eraseFromParent(); 303 ToErase = nullptr; 304 } 305 306 // Ignore debug instructions. 307 if (MI.isDebugInstr()) 308 continue; 309 310 // Per-opcode peepholes. 311 switch (MI.getOpcode()) { 312 313 default: 314 break; 315 316 case PPC::STD: { 317 MachineFrameInfo &MFI = MF->getFrameInfo(); 318 if (MFI.hasVarSizedObjects() || 319 !MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) 320 break; 321 // When encountering a TOC save instruction, call UpdateTOCSaves 322 // to add it to the TOCSaves map and mark any existing TOC saves 323 // it dominates as redundant. 324 if (TII->isTOCSaveMI(MI)) 325 UpdateTOCSaves(TOCSaves, &MI); 326 break; 327 } 328 case PPC::XXPERMDI: { 329 // Perform simplifications of 2x64 vector swaps and splats. 330 // A swap is identified by an immediate value of 2, and a splat 331 // is identified by an immediate value of 0 or 3. 332 int Immed = MI.getOperand(3).getImm(); 333 334 if (Immed != 1) { 335 336 // For each of these simplifications, we need the two source 337 // regs to match. Unfortunately, MachineCSE ignores COPY and 338 // SUBREG_TO_REG, so for example we can see 339 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed. 340 // We have to look through chains of COPY and SUBREG_TO_REG 341 // to find the real source values for comparison. 342 unsigned TrueReg1 = 343 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 344 unsigned TrueReg2 = 345 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); 346 347 if (TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)) { 348 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 349 unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0; 350 351 // If this is a splat fed by a splatting load, the splat is 352 // redundant. Replace with a copy. This doesn't happen directly due 353 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting 354 // a load of a double to a vector of 64-bit integers. 355 auto isConversionOfLoadAndSplat = [=]() -> bool { 356 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) 357 return false; 358 unsigned DefReg = 359 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 360 if (Register::isVirtualRegister(DefReg)) { 361 MachineInstr *LoadMI = MRI->getVRegDef(DefReg); 362 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) 363 return true; 364 } 365 return false; 366 }; 367 if (DefMI && (Immed == 0 || Immed == 3)) { 368 if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) { 369 LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat " 370 "to load-and-splat/copy: "); 371 LLVM_DEBUG(MI.dump()); 372 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 373 MI.getOperand(0).getReg()) 374 .add(MI.getOperand(1)); 375 ToErase = &MI; 376 Simplified = true; 377 } 378 } 379 380 // If this is a splat or a swap fed by another splat, we 381 // can replace it with a copy. 382 if (DefOpc == PPC::XXPERMDI) { 383 unsigned FeedImmed = DefMI->getOperand(3).getImm(); 384 unsigned FeedReg1 = 385 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 386 unsigned FeedReg2 = 387 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 388 389 if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) { 390 LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat " 391 "to splat/copy: "); 392 LLVM_DEBUG(MI.dump()); 393 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 394 MI.getOperand(0).getReg()) 395 .add(MI.getOperand(1)); 396 ToErase = &MI; 397 Simplified = true; 398 } 399 400 // If this is a splat fed by a swap, we can simplify modify 401 // the splat to splat the other value from the swap's input 402 // parameter. 403 else if ((Immed == 0 || Immed == 3) 404 && FeedImmed == 2 && FeedReg1 == FeedReg2) { 405 LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: "); 406 LLVM_DEBUG(MI.dump()); 407 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); 408 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); 409 MI.getOperand(3).setImm(3 - Immed); 410 Simplified = true; 411 } 412 413 // If this is a swap fed by a swap, we can replace it 414 // with a copy from the first swap's input. 415 else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) { 416 LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: "); 417 LLVM_DEBUG(MI.dump()); 418 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 419 MI.getOperand(0).getReg()) 420 .add(DefMI->getOperand(1)); 421 ToErase = &MI; 422 Simplified = true; 423 } 424 } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs && 425 (DefMI->getOperand(2).getImm() == 0 || 426 DefMI->getOperand(2).getImm() == 3)) { 427 // Splat fed by another splat - switch the output of the first 428 // and remove the second. 429 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 430 ToErase = &MI; 431 Simplified = true; 432 LLVM_DEBUG(dbgs() << "Removing redundant splat: "); 433 LLVM_DEBUG(MI.dump()); 434 } 435 } 436 } 437 break; 438 } 439 case PPC::VSPLTB: 440 case PPC::VSPLTH: 441 case PPC::XXSPLTW: { 442 unsigned MyOpcode = MI.getOpcode(); 443 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; 444 unsigned TrueReg = 445 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI); 446 if (!Register::isVirtualRegister(TrueReg)) 447 break; 448 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 449 if (!DefMI) 450 break; 451 unsigned DefOpcode = DefMI->getOpcode(); 452 auto isConvertOfSplat = [=]() -> bool { 453 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) 454 return false; 455 Register ConvReg = DefMI->getOperand(1).getReg(); 456 if (!Register::isVirtualRegister(ConvReg)) 457 return false; 458 MachineInstr *Splt = MRI->getVRegDef(ConvReg); 459 return Splt && (Splt->getOpcode() == PPC::LXVWSX || 460 Splt->getOpcode() == PPC::XXSPLTW); 461 }; 462 bool AlreadySplat = (MyOpcode == DefOpcode) || 463 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || 464 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || 465 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || 466 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || 467 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| 468 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); 469 // If the instruction[s] that feed this splat have already splat 470 // the value, this splat is redundant. 471 if (AlreadySplat) { 472 LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: "); 473 LLVM_DEBUG(MI.dump()); 474 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 475 MI.getOperand(0).getReg()) 476 .add(MI.getOperand(OpNo)); 477 ToErase = &MI; 478 Simplified = true; 479 } 480 // Splat fed by a shift. Usually when we align value to splat into 481 // vector element zero. 482 if (DefOpcode == PPC::XXSLDWI) { 483 Register ShiftRes = DefMI->getOperand(0).getReg(); 484 Register ShiftOp1 = DefMI->getOperand(1).getReg(); 485 Register ShiftOp2 = DefMI->getOperand(2).getReg(); 486 unsigned ShiftImm = DefMI->getOperand(3).getImm(); 487 unsigned SplatImm = MI.getOperand(2).getImm(); 488 if (ShiftOp1 == ShiftOp2) { 489 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; 490 if (MRI->hasOneNonDBGUse(ShiftRes)) { 491 LLVM_DEBUG(dbgs() << "Removing redundant shift: "); 492 LLVM_DEBUG(DefMI->dump()); 493 ToErase = DefMI; 494 } 495 Simplified = true; 496 LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm 497 << " to " << NewElem << " in instruction: "); 498 LLVM_DEBUG(MI.dump()); 499 MI.getOperand(1).setReg(ShiftOp1); 500 MI.getOperand(2).setImm(NewElem); 501 } 502 } 503 break; 504 } 505 case PPC::XVCVDPSP: { 506 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant. 507 unsigned TrueReg = 508 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 509 if (!Register::isVirtualRegister(TrueReg)) 510 break; 511 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 512 513 // This can occur when building a vector of single precision or integer 514 // values. 515 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 516 unsigned DefsReg1 = 517 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 518 unsigned DefsReg2 = 519 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 520 if (!Register::isVirtualRegister(DefsReg1) || 521 !Register::isVirtualRegister(DefsReg2)) 522 break; 523 MachineInstr *P1 = MRI->getVRegDef(DefsReg1); 524 MachineInstr *P2 = MRI->getVRegDef(DefsReg2); 525 526 if (!P1 || !P2) 527 break; 528 529 // Remove the passed FRSP instruction if it only feeds this MI and 530 // set any uses of that FRSP (in this MI) to the source of the FRSP. 531 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) { 532 if (RoundInstr->getOpcode() == PPC::FRSP && 533 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) { 534 Simplified = true; 535 Register ConvReg1 = RoundInstr->getOperand(1).getReg(); 536 Register FRSPDefines = RoundInstr->getOperand(0).getReg(); 537 MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines)); 538 for (int i = 0, e = Use.getNumOperands(); i < e; ++i) 539 if (Use.getOperand(i).isReg() && 540 Use.getOperand(i).getReg() == FRSPDefines) 541 Use.getOperand(i).setReg(ConvReg1); 542 LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n"); 543 LLVM_DEBUG(RoundInstr->dump()); 544 LLVM_DEBUG(dbgs() << "As it feeds instruction:\n"); 545 LLVM_DEBUG(MI.dump()); 546 LLVM_DEBUG(dbgs() << "Through instruction:\n"); 547 LLVM_DEBUG(DefMI->dump()); 548 RoundInstr->eraseFromParent(); 549 } 550 }; 551 552 // If the input to XVCVDPSP is a vector that was built (even 553 // partially) out of FRSP's, the FRSP(s) can safely be removed 554 // since this instruction performs the same operation. 555 if (P1 != P2) { 556 removeFRSPIfPossible(P1); 557 removeFRSPIfPossible(P2); 558 break; 559 } 560 removeFRSPIfPossible(P1); 561 } 562 break; 563 } 564 case PPC::EXTSH: 565 case PPC::EXTSH8: 566 case PPC::EXTSH8_32_64: { 567 if (!EnableSExtElimination) break; 568 Register NarrowReg = MI.getOperand(1).getReg(); 569 if (!Register::isVirtualRegister(NarrowReg)) 570 break; 571 572 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 573 // If we've used a zero-extending load that we will sign-extend, 574 // just do a sign-extending load. 575 if (SrcMI->getOpcode() == PPC::LHZ || 576 SrcMI->getOpcode() == PPC::LHZX) { 577 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 578 break; 579 auto is64Bit = [] (unsigned Opcode) { 580 return Opcode == PPC::EXTSH8; 581 }; 582 auto isXForm = [] (unsigned Opcode) { 583 return Opcode == PPC::LHZX; 584 }; 585 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 586 if (is64Bit) 587 if (isXForm) return PPC::LHAX8; 588 else return PPC::LHA8; 589 else 590 if (isXForm) return PPC::LHAX; 591 else return PPC::LHA; 592 }; 593 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 594 isXForm(SrcMI->getOpcode())); 595 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 596 LLVM_DEBUG(SrcMI->dump()); 597 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 598 LLVM_DEBUG(MI.dump()); 599 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 600 SrcMI->setDesc(TII->get(Opc)); 601 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 602 ToErase = &MI; 603 Simplified = true; 604 NumEliminatedSExt++; 605 } 606 break; 607 } 608 case PPC::EXTSW: 609 case PPC::EXTSW_32: 610 case PPC::EXTSW_32_64: { 611 if (!EnableSExtElimination) break; 612 Register NarrowReg = MI.getOperand(1).getReg(); 613 if (!Register::isVirtualRegister(NarrowReg)) 614 break; 615 616 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 617 // If we've used a zero-extending load that we will sign-extend, 618 // just do a sign-extending load. 619 if (SrcMI->getOpcode() == PPC::LWZ || 620 SrcMI->getOpcode() == PPC::LWZX) { 621 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 622 break; 623 auto is64Bit = [] (unsigned Opcode) { 624 return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64; 625 }; 626 auto isXForm = [] (unsigned Opcode) { 627 return Opcode == PPC::LWZX; 628 }; 629 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 630 if (is64Bit) 631 if (isXForm) return PPC::LWAX; 632 else return PPC::LWA; 633 else 634 if (isXForm) return PPC::LWAX_32; 635 else return PPC::LWA_32; 636 }; 637 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 638 isXForm(SrcMI->getOpcode())); 639 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 640 LLVM_DEBUG(SrcMI->dump()); 641 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 642 LLVM_DEBUG(MI.dump()); 643 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 644 SrcMI->setDesc(TII->get(Opc)); 645 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 646 ToErase = &MI; 647 Simplified = true; 648 NumEliminatedSExt++; 649 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && 650 TII->isSignExtended(*SrcMI)) { 651 // We can eliminate EXTSW if the input is known to be already 652 // sign-extended. 653 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n"); 654 Register TmpReg = 655 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); 656 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 657 TmpReg); 658 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 659 MI.getOperand(0).getReg()) 660 .addReg(TmpReg) 661 .addReg(NarrowReg) 662 .addImm(PPC::sub_32); 663 ToErase = &MI; 664 Simplified = true; 665 NumEliminatedSExt++; 666 } 667 break; 668 } 669 case PPC::RLDICL: { 670 // We can eliminate RLDICL (e.g. for zero-extension) 671 // if all bits to clear are already zero in the input. 672 // This code assume following code sequence for zero-extension. 673 // %6 = COPY %5:sub_32; (optional) 674 // %8 = IMPLICIT_DEF; 675 // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32; 676 if (!EnableZExtElimination) break; 677 678 if (MI.getOperand(2).getImm() != 0) 679 break; 680 681 Register SrcReg = MI.getOperand(1).getReg(); 682 if (!Register::isVirtualRegister(SrcReg)) 683 break; 684 685 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 686 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && 687 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) 688 break; 689 690 MachineInstr *ImpDefMI, *SubRegMI; 691 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 692 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg()); 693 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; 694 695 SrcMI = SubRegMI; 696 if (SubRegMI->getOpcode() == PPC::COPY) { 697 Register CopyReg = SubRegMI->getOperand(1).getReg(); 698 if (Register::isVirtualRegister(CopyReg)) 699 SrcMI = MRI->getVRegDef(CopyReg); 700 } 701 702 unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII); 703 if (MI.getOperand(3).getImm() <= KnownZeroCount) { 704 LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n"); 705 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 706 MI.getOperand(0).getReg()) 707 .addReg(SrcReg); 708 ToErase = &MI; 709 Simplified = true; 710 NumEliminatedZExt++; 711 } 712 break; 713 } 714 715 // TODO: Any instruction that has an immediate form fed only by a PHI 716 // whose operands are all load immediate can be folded away. We currently 717 // do this for ADD instructions, but should expand it to arithmetic and 718 // binary instructions with immediate forms in the future. 719 case PPC::ADD4: 720 case PPC::ADD8: { 721 auto isSingleUsePHI = [&](MachineOperand *PhiOp) { 722 assert(PhiOp && "Invalid Operand!"); 723 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 724 725 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && 726 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg()); 727 }; 728 729 auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp, 730 MachineOperand *PhiOp) { 731 assert(PhiOp && "Invalid Operand!"); 732 assert(DominatorOp && "Invalid Operand!"); 733 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 734 MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI); 735 736 // Note: the vregs only show up at odd indices position of PHI Node, 737 // the even indices position save the BB info. 738 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 739 MachineInstr *LiMI = 740 getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 741 if (!LiMI || 742 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) 743 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) || 744 !MDT->dominates(DefDomMI, LiMI)) 745 return false; 746 } 747 748 return true; 749 }; 750 751 MachineOperand Op1 = MI.getOperand(1); 752 MachineOperand Op2 = MI.getOperand(2); 753 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2)) 754 std::swap(Op1, Op2); 755 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1)) 756 break; // We don't have an ADD fed by LI's that can be transformed 757 758 // Now we know that Op1 is the PHI node and Op2 is the dominator 759 Register DominatorReg = Op2.getReg(); 760 761 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 762 ? &PPC::G8RC_and_G8RC_NOX0RegClass 763 : &PPC::GPRC_and_GPRC_NOR0RegClass; 764 MRI->setRegClass(DominatorReg, TRC); 765 766 // replace LIs with ADDIs 767 MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); 768 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 769 MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 770 LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: "); 771 LLVM_DEBUG(LiMI->dump()); 772 773 // There could be repeated registers in the PHI, e.g: %1 = 774 // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've 775 // already replaced the def instruction, skip. 776 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) 777 continue; 778 779 assert((LiMI->getOpcode() == PPC::LI || 780 LiMI->getOpcode() == PPC::LI8) && 781 "Invalid Opcode!"); 782 auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI 783 LiMI->RemoveOperand(1); // remove the imm of LI 784 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI 785 : PPC::ADDI8)); 786 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI) 787 .addReg(DominatorReg) 788 .addImm(LiImm); // restore the imm of LI 789 LLVM_DEBUG(LiMI->dump()); 790 } 791 792 // Replace ADD with COPY 793 LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: "); 794 LLVM_DEBUG(MI.dump()); 795 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 796 MI.getOperand(0).getReg()) 797 .add(Op1); 798 ToErase = &MI; 799 Simplified = true; 800 NumOptADDLIs++; 801 break; 802 } 803 case PPC::RLDICR: { 804 Simplified |= emitRLDICWhenLoweringJumpTables(MI) || 805 combineSEXTAndSHL(MI, ToErase); 806 break; 807 } 808 } 809 } 810 811 // If the last instruction was marked for elimination, 812 // remove it now. 813 if (ToErase) { 814 ToErase->eraseFromParent(); 815 ToErase = nullptr; 816 } 817 } 818 819 // Eliminate all the TOC save instructions which are redundant. 820 Simplified |= eliminateRedundantTOCSaves(TOCSaves); 821 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 822 if (FI->mustSaveTOC()) 823 NumTOCSavesInPrologue++; 824 825 // We try to eliminate redundant compare instruction. 826 Simplified |= eliminateRedundantCompare(); 827 828 return Simplified; 829 } 830 831 // helper functions for eliminateRedundantCompare 832 static bool isEqOrNe(MachineInstr *BI) { 833 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 834 unsigned PredCond = PPC::getPredicateCondition(Pred); 835 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); 836 } 837 838 static bool isSupportedCmpOp(unsigned opCode) { 839 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 840 opCode == PPC::CMPLW || opCode == PPC::CMPW || 841 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || 842 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); 843 } 844 845 static bool is64bitCmpOp(unsigned opCode) { 846 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 847 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); 848 } 849 850 static bool isSignedCmpOp(unsigned opCode) { 851 return (opCode == PPC::CMPD || opCode == PPC::CMPW || 852 opCode == PPC::CMPDI || opCode == PPC::CMPWI); 853 } 854 855 static unsigned getSignedCmpOpCode(unsigned opCode) { 856 if (opCode == PPC::CMPLD) return PPC::CMPD; 857 if (opCode == PPC::CMPLW) return PPC::CMPW; 858 if (opCode == PPC::CMPLDI) return PPC::CMPDI; 859 if (opCode == PPC::CMPLWI) return PPC::CMPWI; 860 return opCode; 861 } 862 863 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or 864 // (LT x) to (LE x-1) 865 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) { 866 uint64_t Imm = CMPI->getOperand(2).getImm(); 867 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 868 if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000)) 869 return 0; 870 871 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 872 unsigned PredCond = PPC::getPredicateCondition(Pred); 873 unsigned PredHint = PPC::getPredicateHint(Pred); 874 if (PredCond == PPC::PRED_GE) 875 return PPC::getPredicate(PPC::PRED_GT, PredHint); 876 if (PredCond == PPC::PRED_LT) 877 return PPC::getPredicate(PPC::PRED_LE, PredHint); 878 879 return 0; 880 } 881 882 // We can increment immediate x in (GT x) by changing it to (GE x+1) or 883 // (LE x) to (LT x+1) 884 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) { 885 uint64_t Imm = CMPI->getOperand(2).getImm(); 886 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 887 if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF)) 888 return 0; 889 890 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 891 unsigned PredCond = PPC::getPredicateCondition(Pred); 892 unsigned PredHint = PPC::getPredicateHint(Pred); 893 if (PredCond == PPC::PRED_GT) 894 return PPC::getPredicate(PPC::PRED_GE, PredHint); 895 if (PredCond == PPC::PRED_LE) 896 return PPC::getPredicate(PPC::PRED_LT, PredHint); 897 898 return 0; 899 } 900 901 // This takes a Phi node and returns a register value for the specified BB. 902 static unsigned getIncomingRegForBlock(MachineInstr *Phi, 903 MachineBasicBlock *MBB) { 904 for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) { 905 MachineOperand &MO = Phi->getOperand(I); 906 if (MO.getMBB() == MBB) 907 return Phi->getOperand(I-1).getReg(); 908 } 909 llvm_unreachable("invalid src basic block for this Phi node\n"); 910 return 0; 911 } 912 913 // This function tracks the source of the register through register copy. 914 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2 915 // assuming that the control comes from BB1 into BB2. 916 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1, 917 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) { 918 unsigned SrcReg = Reg; 919 while (1) { 920 unsigned NextReg = SrcReg; 921 MachineInstr *Inst = MRI->getVRegDef(SrcReg); 922 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { 923 NextReg = getIncomingRegForBlock(Inst, BB1); 924 // We track through PHI only once to avoid infinite loop. 925 BB1 = nullptr; 926 } 927 else if (Inst->isFullCopy()) 928 NextReg = Inst->getOperand(1).getReg(); 929 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) 930 break; 931 SrcReg = NextReg; 932 } 933 return SrcReg; 934 } 935 936 static bool eligibleForCompareElimination(MachineBasicBlock &MBB, 937 MachineBasicBlock *&PredMBB, 938 MachineBasicBlock *&MBBtoMoveCmp, 939 MachineRegisterInfo *MRI) { 940 941 auto isEligibleBB = [&](MachineBasicBlock &BB) { 942 auto BII = BB.getFirstInstrTerminator(); 943 // We optimize BBs ending with a conditional branch. 944 // We check only for BCC here, not BCCLR, because BCCLR 945 // will be formed only later in the pipeline. 946 if (BB.succ_size() == 2 && 947 BII != BB.instr_end() && 948 (*BII).getOpcode() == PPC::BCC && 949 (*BII).getOperand(1).isReg()) { 950 // We optimize only if the condition code is used only by one BCC. 951 Register CndReg = (*BII).getOperand(1).getReg(); 952 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg)) 953 return false; 954 955 MachineInstr *CMPI = MRI->getVRegDef(CndReg); 956 // We assume compare and branch are in the same BB for ease of analysis. 957 if (CMPI->getParent() != &BB) 958 return false; 959 960 // We skip this BB if a physical register is used in comparison. 961 for (MachineOperand &MO : CMPI->operands()) 962 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg())) 963 return false; 964 965 return true; 966 } 967 return false; 968 }; 969 970 // If this BB has more than one successor, we can create a new BB and 971 // move the compare instruction in the new BB. 972 // So far, we do not move compare instruction to a BB having multiple 973 // successors to avoid potentially increasing code size. 974 auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) { 975 return BB.succ_size() == 1; 976 }; 977 978 if (!isEligibleBB(MBB)) 979 return false; 980 981 unsigned NumPredBBs = MBB.pred_size(); 982 if (NumPredBBs == 1) { 983 MachineBasicBlock *TmpMBB = *MBB.pred_begin(); 984 if (isEligibleBB(*TmpMBB)) { 985 PredMBB = TmpMBB; 986 MBBtoMoveCmp = nullptr; 987 return true; 988 } 989 } 990 else if (NumPredBBs == 2) { 991 // We check for partially redundant case. 992 // So far, we support cases with only two predecessors 993 // to avoid increasing the number of instructions. 994 MachineBasicBlock::pred_iterator PI = MBB.pred_begin(); 995 MachineBasicBlock *Pred1MBB = *PI; 996 MachineBasicBlock *Pred2MBB = *(PI+1); 997 998 if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) { 999 // We assume Pred1MBB is the BB containing the compare to be merged and 1000 // Pred2MBB is the BB to which we will append a compare instruction. 1001 // Hence we can proceed as is. 1002 } 1003 else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) { 1004 // We need to swap Pred1MBB and Pred2MBB to canonicalize. 1005 std::swap(Pred1MBB, Pred2MBB); 1006 } 1007 else return false; 1008 1009 // Here, Pred2MBB is the BB to which we need to append a compare inst. 1010 // We cannot move the compare instruction if operands are not available 1011 // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI). 1012 MachineInstr *BI = &*MBB.getFirstInstrTerminator(); 1013 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg()); 1014 for (int I = 1; I <= 2; I++) 1015 if (CMPI->getOperand(I).isReg()) { 1016 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg()); 1017 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) 1018 return false; 1019 } 1020 1021 PredMBB = Pred1MBB; 1022 MBBtoMoveCmp = Pred2MBB; 1023 return true; 1024 } 1025 1026 return false; 1027 } 1028 1029 // This function will iterate over the input map containing a pair of TOC save 1030 // instruction and a flag. The flag will be set to false if the TOC save is 1031 // proven redundant. This function will erase from the basic block all the TOC 1032 // saves marked as redundant. 1033 bool PPCMIPeephole::eliminateRedundantTOCSaves( 1034 std::map<MachineInstr *, bool> &TOCSaves) { 1035 bool Simplified = false; 1036 int NumKept = 0; 1037 for (auto TOCSave : TOCSaves) { 1038 if (!TOCSave.second) { 1039 TOCSave.first->eraseFromParent(); 1040 RemoveTOCSave++; 1041 Simplified = true; 1042 } else { 1043 NumKept++; 1044 } 1045 } 1046 1047 if (NumKept > 1) 1048 MultiTOCSaves++; 1049 1050 return Simplified; 1051 } 1052 1053 // If multiple conditional branches are executed based on the (essentially) 1054 // same comparison, we merge compare instructions into one and make multiple 1055 // conditional branches on this comparison. 1056 // For example, 1057 // if (a == 0) { ... } 1058 // else if (a < 0) { ... } 1059 // can be executed by one compare and two conditional branches instead of 1060 // two pairs of a compare and a conditional branch. 1061 // 1062 // This method merges two compare instructions in two MBBs and modifies the 1063 // compare and conditional branch instructions if needed. 1064 // For the above example, the input for this pass looks like: 1065 // cmplwi r3, 0 1066 // beq 0, .LBB0_3 1067 // cmpwi r3, -1 1068 // bgt 0, .LBB0_4 1069 // So, before merging two compares, we need to modify these instructions as 1070 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq 1071 // beq 0, .LBB0_3 1072 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0 1073 // bge 0, .LBB0_4 1074 1075 bool PPCMIPeephole::eliminateRedundantCompare(void) { 1076 bool Simplified = false; 1077 1078 for (MachineBasicBlock &MBB2 : *MF) { 1079 MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr; 1080 1081 // For fully redundant case, we select two basic blocks MBB1 and MBB2 1082 // as an optimization target if 1083 // - both MBBs end with a conditional branch, 1084 // - MBB1 is the only predecessor of MBB2, and 1085 // - compare does not take a physical register as a operand in both MBBs. 1086 // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr. 1087 // 1088 // As partially redundant case, we additionally handle if MBB2 has one 1089 // additional predecessor, which has only one successor (MBB2). 1090 // In this case, we move the compare instruction originally in MBB2 into 1091 // MBBtoMoveCmp. This partially redundant case is typically appear by 1092 // compiling a while loop; here, MBBtoMoveCmp is the loop preheader. 1093 // 1094 // Overview of CFG of related basic blocks 1095 // Fully redundant case Partially redundant case 1096 // -------- ---------------- -------- 1097 // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ) 1098 // -------- ---------------- -------- 1099 // | \ (w/ 1 succ) \ | \ 1100 // | \ \ | \ 1101 // | \ | 1102 // -------- -------- 1103 // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred 1104 // -------- and 2 succ) -------- and 2 succ) 1105 // | \ | \ 1106 // | \ | \ 1107 // 1108 if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI)) 1109 continue; 1110 1111 MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator(); 1112 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg()); 1113 1114 MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator(); 1115 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg()); 1116 bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr); 1117 1118 // We cannot optimize an unsupported compare opcode or 1119 // a mix of 32-bit and 64-bit comaprisons 1120 if (!isSupportedCmpOp(CMPI1->getOpcode()) || 1121 !isSupportedCmpOp(CMPI2->getOpcode()) || 1122 is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode())) 1123 continue; 1124 1125 unsigned NewOpCode = 0; 1126 unsigned NewPredicate1 = 0, NewPredicate2 = 0; 1127 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; 1128 bool SwapOperands = false; 1129 1130 if (CMPI1->getOpcode() != CMPI2->getOpcode()) { 1131 // Typically, unsigned comparison is used for equality check, but 1132 // we replace it with a signed comparison if the comparison 1133 // to be merged is a signed comparison. 1134 // In other cases of opcode mismatch, we cannot optimize this. 1135 1136 // We cannot change opcode when comparing against an immediate 1137 // if the most significant bit of the immediate is one 1138 // due to the difference in sign extension. 1139 auto CmpAgainstImmWithSignBit = [](MachineInstr *I) { 1140 if (!I->getOperand(2).isImm()) 1141 return false; 1142 int16_t Imm = (int16_t)I->getOperand(2).getImm(); 1143 return Imm < 0; 1144 }; 1145 1146 if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) && 1147 CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode())) 1148 NewOpCode = CMPI1->getOpcode(); 1149 else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) && 1150 getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode()) 1151 NewOpCode = CMPI2->getOpcode(); 1152 else continue; 1153 } 1154 1155 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { 1156 // In case of comparisons between two registers, these two registers 1157 // must be same to merge two comparisons. 1158 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1159 nullptr, nullptr, MRI); 1160 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(), 1161 nullptr, nullptr, MRI); 1162 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1163 MBB1, &MBB2, MRI); 1164 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(), 1165 MBB1, &MBB2, MRI); 1166 1167 if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) { 1168 // Same pair of registers in the same order; ready to merge as is. 1169 } 1170 else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) { 1171 // Same pair of registers in different order. 1172 // We reverse the predicate to merge compare instructions. 1173 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); 1174 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); 1175 // In case of partial redundancy, we need to swap operands 1176 // in another compare instruction. 1177 SwapOperands = true; 1178 } 1179 else continue; 1180 } 1181 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { 1182 // In case of comparisons between a register and an immediate, 1183 // the operand register must be same for two compare instructions. 1184 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1185 nullptr, nullptr, MRI); 1186 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1187 MBB1, &MBB2, MRI); 1188 if (Cmp1Operand1 != Cmp2Operand1) 1189 continue; 1190 1191 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); 1192 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm(); 1193 1194 // If immediate are not same, we try to adjust by changing predicate; 1195 // e.g. GT imm means GE (imm+1). 1196 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { 1197 int Diff = Imm1 - Imm2; 1198 if (Diff < -2 || Diff > 2) 1199 continue; 1200 1201 unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1); 1202 unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1); 1203 unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2); 1204 unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2); 1205 if (Diff == 2) { 1206 if (PredToInc2 && PredToDec1) { 1207 NewPredicate2 = PredToInc2; 1208 NewPredicate1 = PredToDec1; 1209 NewImm2++; 1210 NewImm1--; 1211 } 1212 } 1213 else if (Diff == 1) { 1214 if (PredToInc2) { 1215 NewImm2++; 1216 NewPredicate2 = PredToInc2; 1217 } 1218 else if (PredToDec1) { 1219 NewImm1--; 1220 NewPredicate1 = PredToDec1; 1221 } 1222 } 1223 else if (Diff == -1) { 1224 if (PredToDec2) { 1225 NewImm2--; 1226 NewPredicate2 = PredToDec2; 1227 } 1228 else if (PredToInc1) { 1229 NewImm1++; 1230 NewPredicate1 = PredToInc1; 1231 } 1232 } 1233 else if (Diff == -2) { 1234 if (PredToDec2 && PredToInc1) { 1235 NewPredicate2 = PredToDec2; 1236 NewPredicate1 = PredToInc1; 1237 NewImm2--; 1238 NewImm1++; 1239 } 1240 } 1241 } 1242 1243 // We cannot merge two compares if the immediates are not same. 1244 if (NewImm2 != NewImm1) 1245 continue; 1246 } 1247 1248 LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); 1249 LLVM_DEBUG(CMPI1->dump()); 1250 LLVM_DEBUG(BI1->dump()); 1251 LLVM_DEBUG(CMPI2->dump()); 1252 LLVM_DEBUG(BI2->dump()); 1253 1254 // We adjust opcode, predicates and immediate as we determined above. 1255 if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) { 1256 CMPI1->setDesc(TII->get(NewOpCode)); 1257 } 1258 if (NewPredicate1) { 1259 BI1->getOperand(0).setImm(NewPredicate1); 1260 } 1261 if (NewPredicate2) { 1262 BI2->getOperand(0).setImm(NewPredicate2); 1263 } 1264 if (NewImm1 != Imm1) { 1265 CMPI1->getOperand(2).setImm(NewImm1); 1266 } 1267 1268 if (IsPartiallyRedundant) { 1269 // We touch up the compare instruction in MBB2 and move it to 1270 // a previous BB to handle partially redundant case. 1271 if (SwapOperands) { 1272 Register Op1 = CMPI2->getOperand(1).getReg(); 1273 Register Op2 = CMPI2->getOperand(2).getReg(); 1274 CMPI2->getOperand(1).setReg(Op2); 1275 CMPI2->getOperand(2).setReg(Op1); 1276 } 1277 if (NewImm2 != Imm2) 1278 CMPI2->getOperand(2).setImm(NewImm2); 1279 1280 for (int I = 1; I <= 2; I++) { 1281 if (CMPI2->getOperand(I).isReg()) { 1282 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg()); 1283 if (Inst->getParent() != &MBB2) 1284 continue; 1285 1286 assert(Inst->getOpcode() == PPC::PHI && 1287 "We cannot support if an operand comes from this BB."); 1288 unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp); 1289 CMPI2->getOperand(I).setReg(SrcReg); 1290 } 1291 } 1292 auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator()); 1293 MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2)); 1294 1295 DebugLoc DL = CMPI2->getDebugLoc(); 1296 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); 1297 BuildMI(MBB2, MBB2.begin(), DL, 1298 TII->get(PPC::PHI), NewVReg) 1299 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1) 1300 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp); 1301 BI2->getOperand(1).setReg(NewVReg); 1302 } 1303 else { 1304 // We finally eliminate compare instruction in MBB2. 1305 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); 1306 CMPI2->eraseFromParent(); 1307 } 1308 BI2->getOperand(1).setIsKill(true); 1309 BI1->getOperand(1).setIsKill(false); 1310 1311 LLVM_DEBUG(dbgs() << "into a compare and two branches:\n"); 1312 LLVM_DEBUG(CMPI1->dump()); 1313 LLVM_DEBUG(BI1->dump()); 1314 LLVM_DEBUG(BI2->dump()); 1315 if (IsPartiallyRedundant) { 1316 LLVM_DEBUG(dbgs() << "The following compare is moved into " 1317 << printMBBReference(*MBBtoMoveCmp) 1318 << " to handle partial redundancy.\n"); 1319 LLVM_DEBUG(CMPI2->dump()); 1320 } 1321 1322 Simplified = true; 1323 } 1324 1325 return Simplified; 1326 } 1327 1328 // We miss the opportunity to emit an RLDIC when lowering jump tables 1329 // since ISEL sees only a single basic block. When selecting, the clear 1330 // and shift left will be in different blocks. 1331 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) { 1332 if (MI.getOpcode() != PPC::RLDICR) 1333 return false; 1334 1335 Register SrcReg = MI.getOperand(1).getReg(); 1336 if (!Register::isVirtualRegister(SrcReg)) 1337 return false; 1338 1339 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1340 if (SrcMI->getOpcode() != PPC::RLDICL) 1341 return false; 1342 1343 MachineOperand MOpSHSrc = SrcMI->getOperand(2); 1344 MachineOperand MOpMBSrc = SrcMI->getOperand(3); 1345 MachineOperand MOpSHMI = MI.getOperand(2); 1346 MachineOperand MOpMEMI = MI.getOperand(3); 1347 if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() && 1348 MOpMEMI.isImm())) 1349 return false; 1350 1351 uint64_t SHSrc = MOpSHSrc.getImm(); 1352 uint64_t MBSrc = MOpMBSrc.getImm(); 1353 uint64_t SHMI = MOpSHMI.getImm(); 1354 uint64_t MEMI = MOpMEMI.getImm(); 1355 uint64_t NewSH = SHSrc + SHMI; 1356 uint64_t NewMB = MBSrc - SHMI; 1357 if (NewMB > 63 || NewSH > 63) 1358 return false; 1359 1360 // The bits cleared with RLDICL are [0, MBSrc). 1361 // The bits cleared with RLDICR are (MEMI, 63]. 1362 // After the sequence, the bits cleared are: 1363 // [0, MBSrc-SHMI) and (MEMI, 63). 1364 // 1365 // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63]. 1366 if ((63 - NewSH) != MEMI) 1367 return false; 1368 1369 LLVM_DEBUG(dbgs() << "Converting pair: "); 1370 LLVM_DEBUG(SrcMI->dump()); 1371 LLVM_DEBUG(MI.dump()); 1372 1373 MI.setDesc(TII->get(PPC::RLDIC)); 1374 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 1375 MI.getOperand(2).setImm(NewSH); 1376 MI.getOperand(3).setImm(NewMB); 1377 1378 LLVM_DEBUG(dbgs() << "To: "); 1379 LLVM_DEBUG(MI.dump()); 1380 NumRotatesCollapsed++; 1381 return true; 1382 } 1383 1384 // For case in LLVM IR 1385 // entry: 1386 // %iconv = sext i32 %index to i64 1387 // br i1 undef label %true, label %false 1388 // true: 1389 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv 1390 // ... 1391 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in 1392 // different BBs when conducting instruction selection. We can do a peephole 1393 // optimization to combine these two instructions into extswsli after 1394 // instruction selection. 1395 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI, 1396 MachineInstr *&ToErase) { 1397 if (MI.getOpcode() != PPC::RLDICR) 1398 return false; 1399 1400 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0()) 1401 return false; 1402 1403 assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands"); 1404 1405 MachineOperand MOpSHMI = MI.getOperand(2); 1406 MachineOperand MOpMEMI = MI.getOperand(3); 1407 if (!(MOpSHMI.isImm() && MOpMEMI.isImm())) 1408 return false; 1409 1410 uint64_t SHMI = MOpSHMI.getImm(); 1411 uint64_t MEMI = MOpMEMI.getImm(); 1412 if (SHMI + MEMI != 63) 1413 return false; 1414 1415 Register SrcReg = MI.getOperand(1).getReg(); 1416 if (!Register::isVirtualRegister(SrcReg)) 1417 return false; 1418 1419 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1420 if (SrcMI->getOpcode() != PPC::EXTSW && 1421 SrcMI->getOpcode() != PPC::EXTSW_32_64) 1422 return false; 1423 1424 // If the register defined by extsw has more than one use, combination is not 1425 // needed. 1426 if (!MRI->hasOneNonDBGUse(SrcReg)) 1427 return false; 1428 1429 assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands"); 1430 assert(SrcMI->getOperand(1).isReg() && 1431 "EXTSW's second operand should be a register"); 1432 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) 1433 return false; 1434 1435 LLVM_DEBUG(dbgs() << "Combining pair: "); 1436 LLVM_DEBUG(SrcMI->dump()); 1437 LLVM_DEBUG(MI.dump()); 1438 1439 MachineInstr *NewInstr = 1440 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), 1441 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) 1442 : TII->get(PPC::EXTSWSLI_32_64), 1443 MI.getOperand(0).getReg()) 1444 .add(SrcMI->getOperand(1)) 1445 .add(MOpSHMI); 1446 (void)NewInstr; 1447 1448 LLVM_DEBUG(dbgs() << "TO: "); 1449 LLVM_DEBUG(NewInstr->dump()); 1450 ++NumEXTSWAndSLDICombined; 1451 ToErase = &MI; 1452 // SrcMI, which is extsw, is of no use now, erase it. 1453 SrcMI->eraseFromParent(); 1454 return true; 1455 } 1456 1457 } // end default namespace 1458 1459 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, 1460 "PowerPC MI Peephole Optimization", false, false) 1461 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) 1462 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 1463 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) 1464 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE, 1465 "PowerPC MI Peephole Optimization", false, false) 1466 1467 char PPCMIPeephole::ID = 0; 1468 FunctionPass* 1469 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); } 1470 1471