xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrVSX.td (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the VSX extension to the PowerPC instruction set.
10//
11//===----------------------------------------------------------------------===//
12
13// *********************************** NOTE ***********************************
14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing  **
15// ** which VMX and VSX instructions are lane-sensitive and which are not.   **
16// ** A lane-sensitive instruction relies, implicitly or explicitly, on      **
17// ** whether lanes are numbered from left to right.  An instruction like    **
18// ** VADDFP is not lane-sensitive, because each lane of the result vector   **
19// ** relies only on the corresponding lane of the source vectors.  However, **
20// ** an instruction like VMULESB is lane-sensitive, because "even" and      **
21// ** "odd" lanes are different for big-endian and little-endian numbering.  **
22// **                                                                        **
23// ** When adding new VMX and VSX instructions, please consider whether they **
24// ** are lane-sensitive.  If so, they must be added to a switch statement   **
25// ** in PPCVSXSwapRemoval::gatherVectorInstructions().                      **
26// ****************************************************************************
27
28// *********************************** NOTE ***********************************
29// ** When adding new anonymous patterns to this file, please add them to    **
30// ** the section titled Anonymous Patterns. Chances are that the existing   **
31// ** predicate blocks already contain a combination of features that you    **
32// ** are after. There is a list of blocks at the top of the section. If     **
33// ** you definitely need a new combination of predicates, please add that   **
34// ** combination to the list.                                               **
35// ** File Structure:                                                        **
36// ** - Custom PPCISD node definitions                                       **
37// ** - Predicate definitions: predicates to specify the subtargets for      **
38// **   which an instruction or pattern can be emitted.                      **
39// ** - Instruction formats: classes instantiated by the instructions.       **
40// **   These generally correspond to instruction formats in section 1.6 of  **
41// **   the ISA document.                                                    **
42// ** - Instruction definitions: the actual definitions of the instructions  **
43// **   often including input patterns that they match.                      **
44// ** - Helper DAG definitions: We define a number of dag objects to use as  **
45// **   input or output patterns for consciseness of the code.               **
46// ** - Anonymous patterns: input patterns that an instruction matches can   **
47// **   often not be specified as part of the instruction definition, so an  **
48// **   anonymous pattern must be specified mapping an input pattern to an   **
49// **   output pattern. These are generally guarded by subtarget predicates. **
50// ** - Instruction aliases: used to define extended mnemonics for assembly  **
51// **   printing (for example: xxswapd for xxpermdi with 0x2 as the imm).    **
52// ****************************************************************************
53
54def PPCRegVSRCAsmOperand : AsmOperandClass {
55  let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
56}
57def vsrc : RegisterOperand<VSRC> {
58  let ParserMatchClass = PPCRegVSRCAsmOperand;
59}
60
61def PPCRegVSFRCAsmOperand : AsmOperandClass {
62  let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";
63}
64def vsfrc : RegisterOperand<VSFRC> {
65  let ParserMatchClass = PPCRegVSFRCAsmOperand;
66}
67
68def PPCRegVSSRCAsmOperand : AsmOperandClass {
69  let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber";
70}
71def vssrc : RegisterOperand<VSSRC> {
72  let ParserMatchClass = PPCRegVSSRCAsmOperand;
73}
74
75def PPCRegSPILLTOVSRRCAsmOperand : AsmOperandClass {
76  let Name = "RegSPILLTOVSRRC"; let PredicateMethod = "isVSRegNumber";
77}
78
79def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> {
80  let ParserMatchClass = PPCRegSPILLTOVSRRCAsmOperand;
81}
82
83def SDT_PPCldvsxlh : SDTypeProfile<1, 1, [
84  SDTCisVT<0, v4f32>, SDTCisPtrTy<1>
85]>;
86
87def SDT_PPCfpexth : SDTypeProfile<1, 2, [
88  SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2>
89]>;
90
91def SDT_PPCldsplat : SDTypeProfile<1, 1, [
92  SDTCisVec<0>, SDTCisPtrTy<1>
93]>;
94
95// Little-endian-specific nodes.
96def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
97  SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
98]>;
99def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
100  SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
101]>;
102def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
103  SDTCisSameAs<0, 1>
104]>;
105def SDTVecConv : SDTypeProfile<1, 2, [
106  SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>
107]>;
108def SDTVabsd : SDTypeProfile<1, 3, [
109  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
110]>;
111def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
112  SDTCisVec<0>, SDTCisPtrTy<1>
113]>;
114def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
115  SDTCisVec<0>, SDTCisPtrTy<1>
116]>;
117
118//--------------------------- Custom PPC nodes -------------------------------//
119def PPClxvd2x  : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
120                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
122                        [SDNPHasChain, SDNPMayStore]>;
123def PPCld_vec_be  : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be,
124                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
125def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
126                        [SDNPHasChain, SDNPMayStore]>;
127def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
128def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
129def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
130def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
131def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>;
132def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>;
133def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>;
134def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>;
135
136def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>;
137def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh,
138                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,
140                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED",
142                     SDTypeProfile<1, 1, []>, []>;
143
144//-------------------------- Predicate definitions ---------------------------//
145def HasVSX : Predicate<"Subtarget->hasVSX()">;
146def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
147def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
148def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
149def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
150def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
151def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
152def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
153def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
154
155//--------------------- VSX-specific instruction formats ---------------------//
156// By default, all VSX instructions are to be selected over their Altivec
157// counter parts and they do not have unmodeled sideeffects.
158let AddedComplexity = 400, hasSideEffects = 0 in {
159multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase,
160                    string asmstr, InstrItinClass itin, Intrinsic Int,
161                    ValueType OutTy, ValueType InTy> {
162  let BaseName = asmbase in {
163    def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
164                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
165                       [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>;
166    let Defs = [CR6] in
167    def _rec    : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
168                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
169                       [(set InTy:$XT,
170                                (InTy (PPCvcmp_o InTy:$XA, InTy:$XB, xo)))]>,
171                       isRecordForm;
172  }
173}
174
175// Instruction form with a single input register for instructions such as
176// XXPERMDI. The reason for defining this is that specifying multiple chained
177// operands (such as loads) to an instruction will perform both chained
178// operations rather than coalescing them into a single register - even though
179// the source memory location is the same. This simply forces the instruction
180// to use the same register for both inputs.
181// For example, an output DAG such as this:
182//   (XXPERMDI (LXSIBZX xoaddr:$src), (LXSIBZX xoaddr:$src ), 0))
183// would result in two load instructions emitted and used as separate inputs
184// to the XXPERMDI instruction.
185class XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
186                 InstrItinClass itin, list<dag> pattern>
187  : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
188    let XB = XA;
189}
190
191let Predicates = [HasVSX, HasP9Vector] in {
192class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
193                    list<dag> pattern>
194  : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
195                  !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
196
197// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
198class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
199                       list<dag> pattern>
200  : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm;
201
202// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),
203// So we use different operand class for VRB
204class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
205                         RegisterOperand vbtype, list<dag> pattern>
206  : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
207                  !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
208
209// [PO VRT XO VRB XO /]
210class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
211                    list<dag> pattern>
212  : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB),
213                  !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
214
215// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
216class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
217                       list<dag> pattern>
218  : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm;
219
220// [PO T XO B XO BX /]
221class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
222                      list<dag> pattern>
223  : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
224                    !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
225
226// [PO T XO B XO BX TX]
227class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
228                      RegisterOperand vtype, list<dag> pattern>
229  : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB),
230                    !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;
231
232// [PO T A B XO AX BX TX], src and dest register use different operand class
233class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,
234                RegisterOperand xty, RegisterOperand aty, RegisterOperand bty,
235                InstrItinClass itin, list<dag> pattern>
236  : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
237            !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
238
239// [PO VRT VRA VRB XO /]
240class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
241                    list<dag> pattern>
242  : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
243            !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>;
244
245// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
246class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,
247                       list<dag> pattern>
248  : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm;
249
250// [PO VRT VRA VRB XO /]
251class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,
252                        list<dag> pattern>
253  : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB),
254            !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>,
255            RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">;
256
257// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
258class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,
259                        list<dag> pattern>
260  : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm;
261
262class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
263                              list<dag> pattern>
264  : Z23Form_8<opcode, xo,
265              (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
266              !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
267  let RC = ex;
268}
269
270// [PO BF // VRA VRB XO /]
271class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
272                    list<dag> pattern>
273  : XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB),
274             !strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> {
275  let Pattern = pattern;
276}
277
278// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different
279// "out" and "in" dag
280class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
281                    RegisterOperand vtype, list<dag> pattern>
282  : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src),
283            !strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>;
284
285// [PO S RA RB XO SX]
286class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
287                    RegisterOperand vtype, list<dag> pattern>
288  : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst),
289            !strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>;
290} // Predicates = HasP9Vector
291} // AddedComplexity = 400, hasSideEffects = 0
292
293multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> {
294  def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>;
295  def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>;
296}
297
298//-------------------------- Instruction definitions -------------------------//
299// VSX instructions require the VSX feature, they are to be selected over
300// equivalent Altivec patterns (as they address a larger register set) and
301// they do not have unmodeled side effects.
302let Predicates = [HasVSX], AddedComplexity = 400 in {
303let hasSideEffects = 0 in {
304
305  // Load indexed instructions
306  let mayLoad = 1, mayStore = 0 in {
307    let CodeSize = 3 in
308    def LXSDX : XX1Form_memOp<31, 588,
309                        (outs vsfrc:$XT), (ins memrr:$src),
310                        "lxsdx $XT, $src", IIC_LdStLFD,
311                        []>;
312
313    // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
314    let CodeSize = 3 in
315      def XFLOADf64  : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
316                              "#XFLOADf64",
317                              [(set f64:$XT, (load xoaddr:$src))]>;
318
319    let Predicates = [HasVSX, HasOnlySwappingMemOps] in
320    def LXVD2X : XX1Form_memOp<31, 844,
321                         (outs vsrc:$XT), (ins memrr:$src),
322                         "lxvd2x $XT, $src", IIC_LdStLFD,
323                         [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
324
325    def LXVDSX : XX1Form_memOp<31, 332,
326                         (outs vsrc:$XT), (ins memrr:$src),
327                         "lxvdsx $XT, $src", IIC_LdStLFD, []>;
328
329    let Predicates = [HasVSX, HasOnlySwappingMemOps] in
330    def LXVW4X : XX1Form_memOp<31, 780,
331                         (outs vsrc:$XT), (ins memrr:$src),
332                         "lxvw4x $XT, $src", IIC_LdStLFD,
333                         []>;
334  } // mayLoad
335
336  // Store indexed instructions
337  let mayStore = 1, mayLoad = 0 in {
338    let CodeSize = 3 in
339    def STXSDX : XX1Form_memOp<31, 716,
340                        (outs), (ins vsfrc:$XT, memrr:$dst),
341                        "stxsdx $XT, $dst", IIC_LdStSTFD,
342                        []>;
343
344    // Pseudo instruction XFSTOREf64  will be expanded to STXSDX or STFDX later
345    let CodeSize = 3 in
346      def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
347                              "#XFSTOREf64",
348                              [(store f64:$XT, xoaddr:$dst)]>;
349
350    let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
351    // The behaviour of this instruction is endianness-specific so we provide no
352    // pattern to match it without considering endianness.
353    def STXVD2X : XX1Form_memOp<31, 972,
354                         (outs), (ins vsrc:$XT, memrr:$dst),
355                         "stxvd2x $XT, $dst", IIC_LdStSTFD,
356                         []>;
357
358    def STXVW4X : XX1Form_memOp<31, 908,
359                         (outs), (ins vsrc:$XT, memrr:$dst),
360                         "stxvw4x $XT, $dst", IIC_LdStSTFD,
361                         []>;
362    }
363  } // mayStore
364
365  let Uses = [RM], mayRaiseFPException = 1 in {
366  // Add/Mul Instructions
367  let isCommutable = 1 in {
368    def XSADDDP : XX3Form<60, 32,
369                          (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
370                          "xsadddp $XT, $XA, $XB", IIC_VecFP,
371                          [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>;
372    def XSMULDP : XX3Form<60, 48,
373                          (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
374                          "xsmuldp $XT, $XA, $XB", IIC_VecFP,
375                          [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>;
376
377    def XVADDDP : XX3Form<60, 96,
378                          (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
379                          "xvadddp $XT, $XA, $XB", IIC_VecFP,
380                          [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>;
381
382    def XVADDSP : XX3Form<60, 64,
383                          (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
384                          "xvaddsp $XT, $XA, $XB", IIC_VecFP,
385                          [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>;
386
387    def XVMULDP : XX3Form<60, 112,
388                          (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
389                          "xvmuldp $XT, $XA, $XB", IIC_VecFP,
390                          [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>;
391
392    def XVMULSP : XX3Form<60, 80,
393                          (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
394                          "xvmulsp $XT, $XA, $XB", IIC_VecFP,
395                          [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>;
396  }
397
398  // Subtract Instructions
399  def XSSUBDP : XX3Form<60, 40,
400                        (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
401                        "xssubdp $XT, $XA, $XB", IIC_VecFP,
402                        [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>;
403
404  def XVSUBDP : XX3Form<60, 104,
405                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
406                        "xvsubdp $XT, $XA, $XB", IIC_VecFP,
407                        [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>;
408  def XVSUBSP : XX3Form<60, 72,
409                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
410                        "xvsubsp $XT, $XA, $XB", IIC_VecFP,
411                        [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>;
412
413  // FMA Instructions
414  let BaseName = "XSMADDADP" in {
415  let isCommutable = 1 in
416  def XSMADDADP : XX3Form<60, 33,
417                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
418                          "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
419                          [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
420                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
421                          AltVSXFMARel;
422  let IsVSXFMAAlt = 1 in
423  def XSMADDMDP : XX3Form<60, 41,
424                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
425                          "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
426                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
427                          AltVSXFMARel;
428  }
429
430  let BaseName = "XSMSUBADP" in {
431  let isCommutable = 1 in
432  def XSMSUBADP : XX3Form<60, 49,
433                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
434                          "xsmsubadp $XT, $XA, $XB", IIC_VecFP,
435                          [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
436                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
437                          AltVSXFMARel;
438  let IsVSXFMAAlt = 1 in
439  def XSMSUBMDP : XX3Form<60, 57,
440                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
441                          "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
442                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
443                          AltVSXFMARel;
444  }
445
446  let BaseName = "XSNMADDADP" in {
447  let isCommutable = 1 in
448  def XSNMADDADP : XX3Form<60, 161,
449                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
450                          "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
451                          [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
452                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
453                          AltVSXFMARel;
454  let IsVSXFMAAlt = 1 in
455  def XSNMADDMDP : XX3Form<60, 169,
456                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
457                          "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
458                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
459                          AltVSXFMARel;
460  }
461
462  let BaseName = "XSNMSUBADP" in {
463  let isCommutable = 1 in
464  def XSNMSUBADP : XX3Form<60, 177,
465                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
466                          "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
467                          [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
468                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
469                          AltVSXFMARel;
470  let IsVSXFMAAlt = 1 in
471  def XSNMSUBMDP : XX3Form<60, 185,
472                          (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
473                          "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
474                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
475                          AltVSXFMARel;
476  }
477
478  let BaseName = "XVMADDADP" in {
479  let isCommutable = 1 in
480  def XVMADDADP : XX3Form<60, 97,
481                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
482                          "xvmaddadp $XT, $XA, $XB", IIC_VecFP,
483                          [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
484                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
485                          AltVSXFMARel;
486  let IsVSXFMAAlt = 1 in
487  def XVMADDMDP : XX3Form<60, 105,
488                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
489                          "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
490                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
491                          AltVSXFMARel;
492  }
493
494  let BaseName = "XVMADDASP" in {
495  let isCommutable = 1 in
496  def XVMADDASP : XX3Form<60, 65,
497                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
498                          "xvmaddasp $XT, $XA, $XB", IIC_VecFP,
499                          [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
500                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
501                          AltVSXFMARel;
502  let IsVSXFMAAlt = 1 in
503  def XVMADDMSP : XX3Form<60, 73,
504                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
505                          "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
506                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
507                          AltVSXFMARel;
508  }
509
510  let BaseName = "XVMSUBADP" in {
511  let isCommutable = 1 in
512  def XVMSUBADP : XX3Form<60, 113,
513                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
514                          "xvmsubadp $XT, $XA, $XB", IIC_VecFP,
515                          [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
516                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
517                          AltVSXFMARel;
518  let IsVSXFMAAlt = 1 in
519  def XVMSUBMDP : XX3Form<60, 121,
520                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
521                          "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
522                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
523                          AltVSXFMARel;
524  }
525
526  let BaseName = "XVMSUBASP" in {
527  let isCommutable = 1 in
528  def XVMSUBASP : XX3Form<60, 81,
529                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
530                          "xvmsubasp $XT, $XA, $XB", IIC_VecFP,
531                          [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
532                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
533                          AltVSXFMARel;
534  let IsVSXFMAAlt = 1 in
535  def XVMSUBMSP : XX3Form<60, 89,
536                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
537                          "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
538                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
539                          AltVSXFMARel;
540  }
541
542  let BaseName = "XVNMADDADP" in {
543  let isCommutable = 1 in
544  def XVNMADDADP : XX3Form<60, 225,
545                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
546                          "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
547                          [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
548                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
549                          AltVSXFMARel;
550  let IsVSXFMAAlt = 1 in
551  def XVNMADDMDP : XX3Form<60, 233,
552                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
553                          "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
554                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
555                          AltVSXFMARel;
556  }
557
558  let BaseName = "XVNMADDASP" in {
559  let isCommutable = 1 in
560  def XVNMADDASP : XX3Form<60, 193,
561                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
562                          "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
563                          [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
564                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
565                          AltVSXFMARel;
566  let IsVSXFMAAlt = 1 in
567  def XVNMADDMSP : XX3Form<60, 201,
568                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
569                          "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
570                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
571                          AltVSXFMARel;
572  }
573
574  let BaseName = "XVNMSUBADP" in {
575  let isCommutable = 1 in
576  def XVNMSUBADP : XX3Form<60, 241,
577                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
578                          "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
579                          [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
580                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
581                          AltVSXFMARel;
582  let IsVSXFMAAlt = 1 in
583  def XVNMSUBMDP : XX3Form<60, 249,
584                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
585                          "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
586                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
587                          AltVSXFMARel;
588  }
589
590  let BaseName = "XVNMSUBASP" in {
591  let isCommutable = 1 in
592  def XVNMSUBASP : XX3Form<60, 209,
593                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
594                          "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
595                          [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
596                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
597                          AltVSXFMARel;
598  let IsVSXFMAAlt = 1 in
599  def XVNMSUBMSP : XX3Form<60, 217,
600                          (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
601                          "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
602                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
603                          AltVSXFMARel;
604  }
605
606  // Division Instructions
607  def XSDIVDP : XX3Form<60, 56,
608                        (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
609                        "xsdivdp $XT, $XA, $XB", IIC_FPDivD,
610                        [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>;
611  def XSSQRTDP : XX2Form<60, 75,
612                        (outs vsfrc:$XT), (ins vsfrc:$XB),
613                        "xssqrtdp $XT, $XB", IIC_FPSqrtD,
614                        [(set f64:$XT, (any_fsqrt f64:$XB))]>;
615
616  def XSREDP : XX2Form<60, 90,
617                        (outs vsfrc:$XT), (ins vsfrc:$XB),
618                        "xsredp $XT, $XB", IIC_VecFP,
619                        [(set f64:$XT, (PPCfre f64:$XB))]>;
620  def XSRSQRTEDP : XX2Form<60, 74,
621                           (outs vsfrc:$XT), (ins vsfrc:$XB),
622                           "xsrsqrtedp $XT, $XB", IIC_VecFP,
623                           [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
624
625  def XSTDIVDP : XX3Form_1<60, 61,
626                         (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
627                         "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
628  def XSTSQRTDP : XX2Form_1<60, 106,
629                          (outs crrc:$crD), (ins vsfrc:$XB),
630                          "xstsqrtdp $crD, $XB", IIC_FPCompare, []>;
631
632  def XVDIVDP : XX3Form<60, 120,
633                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
634                        "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
635                        [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>;
636  def XVDIVSP : XX3Form<60, 88,
637                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
638                        "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
639                        [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>;
640
641  def XVSQRTDP : XX2Form<60, 203,
642                        (outs vsrc:$XT), (ins vsrc:$XB),
643                        "xvsqrtdp $XT, $XB", IIC_FPSqrtD,
644                        [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>;
645  def XVSQRTSP : XX2Form<60, 139,
646                        (outs vsrc:$XT), (ins vsrc:$XB),
647                        "xvsqrtsp $XT, $XB", IIC_FPSqrtS,
648                        [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>;
649
650  def XVTDIVDP : XX3Form_1<60, 125,
651                         (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
652                         "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
653  def XVTDIVSP : XX3Form_1<60, 93,
654                         (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
655                         "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
656
657  def XVTSQRTDP : XX2Form_1<60, 234,
658                          (outs crrc:$crD), (ins vsrc:$XB),
659                          "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>;
660  def XVTSQRTSP : XX2Form_1<60, 170,
661                          (outs crrc:$crD), (ins vsrc:$XB),
662                          "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>;
663
664  def XVREDP : XX2Form<60, 218,
665                        (outs vsrc:$XT), (ins vsrc:$XB),
666                        "xvredp $XT, $XB", IIC_VecFP,
667                        [(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
668  def XVRESP : XX2Form<60, 154,
669                        (outs vsrc:$XT), (ins vsrc:$XB),
670                        "xvresp $XT, $XB", IIC_VecFP,
671                        [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
672
673  def XVRSQRTEDP : XX2Form<60, 202,
674                           (outs vsrc:$XT), (ins vsrc:$XB),
675                           "xvrsqrtedp $XT, $XB", IIC_VecFP,
676                           [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
677  def XVRSQRTESP : XX2Form<60, 138,
678                           (outs vsrc:$XT), (ins vsrc:$XB),
679                           "xvrsqrtesp $XT, $XB", IIC_VecFP,
680                           [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
681
682  // Compare Instructions
683  def XSCMPODP : XX3Form_1<60, 43,
684                           (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
685                           "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>;
686  def XSCMPUDP : XX3Form_1<60, 35,
687                           (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
688                           "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
689
690  defm XVCMPEQDP : XX3Form_Rcr<60, 99,
691                             "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
692                             int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
693  defm XVCMPEQSP : XX3Form_Rcr<60, 67,
694                             "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
695                             int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;
696  defm XVCMPGEDP : XX3Form_Rcr<60, 115,
697                             "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare,
698                             int_ppc_vsx_xvcmpgedp, v2i64, v2f64>;
699  defm XVCMPGESP : XX3Form_Rcr<60, 83,
700                             "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare,
701                             int_ppc_vsx_xvcmpgesp, v4i32, v4f32>;
702  defm XVCMPGTDP : XX3Form_Rcr<60, 107,
703                             "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare,
704                             int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>;
705  defm XVCMPGTSP : XX3Form_Rcr<60, 75,
706                             "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare,
707                             int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>;
708
709  // Move Instructions
710  def XSABSDP : XX2Form<60, 345,
711                      (outs vsfrc:$XT), (ins vsfrc:$XB),
712                      "xsabsdp $XT, $XB", IIC_VecFP,
713                      [(set f64:$XT, (fabs f64:$XB))]>;
714  def XSNABSDP : XX2Form<60, 361,
715                      (outs vsfrc:$XT), (ins vsfrc:$XB),
716                      "xsnabsdp $XT, $XB", IIC_VecFP,
717                      [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
718  def XSNEGDP : XX2Form<60, 377,
719                      (outs vsfrc:$XT), (ins vsfrc:$XB),
720                      "xsnegdp $XT, $XB", IIC_VecFP,
721                      [(set f64:$XT, (fneg f64:$XB))]>;
722  def XSCPSGNDP : XX3Form<60, 176,
723                      (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
724                      "xscpsgndp $XT, $XA, $XB", IIC_VecFP,
725                      [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
726
727  def XVABSDP : XX2Form<60, 473,
728                      (outs vsrc:$XT), (ins vsrc:$XB),
729                      "xvabsdp $XT, $XB", IIC_VecFP,
730                      [(set v2f64:$XT, (fabs v2f64:$XB))]>;
731
732  def XVABSSP : XX2Form<60, 409,
733                      (outs vsrc:$XT), (ins vsrc:$XB),
734                      "xvabssp $XT, $XB", IIC_VecFP,
735                      [(set v4f32:$XT, (fabs v4f32:$XB))]>;
736
737  def XVCPSGNDP : XX3Form<60, 240,
738                      (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
739                      "xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
740                      [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
741  def XVCPSGNSP : XX3Form<60, 208,
742                      (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
743                      "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
744                      [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
745
746  def XVNABSDP : XX2Form<60, 489,
747                      (outs vsrc:$XT), (ins vsrc:$XB),
748                      "xvnabsdp $XT, $XB", IIC_VecFP,
749                      [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
750  def XVNABSSP : XX2Form<60, 425,
751                      (outs vsrc:$XT), (ins vsrc:$XB),
752                      "xvnabssp $XT, $XB", IIC_VecFP,
753                      [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
754
755  def XVNEGDP : XX2Form<60, 505,
756                      (outs vsrc:$XT), (ins vsrc:$XB),
757                      "xvnegdp $XT, $XB", IIC_VecFP,
758                      [(set v2f64:$XT, (fneg v2f64:$XB))]>;
759  def XVNEGSP : XX2Form<60, 441,
760                      (outs vsrc:$XT), (ins vsrc:$XB),
761                      "xvnegsp $XT, $XB", IIC_VecFP,
762                      [(set v4f32:$XT, (fneg v4f32:$XB))]>;
763
764  // Conversion Instructions
765  def XSCVDPSP : XX2Form<60, 265,
766                      (outs vsfrc:$XT), (ins vsfrc:$XB),
767                      "xscvdpsp $XT, $XB", IIC_VecFP, []>;
768  def XSCVDPSXDS : XX2Form<60, 344,
769                      (outs vsfrc:$XT), (ins vsfrc:$XB),
770                      "xscvdpsxds $XT, $XB", IIC_VecFP,
771                      [(set f64:$XT, (PPCfctidz f64:$XB))]>;
772  let isCodeGenOnly = 1 in
773  def XSCVDPSXDSs : XX2Form<60, 344,
774                      (outs vssrc:$XT), (ins vssrc:$XB),
775                      "xscvdpsxds $XT, $XB", IIC_VecFP,
776                      [(set f32:$XT, (PPCfctidz f32:$XB))]>;
777  def XSCVDPSXWS : XX2Form<60, 88,
778                      (outs vsfrc:$XT), (ins vsfrc:$XB),
779                      "xscvdpsxws $XT, $XB", IIC_VecFP,
780                      [(set f64:$XT, (PPCfctiwz f64:$XB))]>;
781  let isCodeGenOnly = 1 in
782  def XSCVDPSXWSs : XX2Form<60, 88,
783                      (outs vssrc:$XT), (ins vssrc:$XB),
784                      "xscvdpsxws $XT, $XB", IIC_VecFP,
785                      [(set f32:$XT, (PPCfctiwz f32:$XB))]>;
786  def XSCVDPUXDS : XX2Form<60, 328,
787                      (outs vsfrc:$XT), (ins vsfrc:$XB),
788                      "xscvdpuxds $XT, $XB", IIC_VecFP,
789                      [(set f64:$XT, (PPCfctiduz f64:$XB))]>;
790  let isCodeGenOnly = 1 in
791  def XSCVDPUXDSs : XX2Form<60, 328,
792                      (outs vssrc:$XT), (ins vssrc:$XB),
793                      "xscvdpuxds $XT, $XB", IIC_VecFP,
794                      [(set f32:$XT, (PPCfctiduz f32:$XB))]>;
795  def XSCVDPUXWS : XX2Form<60, 72,
796                      (outs vsfrc:$XT), (ins vsfrc:$XB),
797                      "xscvdpuxws $XT, $XB", IIC_VecFP,
798                      [(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
799  let isCodeGenOnly = 1 in
800  def XSCVDPUXWSs : XX2Form<60, 72,
801                      (outs vssrc:$XT), (ins vssrc:$XB),
802                      "xscvdpuxws $XT, $XB", IIC_VecFP,
803                      [(set f32:$XT, (PPCfctiwuz f32:$XB))]>;
804  def XSCVSPDP : XX2Form<60, 329,
805                      (outs vsfrc:$XT), (ins vsfrc:$XB),
806                      "xscvspdp $XT, $XB", IIC_VecFP, []>;
807  def XSCVSXDDP : XX2Form<60, 376,
808                      (outs vsfrc:$XT), (ins vsfrc:$XB),
809                      "xscvsxddp $XT, $XB", IIC_VecFP,
810                      [(set f64:$XT, (PPCfcfid f64:$XB))]>;
811  def XSCVUXDDP : XX2Form<60, 360,
812                      (outs vsfrc:$XT), (ins vsfrc:$XB),
813                      "xscvuxddp $XT, $XB", IIC_VecFP,
814                      [(set f64:$XT, (PPCfcfidu f64:$XB))]>;
815
816  def XVCVDPSP : XX2Form<60, 393,
817                      (outs vsrc:$XT), (ins vsrc:$XB),
818                      "xvcvdpsp $XT, $XB", IIC_VecFP,
819                      [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
820  def XVCVDPSXDS : XX2Form<60, 472,
821                      (outs vsrc:$XT), (ins vsrc:$XB),
822                      "xvcvdpsxds $XT, $XB", IIC_VecFP,
823                      [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
824  def XVCVDPSXWS : XX2Form<60, 216,
825                      (outs vsrc:$XT), (ins vsrc:$XB),
826                      "xvcvdpsxws $XT, $XB", IIC_VecFP,
827                      [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
828  def XVCVDPUXDS : XX2Form<60, 456,
829                      (outs vsrc:$XT), (ins vsrc:$XB),
830                      "xvcvdpuxds $XT, $XB", IIC_VecFP,
831                      [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
832  def XVCVDPUXWS : XX2Form<60, 200,
833                      (outs vsrc:$XT), (ins vsrc:$XB),
834                      "xvcvdpuxws $XT, $XB", IIC_VecFP,
835                      [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
836
837  def XVCVSPDP : XX2Form<60, 457,
838                      (outs vsrc:$XT), (ins vsrc:$XB),
839                      "xvcvspdp $XT, $XB", IIC_VecFP,
840                      [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;
841  def XVCVSPSXDS : XX2Form<60, 408,
842                      (outs vsrc:$XT), (ins vsrc:$XB),
843                      "xvcvspsxds $XT, $XB", IIC_VecFP, []>;
844  def XVCVSPSXWS : XX2Form<60, 152,
845                      (outs vsrc:$XT), (ins vsrc:$XB),
846                      "xvcvspsxws $XT, $XB", IIC_VecFP,
847                      [(set v4i32:$XT, (fp_to_sint v4f32:$XB))]>;
848  def XVCVSPUXDS : XX2Form<60, 392,
849                      (outs vsrc:$XT), (ins vsrc:$XB),
850                      "xvcvspuxds $XT, $XB", IIC_VecFP, []>;
851  def XVCVSPUXWS : XX2Form<60, 136,
852                      (outs vsrc:$XT), (ins vsrc:$XB),
853                      "xvcvspuxws $XT, $XB", IIC_VecFP,
854                      [(set v4i32:$XT, (fp_to_uint v4f32:$XB))]>;
855  def XVCVSXDDP : XX2Form<60, 504,
856                      (outs vsrc:$XT), (ins vsrc:$XB),
857                      "xvcvsxddp $XT, $XB", IIC_VecFP,
858                      [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
859  def XVCVSXDSP : XX2Form<60, 440,
860                      (outs vsrc:$XT), (ins vsrc:$XB),
861                      "xvcvsxdsp $XT, $XB", IIC_VecFP,
862                      [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;
863  def XVCVSXWDP : XX2Form<60, 248,
864                      (outs vsrc:$XT), (ins vsrc:$XB),
865                      "xvcvsxwdp $XT, $XB", IIC_VecFP,
866                      [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
867  def XVCVSXWSP : XX2Form<60, 184,
868                      (outs vsrc:$XT), (ins vsrc:$XB),
869                      "xvcvsxwsp $XT, $XB", IIC_VecFP,
870                      [(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>;
871  def XVCVUXDDP : XX2Form<60, 488,
872                      (outs vsrc:$XT), (ins vsrc:$XB),
873                      "xvcvuxddp $XT, $XB", IIC_VecFP,
874                      [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
875  def XVCVUXDSP : XX2Form<60, 424,
876                      (outs vsrc:$XT), (ins vsrc:$XB),
877                      "xvcvuxdsp $XT, $XB", IIC_VecFP,
878                      [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;
879  def XVCVUXWDP : XX2Form<60, 232,
880                      (outs vsrc:$XT), (ins vsrc:$XB),
881                      "xvcvuxwdp $XT, $XB", IIC_VecFP,
882                      [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
883  def XVCVUXWSP : XX2Form<60, 168,
884                      (outs vsrc:$XT), (ins vsrc:$XB),
885                      "xvcvuxwsp $XT, $XB", IIC_VecFP,
886                      [(set v4f32:$XT, (uint_to_fp v4i32:$XB))]>;
887
888  // Rounding Instructions
889  def XSRDPI : XX2Form<60, 73,
890                      (outs vsfrc:$XT), (ins vsfrc:$XB),
891                      "xsrdpi $XT, $XB", IIC_VecFP,
892                      [(set f64:$XT, (any_fround f64:$XB))]>;
893  def XSRDPIC : XX2Form<60, 107,
894                      (outs vsfrc:$XT), (ins vsfrc:$XB),
895                      "xsrdpic $XT, $XB", IIC_VecFP,
896                      [(set f64:$XT, (any_fnearbyint f64:$XB))]>;
897  def XSRDPIM : XX2Form<60, 121,
898                      (outs vsfrc:$XT), (ins vsfrc:$XB),
899                      "xsrdpim $XT, $XB", IIC_VecFP,
900                      [(set f64:$XT, (any_ffloor f64:$XB))]>;
901  def XSRDPIP : XX2Form<60, 105,
902                      (outs vsfrc:$XT), (ins vsfrc:$XB),
903                      "xsrdpip $XT, $XB", IIC_VecFP,
904                      [(set f64:$XT, (any_fceil f64:$XB))]>;
905  def XSRDPIZ : XX2Form<60, 89,
906                      (outs vsfrc:$XT), (ins vsfrc:$XB),
907                      "xsrdpiz $XT, $XB", IIC_VecFP,
908                      [(set f64:$XT, (any_ftrunc f64:$XB))]>;
909
910  def XVRDPI : XX2Form<60, 201,
911                      (outs vsrc:$XT), (ins vsrc:$XB),
912                      "xvrdpi $XT, $XB", IIC_VecFP,
913                      [(set v2f64:$XT, (any_fround v2f64:$XB))]>;
914  def XVRDPIC : XX2Form<60, 235,
915                      (outs vsrc:$XT), (ins vsrc:$XB),
916                      "xvrdpic $XT, $XB", IIC_VecFP,
917                      [(set v2f64:$XT, (any_fnearbyint v2f64:$XB))]>;
918  def XVRDPIM : XX2Form<60, 249,
919                      (outs vsrc:$XT), (ins vsrc:$XB),
920                      "xvrdpim $XT, $XB", IIC_VecFP,
921                      [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>;
922  def XVRDPIP : XX2Form<60, 233,
923                      (outs vsrc:$XT), (ins vsrc:$XB),
924                      "xvrdpip $XT, $XB", IIC_VecFP,
925                      [(set v2f64:$XT, (any_fceil v2f64:$XB))]>;
926  def XVRDPIZ : XX2Form<60, 217,
927                      (outs vsrc:$XT), (ins vsrc:$XB),
928                      "xvrdpiz $XT, $XB", IIC_VecFP,
929                      [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>;
930
931  def XVRSPI : XX2Form<60, 137,
932                      (outs vsrc:$XT), (ins vsrc:$XB),
933                      "xvrspi $XT, $XB", IIC_VecFP,
934                      [(set v4f32:$XT, (any_fround v4f32:$XB))]>;
935  def XVRSPIC : XX2Form<60, 171,
936                      (outs vsrc:$XT), (ins vsrc:$XB),
937                      "xvrspic $XT, $XB", IIC_VecFP,
938                      [(set v4f32:$XT, (any_fnearbyint v4f32:$XB))]>;
939  def XVRSPIM : XX2Form<60, 185,
940                      (outs vsrc:$XT), (ins vsrc:$XB),
941                      "xvrspim $XT, $XB", IIC_VecFP,
942                      [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>;
943  def XVRSPIP : XX2Form<60, 169,
944                      (outs vsrc:$XT), (ins vsrc:$XB),
945                      "xvrspip $XT, $XB", IIC_VecFP,
946                      [(set v4f32:$XT, (any_fceil v4f32:$XB))]>;
947  def XVRSPIZ : XX2Form<60, 153,
948                      (outs vsrc:$XT), (ins vsrc:$XB),
949                      "xvrspiz $XT, $XB", IIC_VecFP,
950                      [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>;
951
952  // Max/Min Instructions
953  let isCommutable = 1 in {
954  def XSMAXDP : XX3Form<60, 160,
955                        (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
956                        "xsmaxdp $XT, $XA, $XB", IIC_VecFP,
957                        [(set vsfrc:$XT,
958                              (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
959  def XSMINDP : XX3Form<60, 168,
960                        (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
961                        "xsmindp $XT, $XA, $XB", IIC_VecFP,
962                        [(set vsfrc:$XT,
963                              (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;
964
965  def XVMAXDP : XX3Form<60, 224,
966                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
967                        "xvmaxdp $XT, $XA, $XB", IIC_VecFP,
968                        [(set vsrc:$XT,
969                              (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;
970  def XVMINDP : XX3Form<60, 232,
971                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
972                        "xvmindp $XT, $XA, $XB", IIC_VecFP,
973                        [(set vsrc:$XT,
974                              (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;
975
976  def XVMAXSP : XX3Form<60, 192,
977                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
978                        "xvmaxsp $XT, $XA, $XB", IIC_VecFP,
979                        [(set vsrc:$XT,
980                              (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;
981  def XVMINSP : XX3Form<60, 200,
982                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
983                        "xvminsp $XT, $XA, $XB", IIC_VecFP,
984                        [(set vsrc:$XT,
985                              (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;
986  } // isCommutable
987  } // Uses = [RM], mayRaiseFPException
988
989  // Logical Instructions
990  let isCommutable = 1 in
991  def XXLAND : XX3Form<60, 130,
992                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
993                       "xxland $XT, $XA, $XB", IIC_VecGeneral,
994                       [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
995  def XXLANDC : XX3Form<60, 138,
996                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
997                        "xxlandc $XT, $XA, $XB", IIC_VecGeneral,
998                        [(set v4i32:$XT, (and v4i32:$XA,
999                                              (vnot_ppc v4i32:$XB)))]>;
1000  let isCommutable = 1 in {
1001  def XXLNOR : XX3Form<60, 162,
1002                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1003                       "xxlnor $XT, $XA, $XB", IIC_VecGeneral,
1004                       [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
1005                                                   v4i32:$XB)))]>;
1006  def XXLOR : XX3Form<60, 146,
1007                      (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1008                      "xxlor $XT, $XA, $XB", IIC_VecGeneral,
1009                      [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
1010  let isCodeGenOnly = 1 in
1011  def XXLORf: XX3Form<60, 146,
1012                      (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
1013                      "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
1014  def XXLXOR : XX3Form<60, 154,
1015                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1016                       "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
1017                       [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
1018  } // isCommutable
1019
1020  let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
1021      isReMaterializable = 1 in {
1022    def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins),
1023                       "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
1024                       [(set v4i32:$XT, (v4i32 immAllZerosV))]>;
1025    def XXLXORdpz : XX3Form_SameOp<60, 154,
1026                         (outs vsfrc:$XT), (ins),
1027                         "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
1028                         [(set f64:$XT, (fpimm0))]>;
1029    def XXLXORspz : XX3Form_SameOp<60, 154,
1030                         (outs vssrc:$XT), (ins),
1031                         "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
1032                         [(set f32:$XT, (fpimm0))]>;
1033  }
1034
1035  // Permutation Instructions
1036  def XXMRGHW : XX3Form<60, 18,
1037                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1038                       "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
1039  def XXMRGLW : XX3Form<60, 50,
1040                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1041                       "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
1042
1043  def XXPERMDI : XX3Form_2<60, 10,
1044                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
1045                       "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm,
1046                       [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
1047                         imm32SExt16:$DM))]>;
1048  let isCodeGenOnly = 1 in
1049  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
1050                             "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
1051  def XXSEL : XX4Form<60, 3,
1052                      (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
1053                      "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
1054
1055  def XXSLDWI : XX3Form_2<60, 2,
1056                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
1057                       "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm,
1058                       [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB,
1059                                                  imm32SExt16:$SHW))]>;
1060
1061  let isCodeGenOnly = 1 in
1062  def XXSLDWIs : XX3Form_2s<60, 2,
1063                       (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW),
1064                       "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>;
1065
1066  def XXSPLTW : XX2Form_2<60, 164,
1067                       (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
1068                       "xxspltw $XT, $XB, $UIM", IIC_VecPerm,
1069                       [(set v4i32:$XT,
1070                             (PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>;
1071  let isCodeGenOnly = 1 in
1072  def XXSPLTWs : XX2Form_2<60, 164,
1073                       (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM),
1074                       "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
1075
1076// The following VSX instructions were introduced in Power ISA 2.07
1077let Predicates = [HasVSX, HasP8Vector] in {
1078  let isCommutable = 1 in {
1079    def XXLEQV : XX3Form<60, 186,
1080                         (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1081                         "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
1082                         [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
1083    def XXLNAND : XX3Form<60, 178,
1084                          (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1085                          "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
1086                          [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
1087                                                    v4i32:$XB)))]>;
1088  } // isCommutable
1089
1090  let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
1091      isReMaterializable = 1 in {
1092    def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
1093                         "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
1094                         [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;
1095  }
1096
1097  def XXLORC : XX3Form<60, 170,
1098                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1099                       "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
1100                       [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
1101
1102  // VSX scalar loads introduced in ISA 2.07
1103  let mayLoad = 1, mayStore = 0 in {
1104    let CodeSize = 3 in
1105    def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src),
1106                         "lxsspx $XT, $src", IIC_LdStLFD, []>;
1107    def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
1108                          "lxsiwax $XT, $src", IIC_LdStLFD, []>;
1109    def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
1110                          "lxsiwzx $XT, $src", IIC_LdStLFD, []>;
1111
1112    // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later
1113    let CodeSize = 3 in
1114    def XFLOADf32  : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src),
1115                            "#XFLOADf32",
1116                            [(set f32:$XT, (load xoaddr:$src))]>;
1117    // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later
1118    def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
1119                       "#LIWAX",
1120                       [(set f64:$XT, (PPClfiwax xoaddr:$src))]>;
1121    // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later
1122    def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
1123                       "#LIWZX",
1124                       [(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
1125  } // mayLoad
1126
1127  // VSX scalar stores introduced in ISA 2.07
1128  let mayStore = 1, mayLoad = 0 in {
1129    let CodeSize = 3 in
1130    def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
1131                          "stxsspx $XT, $dst", IIC_LdStSTFD, []>;
1132    def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
1133                          "stxsiwx $XT, $dst", IIC_LdStSTFD, []>;
1134
1135    // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later
1136    let CodeSize = 3 in
1137    def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst),
1138                            "#XFSTOREf32",
1139                            [(store f32:$XT, xoaddr:$dst)]>;
1140    // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later
1141    def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
1142                       "#STIWX",
1143                      [(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
1144  } // mayStore
1145
1146  // VSX Elementary Scalar FP arithmetic (SP)
1147  let mayRaiseFPException = 1 in {
1148  let isCommutable = 1 in {
1149    def XSADDSP : XX3Form<60, 0,
1150                          (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1151                          "xsaddsp $XT, $XA, $XB", IIC_VecFP,
1152                          [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>;
1153    def XSMULSP : XX3Form<60, 16,
1154                          (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1155                          "xsmulsp $XT, $XA, $XB", IIC_VecFP,
1156                          [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>;
1157  } // isCommutable
1158
1159  def XSSUBSP : XX3Form<60, 8,
1160                        (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1161                        "xssubsp $XT, $XA, $XB", IIC_VecFP,
1162                        [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>;
1163  def XSDIVSP : XX3Form<60, 24,
1164                        (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1165                        "xsdivsp $XT, $XA, $XB", IIC_FPDivS,
1166                        [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>;
1167
1168  def XSRESP : XX2Form<60, 26,
1169                        (outs vssrc:$XT), (ins vssrc:$XB),
1170                        "xsresp $XT, $XB", IIC_VecFP,
1171                        [(set f32:$XT, (PPCfre f32:$XB))]>;
1172  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1173  let hasSideEffects = 1, mayRaiseFPException = 1 in
1174  def XSRSP : XX2Form<60, 281,
1175                        (outs vssrc:$XT), (ins vsfrc:$XB),
1176                        "xsrsp $XT, $XB", IIC_VecFP,
1177                        [(set f32:$XT, (any_fpround f64:$XB))]>;
1178  def XSSQRTSP : XX2Form<60, 11,
1179                        (outs vssrc:$XT), (ins vssrc:$XB),
1180                        "xssqrtsp $XT, $XB", IIC_FPSqrtS,
1181                        [(set f32:$XT, (any_fsqrt f32:$XB))]>;
1182  def XSRSQRTESP : XX2Form<60, 10,
1183                           (outs vssrc:$XT), (ins vssrc:$XB),
1184                           "xsrsqrtesp $XT, $XB", IIC_VecFP,
1185                           [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
1186
1187  // FMA Instructions
1188  let BaseName = "XSMADDASP" in {
1189  let isCommutable = 1 in
1190  def XSMADDASP : XX3Form<60, 1,
1191                          (outs vssrc:$XT),
1192                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1193                          "xsmaddasp $XT, $XA, $XB", IIC_VecFP,
1194                          [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>,
1195                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1196                          AltVSXFMARel;
1197  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1198  let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1199  def XSMADDMSP : XX3Form<60, 9,
1200                          (outs vssrc:$XT),
1201                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1202                          "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1203                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1204                          AltVSXFMARel;
1205  }
1206
1207  let BaseName = "XSMSUBASP" in {
1208  let isCommutable = 1 in
1209  def XSMSUBASP : XX3Form<60, 17,
1210                          (outs vssrc:$XT),
1211                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1212                          "xsmsubasp $XT, $XA, $XB", IIC_VecFP,
1213                          [(set f32:$XT, (any_fma f32:$XA, f32:$XB,
1214                                              (fneg f32:$XTi)))]>,
1215                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1216                          AltVSXFMARel;
1217  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1218  let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1219  def XSMSUBMSP : XX3Form<60, 25,
1220                          (outs vssrc:$XT),
1221                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1222                          "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1223                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1224                          AltVSXFMARel;
1225  }
1226
1227  let BaseName = "XSNMADDASP" in {
1228  let isCommutable = 1 in
1229  def XSNMADDASP : XX3Form<60, 129,
1230                          (outs vssrc:$XT),
1231                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1232                          "xsnmaddasp $XT, $XA, $XB", IIC_VecFP,
1233                          [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
1234                                                    f32:$XTi)))]>,
1235                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1236                          AltVSXFMARel;
1237  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1238  let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1239  def XSNMADDMSP : XX3Form<60, 137,
1240                          (outs vssrc:$XT),
1241                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1242                          "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1243                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1244                          AltVSXFMARel;
1245  }
1246
1247  let BaseName = "XSNMSUBASP" in {
1248  let isCommutable = 1 in
1249  def XSNMSUBASP : XX3Form<60, 145,
1250                          (outs vssrc:$XT),
1251                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1252                          "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
1253                          [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
1254                                                    (fneg f32:$XTi))))]>,
1255                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1256                          AltVSXFMARel;
1257  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1258  let IsVSXFMAAlt = 1, hasSideEffects = 1 in
1259  def XSNMSUBMSP : XX3Form<60, 153,
1260                          (outs vssrc:$XT),
1261                          (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1262                          "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1263                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1264                          AltVSXFMARel;
1265  }
1266
1267  // Single Precision Conversions (FP <-> INT)
1268  def XSCVSXDSP : XX2Form<60, 312,
1269                      (outs vssrc:$XT), (ins vsfrc:$XB),
1270                      "xscvsxdsp $XT, $XB", IIC_VecFP,
1271                      [(set f32:$XT, (PPCfcfids f64:$XB))]>;
1272  def XSCVUXDSP : XX2Form<60, 296,
1273                      (outs vssrc:$XT), (ins vsfrc:$XB),
1274                      "xscvuxdsp $XT, $XB", IIC_VecFP,
1275                      [(set f32:$XT, (PPCfcfidus f64:$XB))]>;
1276
1277  // Conversions between vector and scalar single precision
1278  def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
1279                          "xscvdpspn $XT, $XB", IIC_VecFP, []>;
1280  def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
1281                          "xscvspdpn $XT, $XB", IIC_VecFP, []>;
1282  } // mayRaiseFPException
1283
1284  let Predicates = [HasVSX, HasDirectMove] in {
1285  // VSX direct move instructions
1286  def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1287                              "mfvsrd $rA, $XT", IIC_VecGeneral,
1288                              [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1289      Requires<[In64BitMode]>;
1290  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1291  let isCodeGenOnly = 1, hasSideEffects = 1 in
1292  def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT),
1293                             "mfvsrd $rA, $XT", IIC_VecGeneral,
1294                             []>,
1295      Requires<[In64BitMode]>;
1296  def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1297                               "mfvsrwz $rA, $XT", IIC_VecGeneral,
1298                               [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1299  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1300  let isCodeGenOnly = 1, hasSideEffects = 1 in
1301  def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
1302                               "mfvsrwz $rA, $XT", IIC_VecGeneral,
1303                               []>;
1304  def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
1305                              "mtvsrd $XT, $rA", IIC_VecGeneral,
1306                              [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1307      Requires<[In64BitMode]>;
1308  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1309  let isCodeGenOnly = 1, hasSideEffects = 1 in
1310  def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA),
1311                              "mtvsrd $XT, $rA", IIC_VecGeneral,
1312                              []>,
1313      Requires<[In64BitMode]>;
1314  def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
1315                               "mtvsrwa $XT, $rA", IIC_VecGeneral,
1316                               [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
1317  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1318  let isCodeGenOnly = 1, hasSideEffects = 1 in
1319  def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA),
1320                               "mtvsrwa $XT, $rA", IIC_VecGeneral,
1321                               []>;
1322  def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
1323                               "mtvsrwz $XT, $rA", IIC_VecGeneral,
1324                               [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
1325  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1326  let isCodeGenOnly = 1, hasSideEffects = 1 in
1327  def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA),
1328                               "mtvsrwz $XT, $rA", IIC_VecGeneral,
1329                               []>;
1330  } // HasDirectMove
1331
1332} // HasVSX, HasP8Vector
1333
1334let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in {
1335def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
1336                            "mtvsrws $XT, $rA", IIC_VecGeneral, []>;
1337
1338def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB),
1339                     "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
1340                     []>, Requires<[In64BitMode]>;
1341
1342def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
1343                            "mfvsrld $rA, $XT", IIC_VecGeneral,
1344                            []>, Requires<[In64BitMode]>;
1345
1346} // HasVSX, IsISA3_0, HasDirectMove
1347
1348let Predicates = [HasVSX, HasP9Vector] in {
1349  // Quad-Precision Scalar Move Instructions:
1350  // Copy Sign
1351  def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp",
1352                                [(set f128:$vT,
1353                                      (fcopysign f128:$vB, f128:$vA))]>;
1354
1355  // Absolute/Negative-Absolute/Negate
1356  def XSABSQP   : X_VT5_XO5_VB5<63,  0, 804, "xsabsqp",
1357                                [(set f128:$vT, (fabs f128:$vB))]>;
1358  def XSNABSQP  : X_VT5_XO5_VB5<63,  8, 804, "xsnabsqp",
1359                                [(set f128:$vT, (fneg (fabs f128:$vB)))]>;
1360  def XSNEGQP   : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp",
1361                                [(set f128:$vT, (fneg f128:$vB))]>;
1362
1363  //===--------------------------------------------------------------------===//
1364  // Quad-Precision Scalar Floating-Point Arithmetic Instructions:
1365
1366  // Add/Divide/Multiply/Subtract
1367  let mayRaiseFPException = 1 in {
1368  let isCommutable = 1 in {
1369  def XSADDQP   : X_VT5_VA5_VB5   <63,   4, "xsaddqp",
1370                                   [(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>;
1371  def XSMULQP   : X_VT5_VA5_VB5   <63,  36, "xsmulqp",
1372                                   [(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>;
1373  }
1374  def XSSUBQP   : X_VT5_VA5_VB5   <63, 516, "xssubqp" ,
1375                                   [(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>;
1376  def XSDIVQP   : X_VT5_VA5_VB5   <63, 548, "xsdivqp",
1377                                   [(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>;
1378  // Square-Root
1379  def XSSQRTQP  : X_VT5_XO5_VB5   <63, 27, 804, "xssqrtqp",
1380                                   [(set f128:$vT, (any_fsqrt f128:$vB))]>;
1381  // (Negative) Multiply-{Add/Subtract}
1382  def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp",
1383                                    [(set f128:$vT,
1384                                          (any_fma f128:$vA, f128:$vB, f128:$vTi))]>;
1385  def XSMSUBQP  : X_VT5_VA5_VB5_FMA   <63, 420, "xsmsubqp"  ,
1386                                       [(set f128:$vT,
1387                                             (any_fma f128:$vA, f128:$vB,
1388                                                      (fneg f128:$vTi)))]>;
1389  def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp",
1390                                     [(set f128:$vT,
1391                                           (fneg (any_fma f128:$vA, f128:$vB,
1392                                                          f128:$vTi)))]>;
1393  def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp",
1394                                     [(set f128:$vT,
1395                                           (fneg (any_fma f128:$vA, f128:$vB,
1396                                                          (fneg f128:$vTi))))]>;
1397
1398  let isCommutable = 1 in {
1399  def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo",
1400                                  [(set f128:$vT,
1401                                  (int_ppc_addf128_round_to_odd
1402                                  f128:$vA, f128:$vB))]>;
1403  def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo",
1404                                  [(set f128:$vT,
1405                                  (int_ppc_mulf128_round_to_odd
1406                                  f128:$vA, f128:$vB))]>;
1407  }
1408  def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo",
1409                                  [(set f128:$vT,
1410                                  (int_ppc_subf128_round_to_odd
1411                                  f128:$vA, f128:$vB))]>;
1412  def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo",
1413                                  [(set f128:$vT,
1414                                  (int_ppc_divf128_round_to_odd
1415                                  f128:$vA, f128:$vB))]>;
1416  def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo",
1417                                  [(set f128:$vT,
1418                                  (int_ppc_sqrtf128_round_to_odd f128:$vB))]>;
1419
1420
1421  def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo",
1422                                      [(set f128:$vT,
1423                                      (int_ppc_fmaf128_round_to_odd
1424                                      f128:$vA,f128:$vB,f128:$vTi))]>;
1425
1426  def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" ,
1427                                      [(set f128:$vT,
1428                                      (int_ppc_fmaf128_round_to_odd
1429                                      f128:$vA, f128:$vB, (fneg f128:$vTi)))]>;
1430  def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo",
1431                                      [(set f128:$vT,
1432                                      (fneg (int_ppc_fmaf128_round_to_odd
1433                                      f128:$vA, f128:$vB, f128:$vTi)))]>;
1434  def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo",
1435                                      [(set f128:$vT,
1436                                      (fneg (int_ppc_fmaf128_round_to_odd
1437                                      f128:$vA, f128:$vB, (fneg f128:$vTi))))]>;
1438  } // mayRaiseFPException
1439
1440  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1441  // QP Compare Ordered/Unordered
1442  let hasSideEffects = 1 in {
1443    def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>;
1444    def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>;
1445
1446    // DP/QP Compare Exponents
1447    def XSCMPEXPDP : XX3Form_1<60, 59,
1448                               (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
1449                               "xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>;
1450    def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>;
1451
1452    // DP Compare ==, >=, >, !=
1453    // Use vsrc for XT, because the entire register of XT is set.
1454    // XT.dword[1] = 0x0000_0000_0000_0000
1455    def XSCMPEQDP : XX3_XT5_XA5_XB5<60,  3, "xscmpeqdp", vsrc, vsfrc, vsfrc,
1456                                    IIC_FPCompare, []>;
1457    def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
1458                                    IIC_FPCompare, []>;
1459    def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
1460                                    IIC_FPCompare, []>;
1461  }
1462
1463  //===--------------------------------------------------------------------===//
1464  // Quad-Precision Floating-Point Conversion Instructions:
1465
1466  let mayRaiseFPException = 1 in {
1467    // Convert DP -> QP
1468    def XSCVDPQP  : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc,
1469                                       [(set f128:$vT, (any_fpextend f64:$vB))]>;
1470
1471    // Round & Convert QP -> DP (dword[1] is set to zero)
1472    def XSCVQPDP  : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
1473    def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",
1474                                          [(set f64:$vT,
1475                                          (int_ppc_truncf128_round_to_odd
1476                                          f128:$vB))]>;
1477  }
1478
1479  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1480  // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
1481  let hasSideEffects = 1 in {
1482    def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
1483    def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
1484    def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
1485    def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz", []>;
1486  }
1487
1488  // Convert (Un)Signed DWord -> QP.
1489  def XSCVSDQP  : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
1490  def XSCVUDQP  : X_VT5_XO5_VB5_TyVB<63,  2, 836, "xscvudqp", vfrc, []>;
1491
1492  // (Round &) Convert DP <-> HP
1493  // Note! xscvdphp's src and dest register both use the left 64 bits, so we use
1494  // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits,
1495  // but we still use vsfrc for it.
1496  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1497  let hasSideEffects = 1 in {
1498    def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>;
1499    def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>;
1500  }
1501
1502  // Vector HP -> SP
1503  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1504  let hasSideEffects = 1 in
1505  def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>;
1506  def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc,
1507                                 [(set v4f32:$XT,
1508                                     (int_ppc_vsx_xvcvsphp v4f32:$XB))]>;
1509
1510  let mayRaiseFPException = 1 in {
1511    // Round to Quad-Precision Integer [with Inexact]
1512    def XSRQPI   : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 0, "xsrqpi" , []>;
1513    def XSRQPIX  : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 1, "xsrqpix", []>;
1514  }
1515
1516  // Round Quad-Precision to Double-Extended Precision (fp80)
1517  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1518  let hasSideEffects = 1 in
1519  def XSRQPXP  : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
1520
1521  //===--------------------------------------------------------------------===//
1522  // Insert/Extract Instructions
1523
1524  // Insert Exponent DP/QP
1525  // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU
1526  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1527  let hasSideEffects = 1 in {
1528    def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
1529                            "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
1530    // vB NOTE: only vB.dword[0] is used, that's why we don't use
1531    //          X_VT5_VA5_VB5 form
1532    def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB),
1533                            "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
1534  }
1535
1536  // Extract Exponent/Significand DP/QP
1537  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1538  let hasSideEffects = 1 in {
1539    def XSXEXPDP : XX2_RT5_XO5_XB6<60,  0, 347, "xsxexpdp", []>;
1540    def XSXSIGDP : XX2_RT5_XO5_XB6<60,  1, 347, "xsxsigdp", []>;
1541
1542    def XSXEXPQP : X_VT5_XO5_VB5  <63,  2, 804, "xsxexpqp", []>;
1543    def XSXSIGQP : X_VT5_XO5_VB5  <63, 18, 804, "xsxsigqp", []>;
1544  }
1545
1546  // Vector Insert Word
1547  // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB.
1548  def XXINSERTW   :
1549    XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT),
1550                     (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM),
1551                     "xxinsertw $XT, $XB, $UIM", IIC_VecFP,
1552                     [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB,
1553                                                   imm32SExt16:$UIM))]>,
1554                     RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1555
1556  // Vector Extract Unsigned Word
1557  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1558  let hasSideEffects = 1 in
1559  def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
1560                                  (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM),
1561                                  "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
1562
1563  // Vector Insert Exponent DP/SP
1564  def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
1565    IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>;
1566  def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
1567    IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;
1568
1569  // Vector Extract Exponent/Significand DP/SP
1570  def XVXEXPDP : XX2_XT6_XO5_XB6<60,  0, 475, "xvxexpdp", vsrc,
1571                                 [(set v2i64: $XT,
1572                                  (int_ppc_vsx_xvxexpdp v2f64:$XB))]>;
1573  def XVXEXPSP : XX2_XT6_XO5_XB6<60,  8, 475, "xvxexpsp", vsrc,
1574                                 [(set v4i32: $XT,
1575                                  (int_ppc_vsx_xvxexpsp v4f32:$XB))]>;
1576  def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", vsrc,
1577                                 [(set v2i64: $XT,
1578                                  (int_ppc_vsx_xvxsigdp v2f64:$XB))]>;
1579  def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", vsrc,
1580                                 [(set v4i32: $XT,
1581                                  (int_ppc_vsx_xvxsigsp v4f32:$XB))]>;
1582
1583  // Test Data Class SP/DP/QP
1584  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1585  let hasSideEffects = 1 in {
1586    def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
1587                                (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
1588                                "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
1589    def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
1590                                (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
1591                                "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
1592    def XSTSTDCQP : X_BF3_DCMX7_RS5  <63, 708,
1593                                (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
1594                                "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
1595  }
1596
1597  // Vector Test Data Class SP/DP
1598  def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
1599                              (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
1600                              "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
1601                              [(set v4i32: $XT,
1602                               (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>;
1603  def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
1604                              (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
1605                              "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,
1606                              [(set v2i64: $XT,
1607                               (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>;
1608
1609  // Maximum/Minimum Type-C/Type-J DP
1610  def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc,
1611                                 IIC_VecFP,
1612                                 [(set f64:$XT, (PPCxsmaxc f64:$XA, f64:$XB))]>;
1613  def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc,
1614                                 IIC_VecFP,
1615                                 [(set f64:$XT, (PPCxsminc f64:$XA, f64:$XB))]>;
1616
1617  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1618  let hasSideEffects = 1 in {
1619    def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
1620                                   IIC_VecFP, []>;
1621    def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
1622                                   IIC_VecFP, []>;
1623  }
1624
1625  // Vector Byte-Reverse H/W/D/Q Word
1626  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1627  let hasSideEffects = 1 in
1628  def XXBRH : XX2_XT6_XO5_XB6<60,  7, 475, "xxbrh", vsrc, []>;
1629  def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc,
1630    [(set v4i32:$XT, (bswap v4i32:$XB))]>;
1631  def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc,
1632    [(set v2i64:$XT, (bswap v2i64:$XB))]>;
1633  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1634  let hasSideEffects = 1 in
1635  def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
1636
1637  // Vector Permute
1638  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1639  let hasSideEffects = 1 in {
1640    def XXPERM  : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
1641                                  IIC_VecPerm, []>;
1642    def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
1643                                  IIC_VecPerm, []>;
1644  }
1645
1646  // Vector Splat Immediate Byte
1647  // FIXME: Setting the hasSideEffects flag here to match current behaviour.
1648  let hasSideEffects = 1 in
1649  def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
1650                            "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
1651
1652  // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
1653  // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
1654  let mayLoad = 1, mayStore = 0 in {
1655  // Load Vector
1656  def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
1657                            "lxv $XT, $src", IIC_LdStLFD, []>;
1658  // Load DWord
1659  def LXSD  : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src),
1660                       "lxsd $vD, $src", IIC_LdStLFD, []>;
1661  // Load SP from src, convert it to DP, and place in dword[0]
1662  def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src),
1663                       "lxssp $vD, $src", IIC_LdStLFD, []>;
1664
1665  // Load as Integer Byte/Halfword & Zero Indexed
1666  def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc,
1667                              [(set f64:$XT, (PPClxsizx xoaddr:$src, 1))]>;
1668  def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc,
1669                              [(set f64:$XT, (PPClxsizx xoaddr:$src, 2))]>;
1670
1671  // Load Vector Halfword*8/Byte*16 Indexed
1672  def LXVH8X  : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>;
1673  def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>;
1674
1675  // Load Vector Indexed
1676  def LXVX    : X_XT6_RA5_RB5<31, 268, "lxvx"   , vsrc,
1677                [(set v2f64:$XT, (load xaddrX16:$src))]>;
1678  // Load Vector (Left-justified) with Length
1679  def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
1680                   "lxvl $XT, $src, $rB", IIC_LdStLoad,
1681                   [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>;
1682  def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
1683                   "lxvll $XT, $src, $rB", IIC_LdStLoad,
1684                   [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>;
1685
1686  // Load Vector Word & Splat Indexed
1687  def LXVWSX  : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
1688  } // mayLoad
1689
1690  // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
1691  // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
1692  let mayStore = 1, mayLoad = 0 in {
1693  // Store Vector
1694  def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
1695                             "stxv $XT, $dst", IIC_LdStSTFD, []>;
1696  // Store DWord
1697  def STXSD  : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst),
1698                        "stxsd $vS, $dst", IIC_LdStSTFD, []>;
1699  // Convert DP of dword[0] to SP, and Store to dst
1700  def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst),
1701                        "stxssp $vS, $dst", IIC_LdStSTFD, []>;
1702
1703  // Store as Integer Byte/Halfword Indexed
1704  def STXSIBX  : X_XS6_RA5_RB5<31,  909, "stxsibx" , vsfrc,
1705                               [(PPCstxsix f64:$XT, xoaddr:$dst, 1)]>;
1706  def STXSIHX  : X_XS6_RA5_RB5<31,  941, "stxsihx" , vsfrc,
1707                               [(PPCstxsix f64:$XT, xoaddr:$dst, 2)]>;
1708  let isCodeGenOnly = 1 in {
1709    def STXSIBXv  : X_XS6_RA5_RB5<31,  909, "stxsibx" , vsrc, []>;
1710    def STXSIHXv  : X_XS6_RA5_RB5<31,  941, "stxsihx" , vsrc, []>;
1711  }
1712
1713  // Store Vector Halfword*8/Byte*16 Indexed
1714  def STXVH8X  : X_XS6_RA5_RB5<31,  940, "stxvh8x" , vsrc, []>;
1715  def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>;
1716
1717  // Store Vector Indexed
1718  def STXVX    : X_XS6_RA5_RB5<31,  396, "stxvx"   , vsrc,
1719                 [(store v2f64:$XT, xaddrX16:$dst)]>;
1720
1721  // Store Vector (Left-justified) with Length
1722  def STXVL : XX1Form_memOp<31, 397, (outs),
1723                            (ins vsrc:$XT, memr:$dst, g8rc:$rB),
1724                            "stxvl $XT, $dst, $rB", IIC_LdStLoad,
1725                            [(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst,
1726                              i64:$rB)]>;
1727  def STXVLL : XX1Form_memOp<31, 429, (outs),
1728                            (ins vsrc:$XT, memr:$dst, g8rc:$rB),
1729                            "stxvll $XT, $dst, $rB", IIC_LdStLoad,
1730                            [(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst,
1731                              i64:$rB)]>;
1732  } // mayStore
1733
1734  def DFLOADf32  : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src),
1735                          "#DFLOADf32",
1736                          [(set f32:$XT, (load iaddrX4:$src))]>;
1737  def DFLOADf64  : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src),
1738                          "#DFLOADf64",
1739                          [(set f64:$XT, (load iaddrX4:$src))]>;
1740  def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst),
1741                          "#DFSTOREf32",
1742                          [(store f32:$XT, iaddrX4:$dst)]>;
1743  def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst),
1744                          "#DFSTOREf64",
1745                          [(store f64:$XT, iaddrX4:$dst)]>;
1746
1747  let mayStore = 1 in {
1748    def SPILLTOVSR_STX : PseudoXFormMemOp<(outs),
1749                                          (ins spilltovsrrc:$XT, memrr:$dst),
1750                                          "#SPILLTOVSR_STX", []>;
1751    def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),
1752                              "#SPILLTOVSR_ST", []>;
1753  }
1754  let mayLoad = 1 in {
1755    def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT),
1756                                          (ins memrr:$src),
1757                                          "#SPILLTOVSR_LDX", []>;
1758    def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src),
1759                              "#SPILLTOVSR_LD", []>;
1760
1761  }
1762  } // HasP9Vector
1763} // hasSideEffects = 0
1764
1765let PPC970_Single = 1, AddedComplexity = 400 in {
1766
1767  def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),
1768                             (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
1769                             "#SELECT_CC_VSRC",
1770                             []>;
1771  def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),
1772                          (ins crbitrc:$cond, vsrc:$T, vsrc:$F),
1773                          "#SELECT_VSRC",
1774                          [(set v2f64:$dst,
1775                                (select i1:$cond, v2f64:$T, v2f64:$F))]>;
1776  def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),
1777                              (ins crrc:$cond, f8rc:$T, f8rc:$F,
1778                               i32imm:$BROPC), "#SELECT_CC_VSFRC",
1779                              []>;
1780  def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),
1781                           (ins crbitrc:$cond, f8rc:$T, f8rc:$F),
1782                           "#SELECT_VSFRC",
1783                           [(set f64:$dst,
1784                                 (select i1:$cond, f64:$T, f64:$F))]>;
1785  def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
1786                              (ins crrc:$cond, f4rc:$T, f4rc:$F,
1787                               i32imm:$BROPC), "#SELECT_CC_VSSRC",
1788                              []>;
1789  def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
1790                           (ins crbitrc:$cond, f4rc:$T, f4rc:$F),
1791                           "#SELECT_VSSRC",
1792                           [(set f32:$dst,
1793                                 (select i1:$cond, f32:$T, f32:$F))]>;
1794}
1795}
1796
1797//----------------------------- DAG Definitions ------------------------------//
1798def FpMinMax {
1799  dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC),
1800                                          (COPY_TO_REGCLASS $B, VSFRC)),
1801                                 VSSRC);
1802  dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC),
1803                                          (COPY_TO_REGCLASS $B, VSFRC)),
1804                                 VSSRC);
1805}
1806
1807def ScalarLoads {
1808  dag Li8 =       (i32 (extloadi8 xoaddr:$src));
1809  dag ZELi8 =     (i32 (zextloadi8 xoaddr:$src));
1810  dag ZELi8i64 =  (i64 (zextloadi8 xoaddr:$src));
1811  dag SELi8 =     (i32 (sext_inreg (extloadi8 xoaddr:$src), i8));
1812  dag SELi8i64 =  (i64 (sext_inreg (extloadi8 xoaddr:$src), i8));
1813
1814  dag Li16 =      (i32 (extloadi16 xoaddr:$src));
1815  dag ZELi16 =    (i32 (zextloadi16 xoaddr:$src));
1816  dag ZELi16i64 = (i64 (zextloadi16 xoaddr:$src));
1817  dag SELi16 =    (i32 (sextloadi16 xoaddr:$src));
1818  dag SELi16i64 = (i64 (sextloadi16 xoaddr:$src));
1819
1820  dag Li32 = (i32 (load xoaddr:$src));
1821}
1822
1823def DWToSPExtractConv {
1824  dag El0US1 = (f32 (PPCfcfidus
1825                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));
1826  dag El1US1 = (f32 (PPCfcfidus
1827                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));
1828  dag El0US2 = (f32 (PPCfcfidus
1829                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));
1830  dag El1US2 = (f32 (PPCfcfidus
1831                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));
1832  dag El0SS1 = (f32 (PPCfcfids
1833                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));
1834  dag El1SS1 = (f32 (PPCfcfids
1835                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));
1836  dag El0SS2 = (f32 (PPCfcfids
1837                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));
1838  dag El1SS2 = (f32 (PPCfcfids
1839                    (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));
1840  dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2));
1841  dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2));
1842}
1843
1844def WToDPExtractConv {
1845  dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0))));
1846  dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1))));
1847  dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2))));
1848  dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3))));
1849  dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0))));
1850  dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1))));
1851  dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2))));
1852  dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3))));
1853  dag BV02S = (v2f64 (build_vector El0S, El2S));
1854  dag BV13S = (v2f64 (build_vector El1S, El3S));
1855  dag BV02U = (v2f64 (build_vector El0U, El2U));
1856  dag BV13U = (v2f64 (build_vector El1U, El3U));
1857}
1858
1859/*  Direct moves of various widths from GPR's into VSR's. Each move lines
1860    the value up into element 0 (both BE and LE). Namely, entities smaller than
1861    a doubleword are shifted left and moved for BE. For LE, they're moved, then
1862    swapped to go into the least significant element of the VSR.
1863*/
1864def MovesToVSR {
1865  dag BE_BYTE_0 =
1866    (MTVSRD
1867      (RLDICR
1868        (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7));
1869  dag BE_HALF_0 =
1870    (MTVSRD
1871      (RLDICR
1872        (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15));
1873  dag BE_WORD_0 =
1874    (MTVSRD
1875      (RLDICR
1876        (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31));
1877  dag BE_DWORD_0 = (MTVSRD $A);
1878
1879  dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32));
1880  dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1881                                        LE_MTVSRW, sub_64));
1882  dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2);
1883  dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1884                                         BE_DWORD_0, sub_64));
1885  dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2);
1886}
1887
1888/*  Patterns for extracting elements out of vectors. Integer elements are
1889    extracted using direct move operations. Patterns for extracting elements
1890    whose indices are not available at compile time are also provided with
1891    various _VARIABLE_ patterns.
1892    The numbering for the DAG's is for LE, but when used on BE, the correct
1893    LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13).
1894*/
1895def VectorExtractions {
1896  // Doubleword extraction
1897  dag LE_DWORD_0 =
1898    (MFVSRD
1899      (EXTRACT_SUBREG
1900        (XXPERMDI (COPY_TO_REGCLASS $S, VSRC),
1901                  (COPY_TO_REGCLASS $S, VSRC), 2), sub_64));
1902  dag LE_DWORD_1 = (MFVSRD
1903                     (EXTRACT_SUBREG
1904                       (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));
1905
1906  // Word extraction
1907  dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64));
1908  dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64));
1909  dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG
1910                             (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64));
1911  dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64));
1912
1913  // Halfword extraction
1914  dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32));
1915  dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32));
1916  dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32));
1917  dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32));
1918  dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32));
1919  dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32));
1920  dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32));
1921  dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32));
1922
1923  // Byte extraction
1924  dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32));
1925  dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32));
1926  dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32));
1927  dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32));
1928  dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32));
1929  dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32));
1930  dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32));
1931  dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32));
1932  dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32));
1933  dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32));
1934  dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32));
1935  dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32));
1936  dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32));
1937  dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32));
1938  dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32));
1939  dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32));
1940
1941  /* Variable element number (BE and LE patterns must be specified separately)
1942     This is a rather involved process.
1943
1944     Conceptually, this is how the move is accomplished:
1945     1. Identify which doubleword contains the element
1946     2. Shift in the VMX register so that the correct doubleword is correctly
1947        lined up for the MFVSRD
1948     3. Perform the move so that the element (along with some extra stuff)
1949        is in the GPR
1950     4. Right shift within the GPR so that the element is right-justified
1951
1952     Of course, the index is an element number which has a different meaning
1953     on LE/BE so the patterns have to be specified separately.
1954
1955     Note: The final result will be the element right-justified with high
1956           order bits being arbitrarily defined (namely, whatever was in the
1957           vector register to the left of the value originally).
1958  */
1959
1960  /*  LE variable byte
1961      Number 1. above:
1962      - For elements 0-7, we shift left by 8 bytes since they're on the right
1963      - For elements 8-15, we need not shift (shift left by zero bytes)
1964      This is accomplished by inverting the bits of the index and AND-ing
1965      with 0x8 (i.e. clearing all bits of the index and inverting bit 60).
1966  */
1967  dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx)));
1968
1969  //  Number 2. above:
1970  //  - Now that we set up the shift amount, we shift in the VMX register
1971  dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC));
1972
1973  //  Number 3. above:
1974  //  - The doubleword containing our element is moved to a GPR
1975  dag LE_MV_VBYTE = (MFVSRD
1976                      (EXTRACT_SUBREG
1977                        (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)),
1978                        sub_64));
1979
1980  /*  Number 4. above:
1981      - Truncate the element number to the range 0-7 (8-15 are symmetrical
1982        and out of range values are truncated accordingly)
1983      - Multiply by 8 as we need to shift right by the number of bits, not bytes
1984      - Shift right in the GPR by the calculated value
1985  */
1986  dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60),
1987                                       sub_32);
1988  dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT),
1989                                         sub_32);
1990
1991  /*  LE variable halfword
1992      Number 1. above:
1993      - For elements 0-3, we shift left by 8 since they're on the right
1994      - For elements 4-7, we need not shift (shift left by zero bytes)
1995      Similarly to the byte pattern, we invert the bits of the index, but we
1996      AND with 0x4 (i.e. clear all bits of the index and invert bit 61).
1997      Of course, the shift is still by 8 bytes, so we must multiply by 2.
1998  */
1999  dag LE_VHALF_PERM_VEC =
2000    (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62)));
2001
2002  //  Number 2. above:
2003  //  - Now that we set up the shift amount, we shift in the VMX register
2004  dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC));
2005
2006  //  Number 3. above:
2007  //  - The doubleword containing our element is moved to a GPR
2008  dag LE_MV_VHALF = (MFVSRD
2009                      (EXTRACT_SUBREG
2010                        (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)),
2011                        sub_64));
2012
2013  /*  Number 4. above:
2014      - Truncate the element number to the range 0-3 (4-7 are symmetrical
2015        and out of range values are truncated accordingly)
2016      - Multiply by 16 as we need to shift right by the number of bits
2017      - Shift right in the GPR by the calculated value
2018  */
2019  dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59),
2020                                       sub_32);
2021  dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT),
2022                                         sub_32);
2023
2024  /*  LE variable word
2025      Number 1. above:
2026      - For elements 0-1, we shift left by 8 since they're on the right
2027      - For elements 2-3, we need not shift
2028  */
2029  dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2030                                       (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61)));
2031
2032  //  Number 2. above:
2033  //  - Now that we set up the shift amount, we shift in the VMX register
2034  dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC));
2035
2036  //  Number 3. above:
2037  //  - The doubleword containing our element is moved to a GPR
2038  dag LE_MV_VWORD = (MFVSRD
2039                      (EXTRACT_SUBREG
2040                        (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)),
2041                        sub_64));
2042
2043  /*  Number 4. above:
2044      - Truncate the element number to the range 0-1 (2-3 are symmetrical
2045        and out of range values are truncated accordingly)
2046      - Multiply by 32 as we need to shift right by the number of bits
2047      - Shift right in the GPR by the calculated value
2048  */
2049  dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58),
2050                                       sub_32);
2051  dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT),
2052                                         sub_32);
2053
2054  /*  LE variable doubleword
2055      Number 1. above:
2056      - For element 0, we shift left by 8 since it's on the right
2057      - For element 1, we need not shift
2058  */
2059  dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2060                                        (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60)));
2061
2062  //  Number 2. above:
2063  //  - Now that we set up the shift amount, we shift in the VMX register
2064  dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC));
2065
2066  // Number 3. above:
2067  //  - The doubleword containing our element is moved to a GPR
2068  //  - Number 4. is not needed for the doubleword as the value is 64-bits
2069  dag LE_VARIABLE_DWORD =
2070        (MFVSRD (EXTRACT_SUBREG
2071                  (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)),
2072                  sub_64));
2073
2074  /*  LE variable float
2075      - Shift the vector to line up the desired element to BE Word 0
2076      - Convert 32-bit float to a 64-bit single precision float
2077  */
2078  dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8,
2079                                  (RLDICR (XOR8 (LI8 3), $Idx), 2, 61)));
2080  dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC);
2081  dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE);
2082
2083  /*  LE variable double
2084      Same as the LE doubleword except there is no move.
2085  */
2086  dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2087                                         (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2088                                         LE_VDWORD_PERM_VEC));
2089  dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC);
2090
2091  /*  BE variable byte
2092      The algorithm here is the same as the LE variable byte except:
2093      - The shift in the VMX register is by 0/8 for opposite element numbers so
2094        we simply AND the element number with 0x8
2095      - The order of elements after the move to GPR is reversed, so we invert
2096        the bits of the index prior to truncating to the range 0-7
2097  */
2098  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8)));
2099  dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));
2100  dag BE_MV_VBYTE = (MFVSRD
2101                      (EXTRACT_SUBREG
2102                        (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)),
2103                        sub_64));
2104  dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60),
2105                                       sub_32);
2106  dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT),
2107                                         sub_32);
2108
2109  /*  BE variable halfword
2110      The algorithm here is the same as the LE variable halfword except:
2111      - The shift in the VMX register is by 0/8 for opposite element numbers so
2112        we simply AND the element number with 0x4 and multiply by 2
2113      - The order of elements after the move to GPR is reversed, so we invert
2114        the bits of the index prior to truncating to the range 0-3
2115  */
2116  dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,
2117                                       (RLDICR (ANDI8_rec $Idx, 4), 1, 62)));
2118  dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));
2119  dag BE_MV_VHALF = (MFVSRD
2120                      (EXTRACT_SUBREG
2121                        (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)),
2122                        sub_64));
2123  dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59),
2124                                       sub_32);
2125  dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT),
2126                                         sub_32);
2127
2128  /*  BE variable word
2129      The algorithm is the same as the LE variable word except:
2130      - The shift in the VMX register happens for opposite element numbers
2131      - The order of elements after the move to GPR is reversed, so we invert
2132        the bits of the index prior to truncating to the range 0-1
2133  */
2134  dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2135                                       (RLDICR (ANDI8_rec $Idx, 2), 2, 61)));
2136  dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));
2137  dag BE_MV_VWORD = (MFVSRD
2138                      (EXTRACT_SUBREG
2139                        (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)),
2140                        sub_64));
2141  dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58),
2142                                       sub_32);
2143  dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT),
2144                                         sub_32);
2145
2146  /*  BE variable doubleword
2147      Same as the LE doubleword except we shift in the VMX register for opposite
2148      element indices.
2149  */
2150  dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
2151                                        (RLDICR (ANDI8_rec $Idx, 1), 3, 60)));
2152  dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));
2153  dag BE_VARIABLE_DWORD =
2154        (MFVSRD (EXTRACT_SUBREG
2155                  (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)),
2156                  sub_64));
2157
2158  /*  BE variable float
2159      - Shift the vector to line up the desired element to BE Word 0
2160      - Convert 32-bit float to a 64-bit single precision float
2161  */
2162  dag BE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, (RLDICR $Idx, 2, 61)));
2163  dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC);
2164  dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE);
2165
2166  /* BE variable double
2167      Same as the BE doubleword except there is no move.
2168  */
2169  dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2170                                         (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
2171                                         BE_VDWORD_PERM_VEC));
2172  dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC);
2173}
2174
2175def AlignValues {
2176  dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3));
2177  dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC);
2178}
2179
2180// Integer extend helper dags 32 -> 64
2181def AnyExts {
2182  dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32);
2183  dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32);
2184  dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32);
2185  dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32);
2186}
2187
2188def DblToFlt {
2189  dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0))));
2190  dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1))));
2191  dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0))));
2192  dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1))));
2193}
2194
2195def ExtDbl {
2196  dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0))))));
2197  dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1))))));
2198  dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0))))));
2199  dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1))))));
2200  dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0))))));
2201  dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1))))));
2202  dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0))))));
2203  dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1))))));
2204}
2205
2206def ByteToWord {
2207  dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8));
2208  dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8));
2209  dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8));
2210  dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8));
2211  dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8));
2212  dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 7)), i8));
2213  dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 11)), i8));
2214  dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 15)), i8));
2215}
2216
2217def ByteToDWord {
2218  dag LE_A0 = (i64 (sext_inreg
2219              (i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8));
2220  dag LE_A1 = (i64 (sext_inreg
2221              (i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8));
2222  dag BE_A0 = (i64 (sext_inreg
2223              (i64 (anyext (i32 (vector_extract v16i8:$A, 7)))), i8));
2224  dag BE_A1 = (i64 (sext_inreg
2225              (i64 (anyext (i32 (vector_extract v16i8:$A, 15)))), i8));
2226}
2227
2228def HWordToWord {
2229  dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16));
2230  dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16));
2231  dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16));
2232  dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16));
2233  dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16));
2234  dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16));
2235  dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16));
2236  dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16));
2237}
2238
2239def HWordToDWord {
2240  dag LE_A0 = (i64 (sext_inreg
2241              (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16));
2242  dag LE_A1 = (i64 (sext_inreg
2243              (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16));
2244  dag BE_A0 = (i64 (sext_inreg
2245              (i64 (anyext (i32 (vector_extract v8i16:$A, 3)))), i16));
2246  dag BE_A1 = (i64 (sext_inreg
2247              (i64 (anyext (i32 (vector_extract v8i16:$A, 7)))), i16));
2248}
2249
2250def WordToDWord {
2251  dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0))));
2252  dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2))));
2253  dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1))));
2254  dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3))));
2255}
2256
2257def FltToIntLoad {
2258  dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 xoaddr:$A)))));
2259}
2260def FltToUIntLoad {
2261  dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 xoaddr:$A)))));
2262}
2263def FltToLongLoad {
2264  dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 xoaddr:$A)))));
2265}
2266def FltToLongLoadP9 {
2267  dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 iaddrX4:$A)))));
2268}
2269def FltToULongLoad {
2270  dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 xoaddr:$A)))));
2271}
2272def FltToULongLoadP9 {
2273  dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 iaddrX4:$A)))));
2274}
2275def FltToLong {
2276  dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A)))));
2277}
2278def FltToULong {
2279  dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A)))));
2280}
2281def DblToInt {
2282  dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A))));
2283  dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B))));
2284  dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C))));
2285  dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D))));
2286}
2287def DblToUInt {
2288  dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A))));
2289  dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B))));
2290  dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C))));
2291  dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D))));
2292}
2293def DblToLong {
2294  dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A))));
2295}
2296def DblToULong {
2297  dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A))));
2298}
2299def DblToIntLoad {
2300  dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load xoaddr:$A)))));
2301}
2302def DblToIntLoadP9 {
2303  dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load iaddrX4:$A)))));
2304}
2305def DblToUIntLoad {
2306  dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load xoaddr:$A)))));
2307}
2308def DblToUIntLoadP9 {
2309  dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load iaddrX4:$A)))));
2310}
2311def DblToLongLoad {
2312  dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load xoaddr:$A)))));
2313}
2314def DblToULongLoad {
2315  dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load xoaddr:$A)))));
2316}
2317
2318// FP load dags (for f32 -> v4f32)
2319def LoadFP {
2320  dag A = (f32 (load xoaddr:$A));
2321  dag B = (f32 (load xoaddr:$B));
2322  dag C = (f32 (load xoaddr:$C));
2323  dag D = (f32 (load xoaddr:$D));
2324}
2325
2326// FP merge dags (for f32 -> v4f32)
2327def MrgFP {
2328  dag LD32A = (COPY_TO_REGCLASS (LIWZX xoaddr:$A), VSRC);
2329  dag LD32B = (COPY_TO_REGCLASS (LIWZX xoaddr:$B), VSRC);
2330  dag LD32C = (COPY_TO_REGCLASS (LIWZX xoaddr:$C), VSRC);
2331  dag LD32D = (COPY_TO_REGCLASS (LIWZX xoaddr:$D), VSRC);
2332  dag AC = (XVCVDPSP (XXPERMDI (COPY_TO_REGCLASS $A, VSRC),
2333                               (COPY_TO_REGCLASS $C, VSRC), 0));
2334  dag BD = (XVCVDPSP (XXPERMDI (COPY_TO_REGCLASS $B, VSRC),
2335                               (COPY_TO_REGCLASS $D, VSRC), 0));
2336  dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0));
2337  dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3));
2338  dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0));
2339  dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3));
2340}
2341
2342// Word-element merge dags - conversions from f64 to i32 merged into vectors.
2343def MrgWords {
2344  // For big endian, we merge low and hi doublewords (A, B).
2345  dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0));
2346  dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3));
2347  dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1));
2348  dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0));
2349  dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1));
2350  dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0));
2351
2352  // For little endian, we merge low and hi doublewords (B, A).
2353  dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0));
2354  dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3));
2355  dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1));
2356  dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0));
2357  dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1));
2358  dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0));
2359
2360  // For big endian, we merge hi doublewords of (A, C) and (B, D), convert
2361  // then merge.
2362  dag AC = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$A, VSRC),
2363                            (COPY_TO_REGCLASS f64:$C, VSRC), 0));
2364  dag BD = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$B, VSRC),
2365                            (COPY_TO_REGCLASS f64:$D, VSRC), 0));
2366  dag CVACS = (v4i32 (XVCVDPSXWS AC));
2367  dag CVBDS = (v4i32 (XVCVDPSXWS BD));
2368  dag CVACU = (v4i32 (XVCVDPUXWS AC));
2369  dag CVBDU = (v4i32 (XVCVDPUXWS BD));
2370
2371  // For little endian, we merge hi doublewords of (D, B) and (C, A), convert
2372  // then merge.
2373  dag DB = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$D, VSRC),
2374                            (COPY_TO_REGCLASS f64:$B, VSRC), 0));
2375  dag CA = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$C, VSRC),
2376                            (COPY_TO_REGCLASS f64:$A, VSRC), 0));
2377  dag CVDBS = (v4i32 (XVCVDPSXWS DB));
2378  dag CVCAS = (v4i32 (XVCVDPSXWS CA));
2379  dag CVDBU = (v4i32 (XVCVDPUXWS DB));
2380  dag CVCAU = (v4i32 (XVCVDPUXWS CA));
2381}
2382
2383//---------------------------- Anonymous Patterns ----------------------------//
2384// Predicate combinations are kept in roughly chronological order in terms of
2385// instruction availability in the architecture. For example, VSX came in with
2386// ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and
2387// ISA 3.0 (Power9). However, the granularity of features on later subtargets
2388// is finer for various reasons. For example, we have Power8Vector,
2389// Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is
2390// similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there
2391// are orthogonal predicates such as endianness for which the order was
2392// arbitrarily chosen to be Big, Little.
2393//
2394// Predicate combinations available:
2395// [HasVSX]
2396// [HasVSX, IsBigEndian]
2397// [HasVSX, IsLittleEndian]
2398// [HasVSX, NoP9Vector]
2399// [HasVSX, HasOnlySwappingMemOps]
2400// [HasVSX, HasOnlySwappingMemOps, IsBigEndian]
2401// [HasVSX, HasP8Vector]
2402// [HasVSX, HasP8Vector, IsBigEndian]
2403// [HasVSX, HasP8Vector, IsLittleEndian]
2404// [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian]
2405// [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian]
2406// [HasVSX, HasDirectMove]
2407// [HasVSX, HasDirectMove, IsBigEndian]
2408// [HasVSX, HasDirectMove, IsLittleEndian]
2409// [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian]
2410// [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian]
2411// [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian]
2412// [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian]
2413// [HasVSX, HasP9Vector]
2414// [HasVSX, HasP9Vector, IsBigEndian]
2415// [HasVSX, HasP9Vector, IsLittleEndian]
2416// [HasVSX, HasP9Altivec]
2417// [HasVSX, HasP9Altivec, IsBigEndian]
2418// [HasVSX, HasP9Altivec, IsLittleEndian]
2419// [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian]
2420// [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian]
2421
2422let AddedComplexity = 400 in {
2423// Valid for any VSX subtarget, regardless of endianness.
2424let Predicates = [HasVSX] in {
2425def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
2426          (v4i32 (XXLNOR $A, $A))>;
2427def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
2428                     (and v4i32:$B, v4i32:$C))),
2429          (v4i32 (XXSEL $A, $B, $C))>;
2430
2431// Additional fnmsub pattern for PPC specific ISD opcode
2432def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
2433          (XSNMSUBADP $C, $A, $B)>;
2434def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
2435          (XSMSUBADP $C, $A, $B)>;
2436def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
2437          (XSNMADDADP $C, $A, $B)>;
2438
2439def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C),
2440          (XVNMSUBADP $C, $A, $B)>;
2441def : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)),
2442          (XVMSUBADP $C, $A, $B)>;
2443def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)),
2444          (XVNMADDADP $C, $A, $B)>;
2445
2446def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),
2447          (XVNMSUBASP $C, $A, $B)>;
2448def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)),
2449          (XVMSUBASP $C, $A, $B)>;
2450def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)),
2451          (XVNMADDASP $C, $A, $B)>;
2452
2453def : Pat<(v2f64 (bitconvert v4f32:$A)),
2454          (COPY_TO_REGCLASS $A, VSRC)>;
2455def : Pat<(v2f64 (bitconvert v4i32:$A)),
2456          (COPY_TO_REGCLASS $A, VSRC)>;
2457def : Pat<(v2f64 (bitconvert v8i16:$A)),
2458          (COPY_TO_REGCLASS $A, VSRC)>;
2459def : Pat<(v2f64 (bitconvert v16i8:$A)),
2460          (COPY_TO_REGCLASS $A, VSRC)>;
2461
2462def : Pat<(v4f32 (bitconvert v2f64:$A)),
2463          (COPY_TO_REGCLASS $A, VRRC)>;
2464def : Pat<(v4i32 (bitconvert v2f64:$A)),
2465          (COPY_TO_REGCLASS $A, VRRC)>;
2466def : Pat<(v8i16 (bitconvert v2f64:$A)),
2467          (COPY_TO_REGCLASS $A, VRRC)>;
2468def : Pat<(v16i8 (bitconvert v2f64:$A)),
2469          (COPY_TO_REGCLASS $A, VRRC)>;
2470
2471def : Pat<(v2i64 (bitconvert v4f32:$A)),
2472          (COPY_TO_REGCLASS $A, VSRC)>;
2473def : Pat<(v2i64 (bitconvert v4i32:$A)),
2474          (COPY_TO_REGCLASS $A, VSRC)>;
2475def : Pat<(v2i64 (bitconvert v8i16:$A)),
2476          (COPY_TO_REGCLASS $A, VSRC)>;
2477def : Pat<(v2i64 (bitconvert v16i8:$A)),
2478          (COPY_TO_REGCLASS $A, VSRC)>;
2479
2480def : Pat<(v4f32 (bitconvert v2i64:$A)),
2481          (COPY_TO_REGCLASS $A, VRRC)>;
2482def : Pat<(v4i32 (bitconvert v2i64:$A)),
2483          (COPY_TO_REGCLASS $A, VRRC)>;
2484def : Pat<(v8i16 (bitconvert v2i64:$A)),
2485          (COPY_TO_REGCLASS $A, VRRC)>;
2486def : Pat<(v16i8 (bitconvert v2i64:$A)),
2487          (COPY_TO_REGCLASS $A, VRRC)>;
2488
2489def : Pat<(v2f64 (bitconvert v2i64:$A)),
2490          (COPY_TO_REGCLASS $A, VRRC)>;
2491def : Pat<(v2i64 (bitconvert v2f64:$A)),
2492          (COPY_TO_REGCLASS $A, VRRC)>;
2493
2494def : Pat<(v2f64 (bitconvert v1i128:$A)),
2495          (COPY_TO_REGCLASS $A, VRRC)>;
2496def : Pat<(v1i128 (bitconvert v2f64:$A)),
2497          (COPY_TO_REGCLASS $A, VRRC)>;
2498
2499def : Pat<(v2i64 (bitconvert f128:$A)),
2500          (COPY_TO_REGCLASS $A, VRRC)>;
2501def : Pat<(v4i32 (bitconvert f128:$A)),
2502          (COPY_TO_REGCLASS $A, VRRC)>;
2503def : Pat<(v8i16 (bitconvert f128:$A)),
2504          (COPY_TO_REGCLASS $A, VRRC)>;
2505def : Pat<(v16i8 (bitconvert f128:$A)),
2506          (COPY_TO_REGCLASS $A, VRRC)>;
2507
2508def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)),
2509          (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>;
2510def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)),
2511          (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>;
2512
2513def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)),
2514          (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>;
2515def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)),
2516          (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>;
2517
2518def : Pat<(v2f64 (PPCfpexth v4f32:$C, 0)), (XVCVSPDP (XXMRGHW $C, $C))>;
2519def : Pat<(v2f64 (PPCfpexth v4f32:$C, 1)), (XVCVSPDP (XXMRGLW $C, $C))>;
2520
2521// Permutes.
2522def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;
2523def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;
2524def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;
2525def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;
2526def : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>;
2527
2528// PPCvecshl XT, XA, XA, 2 can be selected to both XXSLDWI XT,XA,XA,2 and
2529// XXSWAPD XT,XA (i.e. XXPERMDI XT,XA,XA,2), the later one is more profitable.
2530def : Pat<(v4i32 (PPCvecshl v4i32:$src, v4i32:$src, 2)),
2531          (XXPERMDI $src, $src, 2)>;
2532
2533// Selects.
2534def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
2535          (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2536def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)),
2537          (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2538def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
2539          (SELECT_VSRC (CRORC  $lhs, $rhs), $tval, $fval)>;
2540def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)),
2541          (SELECT_VSRC (CRORC  $rhs, $lhs), $tval, $fval)>;
2542def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
2543          (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
2544def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
2545          (SELECT_VSRC (CRORC  $rhs, $lhs), $tval, $fval)>;
2546def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)),
2547          (SELECT_VSRC (CRORC  $lhs, $rhs), $tval, $fval)>;
2548def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
2549          (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2550def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)),
2551          (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2552def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
2553          (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
2554
2555def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2556          (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2557def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
2558          (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2559def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2560          (SELECT_VSFRC (CRORC  $lhs, $rhs), $tval, $fval)>;
2561def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
2562          (SELECT_VSFRC (CRORC  $rhs, $lhs), $tval, $fval)>;
2563def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2564          (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
2565def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2566          (SELECT_VSFRC (CRORC  $rhs, $lhs), $tval, $fval)>;
2567def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
2568          (SELECT_VSFRC (CRORC  $lhs, $rhs), $tval, $fval)>;
2569def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2570          (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
2571def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
2572          (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
2573def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
2574          (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
2575
2576// Divides.
2577def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
2578          (XVDIVSP $A, $B)>;
2579def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
2580          (XVDIVDP $A, $B)>;
2581
2582// Reciprocal estimate
2583def : Pat<(int_ppc_vsx_xvresp v4f32:$A),
2584          (XVRESP $A)>;
2585def : Pat<(int_ppc_vsx_xvredp v2f64:$A),
2586          (XVREDP $A)>;
2587
2588// Recip. square root estimate
2589def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
2590          (XVRSQRTESP $A)>;
2591def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
2592          (XVRSQRTEDP $A)>;
2593
2594// Vector selection
2595def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
2596          (COPY_TO_REGCLASS
2597                 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
2598                        (COPY_TO_REGCLASS $vB, VSRC),
2599                        (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
2600def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
2601          (COPY_TO_REGCLASS
2602                 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
2603                        (COPY_TO_REGCLASS $vB, VSRC),
2604                        (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
2605def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),
2606          (XXSEL $vC, $vB, $vA)>;
2607def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),
2608          (XXSEL $vC, $vB, $vA)>;
2609def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
2610          (XXSEL $vC, $vB, $vA)>;
2611def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
2612          (XXSEL $vC, $vB, $vA)>;
2613
2614def : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)),
2615          (v4f32 (XVMAXSP $src1, $src2))>;
2616def : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)),
2617          (v4f32 (XVMINSP $src1, $src2))>;
2618def : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)),
2619          (v2f64 (XVMAXDP $src1, $src2))>;
2620def : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)),
2621          (v2f64 (XVMINDP $src1, $src2))>;
2622
2623// f32 abs
2624def : Pat<(f32 (fabs f32:$S)),
2625          (f32 (COPY_TO_REGCLASS (XSABSDP
2626               (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2627
2628// f32 nabs
2629def : Pat<(f32 (fneg (fabs f32:$S))),
2630          (f32 (COPY_TO_REGCLASS (XSNABSDP
2631               (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2632
2633// f32 Min.
2634def : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)),
2635          (f32 FpMinMax.F32Min)>;
2636def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), f32:$B)),
2637          (f32 FpMinMax.F32Min)>;
2638def : Pat<(f32 (fminnum_ieee f32:$A, (fcanonicalize f32:$B))),
2639          (f32 FpMinMax.F32Min)>;
2640def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))),
2641          (f32 FpMinMax.F32Min)>;
2642// F32 Max.
2643def : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)),
2644          (f32 FpMinMax.F32Max)>;
2645def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), f32:$B)),
2646          (f32 FpMinMax.F32Max)>;
2647def : Pat<(f32 (fmaxnum_ieee f32:$A, (fcanonicalize f32:$B))),
2648          (f32 FpMinMax.F32Max)>;
2649def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))),
2650          (f32 FpMinMax.F32Max)>;
2651
2652// f64 Min.
2653def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)),
2654          (f64 (XSMINDP $A, $B))>;
2655def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)),
2656          (f64 (XSMINDP $A, $B))>;
2657def : Pat<(f64 (fminnum_ieee f64:$A, (fcanonicalize f64:$B))),
2658          (f64 (XSMINDP $A, $B))>;
2659def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))),
2660          (f64 (XSMINDP $A, $B))>;
2661// f64 Max.
2662def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)),
2663          (f64 (XSMAXDP $A, $B))>;
2664def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), f64:$B)),
2665          (f64 (XSMAXDP $A, $B))>;
2666def : Pat<(f64 (fmaxnum_ieee f64:$A, (fcanonicalize f64:$B))),
2667          (f64 (XSMAXDP $A, $B))>;
2668def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))),
2669          (f64 (XSMAXDP $A, $B))>;
2670
2671def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, xoaddr:$dst),
2672            (STXVD2X $rS, xoaddr:$dst)>;
2673def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, xoaddr:$dst),
2674            (STXVW4X $rS, xoaddr:$dst)>;
2675def : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
2676def : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
2677
2678// Rounding for single precision.
2679def : Pat<(f32 (any_fround f32:$S)),
2680          (f32 (COPY_TO_REGCLASS (XSRDPI
2681                                   (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2682def : Pat<(f32 (any_fnearbyint f32:$S)),
2683          (f32 (COPY_TO_REGCLASS (XSRDPIC
2684                                   (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2685def : Pat<(f32 (any_ffloor f32:$S)),
2686          (f32 (COPY_TO_REGCLASS (XSRDPIM
2687                                   (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2688def : Pat<(f32 (any_fceil f32:$S)),
2689          (f32 (COPY_TO_REGCLASS (XSRDPIP
2690                                   (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2691def : Pat<(f32 (any_ftrunc f32:$S)),
2692          (f32 (COPY_TO_REGCLASS (XSRDPIZ
2693                                   (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2694def : Pat<(f32 (any_frint f32:$S)),
2695          (f32 (COPY_TO_REGCLASS (XSRDPIC
2696                                   (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
2697def : Pat<(v4f32 (frint v4f32:$S)), (v4f32 (XVRSPIC $S))>;
2698
2699// Rounding for double precision.
2700def : Pat<(f64 (frint f64:$S)), (f64 (XSRDPIC $S))>;
2701def : Pat<(v2f64 (frint v2f64:$S)), (v2f64 (XVRDPIC $S))>;
2702
2703// Materialize a zero-vector of long long
2704def : Pat<(v2i64 immAllZerosV),
2705          (v2i64 (XXLXORz))>;
2706
2707// Build vectors of floating point converted to i32.
2708def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A,
2709                               DblToInt.A, DblToInt.A)),
2710          (v4i32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS $A), VSRC), 1))>;
2711def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A,
2712                               DblToUInt.A, DblToUInt.A)),
2713          (v4i32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS $A), VSRC), 1))>;
2714def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)),
2715          (v2i64 (XXPERMDI (COPY_TO_REGCLASS (XSCVDPSXDS $A), VSRC),
2716                           (COPY_TO_REGCLASS (XSCVDPSXDS $A), VSRC), 0))>;
2717def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)),
2718          (v2i64 (XXPERMDI (COPY_TO_REGCLASS (XSCVDPUXDS $A), VSRC),
2719                           (COPY_TO_REGCLASS (XSCVDPUXDS $A), VSRC), 0))>;
2720defm : ScalToVecWPermute<
2721  v4i32, FltToIntLoad.A,
2722  (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWSs (XFLOADf32 xoaddr:$A)), VSRC), 1),
2723  (COPY_TO_REGCLASS (XSCVDPSXWSs (XFLOADf32 xoaddr:$A)), VSRC)>;
2724defm : ScalToVecWPermute<
2725  v4i32, FltToUIntLoad.A,
2726  (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), VSRC), 1),
2727  (COPY_TO_REGCLASS (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), VSRC)>;
2728def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
2729          (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;
2730def : Pat<(v2f64 (PPCldsplat xoaddr:$A)),
2731          (v2f64 (LXVDSX xoaddr:$A))>;
2732def : Pat<(v2i64 (PPCldsplat xoaddr:$A)),
2733          (v2i64 (LXVDSX xoaddr:$A))>;
2734
2735// Build vectors of floating point converted to i64.
2736def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
2737          (v2i64 (XXPERMDIs
2738                   (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
2739def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
2740          (v2i64 (XXPERMDIs
2741                   (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
2742defm : ScalToVecWPermute<
2743  v2i64, DblToLongLoad.A,
2744  (XVCVDPSXDS (LXVDSX xoaddr:$A)), (XVCVDPSXDS (LXVDSX xoaddr:$A))>;
2745defm : ScalToVecWPermute<
2746  v2i64, DblToULongLoad.A,
2747  (XVCVDPUXDS (LXVDSX xoaddr:$A)), (XVCVDPUXDS (LXVDSX xoaddr:$A))>;
2748} // HasVSX
2749
2750// Any big endian VSX subtarget.
2751let Predicates = [HasVSX, IsBigEndian] in {
2752def : Pat<(v2f64 (scalar_to_vector f64:$A)),
2753          (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
2754
2755def : Pat<(f64 (extractelt v2f64:$S, 0)),
2756          (f64 (EXTRACT_SUBREG $S, sub_64))>;
2757def : Pat<(f64 (extractelt v2f64:$S, 1)),
2758          (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
2759def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
2760          (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
2761def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
2762          (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
2763def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
2764          (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
2765def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
2766          (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
2767
2768def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
2769          (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>;
2770
2771def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
2772          (v2f64 (XXPERMDI
2773                    (COPY_TO_REGCLASS $A, VSRC),
2774                    (COPY_TO_REGCLASS $B, VSRC), 0))>;
2775// Using VMRGEW to assemble the final vector would be a lower latency
2776// solution. However, we choose to go with the slightly higher latency
2777// XXPERMDI for 2 reasons:
2778// 1. This is likely to occur in unrolled loops where regpressure is high,
2779//    so we want to use the latter as it has access to all 64 VSX registers.
2780// 2. Using Altivec instructions in this sequence would likely cause the
2781//    allocation of Altivec registers even for the loads which in turn would
2782//    force the use of LXSIWZX for the loads, adding a cycle of latency to
2783//    each of the loads which would otherwise be able to use LFIWZX.
2784def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)),
2785          (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32A, MrgFP.LD32B),
2786                           (XXMRGHW MrgFP.LD32C, MrgFP.LD32D), 3))>;
2787def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)),
2788          (VMRGEW MrgFP.AC, MrgFP.BD)>;
2789def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
2790                               DblToFlt.B0, DblToFlt.B1)),
2791          (v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>;
2792
2793// Convert 4 doubles to a vector of ints.
2794def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,
2795                               DblToInt.C, DblToInt.D)),
2796          (v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>;
2797def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,
2798                               DblToUInt.C, DblToUInt.D)),
2799          (v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>;
2800def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,
2801                               ExtDbl.B0S, ExtDbl.B1S)),
2802          (v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>;
2803def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,
2804                               ExtDbl.B0U, ExtDbl.B1U)),
2805          (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>;
2806def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2807                               (f64 (fpextend (extractelt v4f32:$A, 1))))),
2808          (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>;
2809def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2810                               (f64 (fpextend (extractelt v4f32:$A, 0))))),
2811          (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)),
2812                           (XVCVSPDP (XXMRGHW $A, $A)), 2))>;
2813def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2814                               (f64 (fpextend (extractelt v4f32:$A, 2))))),
2815          (v2f64 (XVCVSPDP $A))>;
2816def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2817                               (f64 (fpextend (extractelt v4f32:$A, 3))))),
2818          (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 3)))>;
2819def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))),
2820                               (f64 (fpextend (extractelt v4f32:$A, 3))))),
2821          (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>;
2822def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
2823                               (f64 (fpextend (extractelt v4f32:$A, 2))))),
2824          (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)),
2825                           (XVCVSPDP (XXMRGLW $A, $A)), 2))>;
2826def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2827                               (f64 (fpextend (extractelt v4f32:$B, 0))))),
2828          (v2f64 (XVCVSPDP (XXPERMDI $A, $B, 0)))>;
2829def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
2830                               (f64 (fpextend (extractelt v4f32:$B, 3))))),
2831          (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $A, $B, 3),
2832                                    (XXPERMDI $A, $B, 3), 1)))>;
2833def : Pat<WToDPExtractConv.BV02S,
2834          (v2f64 (XVCVSXWDP $A))>;
2835def : Pat<WToDPExtractConv.BV13S,
2836          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 3)))>;
2837def : Pat<WToDPExtractConv.BV02U,
2838          (v2f64 (XVCVUXWDP $A))>;
2839def : Pat<WToDPExtractConv.BV13U,
2840          (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 3)))>;
2841} // HasVSX, IsBigEndian
2842
2843// Any little endian VSX subtarget.
2844let Predicates = [HasVSX, IsLittleEndian] in {
2845defm : ScalToVecWPermute<v2f64, (f64 f64:$A),
2846                         (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
2847                                   (SUBREG_TO_REG (i64 1), $A, sub_64), 0),
2848                         (SUBREG_TO_REG (i64 1), $A, sub_64)>;
2849
2850def : Pat<(f64 (extractelt v2f64:$S, 0)),
2851          (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
2852def : Pat<(f64 (extractelt v2f64:$S, 1)),
2853          (f64 (EXTRACT_SUBREG $S, sub_64))>;
2854
2855def : Pat<(v2f64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
2856def : Pat<(PPCst_vec_be v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
2857def : Pat<(v4f32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
2858def : Pat<(PPCst_vec_be v4f32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
2859def : Pat<(v2i64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>;
2860def : Pat<(PPCst_vec_be v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
2861def : Pat<(v4i32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>;
2862def : Pat<(PPCst_vec_be v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>;
2863def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
2864          (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
2865def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
2866          (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
2867def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
2868          (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
2869def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
2870          (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
2871
2872def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
2873          (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>;
2874
2875// Little endian, available on all targets with VSX
2876def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
2877          (v2f64 (XXPERMDI
2878                    (COPY_TO_REGCLASS $B, VSRC),
2879                    (COPY_TO_REGCLASS $A, VSRC), 0))>;
2880// Using VMRGEW to assemble the final vector would be a lower latency
2881// solution. However, we choose to go with the slightly higher latency
2882// XXPERMDI for 2 reasons:
2883// 1. This is likely to occur in unrolled loops where regpressure is high,
2884//    so we want to use the latter as it has access to all 64 VSX registers.
2885// 2. Using Altivec instructions in this sequence would likely cause the
2886//    allocation of Altivec registers even for the loads which in turn would
2887//    force the use of LXSIWZX for the loads, adding a cycle of latency to
2888//    each of the loads which would otherwise be able to use LFIWZX.
2889def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)),
2890          (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32D, MrgFP.LD32C),
2891                           (XXMRGHW MrgFP.LD32B, MrgFP.LD32A), 3))>;
2892def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)),
2893          (VMRGEW MrgFP.AC, MrgFP.BD)>;
2894def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
2895                               DblToFlt.B0, DblToFlt.B1)),
2896          (v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>;
2897
2898// Convert 4 doubles to a vector of ints.
2899def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B,
2900                               DblToInt.C, DblToInt.D)),
2901          (v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>;
2902def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B,
2903                               DblToUInt.C, DblToUInt.D)),
2904          (v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>;
2905def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S,
2906                               ExtDbl.B0S, ExtDbl.B1S)),
2907          (v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>;
2908def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U,
2909                               ExtDbl.B0U, ExtDbl.B1U)),
2910          (v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>;
2911def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2912                               (f64 (fpextend (extractelt v4f32:$A, 1))))),
2913          (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>;
2914def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2915                               (f64 (fpextend (extractelt v4f32:$A, 0))))),
2916          (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)),
2917                           (XVCVSPDP (XXMRGLW $A, $A)), 2))>;
2918def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2919                               (f64 (fpextend (extractelt v4f32:$A, 2))))),
2920          (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>;
2921def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
2922                               (f64 (fpextend (extractelt v4f32:$A, 3))))),
2923          (v2f64 (XVCVSPDP $A))>;
2924def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))),
2925                               (f64 (fpextend (extractelt v4f32:$A, 3))))),
2926          (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>;
2927def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
2928                               (f64 (fpextend (extractelt v4f32:$A, 2))))),
2929          (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)),
2930                           (XVCVSPDP (XXMRGHW $A, $A)), 2))>;
2931def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))),
2932                               (f64 (fpextend (extractelt v4f32:$B, 0))))),
2933          (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $B, $A, 3),
2934                                    (XXPERMDI $B, $A, 3), 1)))>;
2935def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))),
2936                               (f64 (fpextend (extractelt v4f32:$B, 3))))),
2937          (v2f64 (XVCVSPDP (XXPERMDI $B, $A, 0)))>;
2938def : Pat<WToDPExtractConv.BV02S,
2939          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;
2940def : Pat<WToDPExtractConv.BV13S,
2941          (v2f64 (XVCVSXWDP $A))>;
2942def : Pat<WToDPExtractConv.BV02U,
2943          (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>;
2944def : Pat<WToDPExtractConv.BV13U,
2945          (v2f64 (XVCVUXWDP $A))>;
2946} // HasVSX, IsLittleEndian
2947
2948// Any pre-Power9 VSX subtarget.
2949let Predicates = [HasVSX, NoP9Vector] in {
2950def : Pat<(PPCstore_scal_int_from_vsr
2951            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 8),
2952          (STXSDX (XSCVDPSXDS f64:$src), xoaddr:$dst)>;
2953def : Pat<(PPCstore_scal_int_from_vsr
2954            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 8),
2955          (STXSDX (XSCVDPUXDS f64:$src), xoaddr:$dst)>;
2956
2957// Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads).
2958defm : ScalToVecWPermute<
2959  v4i32, DblToIntLoad.A,
2960  (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS (XFLOADf64 xoaddr:$A)), VSRC), 1),
2961  (COPY_TO_REGCLASS (XSCVDPSXWS (XFLOADf64 xoaddr:$A)), VSRC)>;
2962defm : ScalToVecWPermute<
2963  v4i32, DblToUIntLoad.A,
2964  (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS (XFLOADf64 xoaddr:$A)), VSRC), 1),
2965  (COPY_TO_REGCLASS (XSCVDPUXWS (XFLOADf64 xoaddr:$A)), VSRC)>;
2966defm : ScalToVecWPermute<
2967  v2i64, FltToLongLoad.A,
2968  (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A), VSFRC)), 0),
2969  (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A),
2970                                                        VSFRC)), sub_64)>;
2971defm : ScalToVecWPermute<
2972  v2i64, FltToULongLoad.A,
2973  (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A), VSFRC)), 0),
2974  (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A),
2975                                                        VSFRC)), sub_64)>;
2976} // HasVSX, NoP9Vector
2977
2978// Any VSX subtarget that only has loads and stores that load in big endian
2979// order regardless of endianness. This is really pre-Power9 subtargets.
2980let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
2981  def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
2982
2983  // Stores.
2984  def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
2985            (STXVD2X $rS, xoaddr:$dst)>;
2986  def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
2987} // HasVSX, HasOnlySwappingMemOps
2988
2989// Big endian VSX subtarget that only has loads and stores that always load
2990// in big endian order. Really big endian pre-Power9 subtargets.
2991let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in {
2992  def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
2993  def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
2994  def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
2995  def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVW4X xoaddr:$src)>;
2996  def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
2997  def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
2998  def : Pat<(store v4i32:$XT, xoaddr:$dst), (STXVW4X $XT, xoaddr:$dst)>;
2999  def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
3000            (STXVW4X $rS, xoaddr:$dst)>;
3001} // HasVSX, HasOnlySwappingMemOps, IsBigEndian
3002
3003// Any Power8 VSX subtarget.
3004let Predicates = [HasVSX, HasP8Vector] in {
3005def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
3006          (XXLEQV $A, $B)>;
3007def : Pat<(f64 (extloadf32 xoaddr:$src)),
3008          (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$src), VSFRC)>;
3009def : Pat<(f32 (fpround (f64 (extloadf32 xoaddr:$src)))),
3010          (f32 (XFLOADf32 xoaddr:$src))>;
3011def : Pat<(f64 (any_fpextend f32:$src)),
3012          (COPY_TO_REGCLASS $src, VSFRC)>;
3013
3014def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3015          (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3016def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3017          (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3018def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3019          (SELECT_VSSRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3020def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3021          (SELECT_VSSRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3022def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3023          (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;
3024def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3025          (SELECT_VSSRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3026def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3027          (SELECT_VSSRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3028def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3029          (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3030def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3031          (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3032def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3033          (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3034
3035// Additional fnmsub pattern for PPC specific ISD opcode
3036def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C),
3037          (XSNMSUBASP $C, $A, $B)>;
3038def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)),
3039          (XSMSUBASP $C, $A, $B)>;
3040def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)),
3041          (XSNMADDASP $C, $A, $B)>;
3042
3043// f32 neg
3044// Although XSNEGDP is available in P7, we want to select it starting from P8,
3045// so that FNMSUBS can be selected for fneg-fmsub pattern on P7. (VSX version,
3046// XSNMSUBASP, is available since P8)
3047def : Pat<(f32 (fneg f32:$S)),
3048          (f32 (COPY_TO_REGCLASS (XSNEGDP
3049               (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
3050
3051// Instructions for converting float to i32 feeding a store.
3052def : Pat<(PPCstore_scal_int_from_vsr
3053            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 4),
3054          (STIWX (XSCVDPSXWS f64:$src), xoaddr:$dst)>;
3055def : Pat<(PPCstore_scal_int_from_vsr
3056            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 4),
3057          (STIWX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
3058
3059def : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)),
3060          (v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC),
3061                         (COPY_TO_REGCLASS $src2, VRRC)))>;
3062def : Pat<(v2i64 (umax v2i64:$src1, v2i64:$src2)),
3063          (v2i64 (VMAXUD (COPY_TO_REGCLASS $src1, VRRC),
3064                         (COPY_TO_REGCLASS $src2, VRRC)))>;
3065def : Pat<(v2i64 (smin v2i64:$src1, v2i64:$src2)),
3066          (v2i64 (VMINSD (COPY_TO_REGCLASS $src1, VRRC),
3067                         (COPY_TO_REGCLASS $src2, VRRC)))>;
3068def : Pat<(v2i64 (umin v2i64:$src1, v2i64:$src2)),
3069          (v2i64 (VMINUD (COPY_TO_REGCLASS $src1, VRRC),
3070                         (COPY_TO_REGCLASS $src2, VRRC)))>;
3071
3072def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
3073          (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3074def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
3075          (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3076def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
3077          (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3078def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
3079          (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
3080} // HasVSX, HasP8Vector
3081
3082// Big endian Power8 VSX subtarget.
3083let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in {
3084def : Pat<DWToSPExtractConv.El0SS1,
3085          (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
3086def : Pat<DWToSPExtractConv.El1SS1,
3087          (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3088def : Pat<DWToSPExtractConv.El0US1,
3089          (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
3090def : Pat<DWToSPExtractConv.El1US1,
3091          (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3092
3093// v4f32 scalar <-> vector conversions (BE)
3094def : Pat<(v4f32 (scalar_to_vector f32:$A)),
3095          (v4f32 (XSCVDPSPN $A))>;
3096def : Pat<(f32 (vector_extract v4f32:$S, 0)),
3097          (f32 (XSCVSPDPN $S))>;
3098def : Pat<(f32 (vector_extract v4f32:$S, 1)),
3099          (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
3100def : Pat<(f32 (vector_extract v4f32:$S, 2)),
3101          (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
3102def : Pat<(f32 (vector_extract v4f32:$S, 3)),
3103          (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
3104def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
3105          (f32 VectorExtractions.BE_VARIABLE_FLOAT)>;
3106
3107def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3108          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;
3109def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3110          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;
3111def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3112          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;
3113def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3114          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;
3115def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3116          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
3117def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3118          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;
3119def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3120          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;
3121def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3122          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
3123
3124// LIWAX - This instruction is used for sign extending i32 -> i64.
3125// LIWZX - This instruction will be emitted for i32, f32, and when
3126//         zero-extending i32 to i64 (zext i32 -> i64).
3127def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))),
3128          (v2i64 (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC))>;
3129def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))),
3130          (v2i64 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC))>;
3131def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))),
3132          (v4i32 (XXSLDWIs
3133          (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>;
3134def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))),
3135          (v4f32 (XXSLDWIs
3136          (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>;
3137
3138def : Pat<DWToSPExtractConv.BVU,
3139          (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3),
3140                          (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>;
3141def : Pat<DWToSPExtractConv.BVS,
3142          (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3),
3143                          (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>;
3144def : Pat<(store (i32 (extractelt v4i32:$A, 1)), xoaddr:$src),
3145          (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3146def : Pat<(store (f32 (extractelt v4f32:$A, 1)), xoaddr:$src),
3147          (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3148
3149// Elements in a register on a BE system are in order <0, 1, 2, 3>.
3150// The store instructions store the second word from the left.
3151// So to align element zero, we need to modulo-left-shift by 3 words.
3152// Similar logic applies for elements 2 and 3.
3153foreach Idx = [ [0,3], [2,1], [3,2] ] in {
3154  def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), xoaddr:$src),
3155            (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3156                                   sub_64), xoaddr:$src)>;
3157  def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), xoaddr:$src),
3158            (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3159                                   sub_64), xoaddr:$src)>;
3160}
3161} // HasVSX, HasP8Vector, IsBigEndian
3162
3163// Little endian Power8 VSX subtarget.
3164let Predicates = [HasVSX, HasP8Vector, IsLittleEndian] in {
3165def : Pat<DWToSPExtractConv.El0SS1,
3166          (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3167def : Pat<DWToSPExtractConv.El1SS1,
3168          (f32 (XSCVSXDSP (COPY_TO_REGCLASS
3169                            (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;
3170def : Pat<DWToSPExtractConv.El0US1,
3171          (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
3172def : Pat<DWToSPExtractConv.El1US1,
3173          (f32 (XSCVUXDSP (COPY_TO_REGCLASS
3174                            (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;
3175
3176// v4f32 scalar <-> vector conversions (LE)
3177  // The permuted version is no better than the version that puts the value
3178  // into the right element because XSCVDPSPN is different from all the other
3179  // instructions used for PPCSToV.
3180  defm : ScalToVecWPermute<v4f32, (f32 f32:$A),
3181                           (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1),
3182                           (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 3)>;
3183def : Pat<(f32 (vector_extract v4f32:$S, 0)),
3184          (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
3185def : Pat<(f32 (vector_extract v4f32:$S, 1)),
3186          (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
3187def : Pat<(f32 (vector_extract v4f32:$S, 2)),
3188          (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
3189def : Pat<(f32 (vector_extract v4f32:$S, 3)),
3190          (f32 (XSCVSPDPN $S))>;
3191def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
3192          (f32 VectorExtractions.LE_VARIABLE_FLOAT)>;
3193
3194def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3195          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;
3196def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3197          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;
3198def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3199          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;
3200def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3201          (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;
3202def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
3203          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
3204def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
3205          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;
3206def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
3207          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;
3208def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
3209          (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
3210
3211// LIWAX - This instruction is used for sign extending i32 -> i64.
3212// LIWZX - This instruction will be emitted for i32, f32, and when
3213//         zero-extending i32 to i64 (zext i32 -> i64).
3214defm : ScalToVecWPermute<
3215  v2i64, (i64 (sextloadi32 xoaddr:$src)),
3216  (XXPERMDIs (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSFRC), 2),
3217  (SUBREG_TO_REG (i64 1), (LIWAX xoaddr:$src), sub_64)>;
3218
3219defm : ScalToVecWPermute<
3220  v2i64, (i64 (zextloadi32 xoaddr:$src)),
3221  (XXPERMDIs (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2),
3222  (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>;
3223
3224defm : ScalToVecWPermute<
3225  v4i32, (i32 (load xoaddr:$src)),
3226  (XXPERMDIs (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2),
3227  (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>;
3228
3229defm : ScalToVecWPermute<
3230  v4f32, (f32 (load xoaddr:$src)),
3231  (XXPERMDIs (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2),
3232  (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>;
3233
3234def : Pat<DWToSPExtractConv.BVU,
3235          (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3),
3236                          (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>;
3237def : Pat<DWToSPExtractConv.BVS,
3238          (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3),
3239                          (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>;
3240def : Pat<(store (i32 (extractelt v4i32:$A, 2)), xoaddr:$src),
3241          (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3242def : Pat<(store (f32 (extractelt v4f32:$A, 2)), xoaddr:$src),
3243          (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3244
3245// Elements in a register on a LE system are in order <3, 2, 1, 0>.
3246// The store instructions store the second word from the left.
3247// So to align element 3, we need to modulo-left-shift by 3 words.
3248// Similar logic applies for elements 0 and 1.
3249foreach Idx = [ [0,2], [1,1], [3,3] ] in {
3250  def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), xoaddr:$src),
3251            (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3252                                   sub_64), xoaddr:$src)>;
3253  def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), xoaddr:$src),
3254            (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))),
3255                                   sub_64), xoaddr:$src)>;
3256}
3257} // HasVSX, HasP8Vector, IsLittleEndian
3258
3259// Big endian pre-Power9 VSX subtarget.
3260let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian] in {
3261def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xoaddr:$src),
3262          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3263def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xoaddr:$src),
3264          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3265def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xoaddr:$src),
3266          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3267                      xoaddr:$src)>;
3268def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xoaddr:$src),
3269          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3270                      xoaddr:$src)>;
3271} // HasVSX, HasP8Vector, NoP9Vector, IsBigEndian
3272
3273// Little endian pre-Power9 VSX subtarget.
3274let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] in {
3275def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xoaddr:$src),
3276          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3277                      xoaddr:$src)>;
3278def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xoaddr:$src),
3279          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
3280                      xoaddr:$src)>;
3281def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xoaddr:$src),
3282          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3283def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xoaddr:$src),
3284          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>;
3285} // HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian
3286
3287// Any VSX target with direct moves.
3288let Predicates = [HasVSX, HasDirectMove] in {
3289// bitconvert f32 -> i32
3290// (convert to 32-bit fp single, shift right 1 word, move to GPR)
3291def : Pat<(i32 (bitconvert f32:$S)),
3292          (i32 (MFVSRWZ (EXTRACT_SUBREG
3293                          (XXSLDWI (XSCVDPSPN $S), (XSCVDPSPN $S), 3),
3294                          sub_64)))>;
3295// bitconvert i32 -> f32
3296// (move to FPR, shift left 1 word, convert to 64-bit fp single)
3297def : Pat<(f32 (bitconvert i32:$A)),
3298          (f32 (XSCVSPDPN
3299                 (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>;
3300
3301// bitconvert f64 -> i64
3302// (move to GPR, nothing else needed)
3303def : Pat<(i64 (bitconvert f64:$S)),
3304          (i64 (MFVSRD $S))>;
3305
3306// bitconvert i64 -> f64
3307// (move to FPR, nothing else needed)
3308def : Pat<(f64 (bitconvert i64:$S)),
3309          (f64 (MTVSRD $S))>;
3310
3311// Rounding to integer.
3312def : Pat<(i64 (lrint f64:$S)),
3313          (i64 (MFVSRD (FCTID $S)))>;
3314def : Pat<(i64 (lrint f32:$S)),
3315          (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;
3316def : Pat<(i64 (llrint f64:$S)),
3317          (i64 (MFVSRD (FCTID $S)))>;
3318def : Pat<(i64 (llrint f32:$S)),
3319          (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>;
3320def : Pat<(i64 (lround f64:$S)),
3321          (i64 (MFVSRD (FCTID (XSRDPI $S))))>;
3322def : Pat<(i64 (lround f32:$S)),
3323          (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;
3324def : Pat<(i64 (llround f64:$S)),
3325          (i64 (MFVSRD (FCTID (XSRDPI $S))))>;
3326def : Pat<(i64 (llround f32:$S)),
3327          (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>;
3328
3329// Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead
3330// of f64
3331def : Pat<(v8i16 (PPCmtvsrz i32:$A)),
3332          (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;
3333def : Pat<(v16i8 (PPCmtvsrz i32:$A)),
3334          (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>;
3335
3336// Endianness-neutral constant splat on P8 and newer targets. The reason
3337// for this pattern is that on targets with direct moves, we don't expand
3338// BUILD_VECTOR nodes for v4i32.
3339def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,
3340                               immSExt5NonZero:$A, immSExt5NonZero:$A)),
3341          (v4i32 (VSPLTISW imm:$A))>;
3342} // HasVSX, HasDirectMove
3343
3344// Big endian VSX subtarget with direct moves.
3345let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in {
3346// v16i8 scalar <-> vector conversions (BE)
3347def : Pat<(v16i8 (scalar_to_vector i32:$A)),
3348          (v16i8 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64))>;
3349def : Pat<(v8i16 (scalar_to_vector i32:$A)),
3350          (v8i16 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64))>;
3351def : Pat<(v4i32 (scalar_to_vector i32:$A)),
3352          (v4i32 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64))>;
3353def : Pat<(v2i64 (scalar_to_vector i64:$A)),
3354          (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>;
3355
3356// v2i64 scalar <-> vector conversions (BE)
3357def : Pat<(i64 (vector_extract v2i64:$S, 0)),
3358          (i64 VectorExtractions.LE_DWORD_1)>;
3359def : Pat<(i64 (vector_extract v2i64:$S, 1)),
3360          (i64 VectorExtractions.LE_DWORD_0)>;
3361def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
3362          (i64 VectorExtractions.BE_VARIABLE_DWORD)>;
3363} // HasVSX, HasDirectMove, IsBigEndian
3364
3365// Little endian VSX subtarget with direct moves.
3366let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in {
3367  // v16i8 scalar <-> vector conversions (LE)
3368  defm : ScalToVecWPermute<v16i8, (i32 i32:$A),
3369                           (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC),
3370                           (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>;
3371  defm : ScalToVecWPermute<v8i16, (i32 i32:$A),
3372                           (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC),
3373                           (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>;
3374  defm : ScalToVecWPermute<v4i32, (i32 i32:$A), MovesToVSR.LE_WORD_0,
3375                           (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
3376  defm : ScalToVecWPermute<v2i64, (i64 i64:$A), MovesToVSR.LE_DWORD_0,
3377                           MovesToVSR.LE_DWORD_1>;
3378
3379  // v2i64 scalar <-> vector conversions (LE)
3380  def : Pat<(i64 (vector_extract v2i64:$S, 0)),
3381            (i64 VectorExtractions.LE_DWORD_0)>;
3382  def : Pat<(i64 (vector_extract v2i64:$S, 1)),
3383            (i64 VectorExtractions.LE_DWORD_1)>;
3384  def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
3385            (i64 VectorExtractions.LE_VARIABLE_DWORD)>;
3386} // HasVSX, HasDirectMove, IsLittleEndian
3387
3388// Big endian pre-P9 VSX subtarget with direct moves.
3389let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] in {
3390def : Pat<(i32 (vector_extract v16i8:$S, 0)),
3391          (i32 VectorExtractions.LE_BYTE_15)>;
3392def : Pat<(i32 (vector_extract v16i8:$S, 1)),
3393          (i32 VectorExtractions.LE_BYTE_14)>;
3394def : Pat<(i32 (vector_extract v16i8:$S, 2)),
3395          (i32 VectorExtractions.LE_BYTE_13)>;
3396def : Pat<(i32 (vector_extract v16i8:$S, 3)),
3397          (i32 VectorExtractions.LE_BYTE_12)>;
3398def : Pat<(i32 (vector_extract v16i8:$S, 4)),
3399          (i32 VectorExtractions.LE_BYTE_11)>;
3400def : Pat<(i32 (vector_extract v16i8:$S, 5)),
3401          (i32 VectorExtractions.LE_BYTE_10)>;
3402def : Pat<(i32 (vector_extract v16i8:$S, 6)),
3403          (i32 VectorExtractions.LE_BYTE_9)>;
3404def : Pat<(i32 (vector_extract v16i8:$S, 7)),
3405          (i32 VectorExtractions.LE_BYTE_8)>;
3406def : Pat<(i32 (vector_extract v16i8:$S, 8)),
3407          (i32 VectorExtractions.LE_BYTE_7)>;
3408def : Pat<(i32 (vector_extract v16i8:$S, 9)),
3409          (i32 VectorExtractions.LE_BYTE_6)>;
3410def : Pat<(i32 (vector_extract v16i8:$S, 10)),
3411          (i32 VectorExtractions.LE_BYTE_5)>;
3412def : Pat<(i32 (vector_extract v16i8:$S, 11)),
3413          (i32 VectorExtractions.LE_BYTE_4)>;
3414def : Pat<(i32 (vector_extract v16i8:$S, 12)),
3415          (i32 VectorExtractions.LE_BYTE_3)>;
3416def : Pat<(i32 (vector_extract v16i8:$S, 13)),
3417          (i32 VectorExtractions.LE_BYTE_2)>;
3418def : Pat<(i32 (vector_extract v16i8:$S, 14)),
3419          (i32 VectorExtractions.LE_BYTE_1)>;
3420def : Pat<(i32 (vector_extract v16i8:$S, 15)),
3421          (i32 VectorExtractions.LE_BYTE_0)>;
3422def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
3423          (i32 VectorExtractions.BE_VARIABLE_BYTE)>;
3424
3425// v8i16 scalar <-> vector conversions (BE)
3426def : Pat<(i32 (vector_extract v8i16:$S, 0)),
3427          (i32 VectorExtractions.LE_HALF_7)>;
3428def : Pat<(i32 (vector_extract v8i16:$S, 1)),
3429          (i32 VectorExtractions.LE_HALF_6)>;
3430def : Pat<(i32 (vector_extract v8i16:$S, 2)),
3431          (i32 VectorExtractions.LE_HALF_5)>;
3432def : Pat<(i32 (vector_extract v8i16:$S, 3)),
3433          (i32 VectorExtractions.LE_HALF_4)>;
3434def : Pat<(i32 (vector_extract v8i16:$S, 4)),
3435          (i32 VectorExtractions.LE_HALF_3)>;
3436def : Pat<(i32 (vector_extract v8i16:$S, 5)),
3437          (i32 VectorExtractions.LE_HALF_2)>;
3438def : Pat<(i32 (vector_extract v8i16:$S, 6)),
3439          (i32 VectorExtractions.LE_HALF_1)>;
3440def : Pat<(i32 (vector_extract v8i16:$S, 7)),
3441          (i32 VectorExtractions.LE_HALF_0)>;
3442def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
3443          (i32 VectorExtractions.BE_VARIABLE_HALF)>;
3444
3445// v4i32 scalar <-> vector conversions (BE)
3446def : Pat<(i32 (vector_extract v4i32:$S, 0)),
3447          (i32 VectorExtractions.LE_WORD_3)>;
3448def : Pat<(i32 (vector_extract v4i32:$S, 1)),
3449          (i32 VectorExtractions.LE_WORD_2)>;
3450def : Pat<(i32 (vector_extract v4i32:$S, 2)),
3451          (i32 VectorExtractions.LE_WORD_1)>;
3452def : Pat<(i32 (vector_extract v4i32:$S, 3)),
3453          (i32 VectorExtractions.LE_WORD_0)>;
3454def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
3455          (i32 VectorExtractions.BE_VARIABLE_WORD)>;
3456} // HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian
3457
3458// Little endian pre-P9 VSX subtarget with direct moves.
3459let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] in {
3460def : Pat<(i32 (vector_extract v16i8:$S, 0)),
3461          (i32 VectorExtractions.LE_BYTE_0)>;
3462def : Pat<(i32 (vector_extract v16i8:$S, 1)),
3463          (i32 VectorExtractions.LE_BYTE_1)>;
3464def : Pat<(i32 (vector_extract v16i8:$S, 2)),
3465          (i32 VectorExtractions.LE_BYTE_2)>;
3466def : Pat<(i32 (vector_extract v16i8:$S, 3)),
3467          (i32 VectorExtractions.LE_BYTE_3)>;
3468def : Pat<(i32 (vector_extract v16i8:$S, 4)),
3469          (i32 VectorExtractions.LE_BYTE_4)>;
3470def : Pat<(i32 (vector_extract v16i8:$S, 5)),
3471          (i32 VectorExtractions.LE_BYTE_5)>;
3472def : Pat<(i32 (vector_extract v16i8:$S, 6)),
3473          (i32 VectorExtractions.LE_BYTE_6)>;
3474def : Pat<(i32 (vector_extract v16i8:$S, 7)),
3475          (i32 VectorExtractions.LE_BYTE_7)>;
3476def : Pat<(i32 (vector_extract v16i8:$S, 8)),
3477          (i32 VectorExtractions.LE_BYTE_8)>;
3478def : Pat<(i32 (vector_extract v16i8:$S, 9)),
3479          (i32 VectorExtractions.LE_BYTE_9)>;
3480def : Pat<(i32 (vector_extract v16i8:$S, 10)),
3481          (i32 VectorExtractions.LE_BYTE_10)>;
3482def : Pat<(i32 (vector_extract v16i8:$S, 11)),
3483          (i32 VectorExtractions.LE_BYTE_11)>;
3484def : Pat<(i32 (vector_extract v16i8:$S, 12)),
3485          (i32 VectorExtractions.LE_BYTE_12)>;
3486def : Pat<(i32 (vector_extract v16i8:$S, 13)),
3487          (i32 VectorExtractions.LE_BYTE_13)>;
3488def : Pat<(i32 (vector_extract v16i8:$S, 14)),
3489          (i32 VectorExtractions.LE_BYTE_14)>;
3490def : Pat<(i32 (vector_extract v16i8:$S, 15)),
3491          (i32 VectorExtractions.LE_BYTE_15)>;
3492def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
3493          (i32 VectorExtractions.LE_VARIABLE_BYTE)>;
3494
3495// v8i16 scalar <-> vector conversions (LE)
3496def : Pat<(i32 (vector_extract v8i16:$S, 0)),
3497          (i32 VectorExtractions.LE_HALF_0)>;
3498def : Pat<(i32 (vector_extract v8i16:$S, 1)),
3499          (i32 VectorExtractions.LE_HALF_1)>;
3500def : Pat<(i32 (vector_extract v8i16:$S, 2)),
3501          (i32 VectorExtractions.LE_HALF_2)>;
3502def : Pat<(i32 (vector_extract v8i16:$S, 3)),
3503          (i32 VectorExtractions.LE_HALF_3)>;
3504def : Pat<(i32 (vector_extract v8i16:$S, 4)),
3505          (i32 VectorExtractions.LE_HALF_4)>;
3506def : Pat<(i32 (vector_extract v8i16:$S, 5)),
3507          (i32 VectorExtractions.LE_HALF_5)>;
3508def : Pat<(i32 (vector_extract v8i16:$S, 6)),
3509          (i32 VectorExtractions.LE_HALF_6)>;
3510def : Pat<(i32 (vector_extract v8i16:$S, 7)),
3511          (i32 VectorExtractions.LE_HALF_7)>;
3512def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
3513          (i32 VectorExtractions.LE_VARIABLE_HALF)>;
3514
3515// v4i32 scalar <-> vector conversions (LE)
3516def : Pat<(i32 (vector_extract v4i32:$S, 0)),
3517          (i32 VectorExtractions.LE_WORD_0)>;
3518def : Pat<(i32 (vector_extract v4i32:$S, 1)),
3519          (i32 VectorExtractions.LE_WORD_1)>;
3520def : Pat<(i32 (vector_extract v4i32:$S, 2)),
3521          (i32 VectorExtractions.LE_WORD_2)>;
3522def : Pat<(i32 (vector_extract v4i32:$S, 3)),
3523          (i32 VectorExtractions.LE_WORD_3)>;
3524def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
3525          (i32 VectorExtractions.LE_VARIABLE_WORD)>;
3526} // HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian
3527
3528// Big endian pre-Power9 VSX subtarget that has direct moves.
3529let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian] in {
3530// Big endian integer vectors using direct moves.
3531def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),
3532          (v2i64 (XXPERMDI
3533                    (COPY_TO_REGCLASS (MTVSRD $A), VSRC),
3534                    (COPY_TO_REGCLASS (MTVSRD $B), VSRC), 0))>;
3535def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
3536          (XXPERMDI
3537            (COPY_TO_REGCLASS
3538              (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), VSRC),
3539            (COPY_TO_REGCLASS
3540              (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), VSRC), 0)>;
3541def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
3542          (XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
3543} // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian
3544
3545// Little endian pre-Power9 VSX subtarget that has direct moves.
3546let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in {
3547// Little endian integer vectors using direct moves.
3548def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),
3549          (v2i64 (XXPERMDI
3550                    (COPY_TO_REGCLASS (MTVSRD $B), VSRC),
3551                    (COPY_TO_REGCLASS (MTVSRD $A), VSRC), 0))>;
3552def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
3553          (XXPERMDI
3554            (COPY_TO_REGCLASS
3555              (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), VSRC),
3556            (COPY_TO_REGCLASS
3557              (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), VSRC), 0)>;
3558def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
3559          (XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
3560}
3561
3562// Any Power9 VSX subtarget.
3563let Predicates = [HasVSX, HasP9Vector] in {
3564// Additional fnmsub pattern for PPC specific ISD opcode
3565def : Pat<(PPCfnmsub f128:$A, f128:$B, f128:$C),
3566          (XSNMSUBQP $C, $A, $B)>;
3567def : Pat<(fneg (PPCfnmsub f128:$A, f128:$B, f128:$C)),
3568          (XSMSUBQP $C, $A, $B)>;
3569def : Pat<(PPCfnmsub f128:$A, f128:$B, (fneg f128:$C)),
3570          (XSNMADDQP $C, $A, $B)>;
3571
3572def : Pat<(f128 (sint_to_fp i64:$src)),
3573          (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
3574def : Pat<(f128 (sint_to_fp (i64 (PPCmfvsr f64:$src)))),
3575          (f128 (XSCVSDQP $src))>;
3576def : Pat<(f128 (sint_to_fp (i32 (PPCmfvsr f64:$src)))),
3577          (f128 (XSCVSDQP (VEXTSW2Ds $src)))>;
3578def : Pat<(f128 (uint_to_fp i64:$src)),
3579          (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
3580def : Pat<(f128 (uint_to_fp (i64 (PPCmfvsr f64:$src)))),
3581          (f128 (XSCVUDQP $src))>;
3582
3583// Convert (Un)Signed Word -> QP.
3584def : Pat<(f128 (sint_to_fp i32:$src)),
3585          (f128 (XSCVSDQP (MTVSRWA $src)))>;
3586def : Pat<(f128 (sint_to_fp (i32 (load xoaddr:$src)))),
3587          (f128 (XSCVSDQP (LIWAX xoaddr:$src)))>;
3588def : Pat<(f128 (uint_to_fp i32:$src)),
3589          (f128 (XSCVUDQP (MTVSRWZ $src)))>;
3590def : Pat<(f128 (uint_to_fp (i32 (load xoaddr:$src)))),
3591          (f128 (XSCVUDQP (LIWZX xoaddr:$src)))>;
3592
3593// Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a
3594// separate pattern so that it can convert the input register class from
3595// VRRC(v8i16) to VSRC.
3596def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)),
3597          (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>;
3598
3599// Use current rounding mode
3600def : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>;
3601// Round to nearest, ties away from zero
3602def : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>;
3603// Round towards Zero
3604def : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>;
3605// Round towards +Inf
3606def : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>;
3607// Round towards -Inf
3608def : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>;
3609// Use current rounding mode, [with Inexact]
3610def : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>;
3611
3612def : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)),
3613          (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>;
3614
3615def : Pat<(i64 (int_ppc_scalar_extract_expq  f128:$vA)),
3616          (i64 (MFVSRD (EXTRACT_SUBREG
3617                          (v2i64 (XSXEXPQP $vA)), sub_64)))>;
3618
3619// Extra patterns expanding to vector Extract Word/Insert Word
3620def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)),
3621          (v4i32 (XXINSERTW $A, $B, imm:$IMM))>;
3622def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),
3623          (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;
3624
3625// Vector Reverse
3626def : Pat<(v8i16 (bswap v8i16 :$A)),
3627          (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
3628def : Pat<(v1i128 (bswap v1i128 :$A)),
3629          (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
3630
3631// D-Form Load/Store
3632def : Pat<(v4i32 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>;
3633def : Pat<(v4f32 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>;
3634def : Pat<(v2i64 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>;
3635def : Pat<(v2f64 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>;
3636def : Pat<(f128  (quadwOffsetLoad iaddrX16:$src)),
3637          (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>;
3638def : Pat<(v4i32 (int_ppc_vsx_lxvw4x iaddrX16:$src)), (LXV memrix16:$src)>;
3639def : Pat<(v2f64 (int_ppc_vsx_lxvd2x iaddrX16:$src)), (LXV memrix16:$src)>;
3640
3641def : Pat<(quadwOffsetStore v4f32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>;
3642def : Pat<(quadwOffsetStore v4i32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>;
3643def : Pat<(quadwOffsetStore v2f64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>;
3644def : Pat<(quadwOffsetStore  f128:$rS, iaddrX16:$dst),
3645          (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>;
3646def : Pat<(quadwOffsetStore v2i64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>;
3647def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, iaddrX16:$dst),
3648          (STXV $rS, memrix16:$dst)>;
3649def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, iaddrX16:$dst),
3650          (STXV $rS, memrix16:$dst)>;
3651
3652def : Pat<(v2f64 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>;
3653def : Pat<(v2i64 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>;
3654def : Pat<(v4f32 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>;
3655def : Pat<(v4i32 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>;
3656def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVX xoaddr:$src)>;
3657def : Pat<(v2f64 (int_ppc_vsx_lxvd2x xoaddr:$src)), (LXVX xoaddr:$src)>;
3658def : Pat<(f128  (nonQuadwOffsetLoad xoaddr:$src)),
3659          (COPY_TO_REGCLASS (LXVX xoaddr:$src), VRRC)>;
3660def : Pat<(nonQuadwOffsetStore f128:$rS, xoaddr:$dst),
3661          (STXVX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
3662def : Pat<(nonQuadwOffsetStore v2f64:$rS, xoaddr:$dst),
3663          (STXVX $rS, xoaddr:$dst)>;
3664def : Pat<(nonQuadwOffsetStore v2i64:$rS, xoaddr:$dst),
3665          (STXVX $rS, xoaddr:$dst)>;
3666def : Pat<(nonQuadwOffsetStore v4f32:$rS, xoaddr:$dst),
3667          (STXVX $rS, xoaddr:$dst)>;
3668def : Pat<(nonQuadwOffsetStore v4i32:$rS, xoaddr:$dst),
3669          (STXVX $rS, xoaddr:$dst)>;
3670def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
3671          (STXVX $rS, xoaddr:$dst)>;
3672def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
3673          (STXVX $rS, xoaddr:$dst)>;
3674
3675// Build vectors from i8 loads
3676defm : ScalToVecWPermute<v16i8, ScalarLoads.Li8,
3677                         (VSPLTBs 7, (LXSIBZX xoaddr:$src)),
3678                         (VSPLTBs 7, (LXSIBZX xoaddr:$src))>;
3679defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,
3680                         (VSPLTHs 3, (LXSIBZX xoaddr:$src)),
3681                         (VSPLTHs 3, (LXSIBZX xoaddr:$src))>;
3682defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,
3683                         (XXSPLTWs (LXSIBZX xoaddr:$src), 1),
3684                         (XXSPLTWs (LXSIBZX xoaddr:$src), 1)>;
3685defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,
3686                         (XXPERMDIs (LXSIBZX xoaddr:$src), 0),
3687                         (XXPERMDIs (LXSIBZX xoaddr:$src), 0)>;
3688defm : ScalToVecWPermute<v4i32, ScalarLoads.SELi8,
3689                         (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1),
3690                         (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1)>;
3691defm : ScalToVecWPermute<v2i64, ScalarLoads.SELi8i64,
3692                         (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0),
3693                         (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0)>;
3694
3695// Build vectors from i16 loads
3696defm : ScalToVecWPermute<v8i16, ScalarLoads.Li16,
3697                         (VSPLTHs 3, (LXSIHZX xoaddr:$src)),
3698                         (VSPLTHs 3, (LXSIHZX xoaddr:$src))>;
3699defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi16,
3700                         (XXSPLTWs (LXSIHZX xoaddr:$src), 1),
3701                         (XXSPLTWs (LXSIHZX xoaddr:$src), 1)>;
3702defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi16i64,
3703                         (XXPERMDIs (LXSIHZX xoaddr:$src), 0),
3704                         (XXPERMDIs (LXSIHZX xoaddr:$src), 0)>;
3705defm : ScalToVecWPermute<v4i32, ScalarLoads.SELi16,
3706                         (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1),
3707                         (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1)>;
3708defm : ScalToVecWPermute<v2i64, ScalarLoads.SELi16i64,
3709                         (XXPERMDIs (VEXTSH2Ds (LXSIHZX xoaddr:$src)), 0),
3710                         (XXPERMDIs (VEXTSH2Ds (LXSIHZX xoaddr:$src)), 0)>;
3711
3712// Load/convert and convert/store patterns for f16.
3713def : Pat<(f64 (extloadf16 xoaddr:$src)),
3714          (f64 (XSCVHPDP (LXSIHZX xoaddr:$src)))>;
3715def : Pat<(truncstoref16 f64:$src, xoaddr:$dst),
3716          (STXSIHX (XSCVDPHP $src), xoaddr:$dst)>;
3717def : Pat<(f32 (extloadf16 xoaddr:$src)),
3718          (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX xoaddr:$src)), VSSRC))>;
3719def : Pat<(truncstoref16 f32:$src, xoaddr:$dst),
3720          (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), xoaddr:$dst)>;
3721def : Pat<(f64 (f16_to_fp i32:$A)),
3722          (f64 (XSCVHPDP (MTVSRWZ $A)))>;
3723def : Pat<(f32 (f16_to_fp i32:$A)),
3724          (f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>;
3725def : Pat<(i32 (fp_to_f16 f32:$A)),
3726          (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>;
3727def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>;
3728
3729// Vector sign extensions
3730def : Pat<(f64 (PPCVexts f64:$A, 1)),
3731          (f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>;
3732def : Pat<(f64 (PPCVexts f64:$A, 2)),
3733          (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>;
3734
3735def : Pat<(f64 (extloadf32 iaddrX4:$src)),
3736          (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$src), VSFRC)>;
3737def : Pat<(f32 (fpround (f64 (extloadf32 iaddrX4:$src)))),
3738          (f32 (DFLOADf32 iaddrX4:$src))>;
3739
3740def : Pat<(v4f32 (PPCldvsxlh xaddr:$src)),
3741          (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC)>;
3742def : Pat<(v4f32 (PPCldvsxlh iaddrX4:$src)),
3743          (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC)>;
3744
3745// Convert (Un)Signed DWord in memory -> QP
3746def : Pat<(f128 (sint_to_fp (i64 (load xaddrX4:$src)))),
3747          (f128 (XSCVSDQP (LXSDX xaddrX4:$src)))>;
3748def : Pat<(f128 (sint_to_fp (i64 (load iaddrX4:$src)))),
3749          (f128 (XSCVSDQP (LXSD iaddrX4:$src)))>;
3750def : Pat<(f128 (uint_to_fp (i64 (load xaddrX4:$src)))),
3751          (f128 (XSCVUDQP (LXSDX xaddrX4:$src)))>;
3752def : Pat<(f128 (uint_to_fp (i64 (load iaddrX4:$src)))),
3753          (f128 (XSCVUDQP (LXSD iaddrX4:$src)))>;
3754
3755// Convert Unsigned HWord in memory -> QP
3756def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)),
3757          (f128 (XSCVUDQP (LXSIHZX xaddr:$src)))>;
3758
3759// Convert Unsigned Byte in memory -> QP
3760def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),
3761          (f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>;
3762
3763// Truncate & Convert QP -> (Un)Signed (D)Word.
3764def : Pat<(i64 (fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;
3765def : Pat<(i64 (fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;
3766def : Pat<(i32 (fp_to_sint f128:$src)),
3767          (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;
3768def : Pat<(i32 (fp_to_uint f128:$src)),
3769          (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;
3770
3771// Instructions for store(fptosi).
3772// The 8-byte version is repeated here due to availability of D-Form STXSD.
3773def : Pat<(PPCstore_scal_int_from_vsr
3774            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xaddrX4:$dst, 8),
3775          (STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
3776                  xaddrX4:$dst)>;
3777def : Pat<(PPCstore_scal_int_from_vsr
3778            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), iaddrX4:$dst, 8),
3779          (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
3780                 iaddrX4:$dst)>;
3781def : Pat<(PPCstore_scal_int_from_vsr
3782            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 4),
3783          (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>;
3784def : Pat<(PPCstore_scal_int_from_vsr
3785            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 2),
3786          (STXSIHX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>;
3787def : Pat<(PPCstore_scal_int_from_vsr
3788            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 1),
3789          (STXSIBX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>;
3790def : Pat<(PPCstore_scal_int_from_vsr
3791            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xaddrX4:$dst, 8),
3792          (STXSDX (XSCVDPSXDS f64:$src), xaddrX4:$dst)>;
3793def : Pat<(PPCstore_scal_int_from_vsr
3794            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), iaddrX4:$dst, 8),
3795          (STXSD (XSCVDPSXDS f64:$src), iaddrX4:$dst)>;
3796def : Pat<(PPCstore_scal_int_from_vsr
3797            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 2),
3798          (STXSIHX (XSCVDPSXWS f64:$src), xoaddr:$dst)>;
3799def : Pat<(PPCstore_scal_int_from_vsr
3800            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 1),
3801          (STXSIBX (XSCVDPSXWS f64:$src), xoaddr:$dst)>;
3802
3803// Instructions for store(fptoui).
3804def : Pat<(PPCstore_scal_int_from_vsr
3805            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xaddrX4:$dst, 8),
3806          (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
3807                  xaddrX4:$dst)>;
3808def : Pat<(PPCstore_scal_int_from_vsr
3809            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), iaddrX4:$dst, 8),
3810          (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
3811                 iaddrX4:$dst)>;
3812def : Pat<(PPCstore_scal_int_from_vsr
3813            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 4),
3814          (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;
3815def : Pat<(PPCstore_scal_int_from_vsr
3816            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 2),
3817          (STXSIHX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;
3818def : Pat<(PPCstore_scal_int_from_vsr
3819            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 1),
3820          (STXSIBX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;
3821def : Pat<(PPCstore_scal_int_from_vsr
3822            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xaddrX4:$dst, 8),
3823          (STXSDX (XSCVDPUXDS f64:$src), xaddrX4:$dst)>;
3824def : Pat<(PPCstore_scal_int_from_vsr
3825            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), iaddrX4:$dst, 8),
3826          (STXSD (XSCVDPUXDS f64:$src), iaddrX4:$dst)>;
3827def : Pat<(PPCstore_scal_int_from_vsr
3828            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 2),
3829          (STXSIHX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
3830def : Pat<(PPCstore_scal_int_from_vsr
3831            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 1),
3832          (STXSIBX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
3833
3834// Round & Convert QP -> DP/SP
3835def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>;
3836def : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
3837
3838// Convert SP -> QP
3839def : Pat<(f128 (any_fpextend f32:$src)),
3840          (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>;
3841
3842def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)),
3843          (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC),
3844                                           (COPY_TO_REGCLASS $XB, VSSRC)),
3845                                 VSSRC))>;
3846def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)),
3847          (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC),
3848                                           (COPY_TO_REGCLASS $XB, VSSRC)),
3849                                 VSSRC))>;
3850
3851// Endianness-neutral patterns for const splats with ISA 3.0 instructions.
3852defm : ScalToVecWPermute<v4i32, (i32 i32:$A), (MTVSRWS $A), (MTVSRWS $A)>;
3853def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
3854          (v4i32 (MTVSRWS $A))>;
3855def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3856                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3857                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3858                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3859                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3860                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3861                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
3862                               immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)),
3863          (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
3864defm : ScalToVecWPermute<v4i32, FltToIntLoad.A,
3865                         (XVCVSPSXWS (LXVWSX xoaddr:$A)),
3866                         (XVCVSPSXWS (LXVWSX xoaddr:$A))>;
3867defm : ScalToVecWPermute<v4i32, FltToUIntLoad.A,
3868                         (XVCVSPUXWS (LXVWSX xoaddr:$A)),
3869                         (XVCVSPUXWS (LXVWSX xoaddr:$A))>;
3870defm : ScalToVecWPermute<
3871  v4i32, DblToIntLoadP9.A,
3872  (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1),
3873  (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), sub_64)>;
3874defm : ScalToVecWPermute<
3875  v4i32, DblToUIntLoadP9.A,
3876  (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1),
3877  (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 iaddrX4:$A)), sub_64)>;
3878defm : ScalToVecWPermute<
3879  v2i64, FltToLongLoadP9.A,
3880  (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), 0),
3881  (SUBREG_TO_REG
3882     (i64 1),
3883     (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), sub_64)>;
3884defm : ScalToVecWPermute<
3885  v2i64, FltToULongLoadP9.A,
3886  (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), 0),
3887  (SUBREG_TO_REG
3888     (i64 1),
3889     (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), sub_64)>;
3890def : Pat<(v4f32 (PPCldsplat xoaddr:$A)),
3891          (v4f32 (LXVWSX xoaddr:$A))>;
3892def : Pat<(v4i32 (PPCldsplat xoaddr:$A)),
3893          (v4i32 (LXVWSX xoaddr:$A))>;
3894} // HasVSX, HasP9Vector
3895
3896// Big endian Power9 subtarget.
3897let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in {
3898def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
3899          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
3900def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
3901          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
3902def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
3903          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;
3904def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
3905          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
3906def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
3907          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
3908def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
3909          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;
3910def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
3911          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;
3912def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
3913          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
3914def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
3915          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
3916def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
3917          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
3918def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
3919          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
3920def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
3921          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
3922def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
3923          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
3924def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
3925          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
3926def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
3927          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
3928def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
3929          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
3930
3931// Scalar stores of i8
3932def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), xoaddr:$dst),
3933          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), xoaddr:$dst)>;
3934def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), xoaddr:$dst),
3935          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
3936def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), xoaddr:$dst),
3937          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), xoaddr:$dst)>;
3938def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), xoaddr:$dst),
3939          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
3940def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), xoaddr:$dst),
3941          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), xoaddr:$dst)>;
3942def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), xoaddr:$dst),
3943          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
3944def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), xoaddr:$dst),
3945          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), xoaddr:$dst)>;
3946def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), xoaddr:$dst),
3947          (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
3948def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), xoaddr:$dst),
3949          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), xoaddr:$dst)>;
3950def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), xoaddr:$dst),
3951          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
3952def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), xoaddr:$dst),
3953          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), xoaddr:$dst)>;
3954def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), xoaddr:$dst),
3955          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
3956def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), xoaddr:$dst),
3957          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), xoaddr:$dst)>;
3958def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), xoaddr:$dst),
3959          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
3960def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), xoaddr:$dst),
3961          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), xoaddr:$dst)>;
3962def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), xoaddr:$dst),
3963          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
3964
3965// Scalar stores of i16
3966def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), xoaddr:$dst),
3967          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
3968def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), xoaddr:$dst),
3969          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
3970def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), xoaddr:$dst),
3971          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
3972def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), xoaddr:$dst),
3973          (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
3974def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), xoaddr:$dst),
3975          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
3976def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), xoaddr:$dst),
3977          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
3978def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), xoaddr:$dst),
3979          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
3980def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), xoaddr:$dst),
3981          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
3982
3983def : Pat<(v2i64 (scalar_to_vector (i64 (load iaddrX4:$src)))),
3984          (v2i64 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC))>;
3985def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddrX4:$src)))),
3986          (v2i64 (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC))>;
3987
3988def : Pat<(v2f64 (scalar_to_vector (f64 (load iaddrX4:$src)))),
3989          (v2f64 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC))>;
3990def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddrX4:$src)))),
3991          (v2f64 (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC))>;
3992def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xaddrX4:$src),
3993          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
3994                       sub_64), xaddrX4:$src)>;
3995def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xaddrX4:$src),
3996          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
3997                       sub_64), xaddrX4:$src)>;
3998def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xaddrX4:$src),
3999          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>;
4000def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xaddrX4:$src),
4001          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>;
4002def : Pat<(store (i64 (extractelt v2i64:$A, 1)), iaddrX4:$src),
4003          (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4004                       sub_64), iaddrX4:$src)>;
4005def : Pat<(store (f64 (extractelt v2f64:$A, 1)), iaddrX4:$src),
4006          (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4007                       sub_64), iaddrX4:$src)>;
4008def : Pat<(store (i64 (extractelt v2i64:$A, 0)), iaddrX4:$src),
4009          (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>;
4010def : Pat<(store (f64 (extractelt v2f64:$A, 0)), iaddrX4:$src),
4011          (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>;
4012
4013// (Un)Signed DWord vector extract -> QP
4014def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4015          (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4016def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4017          (f128 (XSCVSDQP
4018                  (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4019def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4020          (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4021def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4022          (f128 (XSCVUDQP
4023                  (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4024
4025// (Un)Signed Word vector extract -> QP
4026def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))),
4027          (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
4028foreach Idx = [0,2,3] in {
4029  def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
4030            (f128 (XSCVSDQP (EXTRACT_SUBREG
4031                            (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>;
4032}
4033foreach Idx = 0-3 in {
4034  def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
4035            (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;
4036}
4037
4038// (Un)Signed HWord vector extract -> QP
4039foreach Idx = 0-7 in {
4040  def : Pat<(f128 (sint_to_fp
4041                    (i32 (sext_inreg
4042                           (vector_extract v8i16:$src, Idx), i16)))),
4043          (f128 (XSCVSDQP (EXTRACT_SUBREG
4044                            (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
4045                            sub_64)))>;
4046  // The SDAG adds the `and` since an `i16` is being extracted as an `i32`.
4047  def : Pat<(f128 (uint_to_fp
4048                    (and (i32 (vector_extract v8i16:$src, Idx)), 65535))),
4049            (f128 (XSCVUDQP (EXTRACT_SUBREG
4050                              (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
4051}
4052
4053// (Un)Signed Byte vector extract -> QP
4054foreach Idx = 0-15 in {
4055  def : Pat<(f128 (sint_to_fp
4056                    (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
4057                                     i8)))),
4058            (f128 (XSCVSDQP (EXTRACT_SUBREG
4059                              (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>;
4060  def : Pat<(f128 (uint_to_fp
4061                    (and (i32 (vector_extract v16i8:$src, Idx)), 255))),
4062            (f128 (XSCVUDQP
4063                    (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>;
4064}
4065
4066// Unsiged int in vsx register -> QP
4067def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
4068          (f128 (XSCVUDQP
4069                  (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>;
4070} // HasVSX, HasP9Vector, IsBigEndian
4071
4072// Little endian Power9 subtarget.
4073let Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in {
4074def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
4075          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
4076def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
4077          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;
4078def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
4079          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
4080def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
4081          (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
4082def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
4083          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
4084def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
4085          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;
4086def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
4087          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;
4088def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
4089          (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
4090def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
4091          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
4092def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
4093          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
4094def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
4095          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
4096def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
4097          (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
4098def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
4099          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
4100def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
4101          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
4102def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
4103          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
4104def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
4105          (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
4106
4107def : Pat<(v8i16 (PPCld_vec_be xoaddr:$src)),
4108          (COPY_TO_REGCLASS (LXVH8X xoaddr:$src), VRRC)>;
4109def : Pat<(PPCst_vec_be v8i16:$rS, xoaddr:$dst),
4110          (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
4111
4112def : Pat<(v16i8 (PPCld_vec_be xoaddr:$src)),
4113          (COPY_TO_REGCLASS (LXVB16X xoaddr:$src), VRRC)>;
4114def : Pat<(PPCst_vec_be v16i8:$rS, xoaddr:$dst),
4115          (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>;
4116
4117// Scalar stores of i8
4118def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), xoaddr:$dst),
4119          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
4120def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), xoaddr:$dst),
4121          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), xoaddr:$dst)>;
4122def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), xoaddr:$dst),
4123          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
4124def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), xoaddr:$dst),
4125          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), xoaddr:$dst)>;
4126def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), xoaddr:$dst),
4127          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
4128def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), xoaddr:$dst),
4129          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), xoaddr:$dst)>;
4130def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), xoaddr:$dst),
4131          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
4132def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), xoaddr:$dst),
4133          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), xoaddr:$dst)>;
4134def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), xoaddr:$dst),
4135          (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
4136def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), xoaddr:$dst),
4137          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), xoaddr:$dst)>;
4138def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), xoaddr:$dst),
4139          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
4140def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), xoaddr:$dst),
4141          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), xoaddr:$dst)>;
4142def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), xoaddr:$dst),
4143          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
4144def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), xoaddr:$dst),
4145          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), xoaddr:$dst)>;
4146def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), xoaddr:$dst),
4147          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
4148def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), xoaddr:$dst),
4149          (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), xoaddr:$dst)>;
4150
4151// Scalar stores of i16
4152def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), xoaddr:$dst),
4153          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>;
4154def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), xoaddr:$dst),
4155          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>;
4156def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), xoaddr:$dst),
4157          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>;
4158def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), xoaddr:$dst),
4159          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>;
4160def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), xoaddr:$dst),
4161          (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>;
4162def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), xoaddr:$dst),
4163          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>;
4164def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), xoaddr:$dst),
4165          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>;
4166def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), xoaddr:$dst),
4167          (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>;
4168
4169defm : ScalToVecWPermute<
4170  v2i64, (i64 (load iaddrX4:$src)),
4171  (XXPERMDIs (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSFRC), 2),
4172  (SUBREG_TO_REG (i64 1), (DFLOADf64 iaddrX4:$src), sub_64)>;
4173defm : ScalToVecWPermute<
4174  v2i64, (i64 (load xaddrX4:$src)),
4175  (XXPERMDIs (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSFRC), 2),
4176  (SUBREG_TO_REG (i64 1), (XFLOADf64 xaddrX4:$src), sub_64)>;
4177defm : ScalToVecWPermute<
4178  v2f64, (f64 (load iaddrX4:$src)),
4179  (XXPERMDIs (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSFRC), 2),
4180  (SUBREG_TO_REG (i64 1), (DFLOADf64 iaddrX4:$src), sub_64)>;
4181defm : ScalToVecWPermute<
4182  v2f64, (f64 (load xaddrX4:$src)),
4183  (XXPERMDIs (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSFRC), 2),
4184  (SUBREG_TO_REG (i64 1), (XFLOADf64 xaddrX4:$src), sub_64)>;
4185
4186def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xaddrX4:$src),
4187          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4188                       sub_64), xaddrX4:$src)>;
4189def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xaddrX4:$src),
4190          (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4191                       sub_64), xaddrX4:$src)>;
4192def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xaddrX4:$src),
4193          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>;
4194def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xaddrX4:$src),
4195          (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>;
4196def : Pat<(store (i64 (extractelt v2i64:$A, 0)), iaddrX4:$src),
4197          (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
4198                       sub_64), iaddrX4:$src)>;
4199def : Pat<(store (f64 (extractelt v2f64:$A, 0)), iaddrX4:$src),
4200          (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64),
4201                      iaddrX4:$src)>;
4202def : Pat<(store (i64 (extractelt v2i64:$A, 1)), iaddrX4:$src),
4203          (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>;
4204def : Pat<(store (f64 (extractelt v2f64:$A, 1)), iaddrX4:$src),
4205          (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>;
4206
4207// (Un)Signed DWord vector extract -> QP
4208def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4209          (f128 (XSCVSDQP
4210                  (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4211def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4212          (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4213def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
4214          (f128 (XSCVUDQP
4215                  (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
4216def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
4217          (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
4218
4219// (Un)Signed Word vector extract -> QP
4220foreach Idx = [[0,3],[1,2],[3,0]] in {
4221  def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
4222            (f128 (XSCVSDQP (EXTRACT_SUBREG
4223                              (VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)),
4224                              sub_64)))>;
4225}
4226def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))),
4227          (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
4228
4229foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in {
4230  def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
4231            (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;
4232}
4233
4234// (Un)Signed HWord vector extract -> QP
4235// The Nested foreach lists identifies the vector element and corresponding
4236// register byte location.
4237foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in {
4238  def : Pat<(f128 (sint_to_fp
4239                    (i32 (sext_inreg
4240                           (vector_extract v8i16:$src, !head(Idx)), i16)))),
4241            (f128 (XSCVSDQP
4242                    (EXTRACT_SUBREG (VEXTSH2D
4243                                      (VEXTRACTUH !head(!tail(Idx)), $src)),
4244                                    sub_64)))>;
4245  def : Pat<(f128 (uint_to_fp
4246                    (and (i32 (vector_extract v8i16:$src, !head(Idx))),
4247                         65535))),
4248            (f128 (XSCVUDQP (EXTRACT_SUBREG
4249                              (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
4250}
4251
4252// (Un)Signed Byte vector extract -> QP
4253foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7],
4254               [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in {
4255  def : Pat<(f128 (sint_to_fp
4256                    (i32 (sext_inreg
4257                           (vector_extract v16i8:$src, !head(Idx)), i8)))),
4258            (f128 (XSCVSDQP
4259                    (EXTRACT_SUBREG
4260                      (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)),
4261                      sub_64)))>;
4262  def : Pat<(f128 (uint_to_fp
4263                    (and (i32 (vector_extract v16i8:$src, !head(Idx))),
4264                         255))),
4265            (f128 (XSCVUDQP
4266                    (EXTRACT_SUBREG
4267                      (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
4268}
4269
4270// Unsiged int in vsx register -> QP
4271def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
4272          (f128 (XSCVUDQP
4273                  (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>;
4274} // HasVSX, HasP9Vector, IsLittleEndian
4275
4276// Any Power9 VSX subtarget that supports Power9 Altivec.
4277let Predicates = [HasVSX, HasP9Altivec] in {
4278// Put this P9Altivec related definition here since it's possible to be
4279// selected to VSX instruction xvnegsp, avoid possible undef.
4280def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 0))),
4281          (v4i32 (VABSDUW $A, $B))>;
4282
4283def : Pat<(v8i16 (PPCvabsd v8i16:$A, v8i16:$B, (i32 0))),
4284          (v8i16 (VABSDUH $A, $B))>;
4285
4286def : Pat<(v16i8 (PPCvabsd v16i8:$A, v16i8:$B, (i32 0))),
4287          (v16i8 (VABSDUB $A, $B))>;
4288
4289// As PPCVABSD description, the last operand indicates whether do the
4290// sign bit flip.
4291def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 1))),
4292          (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>;
4293} // HasVSX, HasP9Altivec
4294
4295// Big endian Power9 VSX subtargets with P9 Altivec support.
4296let Predicates = [HasVSX, HasP9Altivec, IsBigEndian] in {
4297def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),
4298          (VEXTUBLX $Idx, $S)>;
4299
4300def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))),
4301          (VEXTUHLX (RLWINM8 $Idx, 1, 28, 30), $S)>;
4302def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),
4303          (VEXTUHLX (LI8 0), $S)>;
4304def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),
4305          (VEXTUHLX (LI8 2), $S)>;
4306def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),
4307          (VEXTUHLX (LI8 4), $S)>;
4308def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),
4309          (VEXTUHLX (LI8 6), $S)>;
4310def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),
4311          (VEXTUHLX (LI8 8), $S)>;
4312def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),
4313          (VEXTUHLX (LI8 10), $S)>;
4314def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),
4315          (VEXTUHLX (LI8 12), $S)>;
4316def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),
4317          (VEXTUHLX (LI8 14), $S)>;
4318
4319def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4320          (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S)>;
4321def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))),
4322          (VEXTUWLX (LI8 0), $S)>;
4323
4324// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX
4325def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))),
4326          (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4327          (i32 VectorExtractions.LE_WORD_2), sub_32)>;
4328def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))),
4329          (VEXTUWLX (LI8 8), $S)>;
4330def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))),
4331          (VEXTUWLX (LI8 12), $S)>;
4332
4333def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4334          (EXTSW (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S))>;
4335def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))),
4336          (EXTSW (VEXTUWLX (LI8 0), $S))>;
4337// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX
4338def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))),
4339          (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4340          (i32 VectorExtractions.LE_WORD_2), sub_32))>;
4341def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))),
4342          (EXTSW (VEXTUWLX (LI8 8), $S))>;
4343def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))),
4344          (EXTSW (VEXTUWLX (LI8 12), $S))>;
4345
4346def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
4347          (i32 (EXTRACT_SUBREG (VEXTUBLX $Idx, $S), sub_32))>;
4348def : Pat<(i32 (vector_extract v16i8:$S, 0)),
4349          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 0), $S), sub_32))>;
4350def : Pat<(i32 (vector_extract v16i8:$S, 1)),
4351          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 1), $S), sub_32))>;
4352def : Pat<(i32 (vector_extract v16i8:$S, 2)),
4353          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 2), $S), sub_32))>;
4354def : Pat<(i32 (vector_extract v16i8:$S, 3)),
4355          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 3), $S), sub_32))>;
4356def : Pat<(i32 (vector_extract v16i8:$S, 4)),
4357          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 4), $S), sub_32))>;
4358def : Pat<(i32 (vector_extract v16i8:$S, 5)),
4359          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 5), $S), sub_32))>;
4360def : Pat<(i32 (vector_extract v16i8:$S, 6)),
4361          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 6), $S), sub_32))>;
4362def : Pat<(i32 (vector_extract v16i8:$S, 7)),
4363          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 7), $S), sub_32))>;
4364def : Pat<(i32 (vector_extract v16i8:$S, 8)),
4365          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 8), $S), sub_32))>;
4366def : Pat<(i32 (vector_extract v16i8:$S, 9)),
4367          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 9), $S), sub_32))>;
4368def : Pat<(i32 (vector_extract v16i8:$S, 10)),
4369          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 10), $S), sub_32))>;
4370def : Pat<(i32 (vector_extract v16i8:$S, 11)),
4371          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 11), $S), sub_32))>;
4372def : Pat<(i32 (vector_extract v16i8:$S, 12)),
4373          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 12), $S), sub_32))>;
4374def : Pat<(i32 (vector_extract v16i8:$S, 13)),
4375          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 13), $S), sub_32))>;
4376def : Pat<(i32 (vector_extract v16i8:$S, 14)),
4377          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 14), $S), sub_32))>;
4378def : Pat<(i32 (vector_extract v16i8:$S, 15)),
4379          (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 15), $S), sub_32))>;
4380
4381def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
4382          (i32 (EXTRACT_SUBREG (VEXTUHLX
4383          (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>;
4384def : Pat<(i32 (vector_extract v8i16:$S, 0)),
4385          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 0), $S), sub_32))>;
4386def : Pat<(i32 (vector_extract v8i16:$S, 1)),
4387          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 2), $S), sub_32))>;
4388def : Pat<(i32 (vector_extract v8i16:$S, 2)),
4389          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 4), $S), sub_32))>;
4390def : Pat<(i32 (vector_extract v8i16:$S, 3)),
4391          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 6), $S), sub_32))>;
4392def : Pat<(i32 (vector_extract v8i16:$S, 4)),
4393          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 8), $S), sub_32))>;
4394def : Pat<(i32 (vector_extract v8i16:$S, 5)),
4395          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 10), $S), sub_32))>;
4396def : Pat<(i32 (vector_extract v8i16:$S, 6)),
4397          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 12), $S), sub_32))>;
4398def : Pat<(i32 (vector_extract v8i16:$S, 6)),
4399          (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 14), $S), sub_32))>;
4400
4401def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
4402          (i32 (EXTRACT_SUBREG (VEXTUWLX
4403          (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>;
4404def : Pat<(i32 (vector_extract v4i32:$S, 0)),
4405          (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 0), $S), sub_32))>;
4406// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX
4407def : Pat<(i32 (vector_extract v4i32:$S, 1)),
4408          (i32 VectorExtractions.LE_WORD_2)>;
4409def : Pat<(i32 (vector_extract v4i32:$S, 2)),
4410          (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 8), $S), sub_32))>;
4411def : Pat<(i32 (vector_extract v4i32:$S, 3)),
4412          (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 12), $S), sub_32))>;
4413
4414// P9 Altivec instructions that can be used to build vectors.
4415// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete
4416// with complexities of existing build vector patterns in this file.
4417def : Pat<(v2i64 (build_vector WordToDWord.BE_A0, WordToDWord.BE_A1)),
4418          (v2i64 (VEXTSW2D $A))>;
4419def : Pat<(v2i64 (build_vector HWordToDWord.BE_A0, HWordToDWord.BE_A1)),
4420          (v2i64 (VEXTSH2D $A))>;
4421def : Pat<(v4i32 (build_vector HWordToWord.BE_A0, HWordToWord.BE_A1,
4422                  HWordToWord.BE_A2, HWordToWord.BE_A3)),
4423          (v4i32 (VEXTSH2W $A))>;
4424def : Pat<(v4i32 (build_vector ByteToWord.BE_A0, ByteToWord.BE_A1,
4425                  ByteToWord.BE_A2, ByteToWord.BE_A3)),
4426          (v4i32 (VEXTSB2W $A))>;
4427def : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)),
4428          (v2i64 (VEXTSB2D $A))>;
4429} // HasVSX, HasP9Altivec, IsBigEndian
4430
4431// Little endian Power9 VSX subtargets with P9 Altivec support.
4432let Predicates = [HasVSX, HasP9Altivec, IsLittleEndian] in {
4433def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),
4434          (VEXTUBRX $Idx, $S)>;
4435
4436def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))),
4437          (VEXTUHRX (RLWINM8 $Idx, 1, 28, 30), $S)>;
4438def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))),
4439          (VEXTUHRX (LI8 0), $S)>;
4440def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))),
4441          (VEXTUHRX (LI8 2), $S)>;
4442def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))),
4443          (VEXTUHRX (LI8 4), $S)>;
4444def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))),
4445          (VEXTUHRX (LI8 6), $S)>;
4446def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))),
4447          (VEXTUHRX (LI8 8), $S)>;
4448def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))),
4449          (VEXTUHRX (LI8 10), $S)>;
4450def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))),
4451          (VEXTUHRX (LI8 12), $S)>;
4452def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))),
4453          (VEXTUHRX (LI8 14), $S)>;
4454
4455def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4456          (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S)>;
4457def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))),
4458          (VEXTUWRX (LI8 0), $S)>;
4459def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))),
4460          (VEXTUWRX (LI8 4), $S)>;
4461// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX
4462def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))),
4463          (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4464          (i32 VectorExtractions.LE_WORD_2), sub_32)>;
4465def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))),
4466          (VEXTUWRX (LI8 12), $S)>;
4467
4468def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))),
4469          (EXTSW (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S))>;
4470def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))),
4471          (EXTSW (VEXTUWRX (LI8 0), $S))>;
4472def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))),
4473          (EXTSW (VEXTUWRX (LI8 4), $S))>;
4474// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX
4475def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))),
4476          (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
4477          (i32 VectorExtractions.LE_WORD_2), sub_32))>;
4478def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))),
4479          (EXTSW (VEXTUWRX (LI8 12), $S))>;
4480
4481def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)),
4482          (i32 (EXTRACT_SUBREG (VEXTUBRX $Idx, $S), sub_32))>;
4483def : Pat<(i32 (vector_extract v16i8:$S, 0)),
4484          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 0), $S), sub_32))>;
4485def : Pat<(i32 (vector_extract v16i8:$S, 1)),
4486          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 1), $S), sub_32))>;
4487def : Pat<(i32 (vector_extract v16i8:$S, 2)),
4488          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 2), $S), sub_32))>;
4489def : Pat<(i32 (vector_extract v16i8:$S, 3)),
4490          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 3), $S), sub_32))>;
4491def : Pat<(i32 (vector_extract v16i8:$S, 4)),
4492          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 4), $S), sub_32))>;
4493def : Pat<(i32 (vector_extract v16i8:$S, 5)),
4494          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 5), $S), sub_32))>;
4495def : Pat<(i32 (vector_extract v16i8:$S, 6)),
4496          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 6), $S), sub_32))>;
4497def : Pat<(i32 (vector_extract v16i8:$S, 7)),
4498          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 7), $S), sub_32))>;
4499def : Pat<(i32 (vector_extract v16i8:$S, 8)),
4500          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 8), $S), sub_32))>;
4501def : Pat<(i32 (vector_extract v16i8:$S, 9)),
4502          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 9), $S), sub_32))>;
4503def : Pat<(i32 (vector_extract v16i8:$S, 10)),
4504          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 10), $S), sub_32))>;
4505def : Pat<(i32 (vector_extract v16i8:$S, 11)),
4506          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 11), $S), sub_32))>;
4507def : Pat<(i32 (vector_extract v16i8:$S, 12)),
4508          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 12), $S), sub_32))>;
4509def : Pat<(i32 (vector_extract v16i8:$S, 13)),
4510          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 13), $S), sub_32))>;
4511def : Pat<(i32 (vector_extract v16i8:$S, 14)),
4512          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 14), $S), sub_32))>;
4513def : Pat<(i32 (vector_extract v16i8:$S, 15)),
4514          (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 15), $S), sub_32))>;
4515
4516def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)),
4517          (i32 (EXTRACT_SUBREG (VEXTUHRX
4518          (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>;
4519def : Pat<(i32 (vector_extract v8i16:$S, 0)),
4520          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 0), $S), sub_32))>;
4521def : Pat<(i32 (vector_extract v8i16:$S, 1)),
4522          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 2), $S), sub_32))>;
4523def : Pat<(i32 (vector_extract v8i16:$S, 2)),
4524          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 4), $S), sub_32))>;
4525def : Pat<(i32 (vector_extract v8i16:$S, 3)),
4526          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 6), $S), sub_32))>;
4527def : Pat<(i32 (vector_extract v8i16:$S, 4)),
4528          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 8), $S), sub_32))>;
4529def : Pat<(i32 (vector_extract v8i16:$S, 5)),
4530          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 10), $S), sub_32))>;
4531def : Pat<(i32 (vector_extract v8i16:$S, 6)),
4532          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 12), $S), sub_32))>;
4533def : Pat<(i32 (vector_extract v8i16:$S, 6)),
4534          (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 14), $S), sub_32))>;
4535
4536def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)),
4537          (i32 (EXTRACT_SUBREG (VEXTUWRX
4538          (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>;
4539def : Pat<(i32 (vector_extract v4i32:$S, 0)),
4540          (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 0), $S), sub_32))>;
4541def : Pat<(i32 (vector_extract v4i32:$S, 1)),
4542          (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 4), $S), sub_32))>;
4543// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX
4544def : Pat<(i32 (vector_extract v4i32:$S, 2)),
4545          (i32 VectorExtractions.LE_WORD_2)>;
4546def : Pat<(i32 (vector_extract v4i32:$S, 3)),
4547          (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 12), $S), sub_32))>;
4548
4549// P9 Altivec instructions that can be used to build vectors.
4550// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete
4551// with complexities of existing build vector patterns in this file.
4552def : Pat<(v2i64 (build_vector WordToDWord.LE_A0, WordToDWord.LE_A1)),
4553          (v2i64 (VEXTSW2D $A))>;
4554def : Pat<(v2i64 (build_vector HWordToDWord.LE_A0, HWordToDWord.LE_A1)),
4555          (v2i64 (VEXTSH2D $A))>;
4556def : Pat<(v4i32 (build_vector HWordToWord.LE_A0, HWordToWord.LE_A1,
4557                  HWordToWord.LE_A2, HWordToWord.LE_A3)),
4558          (v4i32 (VEXTSH2W $A))>;
4559def : Pat<(v4i32 (build_vector ByteToWord.LE_A0, ByteToWord.LE_A1,
4560                  ByteToWord.LE_A2, ByteToWord.LE_A3)),
4561          (v4i32 (VEXTSB2W $A))>;
4562def : Pat<(v2i64 (build_vector ByteToDWord.LE_A0, ByteToDWord.LE_A1)),
4563          (v2i64 (VEXTSB2D $A))>;
4564} // HasVSX, HasP9Altivec, IsLittleEndian
4565
4566// Big endian VSX subtarget that supports additional direct moves from ISA3.0.
4567let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian] in {
4568def : Pat<(i64 (extractelt v2i64:$A, 1)),
4569          (i64 (MFVSRLD $A))>;
4570// Better way to build integer vectors if we have MTVSRDD. Big endian.
4571def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),
4572          (v2i64 (MTVSRDD $rB, $rA))>;
4573def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
4574          (MTVSRDD
4575            (RLDIMI AnyExts.B, AnyExts.A, 32, 0),
4576            (RLDIMI AnyExts.D, AnyExts.C, 32, 0))>;
4577
4578def : Pat<(f128 (PPCbuild_fp128 i64:$rB, i64:$rA)),
4579          (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;
4580} // HasVSX, IsISA3_0, HasDirectMove, IsBigEndian
4581
4582// Little endian VSX subtarget that supports direct moves from ISA3.0.
4583let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] in {
4584def : Pat<(i64 (extractelt v2i64:$A, 0)),
4585          (i64 (MFVSRLD $A))>;
4586// Better way to build integer vectors if we have MTVSRDD. Little endian.
4587def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),
4588          (v2i64 (MTVSRDD $rB, $rA))>;
4589def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
4590          (MTVSRDD
4591            (RLDIMI AnyExts.C, AnyExts.D, 32, 0),
4592            (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>;
4593
4594def : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)),
4595          (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;
4596} // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian
4597} // AddedComplexity = 400
4598
4599//---------------------------- Instruction aliases ---------------------------//
4600def : InstAlias<"xvmovdp $XT, $XB",
4601                (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
4602def : InstAlias<"xvmovsp $XT, $XB",
4603                (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
4604
4605def : InstAlias<"xxspltd $XT, $XB, 0",
4606                (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
4607def : InstAlias<"xxspltd $XT, $XB, 1",
4608                (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
4609def : InstAlias<"xxmrghd $XT, $XA, $XB",
4610                (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
4611def : InstAlias<"xxmrgld $XT, $XA, $XB",
4612                (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
4613def : InstAlias<"xxswapd $XT, $XB",
4614                (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
4615def : InstAlias<"xxspltd $XT, $XB, 0",
4616                (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;
4617def : InstAlias<"xxspltd $XT, $XB, 1",
4618                (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
4619def : InstAlias<"xxswapd $XT, $XB",
4620                (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
4621def : InstAlias<"mfvrd $rA, $XT",
4622                (MFVRD g8rc:$rA, vrrc:$XT), 0>;
4623def : InstAlias<"mffprd $rA, $src",
4624                (MFVSRD g8rc:$rA, f8rc:$src)>;
4625def : InstAlias<"mtvrd $XT, $rA",
4626                (MTVRD vrrc:$XT, g8rc:$rA), 0>;
4627def : InstAlias<"mtfprd $dst, $rA",
4628                (MTVSRD f8rc:$dst, g8rc:$rA)>;
4629def : InstAlias<"mfvrwz $rA, $XT",
4630                (MFVRWZ gprc:$rA, vrrc:$XT), 0>;
4631def : InstAlias<"mffprwz $rA, $src",
4632                (MFVSRWZ gprc:$rA, f8rc:$src)>;
4633def : InstAlias<"mtvrwa $XT, $rA",
4634                (MTVRWA vrrc:$XT, gprc:$rA), 0>;
4635def : InstAlias<"mtfprwa $dst, $rA",
4636                (MTVSRWA f8rc:$dst, gprc:$rA)>;
4637def : InstAlias<"mtvrwz $XT, $rA",
4638                (MTVRWZ vrrc:$XT, gprc:$rA), 0>;
4639def : InstAlias<"mtfprwz $dst, $rA",
4640                (MTVSRWZ f8rc:$dst, gprc:$rA)>;
4641