1//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the VSX extension to the PowerPC instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// *********************************** NOTE *********************************** 14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 15// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 16// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 17// ** whether lanes are numbered from left to right. An instruction like ** 18// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 19// ** relies only on the corresponding lane of the source vectors. However, ** 20// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 21// ** "odd" lanes are different for big-endian and little-endian numbering. ** 22// ** ** 23// ** When adding new VMX and VSX instructions, please consider whether they ** 24// ** are lane-sensitive. If so, they must be added to a switch statement ** 25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 26// **************************************************************************** 27 28// *********************************** NOTE *********************************** 29// ** When adding new anonymous patterns to this file, please add them to ** 30// ** the section titled Anonymous Patterns. Chances are that the existing ** 31// ** predicate blocks already contain a combination of features that you ** 32// ** are after. There is a list of blocks at the top of the section. If ** 33// ** you definitely need a new combination of predicates, please add that ** 34// ** combination to the list. ** 35// ** File Structure: ** 36// ** - Custom PPCISD node definitions ** 37// ** - Predicate definitions: predicates to specify the subtargets for ** 38// ** which an instruction or pattern can be emitted. ** 39// ** - Instruction formats: classes instantiated by the instructions. ** 40// ** These generally correspond to instruction formats in section 1.6 of ** 41// ** the ISA document. ** 42// ** - Instruction definitions: the actual definitions of the instructions ** 43// ** often including input patterns that they match. ** 44// ** - Helper DAG definitions: We define a number of dag objects to use as ** 45// ** input or output patterns for consciseness of the code. ** 46// ** - Anonymous patterns: input patterns that an instruction matches can ** 47// ** often not be specified as part of the instruction definition, so an ** 48// ** anonymous pattern must be specified mapping an input pattern to an ** 49// ** output pattern. These are generally guarded by subtarget predicates. ** 50// ** - Instruction aliases: used to define extended mnemonics for assembly ** 51// ** printing (for example: xxswapd for xxpermdi with 0x2 as the imm). ** 52// **************************************************************************** 53 54def SDT_PPCldvsxlh : SDTypeProfile<1, 1, [ 55 SDTCisVT<0, v4f32>, SDTCisPtrTy<1> 56]>; 57 58def SDT_PPCfpexth : SDTypeProfile<1, 2, [ 59 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2> 60]>; 61 62def SDT_PPCldsplat : SDTypeProfile<1, 1, [ 63 SDTCisVec<0>, SDTCisPtrTy<1> 64]>; 65 66// Little-endian-specific nodes. 67def SDT_PPClxvd2x : SDTypeProfile<1, 1, [ 68 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 69]>; 70def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [ 71 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 72]>; 73def SDT_PPCxxswapd : SDTypeProfile<1, 1, [ 74 SDTCisSameAs<0, 1> 75]>; 76def SDTVecConv : SDTypeProfile<1, 2, [ 77 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2> 78]>; 79def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [ 80 SDTCisVec<0>, SDTCisPtrTy<1> 81]>; 82def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [ 83 SDTCisVec<0>, SDTCisPtrTy<1> 84]>; 85 86def SDT_PPCxxperm : SDTypeProfile<1, 3, [ 87 SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>, 88 SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>; 89//--------------------------- Custom PPC nodes -------------------------------// 90def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x, 91 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 92def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x, 93 [SDNPHasChain, SDNPMayStore]>; 94def PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be, 95 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 96def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be, 97 [SDNPHasChain, SDNPMayStore]>; 98def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>; 99def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>; 100def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>; 101def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>; 102def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>; 103def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>; 104def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>; 105 106def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>; 107def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh, 108 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 109def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat, 110 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 111def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat, 112 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 113def PPCsextldsplat : SDNode<"PPCISD::SEXT_LD_SPLAT", SDT_PPCldsplat, 114 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 115def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED", 116 SDTypeProfile<1, 1, []>, []>; 117 118def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>; 119//-------------------------- Predicate definitions ---------------------------// 120def HasVSX : Predicate<"Subtarget->hasVSX()">; 121def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; 122def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">; 123def IsPPC64 : Predicate<"Subtarget->isPPC64()">; 124def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; 125def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">; 126def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">; 127def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">; 128def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; 129def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; 130def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">; 131 132def PPCldsplatAlign16 : PatFrag<(ops node:$ptr), (PPCldsplat node:$ptr), [{ 133 return cast<MemIntrinsicSDNode>(N)->getAlign() >= Align(16) && 134 isOffsetMultipleOf(N, 16); 135}]>; 136 137//--------------------- VSX-specific instruction formats ---------------------// 138// By default, all VSX instructions are to be selected over their Altivec 139// counter parts and they do not have unmodeled sideeffects. 140let AddedComplexity = 400, hasSideEffects = 0 in { 141multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase, 142 string asmstr, InstrItinClass itin, Intrinsic Int, 143 ValueType OutTy, ValueType InTy> { 144 let BaseName = asmbase in { 145 def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 146 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 147 [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>; 148 let Defs = [CR6] in 149 def _rec : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 150 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 151 [(set InTy:$XT, 152 (InTy (PPCvcmp_rec InTy:$XA, InTy:$XB, xo)))]>, 153 isRecordForm; 154 } 155} 156 157// Instruction form with a single input register for instructions such as 158// XXPERMDI. The reason for defining this is that specifying multiple chained 159// operands (such as loads) to an instruction will perform both chained 160// operations rather than coalescing them into a single register - even though 161// the source memory location is the same. This simply forces the instruction 162// to use the same register for both inputs. 163// For example, an output DAG such as this: 164// (XXPERMDI (LXSIBZX xoaddr:$src), (LXSIBZX xoaddr:$src ), 0)) 165// would result in two load instructions emitted and used as separate inputs 166// to the XXPERMDI instruction. 167class XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 168 InstrItinClass itin, list<dag> pattern> 169 : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 170 let XB = XA; 171} 172 173let Predicates = [HasVSX, HasP9Vector] in { 174class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 175 list<dag> pattern> 176 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB), 177 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 178 179// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 180class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 181 list<dag> pattern> 182 : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm; 183 184// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less), 185// So we use different operand class for VRB 186class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 187 RegisterOperand vbtype, list<dag> pattern> 188 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB), 189 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 190 191// [PO VRT XO VRB XO /] 192class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 193 list<dag> pattern> 194 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB), 195 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 196 197// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 198class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 199 list<dag> pattern> 200 : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm; 201 202// [PO T XO B XO BX /] 203class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 204 list<dag> pattern> 205 : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB), 206 !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>; 207 208// [PO T XO B XO BX TX] 209class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 210 RegisterOperand vtype, list<dag> pattern> 211 : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB), 212 !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>; 213 214// [PO T A B XO AX BX TX], src and dest register use different operand class 215class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc, 216 RegisterOperand xty, RegisterOperand aty, RegisterOperand bty, 217 InstrItinClass itin, list<dag> pattern> 218 : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB), 219 !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>; 220 221// [PO VRT VRA VRB XO /] 222class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 223 list<dag> pattern> 224 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB), 225 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>; 226 227// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 228class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc, 229 list<dag> pattern> 230 : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm; 231 232// [PO VRT VRA VRB XO /] 233class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc, 234 list<dag> pattern> 235 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB), 236 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>, 237 RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">; 238 239// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 240class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc, 241 list<dag> pattern> 242 : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm; 243 244class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc, 245 list<dag> pattern> 246 : Z23Form_8<opcode, xo, 247 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc), 248 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> { 249 let RC = ex; 250} 251 252// [PO BF // VRA VRB XO /] 253class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 254 list<dag> pattern> 255 : XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB), 256 !strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> { 257 let Pattern = pattern; 258} 259 260// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different 261// "out" and "in" dag 262class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 263 RegisterOperand vtype, list<dag> pattern> 264 : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src), 265 !strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>; 266 267// [PO S RA RB XO SX] 268class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 269 RegisterOperand vtype, list<dag> pattern> 270 : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst), 271 !strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>; 272} // Predicates = HasP9Vector 273} // AddedComplexity = 400, hasSideEffects = 0 274 275multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> { 276 def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>; 277 def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>; 278} 279 280//-------------------------- Instruction definitions -------------------------// 281// VSX instructions require the VSX feature, they are to be selected over 282// equivalent Altivec patterns (as they address a larger register set) and 283// they do not have unmodeled side effects. 284let Predicates = [HasVSX], AddedComplexity = 400 in { 285let hasSideEffects = 0 in { 286 287 // Load indexed instructions 288 let mayLoad = 1, mayStore = 0 in { 289 let CodeSize = 3 in 290 def LXSDX : XX1Form_memOp<31, 588, 291 (outs vsfrc:$XT), (ins memrr:$src), 292 "lxsdx $XT, $src", IIC_LdStLFD, 293 []>; 294 295 // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later 296 let CodeSize = 3 in 297 def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 298 "#XFLOADf64", 299 [(set f64:$XT, (load XForm:$src))]>; 300 301 let Predicates = [HasVSX, HasOnlySwappingMemOps] in 302 def LXVD2X : XX1Form_memOp<31, 844, 303 (outs vsrc:$XT), (ins memrr:$src), 304 "lxvd2x $XT, $src", IIC_LdStLFD, 305 []>; 306 307 def LXVDSX : XX1Form_memOp<31, 332, 308 (outs vsrc:$XT), (ins memrr:$src), 309 "lxvdsx $XT, $src", IIC_LdStLFD, []>; 310 311 let Predicates = [HasVSX, HasOnlySwappingMemOps] in 312 def LXVW4X : XX1Form_memOp<31, 780, 313 (outs vsrc:$XT), (ins memrr:$src), 314 "lxvw4x $XT, $src", IIC_LdStLFD, 315 []>; 316 } // mayLoad 317 318 // Store indexed instructions 319 let mayStore = 1, mayLoad = 0 in { 320 let CodeSize = 3 in 321 def STXSDX : XX1Form_memOp<31, 716, 322 (outs), (ins vsfrc:$XT, memrr:$dst), 323 "stxsdx $XT, $dst", IIC_LdStSTFD, 324 []>; 325 326 // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later 327 let CodeSize = 3 in 328 def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), 329 "#XFSTOREf64", 330 [(store f64:$XT, XForm:$dst)]>; 331 332 let Predicates = [HasVSX, HasOnlySwappingMemOps] in { 333 // The behaviour of this instruction is endianness-specific so we provide no 334 // pattern to match it without considering endianness. 335 def STXVD2X : XX1Form_memOp<31, 972, 336 (outs), (ins vsrc:$XT, memrr:$dst), 337 "stxvd2x $XT, $dst", IIC_LdStSTFD, 338 []>; 339 340 def STXVW4X : XX1Form_memOp<31, 908, 341 (outs), (ins vsrc:$XT, memrr:$dst), 342 "stxvw4x $XT, $dst", IIC_LdStSTFD, 343 []>; 344 } 345 } // mayStore 346 347 let mayRaiseFPException = 1 in { 348 let Uses = [RM] in { 349 // Add/Mul Instructions 350 let isCommutable = 1 in { 351 def XSADDDP : XX3Form<60, 32, 352 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 353 "xsadddp $XT, $XA, $XB", IIC_VecFP, 354 [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>; 355 def XSMULDP : XX3Form<60, 48, 356 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 357 "xsmuldp $XT, $XA, $XB", IIC_VecFP, 358 [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>; 359 360 def XVADDDP : XX3Form<60, 96, 361 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 362 "xvadddp $XT, $XA, $XB", IIC_VecFP, 363 [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>; 364 365 def XVADDSP : XX3Form<60, 64, 366 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 367 "xvaddsp $XT, $XA, $XB", IIC_VecFP, 368 [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>; 369 370 def XVMULDP : XX3Form<60, 112, 371 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 372 "xvmuldp $XT, $XA, $XB", IIC_VecFP, 373 [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>; 374 375 def XVMULSP : XX3Form<60, 80, 376 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 377 "xvmulsp $XT, $XA, $XB", IIC_VecFP, 378 [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>; 379 } 380 381 // Subtract Instructions 382 def XSSUBDP : XX3Form<60, 40, 383 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 384 "xssubdp $XT, $XA, $XB", IIC_VecFP, 385 [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>; 386 387 def XVSUBDP : XX3Form<60, 104, 388 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 389 "xvsubdp $XT, $XA, $XB", IIC_VecFP, 390 [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>; 391 def XVSUBSP : XX3Form<60, 72, 392 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 393 "xvsubsp $XT, $XA, $XB", IIC_VecFP, 394 [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>; 395 396 // FMA Instructions 397 let BaseName = "XSMADDADP" in { 398 let isCommutable = 1 in 399 def XSMADDADP : XX3Form<60, 33, 400 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 401 "xsmaddadp $XT, $XA, $XB", IIC_VecFP, 402 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>, 403 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 404 AltVSXFMARel; 405 let IsVSXFMAAlt = 1 in 406 def XSMADDMDP : XX3Form<60, 41, 407 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 408 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 409 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 410 AltVSXFMARel; 411 } 412 413 let BaseName = "XSMSUBADP" in { 414 let isCommutable = 1 in 415 def XSMSUBADP : XX3Form<60, 49, 416 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 417 "xsmsubadp $XT, $XA, $XB", IIC_VecFP, 418 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>, 419 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 420 AltVSXFMARel; 421 let IsVSXFMAAlt = 1 in 422 def XSMSUBMDP : XX3Form<60, 57, 423 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 424 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 425 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 426 AltVSXFMARel; 427 } 428 429 let BaseName = "XSNMADDADP" in { 430 let isCommutable = 1 in 431 def XSNMADDADP : XX3Form<60, 161, 432 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 433 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP, 434 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>, 435 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 436 AltVSXFMARel; 437 let IsVSXFMAAlt = 1 in 438 def XSNMADDMDP : XX3Form<60, 169, 439 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 440 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 441 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 442 AltVSXFMARel; 443 } 444 445 let BaseName = "XSNMSUBADP" in { 446 let isCommutable = 1 in 447 def XSNMSUBADP : XX3Form<60, 177, 448 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 449 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP, 450 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>, 451 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 452 AltVSXFMARel; 453 let IsVSXFMAAlt = 1 in 454 def XSNMSUBMDP : XX3Form<60, 185, 455 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 456 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 457 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 458 AltVSXFMARel; 459 } 460 461 let BaseName = "XVMADDADP" in { 462 let isCommutable = 1 in 463 def XVMADDADP : XX3Form<60, 97, 464 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 465 "xvmaddadp $XT, $XA, $XB", IIC_VecFP, 466 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>, 467 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 468 AltVSXFMARel; 469 let IsVSXFMAAlt = 1 in 470 def XVMADDMDP : XX3Form<60, 105, 471 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 472 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 473 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 474 AltVSXFMARel; 475 } 476 477 let BaseName = "XVMADDASP" in { 478 let isCommutable = 1 in 479 def XVMADDASP : XX3Form<60, 65, 480 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 481 "xvmaddasp $XT, $XA, $XB", IIC_VecFP, 482 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>, 483 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 484 AltVSXFMARel; 485 let IsVSXFMAAlt = 1 in 486 def XVMADDMSP : XX3Form<60, 73, 487 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 488 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 489 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 490 AltVSXFMARel; 491 } 492 493 let BaseName = "XVMSUBADP" in { 494 let isCommutable = 1 in 495 def XVMSUBADP : XX3Form<60, 113, 496 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 497 "xvmsubadp $XT, $XA, $XB", IIC_VecFP, 498 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>, 499 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 500 AltVSXFMARel; 501 let IsVSXFMAAlt = 1 in 502 def XVMSUBMDP : XX3Form<60, 121, 503 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 504 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 505 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 506 AltVSXFMARel; 507 } 508 509 let BaseName = "XVMSUBASP" in { 510 let isCommutable = 1 in 511 def XVMSUBASP : XX3Form<60, 81, 512 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 513 "xvmsubasp $XT, $XA, $XB", IIC_VecFP, 514 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>, 515 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 516 AltVSXFMARel; 517 let IsVSXFMAAlt = 1 in 518 def XVMSUBMSP : XX3Form<60, 89, 519 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 520 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 521 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 522 AltVSXFMARel; 523 } 524 525 let BaseName = "XVNMADDADP" in { 526 let isCommutable = 1 in 527 def XVNMADDADP : XX3Form<60, 225, 528 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 529 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP, 530 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>, 531 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 532 AltVSXFMARel; 533 let IsVSXFMAAlt = 1 in 534 def XVNMADDMDP : XX3Form<60, 233, 535 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 536 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 537 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 538 AltVSXFMARel; 539 } 540 541 let BaseName = "XVNMADDASP" in { 542 let isCommutable = 1 in 543 def XVNMADDASP : XX3Form<60, 193, 544 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 545 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP, 546 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>, 547 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 548 AltVSXFMARel; 549 let IsVSXFMAAlt = 1 in 550 def XVNMADDMSP : XX3Form<60, 201, 551 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 552 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 553 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 554 AltVSXFMARel; 555 } 556 557 let BaseName = "XVNMSUBADP" in { 558 let isCommutable = 1 in 559 def XVNMSUBADP : XX3Form<60, 241, 560 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 561 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP, 562 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>, 563 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 564 AltVSXFMARel; 565 let IsVSXFMAAlt = 1 in 566 def XVNMSUBMDP : XX3Form<60, 249, 567 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 568 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 569 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 570 AltVSXFMARel; 571 } 572 573 let BaseName = "XVNMSUBASP" in { 574 let isCommutable = 1 in 575 def XVNMSUBASP : XX3Form<60, 209, 576 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 577 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP, 578 [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>, 579 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 580 AltVSXFMARel; 581 let IsVSXFMAAlt = 1 in 582 def XVNMSUBMSP : XX3Form<60, 217, 583 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 584 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 585 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 586 AltVSXFMARel; 587 } 588 589 // Division Instructions 590 def XSDIVDP : XX3Form<60, 56, 591 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 592 "xsdivdp $XT, $XA, $XB", IIC_FPDivD, 593 [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>; 594 def XSSQRTDP : XX2Form<60, 75, 595 (outs vsfrc:$XT), (ins vsfrc:$XB), 596 "xssqrtdp $XT, $XB", IIC_FPSqrtD, 597 [(set f64:$XT, (any_fsqrt f64:$XB))]>; 598 599 def XSREDP : XX2Form<60, 90, 600 (outs vsfrc:$XT), (ins vsfrc:$XB), 601 "xsredp $XT, $XB", IIC_VecFP, 602 [(set f64:$XT, (PPCfre f64:$XB))]>; 603 def XSRSQRTEDP : XX2Form<60, 74, 604 (outs vsfrc:$XT), (ins vsfrc:$XB), 605 "xsrsqrtedp $XT, $XB", IIC_VecFP, 606 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>; 607 608 let mayRaiseFPException = 0 in { 609 def XSTDIVDP : XX3Form_1<60, 61, 610 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 611 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>; 612 def XSTSQRTDP : XX2Form_1<60, 106, 613 (outs crrc:$crD), (ins vsfrc:$XB), 614 "xstsqrtdp $crD, $XB", IIC_FPCompare, 615 [(set i32:$crD, (PPCftsqrt f64:$XB))]>; 616 def XVTDIVDP : XX3Form_1<60, 125, 617 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), 618 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>; 619 def XVTDIVSP : XX3Form_1<60, 93, 620 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), 621 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>; 622 623 def XVTSQRTDP : XX2Form_1<60, 234, 624 (outs crrc:$crD), (ins vsrc:$XB), 625 "xvtsqrtdp $crD, $XB", IIC_FPCompare, 626 [(set i32:$crD, (PPCftsqrt v2f64:$XB))]>; 627 def XVTSQRTSP : XX2Form_1<60, 170, 628 (outs crrc:$crD), (ins vsrc:$XB), 629 "xvtsqrtsp $crD, $XB", IIC_FPCompare, 630 [(set i32:$crD, (PPCftsqrt v4f32:$XB))]>; 631 } 632 633 def XVDIVDP : XX3Form<60, 120, 634 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 635 "xvdivdp $XT, $XA, $XB", IIC_FPDivD, 636 [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>; 637 def XVDIVSP : XX3Form<60, 88, 638 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 639 "xvdivsp $XT, $XA, $XB", IIC_FPDivS, 640 [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>; 641 642 def XVSQRTDP : XX2Form<60, 203, 643 (outs vsrc:$XT), (ins vsrc:$XB), 644 "xvsqrtdp $XT, $XB", IIC_FPSqrtD, 645 [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>; 646 def XVSQRTSP : XX2Form<60, 139, 647 (outs vsrc:$XT), (ins vsrc:$XB), 648 "xvsqrtsp $XT, $XB", IIC_FPSqrtS, 649 [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>; 650 651 def XVREDP : XX2Form<60, 218, 652 (outs vsrc:$XT), (ins vsrc:$XB), 653 "xvredp $XT, $XB", IIC_VecFP, 654 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>; 655 def XVRESP : XX2Form<60, 154, 656 (outs vsrc:$XT), (ins vsrc:$XB), 657 "xvresp $XT, $XB", IIC_VecFP, 658 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>; 659 660 def XVRSQRTEDP : XX2Form<60, 202, 661 (outs vsrc:$XT), (ins vsrc:$XB), 662 "xvrsqrtedp $XT, $XB", IIC_VecFP, 663 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>; 664 def XVRSQRTESP : XX2Form<60, 138, 665 (outs vsrc:$XT), (ins vsrc:$XB), 666 "xvrsqrtesp $XT, $XB", IIC_VecFP, 667 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>; 668 669 // Compare Instructions 670 def XSCMPODP : XX3Form_1<60, 43, 671 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 672 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>; 673 def XSCMPUDP : XX3Form_1<60, 35, 674 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 675 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>; 676 677 defm XVCMPEQDP : XX3Form_Rcr<60, 99, 678 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, 679 int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>; 680 defm XVCMPEQSP : XX3Form_Rcr<60, 67, 681 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, 682 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>; 683 defm XVCMPGEDP : XX3Form_Rcr<60, 115, 684 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, 685 int_ppc_vsx_xvcmpgedp, v2i64, v2f64>; 686 defm XVCMPGESP : XX3Form_Rcr<60, 83, 687 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, 688 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>; 689 defm XVCMPGTDP : XX3Form_Rcr<60, 107, 690 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, 691 int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>; 692 defm XVCMPGTSP : XX3Form_Rcr<60, 75, 693 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, 694 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>; 695 696 // Move Instructions 697 let mayRaiseFPException = 0 in { 698 def XSABSDP : XX2Form<60, 345, 699 (outs vsfrc:$XT), (ins vsfrc:$XB), 700 "xsabsdp $XT, $XB", IIC_VecFP, 701 [(set f64:$XT, (fabs f64:$XB))]>; 702 def XSNABSDP : XX2Form<60, 361, 703 (outs vsfrc:$XT), (ins vsfrc:$XB), 704 "xsnabsdp $XT, $XB", IIC_VecFP, 705 [(set f64:$XT, (fneg (fabs f64:$XB)))]>; 706 let isCodeGenOnly = 1 in 707 def XSNABSDPs : XX2Form<60, 361, 708 (outs vssrc:$XT), (ins vssrc:$XB), 709 "xsnabsdp $XT, $XB", IIC_VecFP, 710 [(set f32:$XT, (fneg (fabs f32:$XB)))]>; 711 def XSNEGDP : XX2Form<60, 377, 712 (outs vsfrc:$XT), (ins vsfrc:$XB), 713 "xsnegdp $XT, $XB", IIC_VecFP, 714 [(set f64:$XT, (fneg f64:$XB))]>; 715 def XSCPSGNDP : XX3Form<60, 176, 716 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 717 "xscpsgndp $XT, $XA, $XB", IIC_VecFP, 718 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>; 719 720 def XVABSDP : XX2Form<60, 473, 721 (outs vsrc:$XT), (ins vsrc:$XB), 722 "xvabsdp $XT, $XB", IIC_VecFP, 723 [(set v2f64:$XT, (fabs v2f64:$XB))]>; 724 725 def XVABSSP : XX2Form<60, 409, 726 (outs vsrc:$XT), (ins vsrc:$XB), 727 "xvabssp $XT, $XB", IIC_VecFP, 728 [(set v4f32:$XT, (fabs v4f32:$XB))]>; 729 730 def XVCPSGNDP : XX3Form<60, 240, 731 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 732 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP, 733 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>; 734 def XVCPSGNSP : XX3Form<60, 208, 735 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 736 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP, 737 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>; 738 739 def XVNABSDP : XX2Form<60, 489, 740 (outs vsrc:$XT), (ins vsrc:$XB), 741 "xvnabsdp $XT, $XB", IIC_VecFP, 742 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>; 743 def XVNABSSP : XX2Form<60, 425, 744 (outs vsrc:$XT), (ins vsrc:$XB), 745 "xvnabssp $XT, $XB", IIC_VecFP, 746 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>; 747 748 def XVNEGDP : XX2Form<60, 505, 749 (outs vsrc:$XT), (ins vsrc:$XB), 750 "xvnegdp $XT, $XB", IIC_VecFP, 751 [(set v2f64:$XT, (fneg v2f64:$XB))]>; 752 def XVNEGSP : XX2Form<60, 441, 753 (outs vsrc:$XT), (ins vsrc:$XB), 754 "xvnegsp $XT, $XB", IIC_VecFP, 755 [(set v4f32:$XT, (fneg v4f32:$XB))]>; 756 } 757 758 // Conversion Instructions 759 def XSCVDPSP : XX2Form<60, 265, 760 (outs vsfrc:$XT), (ins vsfrc:$XB), 761 "xscvdpsp $XT, $XB", IIC_VecFP, []>; 762 def XSCVDPSXDS : XX2Form<60, 344, 763 (outs vsfrc:$XT), (ins vsfrc:$XB), 764 "xscvdpsxds $XT, $XB", IIC_VecFP, 765 [(set f64:$XT, (PPCany_fctidz f64:$XB))]>; 766 let isCodeGenOnly = 1 in 767 def XSCVDPSXDSs : XX2Form<60, 344, 768 (outs vssrc:$XT), (ins vssrc:$XB), 769 "xscvdpsxds $XT, $XB", IIC_VecFP, 770 [(set f32:$XT, (PPCany_fctidz f32:$XB))]>; 771 def XSCVDPSXWS : XX2Form<60, 88, 772 (outs vsfrc:$XT), (ins vsfrc:$XB), 773 "xscvdpsxws $XT, $XB", IIC_VecFP, 774 [(set f64:$XT, (PPCany_fctiwz f64:$XB))]>; 775 let isCodeGenOnly = 1 in 776 def XSCVDPSXWSs : XX2Form<60, 88, 777 (outs vssrc:$XT), (ins vssrc:$XB), 778 "xscvdpsxws $XT, $XB", IIC_VecFP, 779 [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>; 780 def XSCVDPUXDS : XX2Form<60, 328, 781 (outs vsfrc:$XT), (ins vsfrc:$XB), 782 "xscvdpuxds $XT, $XB", IIC_VecFP, 783 [(set f64:$XT, (PPCany_fctiduz f64:$XB))]>; 784 let isCodeGenOnly = 1 in 785 def XSCVDPUXDSs : XX2Form<60, 328, 786 (outs vssrc:$XT), (ins vssrc:$XB), 787 "xscvdpuxds $XT, $XB", IIC_VecFP, 788 [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>; 789 def XSCVDPUXWS : XX2Form<60, 72, 790 (outs vsfrc:$XT), (ins vsfrc:$XB), 791 "xscvdpuxws $XT, $XB", IIC_VecFP, 792 [(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>; 793 let isCodeGenOnly = 1 in 794 def XSCVDPUXWSs : XX2Form<60, 72, 795 (outs vssrc:$XT), (ins vssrc:$XB), 796 "xscvdpuxws $XT, $XB", IIC_VecFP, 797 [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>; 798 def XSCVSPDP : XX2Form<60, 329, 799 (outs vsfrc:$XT), (ins vsfrc:$XB), 800 "xscvspdp $XT, $XB", IIC_VecFP, []>; 801 def XSCVSXDDP : XX2Form<60, 376, 802 (outs vsfrc:$XT), (ins vsfrc:$XB), 803 "xscvsxddp $XT, $XB", IIC_VecFP, 804 [(set f64:$XT, (PPCany_fcfid f64:$XB))]>; 805 def XSCVUXDDP : XX2Form<60, 360, 806 (outs vsfrc:$XT), (ins vsfrc:$XB), 807 "xscvuxddp $XT, $XB", IIC_VecFP, 808 [(set f64:$XT, (PPCany_fcfidu f64:$XB))]>; 809 810 def XVCVDPSP : XX2Form<60, 393, 811 (outs vsrc:$XT), (ins vsrc:$XB), 812 "xvcvdpsp $XT, $XB", IIC_VecFP, 813 [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>; 814 def XVCVDPSXDS : XX2Form<60, 472, 815 (outs vsrc:$XT), (ins vsrc:$XB), 816 "xvcvdpsxds $XT, $XB", IIC_VecFP, 817 [(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>; 818 def XVCVDPSXWS : XX2Form<60, 216, 819 (outs vsrc:$XT), (ins vsrc:$XB), 820 "xvcvdpsxws $XT, $XB", IIC_VecFP, 821 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>; 822 def XVCVDPUXDS : XX2Form<60, 456, 823 (outs vsrc:$XT), (ins vsrc:$XB), 824 "xvcvdpuxds $XT, $XB", IIC_VecFP, 825 [(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>; 826 def XVCVDPUXWS : XX2Form<60, 200, 827 (outs vsrc:$XT), (ins vsrc:$XB), 828 "xvcvdpuxws $XT, $XB", IIC_VecFP, 829 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>; 830 831 def XVCVSPDP : XX2Form<60, 457, 832 (outs vsrc:$XT), (ins vsrc:$XB), 833 "xvcvspdp $XT, $XB", IIC_VecFP, 834 [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>; 835 def XVCVSPSXDS : XX2Form<60, 408, 836 (outs vsrc:$XT), (ins vsrc:$XB), 837 "xvcvspsxds $XT, $XB", IIC_VecFP, 838 [(set v2i64:$XT, (int_ppc_vsx_xvcvspsxds v4f32:$XB))]>; 839 def XVCVSPSXWS : XX2Form<60, 152, 840 (outs vsrc:$XT), (ins vsrc:$XB), 841 "xvcvspsxws $XT, $XB", IIC_VecFP, 842 [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>; 843 def XVCVSPUXDS : XX2Form<60, 392, 844 (outs vsrc:$XT), (ins vsrc:$XB), 845 "xvcvspuxds $XT, $XB", IIC_VecFP, 846 [(set v2i64:$XT, (int_ppc_vsx_xvcvspuxds v4f32:$XB))]>; 847 def XVCVSPUXWS : XX2Form<60, 136, 848 (outs vsrc:$XT), (ins vsrc:$XB), 849 "xvcvspuxws $XT, $XB", IIC_VecFP, 850 [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>; 851 def XVCVSXDDP : XX2Form<60, 504, 852 (outs vsrc:$XT), (ins vsrc:$XB), 853 "xvcvsxddp $XT, $XB", IIC_VecFP, 854 [(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>; 855 def XVCVSXDSP : XX2Form<60, 440, 856 (outs vsrc:$XT), (ins vsrc:$XB), 857 "xvcvsxdsp $XT, $XB", IIC_VecFP, 858 [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>; 859 def XVCVSXWSP : XX2Form<60, 184, 860 (outs vsrc:$XT), (ins vsrc:$XB), 861 "xvcvsxwsp $XT, $XB", IIC_VecFP, 862 [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>; 863 def XVCVUXDDP : XX2Form<60, 488, 864 (outs vsrc:$XT), (ins vsrc:$XB), 865 "xvcvuxddp $XT, $XB", IIC_VecFP, 866 [(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>; 867 def XVCVUXDSP : XX2Form<60, 424, 868 (outs vsrc:$XT), (ins vsrc:$XB), 869 "xvcvuxdsp $XT, $XB", IIC_VecFP, 870 [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>; 871 def XVCVUXWSP : XX2Form<60, 168, 872 (outs vsrc:$XT), (ins vsrc:$XB), 873 "xvcvuxwsp $XT, $XB", IIC_VecFP, 874 [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>; 875 876 let mayRaiseFPException = 0 in { 877 def XVCVSXWDP : XX2Form<60, 248, 878 (outs vsrc:$XT), (ins vsrc:$XB), 879 "xvcvsxwdp $XT, $XB", IIC_VecFP, 880 [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>; 881 def XVCVUXWDP : XX2Form<60, 232, 882 (outs vsrc:$XT), (ins vsrc:$XB), 883 "xvcvuxwdp $XT, $XB", IIC_VecFP, 884 [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>; 885 } 886 887 // Rounding Instructions respecting current rounding mode 888 def XSRDPIC : XX2Form<60, 107, 889 (outs vsfrc:$XT), (ins vsfrc:$XB), 890 "xsrdpic $XT, $XB", IIC_VecFP, []>; 891 def XVRDPIC : XX2Form<60, 235, 892 (outs vsrc:$XT), (ins vsrc:$XB), 893 "xvrdpic $XT, $XB", IIC_VecFP, []>; 894 def XVRSPIC : XX2Form<60, 171, 895 (outs vsrc:$XT), (ins vsrc:$XB), 896 "xvrspic $XT, $XB", IIC_VecFP, []>; 897 // Max/Min Instructions 898 let isCommutable = 1 in { 899 def XSMAXDP : XX3Form<60, 160, 900 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 901 "xsmaxdp $XT, $XA, $XB", IIC_VecFP, 902 [(set vsfrc:$XT, 903 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>; 904 def XSMINDP : XX3Form<60, 168, 905 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 906 "xsmindp $XT, $XA, $XB", IIC_VecFP, 907 [(set vsfrc:$XT, 908 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>; 909 910 def XVMAXDP : XX3Form<60, 224, 911 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 912 "xvmaxdp $XT, $XA, $XB", IIC_VecFP, 913 [(set vsrc:$XT, 914 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>; 915 def XVMINDP : XX3Form<60, 232, 916 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 917 "xvmindp $XT, $XA, $XB", IIC_VecFP, 918 [(set vsrc:$XT, 919 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>; 920 921 def XVMAXSP : XX3Form<60, 192, 922 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 923 "xvmaxsp $XT, $XA, $XB", IIC_VecFP, 924 [(set vsrc:$XT, 925 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>; 926 def XVMINSP : XX3Form<60, 200, 927 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 928 "xvminsp $XT, $XA, $XB", IIC_VecFP, 929 [(set vsrc:$XT, 930 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>; 931 } // isCommutable 932 } // Uses = [RM] 933 934 // Rounding Instructions with static direction. 935 def XSRDPI : XX2Form<60, 73, 936 (outs vsfrc:$XT), (ins vsfrc:$XB), 937 "xsrdpi $XT, $XB", IIC_VecFP, 938 [(set f64:$XT, (any_fround f64:$XB))]>; 939 def XSRDPIM : XX2Form<60, 121, 940 (outs vsfrc:$XT), (ins vsfrc:$XB), 941 "xsrdpim $XT, $XB", IIC_VecFP, 942 [(set f64:$XT, (any_ffloor f64:$XB))]>; 943 def XSRDPIP : XX2Form<60, 105, 944 (outs vsfrc:$XT), (ins vsfrc:$XB), 945 "xsrdpip $XT, $XB", IIC_VecFP, 946 [(set f64:$XT, (any_fceil f64:$XB))]>; 947 def XSRDPIZ : XX2Form<60, 89, 948 (outs vsfrc:$XT), (ins vsfrc:$XB), 949 "xsrdpiz $XT, $XB", IIC_VecFP, 950 [(set f64:$XT, (any_ftrunc f64:$XB))]>; 951 952 def XVRDPI : XX2Form<60, 201, 953 (outs vsrc:$XT), (ins vsrc:$XB), 954 "xvrdpi $XT, $XB", IIC_VecFP, 955 [(set v2f64:$XT, (any_fround v2f64:$XB))]>; 956 def XVRDPIM : XX2Form<60, 249, 957 (outs vsrc:$XT), (ins vsrc:$XB), 958 "xvrdpim $XT, $XB", IIC_VecFP, 959 [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>; 960 def XVRDPIP : XX2Form<60, 233, 961 (outs vsrc:$XT), (ins vsrc:$XB), 962 "xvrdpip $XT, $XB", IIC_VecFP, 963 [(set v2f64:$XT, (any_fceil v2f64:$XB))]>; 964 def XVRDPIZ : XX2Form<60, 217, 965 (outs vsrc:$XT), (ins vsrc:$XB), 966 "xvrdpiz $XT, $XB", IIC_VecFP, 967 [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>; 968 969 def XVRSPI : XX2Form<60, 137, 970 (outs vsrc:$XT), (ins vsrc:$XB), 971 "xvrspi $XT, $XB", IIC_VecFP, 972 [(set v4f32:$XT, (any_fround v4f32:$XB))]>; 973 def XVRSPIM : XX2Form<60, 185, 974 (outs vsrc:$XT), (ins vsrc:$XB), 975 "xvrspim $XT, $XB", IIC_VecFP, 976 [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>; 977 def XVRSPIP : XX2Form<60, 169, 978 (outs vsrc:$XT), (ins vsrc:$XB), 979 "xvrspip $XT, $XB", IIC_VecFP, 980 [(set v4f32:$XT, (any_fceil v4f32:$XB))]>; 981 def XVRSPIZ : XX2Form<60, 153, 982 (outs vsrc:$XT), (ins vsrc:$XB), 983 "xvrspiz $XT, $XB", IIC_VecFP, 984 [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>; 985 } // mayRaiseFPException 986 987 // Logical Instructions 988 let isCommutable = 1 in 989 def XXLAND : XX3Form<60, 130, 990 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 991 "xxland $XT, $XA, $XB", IIC_VecGeneral, 992 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>; 993 def XXLANDC : XX3Form<60, 138, 994 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 995 "xxlandc $XT, $XA, $XB", IIC_VecGeneral, 996 [(set v4i32:$XT, (and v4i32:$XA, 997 (vnot v4i32:$XB)))]>; 998 let isCommutable = 1 in { 999 def XXLNOR : XX3Form<60, 162, 1000 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1001 "xxlnor $XT, $XA, $XB", IIC_VecGeneral, 1002 [(set v4i32:$XT, (vnot (or v4i32:$XA, 1003 v4i32:$XB)))]>; 1004 def XXLOR : XX3Form<60, 146, 1005 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1006 "xxlor $XT, $XA, $XB", IIC_VecGeneral, 1007 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>; 1008 let isCodeGenOnly = 1 in 1009 def XXLORf: XX3Form<60, 146, 1010 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 1011 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>; 1012 def XXLXOR : XX3Form<60, 154, 1013 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1014 "xxlxor $XT, $XA, $XB", IIC_VecGeneral, 1015 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>; 1016 } // isCommutable 1017 1018 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 1019 isReMaterializable = 1 in { 1020 def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins), 1021 "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 1022 [(set v4i32:$XT, (v4i32 immAllZerosV))]>; 1023 def XXLXORdpz : XX3Form_SameOp<60, 154, 1024 (outs vsfrc:$XT), (ins), 1025 "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 1026 [(set f64:$XT, (fpimm0))]>; 1027 def XXLXORspz : XX3Form_SameOp<60, 154, 1028 (outs vssrc:$XT), (ins), 1029 "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 1030 [(set f32:$XT, (fpimm0))]>; 1031 } 1032 1033 // Permutation Instructions 1034 def XXMRGHW : XX3Form<60, 18, 1035 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1036 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>; 1037 def XXMRGLW : XX3Form<60, 50, 1038 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1039 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>; 1040 1041 def XXPERMDI : XX3Form_2<60, 10, 1042 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM), 1043 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, 1044 [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB, 1045 imm32SExt16:$DM))]>; 1046 let isCodeGenOnly = 1 in 1047 // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which 1048 // is not the same with the input register class(`vsrc`) of XXPERMDI instruction. 1049 // We did this on purpose because: 1050 // 1: The input is primarily for loads that load a partial vector(LFIWZX, 1051 // etc.), no need for SUBREG_TO_REG. 1052 // 2: With `vsfrc` register class, in the final assembly, float registers 1053 // like `f0` are used instead of vector scalar register like `vs0`. This 1054 // helps readability. 1055 def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM), 1056 "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>; 1057 def XXSEL : XX4Form<60, 3, 1058 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), 1059 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; 1060 1061 def XXSLDWI : XX3Form_2<60, 2, 1062 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW), 1063 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, 1064 [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, 1065 imm32SExt16:$SHW))]>; 1066 1067 let isCodeGenOnly = 1 in 1068 def XXSLDWIs : XX3Form_2s<60, 2, 1069 (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), 1070 "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; 1071 1072 def XXSPLTW : XX2Form_2<60, 164, 1073 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), 1074 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, 1075 [(set v4i32:$XT, 1076 (PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>; 1077 let isCodeGenOnly = 1 in 1078 def XXSPLTWs : XX2Form_2<60, 164, 1079 (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM), 1080 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; 1081 1082// The following VSX instructions were introduced in Power ISA 2.07 1083let Predicates = [HasVSX, HasP8Vector] in { 1084 let isCommutable = 1 in { 1085 def XXLEQV : XX3Form<60, 186, 1086 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1087 "xxleqv $XT, $XA, $XB", IIC_VecGeneral, 1088 [(set v4i32:$XT, (vnot (xor v4i32:$XA, v4i32:$XB)))]>; 1089 def XXLNAND : XX3Form<60, 178, 1090 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1091 "xxlnand $XT, $XA, $XB", IIC_VecGeneral, 1092 [(set v4i32:$XT, (vnot (and v4i32:$XA, v4i32:$XB)))]>; 1093 } // isCommutable 1094 1095 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 1096 isReMaterializable = 1 in { 1097 def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins), 1098 "xxleqv $XT, $XT, $XT", IIC_VecGeneral, 1099 [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>; 1100 } 1101 1102 def XXLORC : XX3Form<60, 170, 1103 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1104 "xxlorc $XT, $XA, $XB", IIC_VecGeneral, 1105 [(set v4i32:$XT, (or v4i32:$XA, (vnot v4i32:$XB)))]>; 1106 1107 // VSX scalar loads introduced in ISA 2.07 1108 let mayLoad = 1, mayStore = 0 in { 1109 let CodeSize = 3 in 1110 def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src), 1111 "lxsspx $XT, $src", IIC_LdStLFD, []>; 1112 def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src), 1113 "lxsiwax $XT, $src", IIC_LdStLFD, []>; 1114 def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src), 1115 "lxsiwzx $XT, $src", IIC_LdStLFD, []>; 1116 1117 // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later 1118 let CodeSize = 3 in 1119 def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), 1120 "#XFLOADf32", 1121 [(set f32:$XT, (load XForm:$src))]>; 1122 // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later 1123 def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 1124 "#LIWAX", 1125 [(set f64:$XT, (PPClfiwax ForceXForm:$src))]>; 1126 // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later 1127 def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 1128 "#LIWZX", 1129 [(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>; 1130 } // mayLoad 1131 1132 // VSX scalar stores introduced in ISA 2.07 1133 let mayStore = 1, mayLoad = 0 in { 1134 let CodeSize = 3 in 1135 def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst), 1136 "stxsspx $XT, $dst", IIC_LdStSTFD, []>; 1137 def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), 1138 "stxsiwx $XT, $dst", IIC_LdStSTFD, []>; 1139 1140 // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later 1141 let CodeSize = 3 in 1142 def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), 1143 "#XFSTOREf32", 1144 [(store f32:$XT, XForm:$dst)]>; 1145 // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later 1146 def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), 1147 "#STIWX", 1148 [(PPCstfiwx f64:$XT, ForceXForm:$dst)]>; 1149 } // mayStore 1150 1151 // VSX Elementary Scalar FP arithmetic (SP) 1152 let mayRaiseFPException = 1 in { 1153 let isCommutable = 1 in { 1154 def XSADDSP : XX3Form<60, 0, 1155 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1156 "xsaddsp $XT, $XA, $XB", IIC_VecFP, 1157 [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>; 1158 def XSMULSP : XX3Form<60, 16, 1159 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1160 "xsmulsp $XT, $XA, $XB", IIC_VecFP, 1161 [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>; 1162 } // isCommutable 1163 1164 def XSSUBSP : XX3Form<60, 8, 1165 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1166 "xssubsp $XT, $XA, $XB", IIC_VecFP, 1167 [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>; 1168 def XSDIVSP : XX3Form<60, 24, 1169 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1170 "xsdivsp $XT, $XA, $XB", IIC_FPDivS, 1171 [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>; 1172 1173 def XSRESP : XX2Form<60, 26, 1174 (outs vssrc:$XT), (ins vssrc:$XB), 1175 "xsresp $XT, $XB", IIC_VecFP, 1176 [(set f32:$XT, (PPCfre f32:$XB))]>; 1177 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1178 let hasSideEffects = 1 in 1179 def XSRSP : XX2Form<60, 281, 1180 (outs vssrc:$XT), (ins vsfrc:$XB), 1181 "xsrsp $XT, $XB", IIC_VecFP, 1182 [(set f32:$XT, (any_fpround f64:$XB))]>; 1183 def XSSQRTSP : XX2Form<60, 11, 1184 (outs vssrc:$XT), (ins vssrc:$XB), 1185 "xssqrtsp $XT, $XB", IIC_FPSqrtS, 1186 [(set f32:$XT, (any_fsqrt f32:$XB))]>; 1187 def XSRSQRTESP : XX2Form<60, 10, 1188 (outs vssrc:$XT), (ins vssrc:$XB), 1189 "xsrsqrtesp $XT, $XB", IIC_VecFP, 1190 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>; 1191 1192 // FMA Instructions 1193 let BaseName = "XSMADDASP" in { 1194 let isCommutable = 1 in 1195 def XSMADDASP : XX3Form<60, 1, 1196 (outs vssrc:$XT), 1197 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1198 "xsmaddasp $XT, $XA, $XB", IIC_VecFP, 1199 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>, 1200 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1201 AltVSXFMARel; 1202 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1203 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1204 def XSMADDMSP : XX3Form<60, 9, 1205 (outs vssrc:$XT), 1206 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1207 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 1208 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1209 AltVSXFMARel; 1210 } 1211 1212 let BaseName = "XSMSUBASP" in { 1213 let isCommutable = 1 in 1214 def XSMSUBASP : XX3Form<60, 17, 1215 (outs vssrc:$XT), 1216 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1217 "xsmsubasp $XT, $XA, $XB", IIC_VecFP, 1218 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, 1219 (fneg f32:$XTi)))]>, 1220 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1221 AltVSXFMARel; 1222 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1223 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1224 def XSMSUBMSP : XX3Form<60, 25, 1225 (outs vssrc:$XT), 1226 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1227 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 1228 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1229 AltVSXFMARel; 1230 } 1231 1232 let BaseName = "XSNMADDASP" in { 1233 let isCommutable = 1 in 1234 def XSNMADDASP : XX3Form<60, 129, 1235 (outs vssrc:$XT), 1236 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1237 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP, 1238 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB, 1239 f32:$XTi)))]>, 1240 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1241 AltVSXFMARel; 1242 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1243 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1244 def XSNMADDMSP : XX3Form<60, 137, 1245 (outs vssrc:$XT), 1246 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1247 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 1248 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1249 AltVSXFMARel; 1250 } 1251 1252 let BaseName = "XSNMSUBASP" in { 1253 let isCommutable = 1 in 1254 def XSNMSUBASP : XX3Form<60, 145, 1255 (outs vssrc:$XT), 1256 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1257 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP, 1258 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB, 1259 (fneg f32:$XTi))))]>, 1260 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1261 AltVSXFMARel; 1262 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1263 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1264 def XSNMSUBMSP : XX3Form<60, 153, 1265 (outs vssrc:$XT), 1266 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1267 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 1268 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1269 AltVSXFMARel; 1270 } 1271 1272 // Single Precision Conversions (FP <-> INT) 1273 def XSCVSXDSP : XX2Form<60, 312, 1274 (outs vssrc:$XT), (ins vsfrc:$XB), 1275 "xscvsxdsp $XT, $XB", IIC_VecFP, 1276 [(set f32:$XT, (PPCany_fcfids f64:$XB))]>; 1277 def XSCVUXDSP : XX2Form<60, 296, 1278 (outs vssrc:$XT), (ins vsfrc:$XB), 1279 "xscvuxdsp $XT, $XB", IIC_VecFP, 1280 [(set f32:$XT, (PPCany_fcfidus f64:$XB))]>; 1281 } // mayRaiseFPException 1282 1283 // Conversions between vector and scalar single precision 1284 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB), 1285 "xscvdpspn $XT, $XB", IIC_VecFP, []>; 1286 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB), 1287 "xscvspdpn $XT, $XB", IIC_VecFP, []>; 1288 1289 let Predicates = [HasVSX, HasDirectMove] in { 1290 // VSX direct move instructions 1291 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT), 1292 "mfvsrd $rA, $XT", IIC_VecGeneral, 1293 [(set i64:$rA, (PPCmfvsr f64:$XT))]>, 1294 Requires<[In64BitMode]>; 1295 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1296 let isCodeGenOnly = 1, hasSideEffects = 1 in 1297 def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT), 1298 "mfvsrd $rA, $XT", IIC_VecGeneral, 1299 []>, 1300 Requires<[In64BitMode]>; 1301 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT), 1302 "mfvsrwz $rA, $XT", IIC_VecGeneral, 1303 [(set i32:$rA, (PPCmfvsr f64:$XT))]>, ZExt32To64; 1304 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1305 let isCodeGenOnly = 1, hasSideEffects = 1 in 1306 def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT), 1307 "mfvsrwz $rA, $XT", IIC_VecGeneral, 1308 []>; 1309 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA), 1310 "mtvsrd $XT, $rA", IIC_VecGeneral, 1311 [(set f64:$XT, (PPCmtvsra i64:$rA))]>, 1312 Requires<[In64BitMode]>; 1313 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1314 let isCodeGenOnly = 1, hasSideEffects = 1 in 1315 def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA), 1316 "mtvsrd $XT, $rA", IIC_VecGeneral, 1317 []>, 1318 Requires<[In64BitMode]>; 1319 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA), 1320 "mtvsrwa $XT, $rA", IIC_VecGeneral, 1321 [(set f64:$XT, (PPCmtvsra i32:$rA))]>; 1322 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1323 let isCodeGenOnly = 1, hasSideEffects = 1 in 1324 def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA), 1325 "mtvsrwa $XT, $rA", IIC_VecGeneral, 1326 []>; 1327 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA), 1328 "mtvsrwz $XT, $rA", IIC_VecGeneral, 1329 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>; 1330 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1331 let isCodeGenOnly = 1, hasSideEffects = 1 in 1332 def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA), 1333 "mtvsrwz $XT, $rA", IIC_VecGeneral, 1334 []>; 1335 } // HasDirectMove 1336 1337} // HasVSX, HasP8Vector 1338 1339let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in { 1340def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA), 1341 "mtvsrws $XT, $rA", IIC_VecGeneral, []>; 1342 1343def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB), 1344 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral, 1345 []>, Requires<[In64BitMode]>; 1346 1347def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT), 1348 "mfvsrld $rA, $XT", IIC_VecGeneral, 1349 []>, Requires<[In64BitMode]>; 1350 1351} // HasVSX, IsISA3_0, HasDirectMove 1352 1353let Predicates = [HasVSX, HasP9Vector] in { 1354 // Quad-Precision Scalar Move Instructions: 1355 // Copy Sign 1356 def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", 1357 [(set f128:$vT, 1358 (fcopysign f128:$vB, f128:$vA))]>; 1359 1360 // Absolute/Negative-Absolute/Negate 1361 def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp", 1362 [(set f128:$vT, (fabs f128:$vB))]>; 1363 def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", 1364 [(set f128:$vT, (fneg (fabs f128:$vB)))]>; 1365 def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp", 1366 [(set f128:$vT, (fneg f128:$vB))]>; 1367 1368 //===--------------------------------------------------------------------===// 1369 // Quad-Precision Scalar Floating-Point Arithmetic Instructions: 1370 1371 // Add/Divide/Multiply/Subtract 1372 let mayRaiseFPException = 1 in { 1373 let isCommutable = 1 in { 1374 def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp", 1375 [(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>; 1376 def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp", 1377 [(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>; 1378 } 1379 def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , 1380 [(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>; 1381 def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp", 1382 [(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>; 1383 // Square-Root 1384 def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp", 1385 [(set f128:$vT, (any_fsqrt f128:$vB))]>; 1386 // (Negative) Multiply-{Add/Subtract} 1387 def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp", 1388 [(set f128:$vT, 1389 (any_fma f128:$vA, f128:$vB, f128:$vTi))]>; 1390 def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" , 1391 [(set f128:$vT, 1392 (any_fma f128:$vA, f128:$vB, 1393 (fneg f128:$vTi)))]>; 1394 def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp", 1395 [(set f128:$vT, 1396 (fneg (any_fma f128:$vA, f128:$vB, 1397 f128:$vTi)))]>; 1398 def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp", 1399 [(set f128:$vT, 1400 (fneg (any_fma f128:$vA, f128:$vB, 1401 (fneg f128:$vTi))))]>; 1402 1403 let isCommutable = 1 in { 1404 def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", 1405 [(set f128:$vT, 1406 (int_ppc_addf128_round_to_odd 1407 f128:$vA, f128:$vB))]>; 1408 def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", 1409 [(set f128:$vT, 1410 (int_ppc_mulf128_round_to_odd 1411 f128:$vA, f128:$vB))]>; 1412 } 1413 def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", 1414 [(set f128:$vT, 1415 (int_ppc_subf128_round_to_odd 1416 f128:$vA, f128:$vB))]>; 1417 def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", 1418 [(set f128:$vT, 1419 (int_ppc_divf128_round_to_odd 1420 f128:$vA, f128:$vB))]>; 1421 def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", 1422 [(set f128:$vT, 1423 (int_ppc_sqrtf128_round_to_odd f128:$vB))]>; 1424 1425 1426 def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo", 1427 [(set f128:$vT, 1428 (int_ppc_fmaf128_round_to_odd 1429 f128:$vA,f128:$vB,f128:$vTi))]>; 1430 1431 def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" , 1432 [(set f128:$vT, 1433 (int_ppc_fmaf128_round_to_odd 1434 f128:$vA, f128:$vB, (fneg f128:$vTi)))]>; 1435 def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo", 1436 [(set f128:$vT, 1437 (fneg (int_ppc_fmaf128_round_to_odd 1438 f128:$vA, f128:$vB, f128:$vTi)))]>; 1439 def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo", 1440 [(set f128:$vT, 1441 (fneg (int_ppc_fmaf128_round_to_odd 1442 f128:$vA, f128:$vB, (fneg f128:$vTi))))]>; 1443 } // mayRaiseFPException 1444 1445 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1446 // QP Compare Ordered/Unordered 1447 let hasSideEffects = 1 in { 1448 // DP/QP Compare Exponents 1449 def XSCMPEXPDP : XX3Form_1<60, 59, 1450 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 1451 "xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>; 1452 def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>; 1453 1454 let mayRaiseFPException = 1 in { 1455 def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>; 1456 def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>; 1457 1458 // DP Compare ==, >=, >, != 1459 // Use vsrc for XT, because the entire register of XT is set. 1460 // XT.dword[1] = 0x0000_0000_0000_0000 1461 def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc, 1462 IIC_FPCompare, []>; 1463 def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc, 1464 IIC_FPCompare, []>; 1465 def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc, 1466 IIC_FPCompare, []>; 1467 } 1468 } 1469 1470 //===--------------------------------------------------------------------===// 1471 // Quad-Precision Floating-Point Conversion Instructions: 1472 1473 let mayRaiseFPException = 1 in { 1474 // Convert DP -> QP 1475 def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, 1476 [(set f128:$vT, (any_fpextend f64:$vB))]>; 1477 1478 // Round & Convert QP -> DP (dword[1] is set to zero) 1479 def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; 1480 def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", 1481 [(set f64:$vT, 1482 (int_ppc_truncf128_round_to_odd 1483 f128:$vB))]>; 1484 } 1485 1486 // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) 1487 let mayRaiseFPException = 1 in { 1488 def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>; 1489 def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>; 1490 def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>; 1491 def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>; 1492 } 1493 1494 // Convert (Un)Signed DWord -> QP. 1495 def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; 1496 def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; 1497 1498 // (Round &) Convert DP <-> HP 1499 // Note! xscvdphp's src and dest register both use the left 64 bits, so we use 1500 // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits, 1501 // but we still use vsfrc for it. 1502 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1503 let hasSideEffects = 1, mayRaiseFPException = 1 in { 1504 def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>; 1505 def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>; 1506 } 1507 1508 let mayRaiseFPException = 1 in { 1509 // Vector HP -> SP 1510 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1511 let hasSideEffects = 1 in 1512 def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>; 1513 def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, 1514 [(set v4f32:$XT, 1515 (int_ppc_vsx_xvcvsphp v4f32:$XB))]>; 1516 1517 // Round to Quad-Precision Integer [with Inexact] 1518 def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>; 1519 def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>; 1520 1521 // Round Quad-Precision to Double-Extended Precision (fp80) 1522 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1523 let hasSideEffects = 1 in 1524 def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>; 1525 } 1526 1527 //===--------------------------------------------------------------------===// 1528 // Insert/Extract Instructions 1529 1530 // Insert Exponent DP/QP 1531 // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU 1532 def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB), 1533 "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>; 1534 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1535 let hasSideEffects = 1 in { 1536 // vB NOTE: only vB.dword[0] is used, that's why we don't use 1537 // X_VT5_VA5_VB5 form 1538 def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB), 1539 "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>; 1540 } 1541 1542 // Extract Exponent/Significand DP/QP 1543 def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>; 1544 def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>; 1545 1546 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1547 let hasSideEffects = 1 in { 1548 def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>; 1549 def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>; 1550 } 1551 1552 // Vector Insert Word 1553 // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB. 1554 def XXINSERTW : 1555 XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT), 1556 (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM), 1557 "xxinsertw $XT, $XB, $UIM", IIC_VecFP, 1558 [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB, 1559 imm32SExt16:$UIM))]>, 1560 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1561 1562 // Vector Extract Unsigned Word 1563 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1564 let hasSideEffects = 1 in 1565 def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165, 1566 (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM), 1567 "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>; 1568 1569 // Vector Insert Exponent DP/SP 1570 def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc, 1571 IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>; 1572 def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc, 1573 IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>; 1574 1575 // Vector Extract Exponent/Significand DP/SP 1576 def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, 1577 [(set v2i64: $XT, 1578 (int_ppc_vsx_xvxexpdp v2f64:$XB))]>; 1579 def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, 1580 [(set v4i32: $XT, 1581 (int_ppc_vsx_xvxexpsp v4f32:$XB))]>; 1582 def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, 1583 [(set v2i64: $XT, 1584 (int_ppc_vsx_xvxsigdp v2f64:$XB))]>; 1585 def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, 1586 [(set v4i32: $XT, 1587 (int_ppc_vsx_xvxsigsp v4f32:$XB))]>; 1588 1589 // Test Data Class SP/DP/QP 1590 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1591 let hasSideEffects = 1 in { 1592 def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298, 1593 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 1594 "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>; 1595 def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362, 1596 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 1597 "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>; 1598 def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708, 1599 (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB), 1600 "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>; 1601 } 1602 1603 // Vector Test Data Class SP/DP 1604 def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, 1605 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 1606 "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, 1607 [(set v4i32: $XT, 1608 (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>; 1609 def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5, 1610 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 1611 "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, 1612 [(set v2i64: $XT, 1613 (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>; 1614 1615 // Maximum/Minimum Type-C/Type-J DP 1616 let mayRaiseFPException = 1 in { 1617 def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc, 1618 IIC_VecFP, 1619 [(set f64:$XT, (PPCxsmaxc f64:$XA, f64:$XB))]>; 1620 def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc, 1621 IIC_VecFP, 1622 [(set f64:$XT, (PPCxsminc f64:$XA, f64:$XB))]>; 1623 1624 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1625 let hasSideEffects = 1 in { 1626 def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc, 1627 IIC_VecFP, []>; 1628 def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc, 1629 IIC_VecFP, []>; 1630 } 1631 } 1632 1633 // Vector Byte-Reverse H/W/D/Q Word 1634 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1635 let hasSideEffects = 1 in 1636 def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>; 1637 def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, 1638 [(set v4i32:$XT, (bswap v4i32:$XB))]>; 1639 def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, 1640 [(set v2i64:$XT, (bswap v2i64:$XB))]>; 1641 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1642 let hasSideEffects = 1 in 1643 def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>; 1644 1645 // Vector Permute 1646 def XXPERM : XX3Form<60, 26, (outs vsrc:$XT), 1647 (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB), 1648 "xxperm $XT, $XA, $XB", IIC_VecPerm, []>, 1649 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1650 def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT), 1651 (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB), 1652 "xxpermr $XT, $XA, $XB", IIC_VecPerm, []>, 1653 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1654 1655 // Vector Splat Immediate Byte 1656 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1657 let hasSideEffects = 1 in 1658 def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8), 1659 "xxspltib $XT, $IMM8", IIC_VecPerm, []>; 1660 1661 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in 1662 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. 1663 let mayLoad = 1, mayStore = 0 in { 1664 // Load Vector 1665 def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src), 1666 "lxv $XT, $src", IIC_LdStLFD, []>; 1667 // Load DWord 1668 def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src), 1669 "lxsd $vD, $src", IIC_LdStLFD, []>; 1670 // Load SP from src, convert it to DP, and place in dword[0] 1671 def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src), 1672 "lxssp $vD, $src", IIC_LdStLFD, []>; 1673 1674 // Load as Integer Byte/Halfword & Zero Indexed 1675 def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, 1676 [(set f64:$XT, (PPClxsizx ForceXForm:$src, 1))]>; 1677 def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, 1678 [(set f64:$XT, (PPClxsizx ForceXForm:$src, 2))]>; 1679 1680 // Load Vector Halfword*8/Byte*16 Indexed 1681 def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; 1682 def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>; 1683 1684 // Load Vector Indexed 1685 def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, 1686 [(set v2f64:$XT, (load XForm:$src))]>; 1687 // Load Vector (Left-justified) with Length 1688 def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), 1689 "lxvl $XT, $src, $rB", IIC_LdStLoad, 1690 [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>; 1691 def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), 1692 "lxvll $XT, $src, $rB", IIC_LdStLoad, 1693 [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>; 1694 1695 // Load Vector Word & Splat Indexed 1696 def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; 1697 } // mayLoad 1698 1699 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in 1700 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. 1701 let mayStore = 1, mayLoad = 0 in { 1702 // Store Vector 1703 def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst), 1704 "stxv $XT, $dst", IIC_LdStSTFD, []>; 1705 // Store DWord 1706 def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst), 1707 "stxsd $vS, $dst", IIC_LdStSTFD, []>; 1708 // Convert DP of dword[0] to SP, and Store to dst 1709 def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst), 1710 "stxssp $vS, $dst", IIC_LdStSTFD, []>; 1711 1712 // Store as Integer Byte/Halfword Indexed 1713 def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, 1714 [(PPCstxsix f64:$XT, ForceXForm:$dst, 1)]>; 1715 def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, 1716 [(PPCstxsix f64:$XT, ForceXForm:$dst, 2)]>; 1717 let isCodeGenOnly = 1 in { 1718 def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>; 1719 def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>; 1720 } 1721 1722 // Store Vector Halfword*8/Byte*16 Indexed 1723 def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>; 1724 def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>; 1725 1726 // Store Vector Indexed 1727 def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, 1728 [(store v2f64:$XT, XForm:$dst)]>; 1729 1730 // Store Vector (Left-justified) with Length 1731 def STXVL : XX1Form_memOp<31, 397, (outs), 1732 (ins vsrc:$XT, memr:$dst, g8rc:$rB), 1733 "stxvl $XT, $dst, $rB", IIC_LdStLoad, 1734 [(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst, 1735 i64:$rB)]>; 1736 def STXVLL : XX1Form_memOp<31, 429, (outs), 1737 (ins vsrc:$XT, memr:$dst, g8rc:$rB), 1738 "stxvll $XT, $dst, $rB", IIC_LdStLoad, 1739 [(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst, 1740 i64:$rB)]>; 1741 } // mayStore 1742 1743 def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src), 1744 "#DFLOADf32", 1745 [(set f32:$XT, (load DSForm:$src))]>; 1746 def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src), 1747 "#DFLOADf64", 1748 [(set f64:$XT, (load DSForm:$src))]>; 1749 def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst), 1750 "#DFSTOREf32", 1751 [(store f32:$XT, DSForm:$dst)]>; 1752 def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst), 1753 "#DFSTOREf64", 1754 [(store f64:$XT, DSForm:$dst)]>; 1755 1756 let mayStore = 1 in { 1757 def SPILLTOVSR_STX : PseudoXFormMemOp<(outs), 1758 (ins spilltovsrrc:$XT, memrr:$dst), 1759 "#SPILLTOVSR_STX", []>; 1760 def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst), 1761 "#SPILLTOVSR_ST", []>; 1762 } 1763 let mayLoad = 1 in { 1764 def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT), 1765 (ins memrr:$src), 1766 "#SPILLTOVSR_LDX", []>; 1767 def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src), 1768 "#SPILLTOVSR_LD", []>; 1769 1770 } 1771 } // HasP9Vector 1772} // hasSideEffects = 0 1773 1774let PPC970_Single = 1, AddedComplexity = 400 in { 1775 1776 def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst), 1777 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC), 1778 "#SELECT_CC_VSRC", 1779 []>; 1780 def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst), 1781 (ins crbitrc:$cond, vsrc:$T, vsrc:$F), 1782 "#SELECT_VSRC", 1783 [(set v2f64:$dst, 1784 (select i1:$cond, v2f64:$T, v2f64:$F))]>; 1785 def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst), 1786 (ins crrc:$cond, f8rc:$T, f8rc:$F, 1787 i32imm:$BROPC), "#SELECT_CC_VSFRC", 1788 []>; 1789 def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst), 1790 (ins crbitrc:$cond, f8rc:$T, f8rc:$F), 1791 "#SELECT_VSFRC", 1792 [(set f64:$dst, 1793 (select i1:$cond, f64:$T, f64:$F))]>; 1794 def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst), 1795 (ins crrc:$cond, f4rc:$T, f4rc:$F, 1796 i32imm:$BROPC), "#SELECT_CC_VSSRC", 1797 []>; 1798 def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst), 1799 (ins crbitrc:$cond, f4rc:$T, f4rc:$F), 1800 "#SELECT_VSSRC", 1801 [(set f32:$dst, 1802 (select i1:$cond, f32:$T, f32:$F))]>; 1803} 1804} 1805 1806//----------------------------- DAG Definitions ------------------------------// 1807 1808// Output dag used to bitcast f32 to i32 and f64 to i64 1809def Bitcast { 1810 dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64))); 1811 dag DblToLong = (i64 (MFVSRD $A)); 1812} 1813 1814def FpMinMax { 1815 dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC), 1816 (COPY_TO_REGCLASS $B, VSFRC)), 1817 VSSRC); 1818 dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC), 1819 (COPY_TO_REGCLASS $B, VSFRC)), 1820 VSSRC); 1821} 1822 1823def ScalarLoads { 1824 dag Li8 = (i32 (extloadi8 ForceXForm:$src)); 1825 dag ZELi8 = (i32 (zextloadi8 ForceXForm:$src)); 1826 dag ZELi8i64 = (i64 (zextloadi8 ForceXForm:$src)); 1827 dag SELi8 = (i32 (sext_inreg (extloadi8 ForceXForm:$src), i8)); 1828 dag SELi8i64 = (i64 (sext_inreg (extloadi8 ForceXForm:$src), i8)); 1829 1830 dag Li16 = (i32 (extloadi16 ForceXForm:$src)); 1831 dag ZELi16 = (i32 (zextloadi16 ForceXForm:$src)); 1832 dag ZELi16i64 = (i64 (zextloadi16 ForceXForm:$src)); 1833 dag SELi16 = (i32 (sextloadi16 ForceXForm:$src)); 1834 dag SELi16i64 = (i64 (sextloadi16 ForceXForm:$src)); 1835 1836 dag Li32 = (i32 (load ForceXForm:$src)); 1837} 1838 1839def DWToSPExtractConv { 1840 dag El0US1 = (f32 (PPCfcfidus 1841 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); 1842 dag El1US1 = (f32 (PPCfcfidus 1843 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); 1844 dag El0US2 = (f32 (PPCfcfidus 1845 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); 1846 dag El1US2 = (f32 (PPCfcfidus 1847 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); 1848 dag El0SS1 = (f32 (PPCfcfids 1849 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); 1850 dag El1SS1 = (f32 (PPCfcfids 1851 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); 1852 dag El0SS2 = (f32 (PPCfcfids 1853 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); 1854 dag El1SS2 = (f32 (PPCfcfids 1855 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); 1856 dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2)); 1857 dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2)); 1858} 1859 1860def WToDPExtractConv { 1861 dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0)))); 1862 dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1)))); 1863 dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2)))); 1864 dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3)))); 1865 dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0)))); 1866 dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1)))); 1867 dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2)))); 1868 dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3)))); 1869 dag BV02S = (v2f64 (build_vector El0S, El2S)); 1870 dag BV13S = (v2f64 (build_vector El1S, El3S)); 1871 dag BV02U = (v2f64 (build_vector El0U, El2U)); 1872 dag BV13U = (v2f64 (build_vector El1U, El3U)); 1873} 1874 1875/* Direct moves of various widths from GPR's into VSR's. Each move lines 1876 the value up into element 0 (both BE and LE). Namely, entities smaller than 1877 a doubleword are shifted left and moved for BE. For LE, they're moved, then 1878 swapped to go into the least significant element of the VSR. 1879*/ 1880def MovesToVSR { 1881 dag BE_BYTE_0 = 1882 (MTVSRD 1883 (RLDICR 1884 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7)); 1885 dag BE_HALF_0 = 1886 (MTVSRD 1887 (RLDICR 1888 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15)); 1889 dag BE_WORD_0 = 1890 (MTVSRD 1891 (RLDICR 1892 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31)); 1893 dag BE_DWORD_0 = (MTVSRD $A); 1894 1895 dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32)); 1896 dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1897 LE_MTVSRW, sub_64)); 1898 dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2); 1899 dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1900 BE_DWORD_0, sub_64)); 1901 dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2); 1902} 1903 1904/* Patterns for extracting elements out of vectors. Integer elements are 1905 extracted using direct move operations. Patterns for extracting elements 1906 whose indices are not available at compile time are also provided with 1907 various _VARIABLE_ patterns. 1908 The numbering for the DAG's is for LE, but when used on BE, the correct 1909 LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13). 1910*/ 1911def VectorExtractions { 1912 // Doubleword extraction 1913 dag LE_DWORD_0 = 1914 (MFVSRD 1915 (EXTRACT_SUBREG 1916 (XXPERMDI (COPY_TO_REGCLASS $S, VSRC), 1917 (COPY_TO_REGCLASS $S, VSRC), 2), sub_64)); 1918 dag LE_DWORD_1 = (MFVSRD 1919 (EXTRACT_SUBREG 1920 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 1921 1922 // Word extraction 1923 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64)); 1924 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64)); 1925 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG 1926 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 1927 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64)); 1928 1929 // Halfword extraction 1930 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32)); 1931 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32)); 1932 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32)); 1933 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32)); 1934 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32)); 1935 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32)); 1936 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32)); 1937 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32)); 1938 1939 // Byte extraction 1940 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32)); 1941 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32)); 1942 dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32)); 1943 dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32)); 1944 dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32)); 1945 dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32)); 1946 dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32)); 1947 dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32)); 1948 dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32)); 1949 dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32)); 1950 dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32)); 1951 dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32)); 1952 dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32)); 1953 dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32)); 1954 dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32)); 1955 dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32)); 1956 1957 /* Variable element number (BE and LE patterns must be specified separately) 1958 This is a rather involved process. 1959 1960 Conceptually, this is how the move is accomplished: 1961 1. Identify which doubleword contains the element 1962 2. Shift in the VMX register so that the correct doubleword is correctly 1963 lined up for the MFVSRD 1964 3. Perform the move so that the element (along with some extra stuff) 1965 is in the GPR 1966 4. Right shift within the GPR so that the element is right-justified 1967 1968 Of course, the index is an element number which has a different meaning 1969 on LE/BE so the patterns have to be specified separately. 1970 1971 Note: The final result will be the element right-justified with high 1972 order bits being arbitrarily defined (namely, whatever was in the 1973 vector register to the left of the value originally). 1974 */ 1975 1976 /* LE variable byte 1977 Number 1. above: 1978 - For elements 0-7, we shift left by 8 bytes since they're on the right 1979 - For elements 8-15, we need not shift (shift left by zero bytes) 1980 This is accomplished by inverting the bits of the index and AND-ing 1981 with 0x8 (i.e. clearing all bits of the index and inverting bit 60). 1982 */ 1983 dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx))); 1984 1985 // Number 2. above: 1986 // - Now that we set up the shift amount, we shift in the VMX register 1987 dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC)); 1988 1989 // Number 3. above: 1990 // - The doubleword containing our element is moved to a GPR 1991 dag LE_MV_VBYTE = (MFVSRD 1992 (EXTRACT_SUBREG 1993 (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)), 1994 sub_64)); 1995 1996 /* Number 4. above: 1997 - Truncate the element number to the range 0-7 (8-15 are symmetrical 1998 and out of range values are truncated accordingly) 1999 - Multiply by 8 as we need to shift right by the number of bits, not bytes 2000 - Shift right in the GPR by the calculated value 2001 */ 2002 dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60), 2003 sub_32); 2004 dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT), 2005 sub_32); 2006 2007 /* LE variable halfword 2008 Number 1. above: 2009 - For elements 0-3, we shift left by 8 since they're on the right 2010 - For elements 4-7, we need not shift (shift left by zero bytes) 2011 Similarly to the byte pattern, we invert the bits of the index, but we 2012 AND with 0x4 (i.e. clear all bits of the index and invert bit 61). 2013 Of course, the shift is still by 8 bytes, so we must multiply by 2. 2014 */ 2015 dag LE_VHALF_PERM_VEC = 2016 (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62))); 2017 2018 // Number 2. above: 2019 // - Now that we set up the shift amount, we shift in the VMX register 2020 dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC)); 2021 2022 // Number 3. above: 2023 // - The doubleword containing our element is moved to a GPR 2024 dag LE_MV_VHALF = (MFVSRD 2025 (EXTRACT_SUBREG 2026 (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)), 2027 sub_64)); 2028 2029 /* Number 4. above: 2030 - Truncate the element number to the range 0-3 (4-7 are symmetrical 2031 and out of range values are truncated accordingly) 2032 - Multiply by 16 as we need to shift right by the number of bits 2033 - Shift right in the GPR by the calculated value 2034 */ 2035 dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59), 2036 sub_32); 2037 dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT), 2038 sub_32); 2039 2040 /* LE variable word 2041 Number 1. above: 2042 - For elements 0-1, we shift left by 8 since they're on the right 2043 - For elements 2-3, we need not shift 2044 */ 2045 dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2046 (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61))); 2047 2048 // Number 2. above: 2049 // - Now that we set up the shift amount, we shift in the VMX register 2050 dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC)); 2051 2052 // Number 3. above: 2053 // - The doubleword containing our element is moved to a GPR 2054 dag LE_MV_VWORD = (MFVSRD 2055 (EXTRACT_SUBREG 2056 (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)), 2057 sub_64)); 2058 2059 /* Number 4. above: 2060 - Truncate the element number to the range 0-1 (2-3 are symmetrical 2061 and out of range values are truncated accordingly) 2062 - Multiply by 32 as we need to shift right by the number of bits 2063 - Shift right in the GPR by the calculated value 2064 */ 2065 dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58), 2066 sub_32); 2067 dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT), 2068 sub_32); 2069 2070 /* LE variable doubleword 2071 Number 1. above: 2072 - For element 0, we shift left by 8 since it's on the right 2073 - For element 1, we need not shift 2074 */ 2075 dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2076 (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60))); 2077 2078 // Number 2. above: 2079 // - Now that we set up the shift amount, we shift in the VMX register 2080 dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC)); 2081 2082 // Number 3. above: 2083 // - The doubleword containing our element is moved to a GPR 2084 // - Number 4. is not needed for the doubleword as the value is 64-bits 2085 dag LE_VARIABLE_DWORD = 2086 (MFVSRD (EXTRACT_SUBREG 2087 (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)), 2088 sub_64)); 2089 2090 /* LE variable float 2091 - Shift the vector to line up the desired element to BE Word 0 2092 - Convert 32-bit float to a 64-bit single precision float 2093 */ 2094 dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, 2095 (RLDICR (XOR8 (LI8 3), $Idx), 2, 61))); 2096 dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC); 2097 dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE); 2098 2099 /* LE variable double 2100 Same as the LE doubleword except there is no move. 2101 */ 2102 dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2103 (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2104 LE_VDWORD_PERM_VEC)); 2105 dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC); 2106 2107 /* BE variable byte 2108 The algorithm here is the same as the LE variable byte except: 2109 - The shift in the VMX register is by 0/8 for opposite element numbers so 2110 we simply AND the element number with 0x8 2111 - The order of elements after the move to GPR is reversed, so we invert 2112 the bits of the index prior to truncating to the range 0-7 2113 */ 2114 dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8))); 2115 dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC)); 2116 dag BE_MV_VBYTE = (MFVSRD 2117 (EXTRACT_SUBREG 2118 (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)), 2119 sub_64)); 2120 dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60), 2121 sub_32); 2122 dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT), 2123 sub_32); 2124 2125 /* BE variable halfword 2126 The algorithm here is the same as the LE variable halfword except: 2127 - The shift in the VMX register is by 0/8 for opposite element numbers so 2128 we simply AND the element number with 0x4 and multiply by 2 2129 - The order of elements after the move to GPR is reversed, so we invert 2130 the bits of the index prior to truncating to the range 0-3 2131 */ 2132 dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8, 2133 (RLDICR (ANDI8_rec $Idx, 4), 1, 62))); 2134 dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC)); 2135 dag BE_MV_VHALF = (MFVSRD 2136 (EXTRACT_SUBREG 2137 (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)), 2138 sub_64)); 2139 dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59), 2140 sub_32); 2141 dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT), 2142 sub_32); 2143 2144 /* BE variable word 2145 The algorithm is the same as the LE variable word except: 2146 - The shift in the VMX register happens for opposite element numbers 2147 - The order of elements after the move to GPR is reversed, so we invert 2148 the bits of the index prior to truncating to the range 0-1 2149 */ 2150 dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2151 (RLDICR (ANDI8_rec $Idx, 2), 2, 61))); 2152 dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC)); 2153 dag BE_MV_VWORD = (MFVSRD 2154 (EXTRACT_SUBREG 2155 (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)), 2156 sub_64)); 2157 dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58), 2158 sub_32); 2159 dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT), 2160 sub_32); 2161 2162 /* BE variable doubleword 2163 Same as the LE doubleword except we shift in the VMX register for opposite 2164 element indices. 2165 */ 2166 dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2167 (RLDICR (ANDI8_rec $Idx, 1), 3, 60))); 2168 dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC)); 2169 dag BE_VARIABLE_DWORD = 2170 (MFVSRD (EXTRACT_SUBREG 2171 (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)), 2172 sub_64)); 2173 2174 /* BE variable float 2175 - Shift the vector to line up the desired element to BE Word 0 2176 - Convert 32-bit float to a 64-bit single precision float 2177 */ 2178 dag BE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, (RLDICR $Idx, 2, 61))); 2179 dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC); 2180 dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE); 2181 2182 // BE variable float 32-bit version 2183 dag BE_32B_VFLOAT_PERM_VEC = (v16i8 (LVSL (i32 ZERO), (RLWINM $Idx, 2, 0, 29))); 2184 dag BE_32B_VFLOAT_PERMUTE = (VPERM $S, $S, BE_32B_VFLOAT_PERM_VEC); 2185 dag BE_32B_VARIABLE_FLOAT = (XSCVSPDPN BE_32B_VFLOAT_PERMUTE); 2186 2187 /* BE variable double 2188 Same as the BE doubleword except there is no move. 2189 */ 2190 dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2191 (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2192 BE_VDWORD_PERM_VEC)); 2193 dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC); 2194 2195 // BE variable double 32-bit version 2196 dag BE_32B_VDWORD_PERM_VEC = (v16i8 (LVSL (i32 ZERO), 2197 (RLWINM (ANDI_rec $Idx, 1), 3, 0, 28))); 2198 dag BE_32B_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2199 (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2200 BE_32B_VDWORD_PERM_VEC)); 2201 dag BE_32B_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_32B_VDOUBLE_PERMUTE, VSRC); 2202} 2203 2204def AlignValues { 2205 dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B)); 2206 dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64); 2207} 2208 2209// Integer extend helper dags 32 -> 64 2210def AnyExts { 2211 dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32); 2212 dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32); 2213 dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32); 2214 dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32); 2215} 2216 2217def DblToFlt { 2218 dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0)))); 2219 dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1)))); 2220 dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0)))); 2221 dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1)))); 2222} 2223 2224def ExtDbl { 2225 dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0)))))); 2226 dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1)))))); 2227 dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0)))))); 2228 dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1)))))); 2229 dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0)))))); 2230 dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1)))))); 2231 dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0)))))); 2232 dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1)))))); 2233} 2234 2235def ByteToWord { 2236 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8)); 2237 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8)); 2238 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8)); 2239 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8)); 2240 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8)); 2241 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 7)), i8)); 2242 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 11)), i8)); 2243 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 15)), i8)); 2244} 2245 2246def ByteToDWord { 2247 dag LE_A0 = (i64 (sext_inreg 2248 (i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8)); 2249 dag LE_A1 = (i64 (sext_inreg 2250 (i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8)); 2251 dag BE_A0 = (i64 (sext_inreg 2252 (i64 (anyext (i32 (vector_extract v16i8:$A, 7)))), i8)); 2253 dag BE_A1 = (i64 (sext_inreg 2254 (i64 (anyext (i32 (vector_extract v16i8:$A, 15)))), i8)); 2255} 2256 2257def HWordToWord { 2258 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16)); 2259 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16)); 2260 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16)); 2261 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16)); 2262 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16)); 2263 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16)); 2264 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16)); 2265 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16)); 2266} 2267 2268def HWordToDWord { 2269 dag LE_A0 = (i64 (sext_inreg 2270 (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16)); 2271 dag LE_A1 = (i64 (sext_inreg 2272 (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16)); 2273 dag BE_A0 = (i64 (sext_inreg 2274 (i64 (anyext (i32 (vector_extract v8i16:$A, 3)))), i16)); 2275 dag BE_A1 = (i64 (sext_inreg 2276 (i64 (anyext (i32 (vector_extract v8i16:$A, 7)))), i16)); 2277} 2278 2279def WordToDWord { 2280 dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0)))); 2281 dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2)))); 2282 dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1)))); 2283 dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3)))); 2284} 2285 2286def FltToIntLoad { 2287 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 ForceXForm:$A))))); 2288} 2289def FltToUIntLoad { 2290 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 ForceXForm:$A))))); 2291} 2292def FltToLongLoad { 2293 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 ForceXForm:$A))))); 2294} 2295def FltToLongLoadP9 { 2296 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 DSForm:$A))))); 2297} 2298def FltToULongLoad { 2299 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 ForceXForm:$A))))); 2300} 2301def FltToULongLoadP9 { 2302 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 DSForm:$A))))); 2303} 2304def FltToLong { 2305 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A))))); 2306} 2307def FltToULong { 2308 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A))))); 2309} 2310def DblToInt { 2311 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A)))); 2312 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B)))); 2313 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C)))); 2314 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D)))); 2315} 2316def DblToUInt { 2317 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A)))); 2318 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B)))); 2319 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C)))); 2320 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D)))); 2321} 2322def DblToLong { 2323 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A)))); 2324} 2325def DblToULong { 2326 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A)))); 2327} 2328def DblToIntLoad { 2329 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load ForceXForm:$A))))); 2330} 2331def DblToIntLoadP9 { 2332 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load DSForm:$A))))); 2333} 2334def DblToUIntLoad { 2335 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load ForceXForm:$A))))); 2336} 2337def DblToUIntLoadP9 { 2338 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load DSForm:$A))))); 2339} 2340def DblToLongLoad { 2341 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load ForceXForm:$A))))); 2342} 2343def DblToULongLoad { 2344 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load ForceXForm:$A))))); 2345} 2346 2347// FP load dags (for f32 -> v4f32) 2348def LoadFP { 2349 dag A = (f32 (load ForceXForm:$A)); 2350 dag B = (f32 (load ForceXForm:$B)); 2351 dag C = (f32 (load ForceXForm:$C)); 2352 dag D = (f32 (load ForceXForm:$D)); 2353} 2354 2355// FP merge dags (for f32 -> v4f32) 2356def MrgFP { 2357 dag LD32A = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64); 2358 dag LD32B = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$B), sub_64); 2359 dag LD32C = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$C), sub_64); 2360 dag LD32D = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$D), sub_64); 2361 dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), 2362 (SUBREG_TO_REG (i64 1), $C, sub_64), 0)); 2363 dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), 2364 (SUBREG_TO_REG (i64 1), $D, sub_64), 0)); 2365 dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0)); 2366 dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3)); 2367 dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0)); 2368 dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3)); 2369} 2370 2371// Word-element merge dags - conversions from f64 to i32 merged into vectors. 2372def MrgWords { 2373 // For big endian, we merge low and hi doublewords (A, B). 2374 dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0)); 2375 dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3)); 2376 dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1)); 2377 dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0)); 2378 dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1)); 2379 dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0)); 2380 2381 // For little endian, we merge low and hi doublewords (B, A). 2382 dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0)); 2383 dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3)); 2384 dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1)); 2385 dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0)); 2386 dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1)); 2387 dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0)); 2388 2389 // For big endian, we merge hi doublewords of (A, C) and (B, D), convert 2390 // then merge. 2391 dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 2392 (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 0)); 2393 dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 2394 (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 0)); 2395 dag CVACS = (v4i32 (XVCVDPSXWS AC)); 2396 dag CVBDS = (v4i32 (XVCVDPSXWS BD)); 2397 dag CVACU = (v4i32 (XVCVDPUXWS AC)); 2398 dag CVBDU = (v4i32 (XVCVDPUXWS BD)); 2399 2400 // For little endian, we merge hi doublewords of (D, B) and (C, A), convert 2401 // then merge. 2402 dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 2403 (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 0)); 2404 dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 2405 (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 0)); 2406 dag CVDBS = (v4i32 (XVCVDPSXWS DB)); 2407 dag CVCAS = (v4i32 (XVCVDPSXWS CA)); 2408 dag CVDBU = (v4i32 (XVCVDPUXWS DB)); 2409 dag CVCAU = (v4i32 (XVCVDPUXWS CA)); 2410} 2411 2412def DblwdCmp { 2413 dag SGTW = (v2i64 (v2i64 (VCMPGTSW v2i64:$vA, v2i64:$vB))); 2414 dag UGTW = (v2i64 (v2i64 (VCMPGTUW v2i64:$vA, v2i64:$vB))); 2415 dag EQW = (v2i64 (v2i64 (VCMPEQUW v2i64:$vA, v2i64:$vB))); 2416 dag UGTWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI UGTW, UGTW, 1)), EQW)); 2417 dag EQWSHAND = (v2i64 (XXLAND (v2i64 (XXSLDWI EQW, EQW, 1)), EQW)); 2418 dag SGTWOR = (v2i64 (XXLOR SGTW, UGTWSHAND)); 2419 dag UGTWOR = (v2i64 (XXLOR UGTW, UGTWSHAND)); 2420 dag MRGSGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW SGTWOR, 0)), 2421 (v2i64 (XXSPLTW SGTWOR, 2)), 0)); 2422 dag MRGUGT = (v2i64 (XXPERMDI (v2i64 (XXSPLTW UGTWOR, 0)), 2423 (v2i64 (XXSPLTW UGTWOR, 2)), 0)); 2424 dag MRGEQ = (v2i64 (XXPERMDI (v2i64 (XXSPLTW EQWSHAND, 0)), 2425 (v2i64 (XXSPLTW EQWSHAND, 2)), 0)); 2426} 2427 2428//---------------------------- Anonymous Patterns ----------------------------// 2429// Predicate combinations are kept in roughly chronological order in terms of 2430// instruction availability in the architecture. For example, VSX came in with 2431// ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and 2432// ISA 3.0 (Power9). However, the granularity of features on later subtargets 2433// is finer for various reasons. For example, we have Power8Vector, 2434// Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is 2435// similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there 2436// are orthogonal predicates such as endianness for which the order was 2437// arbitrarily chosen to be Big, Little. 2438// 2439// Predicate combinations available: 2440// [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr. 2441// [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr. 2442// [HasVSX] 2443// [HasVSX, IsBigEndian] 2444// [HasVSX, IsLittleEndian] 2445// [HasVSX, NoP9Vector] 2446// [HasVSX, NoP9Vector, IsLittleEndian] 2447// [HasVSX, NoP9Vector, IsBigEndian] 2448// [HasVSX, HasOnlySwappingMemOps] 2449// [HasVSX, HasOnlySwappingMemOps, IsBigEndian] 2450// [HasVSX, HasP8Vector] 2451// [HasVSX, HasP8Vector, IsBigEndian] 2452// [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] 2453// [HasVSX, HasP8Vector, IsLittleEndian] 2454// [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] 2455// [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] 2456// [HasVSX, HasP8Altivec] 2457// [HasVSX, HasDirectMove] 2458// [HasVSX, HasDirectMove, IsBigEndian] 2459// [HasVSX, HasDirectMove, IsLittleEndian] 2460// [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64] 2461// [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] 2462// [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] 2463// [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] 2464// [HasVSX, HasP9Vector] 2465// [HasVSX, HasP9Vector, NoP10Vector] 2466// [HasVSX, HasP9Vector, IsBigEndian] 2467// [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] 2468// [HasVSX, HasP9Vector, IsLittleEndian] 2469// [HasVSX, HasP9Altivec] 2470// [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] 2471// [HasVSX, HasP9Altivec, IsLittleEndian] 2472// [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64] 2473// [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] 2474 2475// These Altivec patterns are here because we need a VSX instruction to match 2476// the intrinsic (but only for little endian system). 2477let Predicates = [HasVSX, IsLittleEndian, HasP8Altivec] in 2478 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a, 2479 v16i8:$b, v16i8:$c)), 2480 (v16i8 (VPERMXOR $a, $b, (XXLNOR (COPY_TO_REGCLASS $c, VSRC), 2481 (COPY_TO_REGCLASS $c, VSRC))))>; 2482let Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in 2483 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a, 2484 v16i8:$b, v16i8:$c)), 2485 (v16i8 (VPERMXOR $a, $b, $c))>; 2486let Predicates = [HasVSX, HasP8Altivec] in 2487 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a, 2488 v16i8:$b, v16i8:$c)), 2489 (v16i8 (VPERMXOR $a, $b, $c))>; 2490 2491let AddedComplexity = 400 in { 2492// Valid for any VSX subtarget, regardless of endianness. 2493let Predicates = [HasVSX] in { 2494def : Pat<(v4i32 (vnot v4i32:$A)), 2495 (v4i32 (XXLNOR $A, $A))>; 2496def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A), 2497 (and v4i32:$B, v4i32:$C))), 2498 (v4i32 (XXSEL $A, $B, $C))>; 2499 2500def : Pat<(f64 (fpimm0neg)), 2501 (f64 (XSNEGDP (XXLXORdpz)))>; 2502 2503def : Pat<(f32 (fpimm0neg)), 2504 (f32 (COPY_TO_REGCLASS (XSNEGDP (XXLXORdpz)), VSSRC))>; 2505 2506def : Pat<(f64 (nzFPImmExactInti5:$A)), 2507 (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS 2508 (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), VSFRC)>; 2509 2510def : Pat<(f32 (nzFPImmExactInti5:$A)), 2511 (COPY_TO_REGCLASS (XVCVSXWDP (COPY_TO_REGCLASS 2512 (VSPLTISW (getFPAs5BitExactInt fpimm:$A)), VSRC)), VSSRC)>; 2513 2514// Additional fnmsub pattern for PPC specific ISD opcode 2515def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 2516 (XSNMSUBADP $C, $A, $B)>; 2517def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 2518 (XSMSUBADP $C, $A, $B)>; 2519def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 2520 (XSNMADDADP $C, $A, $B)>; 2521 2522def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C), 2523 (XVNMSUBADP $C, $A, $B)>; 2524def : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)), 2525 (XVMSUBADP $C, $A, $B)>; 2526def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)), 2527 (XVNMADDADP $C, $A, $B)>; 2528 2529def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), 2530 (XVNMSUBASP $C, $A, $B)>; 2531def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)), 2532 (XVMSUBASP $C, $A, $B)>; 2533def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)), 2534 (XVNMADDASP $C, $A, $B)>; 2535 2536def : Pat<(PPCfsqrt f64:$frA), (XSSQRTDP $frA)>; 2537def : Pat<(PPCfsqrt v2f64:$frA), (XVSQRTDP $frA)>; 2538def : Pat<(PPCfsqrt v4f32:$frA), (XVSQRTSP $frA)>; 2539 2540def : Pat<(v2f64 (bitconvert v4f32:$A)), 2541 (COPY_TO_REGCLASS $A, VSRC)>; 2542def : Pat<(v2f64 (bitconvert v4i32:$A)), 2543 (COPY_TO_REGCLASS $A, VSRC)>; 2544def : Pat<(v2f64 (bitconvert v8i16:$A)), 2545 (COPY_TO_REGCLASS $A, VSRC)>; 2546def : Pat<(v2f64 (bitconvert v16i8:$A)), 2547 (COPY_TO_REGCLASS $A, VSRC)>; 2548 2549def : Pat<(v4f32 (bitconvert v2f64:$A)), 2550 (COPY_TO_REGCLASS $A, VRRC)>; 2551def : Pat<(v4i32 (bitconvert v2f64:$A)), 2552 (COPY_TO_REGCLASS $A, VRRC)>; 2553def : Pat<(v8i16 (bitconvert v2f64:$A)), 2554 (COPY_TO_REGCLASS $A, VRRC)>; 2555def : Pat<(v16i8 (bitconvert v2f64:$A)), 2556 (COPY_TO_REGCLASS $A, VRRC)>; 2557 2558def : Pat<(v2i64 (bitconvert v4f32:$A)), 2559 (COPY_TO_REGCLASS $A, VSRC)>; 2560def : Pat<(v2i64 (bitconvert v4i32:$A)), 2561 (COPY_TO_REGCLASS $A, VSRC)>; 2562def : Pat<(v2i64 (bitconvert v8i16:$A)), 2563 (COPY_TO_REGCLASS $A, VSRC)>; 2564def : Pat<(v2i64 (bitconvert v16i8:$A)), 2565 (COPY_TO_REGCLASS $A, VSRC)>; 2566 2567def : Pat<(v4f32 (bitconvert v2i64:$A)), 2568 (COPY_TO_REGCLASS $A, VRRC)>; 2569def : Pat<(v4i32 (bitconvert v2i64:$A)), 2570 (COPY_TO_REGCLASS $A, VRRC)>; 2571def : Pat<(v8i16 (bitconvert v2i64:$A)), 2572 (COPY_TO_REGCLASS $A, VRRC)>; 2573def : Pat<(v16i8 (bitconvert v2i64:$A)), 2574 (COPY_TO_REGCLASS $A, VRRC)>; 2575 2576def : Pat<(v2f64 (bitconvert v2i64:$A)), 2577 (COPY_TO_REGCLASS $A, VRRC)>; 2578def : Pat<(v2i64 (bitconvert v2f64:$A)), 2579 (COPY_TO_REGCLASS $A, VRRC)>; 2580 2581def : Pat<(v2f64 (bitconvert v1i128:$A)), 2582 (COPY_TO_REGCLASS $A, VRRC)>; 2583def : Pat<(v1i128 (bitconvert v2f64:$A)), 2584 (COPY_TO_REGCLASS $A, VRRC)>; 2585 2586def : Pat<(v2i64 (bitconvert f128:$A)), 2587 (COPY_TO_REGCLASS $A, VRRC)>; 2588def : Pat<(v4i32 (bitconvert f128:$A)), 2589 (COPY_TO_REGCLASS $A, VRRC)>; 2590def : Pat<(v8i16 (bitconvert f128:$A)), 2591 (COPY_TO_REGCLASS $A, VRRC)>; 2592def : Pat<(v16i8 (bitconvert f128:$A)), 2593 (COPY_TO_REGCLASS $A, VRRC)>; 2594 2595def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)), 2596 (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>; 2597def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)), 2598 (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>; 2599 2600def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)), 2601 (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>; 2602def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)), 2603 (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>; 2604 2605def : Pat<(v2f64 (PPCfpexth v4f32:$C, 0)), (XVCVSPDP (XXMRGHW $C, $C))>; 2606def : Pat<(v2f64 (PPCfpexth v4f32:$C, 1)), (XVCVSPDP (XXMRGLW $C, $C))>; 2607 2608// Permutes. 2609def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>; 2610def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>; 2611def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>; 2612def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>; 2613def : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>; 2614 2615// PPCvecshl XT, XA, XA, 2 can be selected to both XXSLDWI XT,XA,XA,2 and 2616// XXSWAPD XT,XA (i.e. XXPERMDI XT,XA,XA,2), the later one is more profitable. 2617def : Pat<(v4i32 (PPCvecshl v4i32:$src, v4i32:$src, 2)), 2618 (XXPERMDI $src, $src, 2)>; 2619 2620// Selects. 2621def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)), 2622 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2623def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)), 2624 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2625def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)), 2626 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 2627def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)), 2628 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 2629def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)), 2630 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>; 2631def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)), 2632 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 2633def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)), 2634 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 2635def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)), 2636 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2637def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)), 2638 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2639def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)), 2640 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 2641 2642def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 2643 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2644def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 2645 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2646def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 2647 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 2648def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 2649 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 2650def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 2651 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>; 2652def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 2653 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 2654def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 2655 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 2656def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 2657 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2658def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 2659 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2660def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 2661 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>; 2662 2663// Divides. 2664def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B), 2665 (XVDIVSP $A, $B)>; 2666def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B), 2667 (XVDIVDP $A, $B)>; 2668 2669// Vector test for software divide and sqrt. 2670def : Pat<(i32 (int_ppc_vsx_xvtdivdp v2f64:$A, v2f64:$B)), 2671 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>; 2672def : Pat<(i32 (int_ppc_vsx_xvtdivsp v4f32:$A, v4f32:$B)), 2673 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>; 2674def : Pat<(i32 (int_ppc_vsx_xvtsqrtdp v2f64:$A)), 2675 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>; 2676def : Pat<(i32 (int_ppc_vsx_xvtsqrtsp v4f32:$A)), 2677 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>; 2678 2679// Reciprocal estimate 2680def : Pat<(int_ppc_vsx_xvresp v4f32:$A), 2681 (XVRESP $A)>; 2682def : Pat<(int_ppc_vsx_xvredp v2f64:$A), 2683 (XVREDP $A)>; 2684 2685// Recip. square root estimate 2686def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A), 2687 (XVRSQRTESP $A)>; 2688def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A), 2689 (XVRSQRTEDP $A)>; 2690 2691// Vector selection 2692def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 2693 (COPY_TO_REGCLASS 2694 (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 2695 (COPY_TO_REGCLASS $vB, VSRC), 2696 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2697def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 2698 (COPY_TO_REGCLASS 2699 (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 2700 (COPY_TO_REGCLASS $vB, VSRC), 2701 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2702def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC), 2703 (XXSEL $vC, $vB, $vA)>; 2704def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC), 2705 (XXSEL $vC, $vB, $vA)>; 2706def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC), 2707 (XXSEL $vC, $vB, $vA)>; 2708def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC), 2709 (XXSEL $vC, $vB, $vA)>; 2710def : Pat<(v1i128 (vselect v1i128:$vA, v1i128:$vB, v1i128:$vC)), 2711 (COPY_TO_REGCLASS 2712 (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 2713 (COPY_TO_REGCLASS $vB, VSRC), 2714 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2715 2716def : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)), 2717 (v4f32 (XVMAXSP $src1, $src2))>; 2718def : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)), 2719 (v4f32 (XVMINSP $src1, $src2))>; 2720def : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)), 2721 (v2f64 (XVMAXDP $src1, $src2))>; 2722def : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)), 2723 (v2f64 (XVMINDP $src1, $src2))>; 2724 2725// f32 abs 2726def : Pat<(f32 (fabs f32:$S)), 2727 (f32 (COPY_TO_REGCLASS (XSABSDP 2728 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2729 2730// f32 nabs 2731def : Pat<(f32 (fneg (fabs f32:$S))), 2732 (f32 (COPY_TO_REGCLASS (XSNABSDP 2733 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2734 2735// f32 Min. 2736def : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)), 2737 (f32 FpMinMax.F32Min)>; 2738def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), f32:$B)), 2739 (f32 FpMinMax.F32Min)>; 2740def : Pat<(f32 (fminnum_ieee f32:$A, (fcanonicalize f32:$B))), 2741 (f32 FpMinMax.F32Min)>; 2742def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))), 2743 (f32 FpMinMax.F32Min)>; 2744// F32 Max. 2745def : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)), 2746 (f32 FpMinMax.F32Max)>; 2747def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), f32:$B)), 2748 (f32 FpMinMax.F32Max)>; 2749def : Pat<(f32 (fmaxnum_ieee f32:$A, (fcanonicalize f32:$B))), 2750 (f32 FpMinMax.F32Max)>; 2751def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))), 2752 (f32 FpMinMax.F32Max)>; 2753 2754// f64 Min. 2755def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)), 2756 (f64 (XSMINDP $A, $B))>; 2757def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)), 2758 (f64 (XSMINDP $A, $B))>; 2759def : Pat<(f64 (fminnum_ieee f64:$A, (fcanonicalize f64:$B))), 2760 (f64 (XSMINDP $A, $B))>; 2761def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))), 2762 (f64 (XSMINDP $A, $B))>; 2763// f64 Max. 2764def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)), 2765 (f64 (XSMAXDP $A, $B))>; 2766def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), f64:$B)), 2767 (f64 (XSMAXDP $A, $B))>; 2768def : Pat<(f64 (fmaxnum_ieee f64:$A, (fcanonicalize f64:$B))), 2769 (f64 (XSMAXDP $A, $B))>; 2770def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))), 2771 (f64 (XSMAXDP $A, $B))>; 2772 2773def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, ForceXForm:$dst), 2774 (STXVD2X $rS, ForceXForm:$dst)>; 2775def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, ForceXForm:$dst), 2776 (STXVW4X $rS, ForceXForm:$dst)>; 2777def : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 2778def : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 2779 2780// Rounding for single precision. 2781def : Pat<(f32 (any_fround f32:$S)), 2782 (f32 (COPY_TO_REGCLASS (XSRDPI 2783 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2784def : Pat<(f32 (any_ffloor f32:$S)), 2785 (f32 (COPY_TO_REGCLASS (XSRDPIM 2786 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2787def : Pat<(f32 (any_fceil f32:$S)), 2788 (f32 (COPY_TO_REGCLASS (XSRDPIP 2789 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2790def : Pat<(f32 (any_ftrunc f32:$S)), 2791 (f32 (COPY_TO_REGCLASS (XSRDPIZ 2792 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2793def : Pat<(f32 (any_frint f32:$S)), 2794 (f32 (COPY_TO_REGCLASS (XSRDPIC 2795 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2796def : Pat<(v4f32 (any_frint v4f32:$S)), (v4f32 (XVRSPIC $S))>; 2797 2798// Rounding for double precision. 2799def : Pat<(f64 (any_frint f64:$S)), (f64 (XSRDPIC $S))>; 2800def : Pat<(v2f64 (any_frint v2f64:$S)), (v2f64 (XVRDPIC $S))>; 2801 2802// Rounding without exceptions (nearbyint). Due to strange tblgen behaviour, 2803// these need to be defined after the any_frint versions so ISEL will correctly 2804// add the chain to the strict versions. 2805def : Pat<(f32 (fnearbyint f32:$S)), 2806 (f32 (COPY_TO_REGCLASS (XSRDPIC 2807 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2808def : Pat<(f64 (fnearbyint f64:$S)), 2809 (f64 (XSRDPIC $S))>; 2810def : Pat<(v2f64 (fnearbyint v2f64:$S)), 2811 (v2f64 (XVRDPIC $S))>; 2812def : Pat<(v4f32 (fnearbyint v4f32:$S)), 2813 (v4f32 (XVRSPIC $S))>; 2814 2815// Materialize a zero-vector of long long 2816def : Pat<(v2i64 immAllZerosV), 2817 (v2i64 (XXLXORz))>; 2818 2819// Build vectors of floating point converted to i32. 2820def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A, 2821 DblToInt.A, DblToInt.A)), 2822 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>; 2823def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A, 2824 DblToUInt.A, DblToUInt.A)), 2825 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>; 2826def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)), 2827 (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 2828 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 0))>; 2829def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)), 2830 (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 2831 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>; 2832def : Pat<(v4i32 (PPCSToV DblToInt.A)), 2833 (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>; 2834def : Pat<(v4i32 (PPCSToV DblToUInt.A)), 2835 (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>; 2836defm : ScalToVecWPermute< 2837 v4i32, FltToIntLoad.A, 2838 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), 2839 (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; 2840defm : ScalToVecWPermute< 2841 v4i32, FltToUIntLoad.A, 2842 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), 2843 (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; 2844def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)), 2845 (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))), 2846 (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>; 2847 2848def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), 2849 (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>; 2850 2851// Splat loads. 2852def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)), 2853 (v2f64 (LXVDSX ForceXForm:$A))>; 2854def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), 2855 (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; 2856def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)), 2857 (v2i64 (LXVDSX ForceXForm:$A))>; 2858def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)), 2859 (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; 2860def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)), 2861 (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>; 2862def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)), 2863 (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>; 2864 2865// Build vectors of floating point converted to i64. 2866def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)), 2867 (v2i64 (XXPERMDIs 2868 (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>; 2869def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)), 2870 (v2i64 (XXPERMDIs 2871 (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>; 2872defm : ScalToVecWPermute< 2873 v2i64, DblToLongLoad.A, 2874 (XVCVDPSXDS (LXVDSX ForceXForm:$A)), (XVCVDPSXDS (LXVDSX ForceXForm:$A))>; 2875defm : ScalToVecWPermute< 2876 v2i64, DblToULongLoad.A, 2877 (XVCVDPUXDS (LXVDSX ForceXForm:$A)), (XVCVDPUXDS (LXVDSX ForceXForm:$A))>; 2878 2879// Doubleword vector predicate comparisons without Power8. 2880let AddedComplexity = 0 in { 2881def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 967)), 2882 (VCMPGTUB_rec DblwdCmp.MRGSGT, (v2i64 (XXLXORz)))>; 2883def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 711)), 2884 (VCMPGTUB_rec DblwdCmp.MRGUGT, (v2i64 (XXLXORz)))>; 2885def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)), 2886 (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>; 2887} // AddedComplexity = 0 2888 2889// XL Compat builtins. 2890def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (XSMSUBMDP $A, $B, $C)>; 2891def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>; 2892def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>; 2893def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>; 2894def : Pat<(int_ppc_fnabs f64:$A), (XSNABSDP $A)>; 2895def : Pat<(int_ppc_fnabss f32:$A), (XSNABSDPs $A)>; 2896 2897// XXMRG[LH]W is a direct replacement for VMRG[LH]W respectively. 2898// Prefer the VSX form for greater register range. 2899def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 2900 (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vA, VSRC), 2901 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2902def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 2903 (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vA, VSRC), 2904 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2905def:Pat<(vmrglw_shuffle v16i8:$vA, v16i8:$vB), 2906 (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vA, VSRC), 2907 (COPY_TO_REGCLASS $vB, VSRC)), VRRC)>; 2908def:Pat<(vmrghw_shuffle v16i8:$vA, v16i8:$vB), 2909 (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vA, VSRC), 2910 (COPY_TO_REGCLASS $vB, VSRC)), VRRC)>; 2911def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 2912 (COPY_TO_REGCLASS (XXMRGLW (COPY_TO_REGCLASS $vB, VSRC), 2913 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2914def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 2915 (COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vB, VSRC), 2916 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2917} // HasVSX 2918 2919// Any big endian VSX subtarget. 2920let Predicates = [HasVSX, IsBigEndian] in { 2921def : Pat<(v2f64 (scalar_to_vector f64:$A)), 2922 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>; 2923 2924def : Pat<(f64 (extractelt v2f64:$S, 0)), 2925 (f64 (EXTRACT_SUBREG $S, sub_64))>; 2926def : Pat<(f64 (extractelt v2f64:$S, 1)), 2927 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 2928def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 2929 (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>; 2930def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 2931 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 2932def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 2933 (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>; 2934def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 2935 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 2936 2937def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 2938 (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>; 2939 2940def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), 2941 (v2f64 (XXPERMDI 2942 (SUBREG_TO_REG (i64 1), $A, sub_64), 2943 (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; 2944// Using VMRGEW to assemble the final vector would be a lower latency 2945// solution. However, we choose to go with the slightly higher latency 2946// XXPERMDI for 2 reasons: 2947// 1. This is likely to occur in unrolled loops where regpressure is high, 2948// so we want to use the latter as it has access to all 64 VSX registers. 2949// 2. Using Altivec instructions in this sequence would likely cause the 2950// allocation of Altivec registers even for the loads which in turn would 2951// force the use of LXSIWZX for the loads, adding a cycle of latency to 2952// each of the loads which would otherwise be able to use LFIWZX. 2953def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)), 2954 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32A, MrgFP.LD32B), 2955 (XXMRGHW MrgFP.LD32C, MrgFP.LD32D), 3))>; 2956def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)), 2957 (VMRGEW MrgFP.AC, MrgFP.BD)>; 2958def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1, 2959 DblToFlt.B0, DblToFlt.B1)), 2960 (v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>; 2961 2962// Convert 4 doubles to a vector of ints. 2963def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B, 2964 DblToInt.C, DblToInt.D)), 2965 (v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>; 2966def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B, 2967 DblToUInt.C, DblToUInt.D)), 2968 (v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>; 2969def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S, 2970 ExtDbl.B0S, ExtDbl.B1S)), 2971 (v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>; 2972def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U, 2973 ExtDbl.B0U, ExtDbl.B1U)), 2974 (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>; 2975def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2976 (f64 (fpextend (extractelt v4f32:$A, 1))))), 2977 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>; 2978def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 2979 (f64 (fpextend (extractelt v4f32:$A, 0))))), 2980 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)), 2981 (XVCVSPDP (XXMRGHW $A, $A)), 2))>; 2982def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2983 (f64 (fpextend (extractelt v4f32:$A, 2))))), 2984 (v2f64 (XVCVSPDP $A))>; 2985def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 2986 (f64 (fpextend (extractelt v4f32:$A, 3))))), 2987 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 3)))>; 2988def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))), 2989 (f64 (fpextend (extractelt v4f32:$A, 3))))), 2990 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>; 2991def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 2992 (f64 (fpextend (extractelt v4f32:$A, 2))))), 2993 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)), 2994 (XVCVSPDP (XXMRGLW $A, $A)), 2))>; 2995def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2996 (f64 (fpextend (extractelt v4f32:$B, 0))))), 2997 (v2f64 (XVCVSPDP (XXPERMDI $A, $B, 0)))>; 2998def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 2999 (f64 (fpextend (extractelt v4f32:$B, 3))))), 3000 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $A, $B, 3), 3001 (XXPERMDI $A, $B, 3), 1)))>; 3002def : Pat<(v2i64 (fp_to_sint 3003 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3004 (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3005 (v2i64 (XVCVSPSXDS $A))>; 3006def : Pat<(v2i64 (fp_to_uint 3007 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3008 (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3009 (v2i64 (XVCVSPUXDS $A))>; 3010def : Pat<(v2i64 (fp_to_sint 3011 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3012 (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3013 (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>; 3014def : Pat<(v2i64 (fp_to_uint 3015 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3016 (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3017 (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>; 3018def : Pat<WToDPExtractConv.BV02S, 3019 (v2f64 (XVCVSXWDP $A))>; 3020def : Pat<WToDPExtractConv.BV13S, 3021 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>; 3022def : Pat<WToDPExtractConv.BV02U, 3023 (v2f64 (XVCVUXWDP $A))>; 3024def : Pat<WToDPExtractConv.BV13U, 3025 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>; 3026def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), 3027 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; 3028def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), 3029 (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; 3030} // HasVSX, IsBigEndian 3031 3032// Any little endian VSX subtarget. 3033let Predicates = [HasVSX, IsLittleEndian] in { 3034defm : ScalToVecWPermute<v2f64, (f64 f64:$A), 3035 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), 3036 (SUBREG_TO_REG (i64 1), $A, sub_64), 0), 3037 (SUBREG_TO_REG (i64 1), $A, sub_64)>; 3038 3039def : Pat<(f64 (extractelt v2f64:$S, 0)), 3040 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 3041def : Pat<(f64 (extractelt v2f64:$S, 1)), 3042 (f64 (EXTRACT_SUBREG $S, sub_64))>; 3043 3044def : Pat<(v2f64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3045def : Pat<(PPCst_vec_be v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3046def : Pat<(v4f32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3047def : Pat<(PPCst_vec_be v4f32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>; 3048def : Pat<(v2i64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3049def : Pat<(PPCst_vec_be v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3050def : Pat<(v4i32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3051def : Pat<(PPCst_vec_be v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>; 3052def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 3053 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 3054def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 3055 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; 3056def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 3057 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 3058def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 3059 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; 3060 3061def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 3062 (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>; 3063 3064// Little endian, available on all targets with VSX 3065def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), 3066 (v2f64 (XXPERMDI 3067 (SUBREG_TO_REG (i64 1), $B, sub_64), 3068 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>; 3069// Using VMRGEW to assemble the final vector would be a lower latency 3070// solution. However, we choose to go with the slightly higher latency 3071// XXPERMDI for 2 reasons: 3072// 1. This is likely to occur in unrolled loops where regpressure is high, 3073// so we want to use the latter as it has access to all 64 VSX registers. 3074// 2. Using Altivec instructions in this sequence would likely cause the 3075// allocation of Altivec registers even for the loads which in turn would 3076// force the use of LXSIWZX for the loads, adding a cycle of latency to 3077// each of the loads which would otherwise be able to use LFIWZX. 3078def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)), 3079 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32D, MrgFP.LD32C), 3080 (XXMRGHW MrgFP.LD32B, MrgFP.LD32A), 3))>; 3081def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)), 3082 (VMRGEW MrgFP.AC, MrgFP.BD)>; 3083def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1, 3084 DblToFlt.B0, DblToFlt.B1)), 3085 (v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>; 3086 3087// Convert 4 doubles to a vector of ints. 3088def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B, 3089 DblToInt.C, DblToInt.D)), 3090 (v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>; 3091def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B, 3092 DblToUInt.C, DblToUInt.D)), 3093 (v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>; 3094def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S, 3095 ExtDbl.B0S, ExtDbl.B1S)), 3096 (v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>; 3097def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U, 3098 ExtDbl.B0U, ExtDbl.B1U)), 3099 (v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>; 3100def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3101 (f64 (fpextend (extractelt v4f32:$A, 1))))), 3102 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>; 3103def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3104 (f64 (fpextend (extractelt v4f32:$A, 0))))), 3105 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)), 3106 (XVCVSPDP (XXMRGLW $A, $A)), 2))>; 3107def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3108 (f64 (fpextend (extractelt v4f32:$A, 2))))), 3109 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>; 3110def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3111 (f64 (fpextend (extractelt v4f32:$A, 3))))), 3112 (v2f64 (XVCVSPDP $A))>; 3113def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))), 3114 (f64 (fpextend (extractelt v4f32:$A, 3))))), 3115 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>; 3116def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 3117 (f64 (fpextend (extractelt v4f32:$A, 2))))), 3118 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)), 3119 (XVCVSPDP (XXMRGHW $A, $A)), 2))>; 3120def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3121 (f64 (fpextend (extractelt v4f32:$B, 0))))), 3122 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $B, $A, 3), 3123 (XXPERMDI $B, $A, 3), 1)))>; 3124def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 3125 (f64 (fpextend (extractelt v4f32:$B, 3))))), 3126 (v2f64 (XVCVSPDP (XXPERMDI $B, $A, 0)))>; 3127def : Pat<(v2i64 (fp_to_sint 3128 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3129 (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3130 (v2i64 (XVCVSPSXDS $A))>; 3131def : Pat<(v2i64 (fp_to_uint 3132 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 3133 (f64 (fpextend (extractelt v4f32:$A, 3)))))), 3134 (v2i64 (XVCVSPUXDS $A))>; 3135def : Pat<(v2i64 (fp_to_sint 3136 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3137 (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3138 (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>; 3139def : Pat<(v2i64 (fp_to_uint 3140 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 3141 (f64 (fpextend (extractelt v4f32:$A, 2)))))), 3142 (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>; 3143def : Pat<WToDPExtractConv.BV02S, 3144 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>; 3145def : Pat<WToDPExtractConv.BV13S, 3146 (v2f64 (XVCVSXWDP $A))>; 3147def : Pat<WToDPExtractConv.BV02U, 3148 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>; 3149def : Pat<WToDPExtractConv.BV13U, 3150 (v2f64 (XVCVUXWDP $A))>; 3151def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), 3152 (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; 3153def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), 3154 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; 3155} // HasVSX, IsLittleEndian 3156 3157// Any pre-Power9 VSX subtarget. 3158let Predicates = [HasVSX, NoP9Vector] in { 3159def : Pat<(PPCstore_scal_int_from_vsr 3160 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 8), 3161 (STXSDX (XSCVDPSXDS f64:$src), ForceXForm:$dst)>; 3162def : Pat<(PPCstore_scal_int_from_vsr 3163 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 8), 3164 (STXSDX (XSCVDPUXDS f64:$src), ForceXForm:$dst)>; 3165 3166// Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads). 3167defm : ScalToVecWPermute< 3168 v4i32, DblToIntLoad.A, 3169 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), 3170 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; 3171defm : ScalToVecWPermute< 3172 v4i32, DblToUIntLoad.A, 3173 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), 3174 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; 3175defm : ScalToVecWPermute< 3176 v2i64, FltToLongLoad.A, 3177 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), 3178 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), 3179 VSFRC)), sub_64)>; 3180defm : ScalToVecWPermute< 3181 v2i64, FltToULongLoad.A, 3182 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), 3183 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), 3184 VSFRC)), sub_64)>; 3185} // HasVSX, NoP9Vector 3186 3187// Any little endian pre-Power9 VSX subtarget. 3188let Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in { 3189// Load-and-splat using only X-Form VSX loads. 3190defm : ScalToVecWPermute< 3191 v2i64, (i64 (load ForceXForm:$src)), 3192 (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), 3193 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; 3194defm : ScalToVecWPermute< 3195 v2f64, (f64 (load ForceXForm:$src)), 3196 (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), 3197 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; 3198 3199// Splat loads. 3200def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)), 3201 (v8i16 (VSPLTH 7, (LVX ForceXForm:$A)))>; 3202def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)), 3203 (v16i8 (VSPLTB 15, (LVX ForceXForm:$A)))>; 3204} // HasVSX, NoP9Vector, IsLittleEndian 3205 3206let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in { 3207 def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)), 3208 (LXVD2X ForceXForm:$src)>; 3209 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst), 3210 (STXVD2X $rS, ForceXForm:$dst)>; 3211 3212 // Splat loads. 3213 def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)), 3214 (v8i16 (VSPLTH 0, (LVX ForceXForm:$A)))>; 3215 def : Pat<(v16i8 (PPCldsplatAlign16 ForceXForm:$A)), 3216 (v16i8 (VSPLTB 0, (LVX ForceXForm:$A)))>; 3217} // HasVSX, NoP9Vector, IsBigEndian 3218 3219// Any VSX subtarget that only has loads and stores that load in big endian 3220// order regardless of endianness. This is really pre-Power9 subtargets. 3221let Predicates = [HasVSX, HasOnlySwappingMemOps] in { 3222 def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3223 3224 // Stores. 3225 def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3226} // HasVSX, HasOnlySwappingMemOps 3227 3228// Big endian VSX subtarget that only has loads and stores that always 3229// load in big endian order. Really big endian pre-Power9 subtargets. 3230let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in { 3231 def : Pat<(v2f64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3232 def : Pat<(v2i64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; 3233 def : Pat<(v4i32 (load ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3234 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; 3235 def : Pat<(store v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3236 def : Pat<(store v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; 3237 def : Pat<(store v4i32:$XT, ForceXForm:$dst), (STXVW4X $XT, ForceXForm:$dst)>; 3238 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst), 3239 (STXVW4X $rS, ForceXForm:$dst)>; 3240 def : Pat<(v2i64 (scalar_to_vector (i64 (load ForceXForm:$src)))), 3241 (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; 3242} // HasVSX, HasOnlySwappingMemOps, IsBigEndian 3243 3244// Any Power8 VSX subtarget. 3245let Predicates = [HasVSX, HasP8Vector] in { 3246def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B), 3247 (XXLEQV $A, $B)>; 3248def : Pat<(f64 (extloadf32 XForm:$src)), 3249 (COPY_TO_REGCLASS (XFLOADf32 XForm:$src), VSFRC)>; 3250def : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))), 3251 (f32 (XFLOADf32 ForceXForm:$src))>; 3252def : Pat<(f64 (any_fpextend f32:$src)), 3253 (COPY_TO_REGCLASS $src, VSFRC)>; 3254 3255def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 3256 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3257def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 3258 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3259def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 3260 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 3261def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 3262 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 3263def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 3264 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>; 3265def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 3266 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 3267def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 3268 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 3269def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 3270 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3271def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 3272 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3273def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 3274 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 3275 3276// Additional fnmsub pattern for PPC specific ISD opcode 3277def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3278 (XSNMSUBASP $C, $A, $B)>; 3279def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3280 (XSMSUBASP $C, $A, $B)>; 3281def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3282 (XSNMADDASP $C, $A, $B)>; 3283 3284// f32 neg 3285// Although XSNEGDP is available in P7, we want to select it starting from P8, 3286// so that FNMSUBS can be selected for fneg-fmsub pattern on P7. (VSX version, 3287// XSNMSUBASP, is available since P8) 3288def : Pat<(f32 (fneg f32:$S)), 3289 (f32 (COPY_TO_REGCLASS (XSNEGDP 3290 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 3291 3292// Instructions for converting float to i32 feeding a store. 3293def : Pat<(PPCstore_scal_int_from_vsr 3294 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 4), 3295 (STIWX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>; 3296def : Pat<(PPCstore_scal_int_from_vsr 3297 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 4), 3298 (STIWX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>; 3299 3300def : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)), 3301 (v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC), 3302 (COPY_TO_REGCLASS $src2, VRRC)))>; 3303def : Pat<(v2i64 (umax v2i64:$src1, v2i64:$src2)), 3304 (v2i64 (VMAXUD (COPY_TO_REGCLASS $src1, VRRC), 3305 (COPY_TO_REGCLASS $src2, VRRC)))>; 3306def : Pat<(v2i64 (smin v2i64:$src1, v2i64:$src2)), 3307 (v2i64 (VMINSD (COPY_TO_REGCLASS $src1, VRRC), 3308 (COPY_TO_REGCLASS $src2, VRRC)))>; 3309def : Pat<(v2i64 (umin v2i64:$src1, v2i64:$src2)), 3310 (v2i64 (VMINUD (COPY_TO_REGCLASS $src1, VRRC), 3311 (COPY_TO_REGCLASS $src2, VRRC)))>; 3312 3313def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))), 3314 (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3315def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))), 3316 (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3317def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))), 3318 (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3319def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))), 3320 (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3321 3322// XL Compat builtins. 3323def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (XSMSUBMSP $A, $B, $C)>; 3324def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (XSNMADDMSP $A, $B, $C)>; 3325def : Pat<(int_ppc_fres f32:$A), (XSRESP $A)>; 3326def : Pat<(i32 (int_ppc_extract_exp f64:$A)), 3327 (EXTRACT_SUBREG (XSXEXPDP (COPY_TO_REGCLASS $A, VSFRC)), sub_32)>; 3328def : Pat<(int_ppc_extract_sig f64:$A), 3329 (XSXSIGDP (COPY_TO_REGCLASS $A, VSFRC))>; 3330def : Pat<(f64 (int_ppc_insert_exp f64:$A, i64:$B)), 3331 (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>; 3332 3333def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 3334 (STXSIWX f64:$XT, ForceXForm:$dst)>; 3335def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>; 3336} // HasVSX, HasP8Vector 3337 3338// Any big endian Power8 VSX subtarget. 3339let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in { 3340def : Pat<DWToSPExtractConv.El0SS1, 3341 (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; 3342def : Pat<DWToSPExtractConv.El1SS1, 3343 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3344def : Pat<DWToSPExtractConv.El0US1, 3345 (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; 3346def : Pat<DWToSPExtractConv.El1US1, 3347 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3348 3349// v4f32 scalar <-> vector conversions (BE) 3350defm : ScalToVecWPermute<v4f32, (f32 f32:$A), (XSCVDPSPN $A), (XSCVDPSPN $A)>; 3351def : Pat<(f32 (vector_extract v4f32:$S, 0)), 3352 (f32 (XSCVSPDPN $S))>; 3353def : Pat<(f32 (vector_extract v4f32:$S, 1)), 3354 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 3355def : Pat<(f32 (vector_extract v4f32:$S, 2)), 3356 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 3357def : Pat<(f32 (vector_extract v4f32:$S, 3)), 3358 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 3359 3360def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3361 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>; 3362def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3363 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>; 3364def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3365 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>; 3366def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3367 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>; 3368def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3369 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>; 3370def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3371 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>; 3372def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3373 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>; 3374def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3375 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>; 3376 3377def : Pat<(f32 (vector_extract v4f32:$S, i32:$Idx)), 3378 (f32 VectorExtractions.BE_32B_VARIABLE_FLOAT)>; 3379 3380def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)), 3381 (f64 VectorExtractions.BE_32B_VARIABLE_DOUBLE)>; 3382 3383defm : ScalToVecWPermute< 3384 v4i32, (i32 (load ForceXForm:$src)), 3385 (XXSLDWIs (LIWZX ForceXForm:$src), 1), 3386 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 3387defm : ScalToVecWPermute< 3388 v4f32, (f32 (load ForceXForm:$src)), 3389 (XXSLDWIs (LIWZX ForceXForm:$src), 1), 3390 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 3391} // HasVSX, HasP8Vector, IsBigEndian 3392 3393// Big endian Power8 64Bit VSX subtarget. 3394let Predicates = [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] in { 3395def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 3396 (f32 VectorExtractions.BE_VARIABLE_FLOAT)>; 3397 3398// LIWAX - This instruction is used for sign extending i32 -> i64. 3399// LIWZX - This instruction will be emitted for i32, f32, and when 3400// zero-extending i32 to i64 (zext i32 -> i64). 3401def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))), 3402 (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>; 3403def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))), 3404 (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>; 3405 3406def : Pat<DWToSPExtractConv.BVU, 3407 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3), 3408 (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>; 3409def : Pat<DWToSPExtractConv.BVS, 3410 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3), 3411 (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>; 3412def : Pat<(store (i32 (extractelt v4i32:$A, 1)), ForceXForm:$src), 3413 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3414def : Pat<(store (f32 (extractelt v4f32:$A, 1)), ForceXForm:$src), 3415 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3416 3417// Elements in a register on a BE system are in order <0, 1, 2, 3>. 3418// The store instructions store the second word from the left. 3419// So to align element zero, we need to modulo-left-shift by 3 words. 3420// Similar logic applies for elements 2 and 3. 3421foreach Idx = [ [0,3], [2,1], [3,2] ] in { 3422 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src), 3423 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3424 sub_64), ForceXForm:$src)>; 3425 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src), 3426 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3427 sub_64), ForceXForm:$src)>; 3428} 3429} // HasVSX, HasP8Vector, IsBigEndian, IsPPC64 3430 3431// Little endian Power8 VSX subtarget. 3432let Predicates = [HasVSX, HasP8Vector, IsLittleEndian] in { 3433def : Pat<DWToSPExtractConv.El0SS1, 3434 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3435def : Pat<DWToSPExtractConv.El1SS1, 3436 (f32 (XSCVSXDSP (COPY_TO_REGCLASS 3437 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; 3438def : Pat<DWToSPExtractConv.El0US1, 3439 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3440def : Pat<DWToSPExtractConv.El1US1, 3441 (f32 (XSCVUXDSP (COPY_TO_REGCLASS 3442 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; 3443 3444// v4f32 scalar <-> vector conversions (LE) 3445 defm : ScalToVecWPermute<v4f32, (f32 f32:$A), 3446 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1), 3447 (XSCVDPSPN $A)>; 3448def : Pat<(f32 (vector_extract v4f32:$S, 0)), 3449 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 3450def : Pat<(f32 (vector_extract v4f32:$S, 1)), 3451 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 3452def : Pat<(f32 (vector_extract v4f32:$S, 2)), 3453 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 3454def : Pat<(f32 (vector_extract v4f32:$S, 3)), 3455 (f32 (XSCVSPDPN $S))>; 3456def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 3457 (f32 VectorExtractions.LE_VARIABLE_FLOAT)>; 3458 3459def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3460 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>; 3461def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3462 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>; 3463def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3464 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>; 3465def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3466 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>; 3467def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3468 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>; 3469def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3470 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>; 3471def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3472 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>; 3473def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3474 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>; 3475 3476// LIWAX - This instruction is used for sign extending i32 -> i64. 3477// LIWZX - This instruction will be emitted for i32, f32, and when 3478// zero-extending i32 to i64 (zext i32 -> i64). 3479defm : ScalToVecWPermute< 3480 v2i64, (i64 (sextloadi32 ForceXForm:$src)), 3481 (XXPERMDIs (LIWAX ForceXForm:$src), 2), 3482 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64)>; 3483 3484defm : ScalToVecWPermute< 3485 v2i64, (i64 (zextloadi32 ForceXForm:$src)), 3486 (XXPERMDIs (LIWZX ForceXForm:$src), 2), 3487 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 3488 3489defm : ScalToVecWPermute< 3490 v4i32, (i32 (load ForceXForm:$src)), 3491 (XXPERMDIs (LIWZX ForceXForm:$src), 2), 3492 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 3493 3494defm : ScalToVecWPermute< 3495 v4f32, (f32 (load ForceXForm:$src)), 3496 (XXPERMDIs (LIWZX ForceXForm:$src), 2), 3497 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; 3498 3499def : Pat<DWToSPExtractConv.BVU, 3500 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3), 3501 (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>; 3502def : Pat<DWToSPExtractConv.BVS, 3503 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3), 3504 (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>; 3505def : Pat<(store (i32 (extractelt v4i32:$A, 2)), ForceXForm:$src), 3506 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3507def : Pat<(store (f32 (extractelt v4f32:$A, 2)), ForceXForm:$src), 3508 (STIWX (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3509 3510// Elements in a register on a LE system are in order <3, 2, 1, 0>. 3511// The store instructions store the second word from the left. 3512// So to align element 3, we need to modulo-left-shift by 3 words. 3513// Similar logic applies for elements 0 and 1. 3514foreach Idx = [ [0,2], [1,1], [3,3] ] in { 3515 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), ForceXForm:$src), 3516 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3517 sub_64), ForceXForm:$src)>; 3518 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), ForceXForm:$src), 3519 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3520 sub_64), ForceXForm:$src)>; 3521} 3522} // HasVSX, HasP8Vector, IsLittleEndian 3523 3524// Big endian pre-Power9 VSX subtarget. 3525let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] in { 3526def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 3527 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3528def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src), 3529 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3530def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 3531 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3532 ForceXForm:$src)>; 3533def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src), 3534 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3535 ForceXForm:$src)>; 3536} // HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64 3537 3538// Little endian pre-Power9 VSX subtarget. 3539let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] in { 3540def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 3541 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3542 ForceXForm:$src)>; 3543def : Pat<(store (f64 (extractelt v2f64:$A, 0)), ForceXForm:$src), 3544 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3545 ForceXForm:$src)>; 3546def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 3547 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3548def : Pat<(store (f64 (extractelt v2f64:$A, 1)), ForceXForm:$src), 3549 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 3550} // HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian 3551 3552// Any VSX target with direct moves. 3553let Predicates = [HasVSX, HasDirectMove] in { 3554// bitconvert f32 -> i32 3555// (convert to 32-bit fp single, shift right 1 word, move to GPR) 3556def : Pat<(i32 (bitconvert f32:$A)), Bitcast.FltToInt>; 3557 3558// bitconvert i32 -> f32 3559// (move to FPR, shift left 1 word, convert to 64-bit fp single) 3560def : Pat<(f32 (bitconvert i32:$A)), 3561 (f32 (XSCVSPDPN 3562 (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>; 3563 3564// bitconvert f64 -> i64 3565// (move to GPR, nothing else needed) 3566def : Pat<(i64 (bitconvert f64:$A)), Bitcast.DblToLong>; 3567 3568// bitconvert i64 -> f64 3569// (move to FPR, nothing else needed) 3570def : Pat<(f64 (bitconvert i64:$S)), 3571 (f64 (MTVSRD $S))>; 3572 3573// Rounding to integer. 3574def : Pat<(i64 (lrint f64:$S)), 3575 (i64 (MFVSRD (FCTID $S)))>; 3576def : Pat<(i64 (lrint f32:$S)), 3577 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>; 3578def : Pat<(i64 (llrint f64:$S)), 3579 (i64 (MFVSRD (FCTID $S)))>; 3580def : Pat<(i64 (llrint f32:$S)), 3581 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>; 3582def : Pat<(i64 (lround f64:$S)), 3583 (i64 (MFVSRD (FCTID (XSRDPI $S))))>; 3584def : Pat<(i64 (lround f32:$S)), 3585 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>; 3586def : Pat<(i64 (llround f64:$S)), 3587 (i64 (MFVSRD (FCTID (XSRDPI $S))))>; 3588def : Pat<(i64 (llround f32:$S)), 3589 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>; 3590 3591// Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead 3592// of f64 3593def : Pat<(v8i16 (PPCmtvsrz i32:$A)), 3594 (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; 3595def : Pat<(v16i8 (PPCmtvsrz i32:$A)), 3596 (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; 3597 3598// Endianness-neutral constant splat on P8 and newer targets. The reason 3599// for this pattern is that on targets with direct moves, we don't expand 3600// BUILD_VECTOR nodes for v4i32. 3601def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A, 3602 immSExt5NonZero:$A, immSExt5NonZero:$A)), 3603 (v4i32 (VSPLTISW imm:$A))>; 3604 3605// Splat loads. 3606def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)), 3607 (v8i16 (VSPLTHs 3, (MTVSRWZ (LHZX ForceXForm:$A))))>; 3608def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)), 3609 (v16i8 (VSPLTBs 7, (MTVSRWZ (LBZX ForceXForm:$A))))>; 3610} // HasVSX, HasDirectMove 3611 3612// Big endian VSX subtarget with direct moves. 3613let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in { 3614// v16i8 scalar <-> vector conversions (BE) 3615defm : ScalToVecWPermute< 3616 v16i8, (i32 i32:$A), 3617 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64), 3618 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3619defm : ScalToVecWPermute< 3620 v8i16, (i32 i32:$A), 3621 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64), 3622 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3623defm : ScalToVecWPermute< 3624 v4i32, (i32 i32:$A), 3625 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64), 3626 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3627def : Pat<(v2i64 (scalar_to_vector i64:$A)), 3628 (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; 3629 3630// v2i64 scalar <-> vector conversions (BE) 3631def : Pat<(i64 (vector_extract v2i64:$S, 0)), 3632 (i64 VectorExtractions.LE_DWORD_1)>; 3633def : Pat<(i64 (vector_extract v2i64:$S, 1)), 3634 (i64 VectorExtractions.LE_DWORD_0)>; 3635def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 3636 (i64 VectorExtractions.BE_VARIABLE_DWORD)>; 3637} // HasVSX, HasDirectMove, IsBigEndian 3638 3639// Little endian VSX subtarget with direct moves. 3640let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in { 3641 // v16i8 scalar <-> vector conversions (LE) 3642 defm : ScalToVecWPermute<v16i8, (i32 i32:$A), 3643 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), 3644 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; 3645 defm : ScalToVecWPermute<v8i16, (i32 i32:$A), 3646 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), 3647 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; 3648 defm : ScalToVecWPermute<v4i32, (i32 i32:$A), MovesToVSR.LE_WORD_0, 3649 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3650 defm : ScalToVecWPermute<v2i64, (i64 i64:$A), MovesToVSR.LE_DWORD_0, 3651 MovesToVSR.LE_DWORD_1>; 3652 3653 // v2i64 scalar <-> vector conversions (LE) 3654 def : Pat<(i64 (vector_extract v2i64:$S, 0)), 3655 (i64 VectorExtractions.LE_DWORD_0)>; 3656 def : Pat<(i64 (vector_extract v2i64:$S, 1)), 3657 (i64 VectorExtractions.LE_DWORD_1)>; 3658 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 3659 (i64 VectorExtractions.LE_VARIABLE_DWORD)>; 3660} // HasVSX, HasDirectMove, IsLittleEndian 3661 3662// Big endian pre-P9 VSX subtarget with direct moves. 3663let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] in { 3664def : Pat<(i32 (vector_extract v16i8:$S, 0)), 3665 (i32 VectorExtractions.LE_BYTE_15)>; 3666def : Pat<(i32 (vector_extract v16i8:$S, 1)), 3667 (i32 VectorExtractions.LE_BYTE_14)>; 3668def : Pat<(i32 (vector_extract v16i8:$S, 2)), 3669 (i32 VectorExtractions.LE_BYTE_13)>; 3670def : Pat<(i32 (vector_extract v16i8:$S, 3)), 3671 (i32 VectorExtractions.LE_BYTE_12)>; 3672def : Pat<(i32 (vector_extract v16i8:$S, 4)), 3673 (i32 VectorExtractions.LE_BYTE_11)>; 3674def : Pat<(i32 (vector_extract v16i8:$S, 5)), 3675 (i32 VectorExtractions.LE_BYTE_10)>; 3676def : Pat<(i32 (vector_extract v16i8:$S, 6)), 3677 (i32 VectorExtractions.LE_BYTE_9)>; 3678def : Pat<(i32 (vector_extract v16i8:$S, 7)), 3679 (i32 VectorExtractions.LE_BYTE_8)>; 3680def : Pat<(i32 (vector_extract v16i8:$S, 8)), 3681 (i32 VectorExtractions.LE_BYTE_7)>; 3682def : Pat<(i32 (vector_extract v16i8:$S, 9)), 3683 (i32 VectorExtractions.LE_BYTE_6)>; 3684def : Pat<(i32 (vector_extract v16i8:$S, 10)), 3685 (i32 VectorExtractions.LE_BYTE_5)>; 3686def : Pat<(i32 (vector_extract v16i8:$S, 11)), 3687 (i32 VectorExtractions.LE_BYTE_4)>; 3688def : Pat<(i32 (vector_extract v16i8:$S, 12)), 3689 (i32 VectorExtractions.LE_BYTE_3)>; 3690def : Pat<(i32 (vector_extract v16i8:$S, 13)), 3691 (i32 VectorExtractions.LE_BYTE_2)>; 3692def : Pat<(i32 (vector_extract v16i8:$S, 14)), 3693 (i32 VectorExtractions.LE_BYTE_1)>; 3694def : Pat<(i32 (vector_extract v16i8:$S, 15)), 3695 (i32 VectorExtractions.LE_BYTE_0)>; 3696def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 3697 (i32 VectorExtractions.BE_VARIABLE_BYTE)>; 3698 3699// v8i16 scalar <-> vector conversions (BE) 3700def : Pat<(i32 (vector_extract v8i16:$S, 0)), 3701 (i32 VectorExtractions.LE_HALF_7)>; 3702def : Pat<(i32 (vector_extract v8i16:$S, 1)), 3703 (i32 VectorExtractions.LE_HALF_6)>; 3704def : Pat<(i32 (vector_extract v8i16:$S, 2)), 3705 (i32 VectorExtractions.LE_HALF_5)>; 3706def : Pat<(i32 (vector_extract v8i16:$S, 3)), 3707 (i32 VectorExtractions.LE_HALF_4)>; 3708def : Pat<(i32 (vector_extract v8i16:$S, 4)), 3709 (i32 VectorExtractions.LE_HALF_3)>; 3710def : Pat<(i32 (vector_extract v8i16:$S, 5)), 3711 (i32 VectorExtractions.LE_HALF_2)>; 3712def : Pat<(i32 (vector_extract v8i16:$S, 6)), 3713 (i32 VectorExtractions.LE_HALF_1)>; 3714def : Pat<(i32 (vector_extract v8i16:$S, 7)), 3715 (i32 VectorExtractions.LE_HALF_0)>; 3716def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 3717 (i32 VectorExtractions.BE_VARIABLE_HALF)>; 3718 3719// v4i32 scalar <-> vector conversions (BE) 3720def : Pat<(i32 (vector_extract v4i32:$S, 0)), 3721 (i32 VectorExtractions.LE_WORD_3)>; 3722def : Pat<(i32 (vector_extract v4i32:$S, 1)), 3723 (i32 VectorExtractions.LE_WORD_2)>; 3724def : Pat<(i32 (vector_extract v4i32:$S, 2)), 3725 (i32 VectorExtractions.LE_WORD_1)>; 3726def : Pat<(i32 (vector_extract v4i32:$S, 3)), 3727 (i32 VectorExtractions.LE_WORD_0)>; 3728def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 3729 (i32 VectorExtractions.BE_VARIABLE_WORD)>; 3730} // HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian 3731 3732// Little endian pre-P9 VSX subtarget with direct moves. 3733let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] in { 3734def : Pat<(i32 (vector_extract v16i8:$S, 0)), 3735 (i32 VectorExtractions.LE_BYTE_0)>; 3736def : Pat<(i32 (vector_extract v16i8:$S, 1)), 3737 (i32 VectorExtractions.LE_BYTE_1)>; 3738def : Pat<(i32 (vector_extract v16i8:$S, 2)), 3739 (i32 VectorExtractions.LE_BYTE_2)>; 3740def : Pat<(i32 (vector_extract v16i8:$S, 3)), 3741 (i32 VectorExtractions.LE_BYTE_3)>; 3742def : Pat<(i32 (vector_extract v16i8:$S, 4)), 3743 (i32 VectorExtractions.LE_BYTE_4)>; 3744def : Pat<(i32 (vector_extract v16i8:$S, 5)), 3745 (i32 VectorExtractions.LE_BYTE_5)>; 3746def : Pat<(i32 (vector_extract v16i8:$S, 6)), 3747 (i32 VectorExtractions.LE_BYTE_6)>; 3748def : Pat<(i32 (vector_extract v16i8:$S, 7)), 3749 (i32 VectorExtractions.LE_BYTE_7)>; 3750def : Pat<(i32 (vector_extract v16i8:$S, 8)), 3751 (i32 VectorExtractions.LE_BYTE_8)>; 3752def : Pat<(i32 (vector_extract v16i8:$S, 9)), 3753 (i32 VectorExtractions.LE_BYTE_9)>; 3754def : Pat<(i32 (vector_extract v16i8:$S, 10)), 3755 (i32 VectorExtractions.LE_BYTE_10)>; 3756def : Pat<(i32 (vector_extract v16i8:$S, 11)), 3757 (i32 VectorExtractions.LE_BYTE_11)>; 3758def : Pat<(i32 (vector_extract v16i8:$S, 12)), 3759 (i32 VectorExtractions.LE_BYTE_12)>; 3760def : Pat<(i32 (vector_extract v16i8:$S, 13)), 3761 (i32 VectorExtractions.LE_BYTE_13)>; 3762def : Pat<(i32 (vector_extract v16i8:$S, 14)), 3763 (i32 VectorExtractions.LE_BYTE_14)>; 3764def : Pat<(i32 (vector_extract v16i8:$S, 15)), 3765 (i32 VectorExtractions.LE_BYTE_15)>; 3766def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 3767 (i32 VectorExtractions.LE_VARIABLE_BYTE)>; 3768 3769// v8i16 scalar <-> vector conversions (LE) 3770def : Pat<(i32 (vector_extract v8i16:$S, 0)), 3771 (i32 VectorExtractions.LE_HALF_0)>; 3772def : Pat<(i32 (vector_extract v8i16:$S, 1)), 3773 (i32 VectorExtractions.LE_HALF_1)>; 3774def : Pat<(i32 (vector_extract v8i16:$S, 2)), 3775 (i32 VectorExtractions.LE_HALF_2)>; 3776def : Pat<(i32 (vector_extract v8i16:$S, 3)), 3777 (i32 VectorExtractions.LE_HALF_3)>; 3778def : Pat<(i32 (vector_extract v8i16:$S, 4)), 3779 (i32 VectorExtractions.LE_HALF_4)>; 3780def : Pat<(i32 (vector_extract v8i16:$S, 5)), 3781 (i32 VectorExtractions.LE_HALF_5)>; 3782def : Pat<(i32 (vector_extract v8i16:$S, 6)), 3783 (i32 VectorExtractions.LE_HALF_6)>; 3784def : Pat<(i32 (vector_extract v8i16:$S, 7)), 3785 (i32 VectorExtractions.LE_HALF_7)>; 3786def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 3787 (i32 VectorExtractions.LE_VARIABLE_HALF)>; 3788 3789// v4i32 scalar <-> vector conversions (LE) 3790def : Pat<(i32 (vector_extract v4i32:$S, 0)), 3791 (i32 VectorExtractions.LE_WORD_0)>; 3792def : Pat<(i32 (vector_extract v4i32:$S, 1)), 3793 (i32 VectorExtractions.LE_WORD_1)>; 3794def : Pat<(i32 (vector_extract v4i32:$S, 2)), 3795 (i32 VectorExtractions.LE_WORD_2)>; 3796def : Pat<(i32 (vector_extract v4i32:$S, 3)), 3797 (i32 VectorExtractions.LE_WORD_3)>; 3798def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 3799 (i32 VectorExtractions.LE_VARIABLE_WORD)>; 3800} // HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian 3801 3802// Big endian pre-Power9 64Bit VSX subtarget that has direct moves. 3803let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] in { 3804// Big endian integer vectors using direct moves. 3805def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), 3806 (v2i64 (XXPERMDI 3807 (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 3808 (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 0))>; 3809def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 3810 (XXPERMDI 3811 (SUBREG_TO_REG (i64 1), 3812 (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), sub_64), 3813 (SUBREG_TO_REG (i64 1), 3814 (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), sub_64), 0)>; 3815def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3816 (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; 3817} // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64 3818 3819// Little endian pre-Power9 VSX subtarget that has direct moves. 3820let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in { 3821// Little endian integer vectors using direct moves. 3822def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), 3823 (v2i64 (XXPERMDI 3824 (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 3825 (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 0))>; 3826def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 3827 (XXPERMDI 3828 (SUBREG_TO_REG (i64 1), 3829 (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), sub_64), 3830 (SUBREG_TO_REG (i64 1), 3831 (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), sub_64), 0)>; 3832def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3833 (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; 3834} 3835 3836// Any Power9 VSX subtarget. 3837let Predicates = [HasVSX, HasP9Vector] in { 3838// Additional fnmsub pattern for PPC specific ISD opcode 3839def : Pat<(PPCfnmsub f128:$A, f128:$B, f128:$C), 3840 (XSNMSUBQP $C, $A, $B)>; 3841def : Pat<(fneg (PPCfnmsub f128:$A, f128:$B, f128:$C)), 3842 (XSMSUBQP $C, $A, $B)>; 3843def : Pat<(PPCfnmsub f128:$A, f128:$B, (fneg f128:$C)), 3844 (XSNMADDQP $C, $A, $B)>; 3845 3846def : Pat<(f128 (any_sint_to_fp i64:$src)), 3847 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 3848def : Pat<(f128 (any_sint_to_fp (i64 (PPCmfvsr f64:$src)))), 3849 (f128 (XSCVSDQP $src))>; 3850def : Pat<(f128 (any_sint_to_fp (i32 (PPCmfvsr f64:$src)))), 3851 (f128 (XSCVSDQP (VEXTSW2Ds $src)))>; 3852def : Pat<(f128 (any_uint_to_fp i64:$src)), 3853 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 3854def : Pat<(f128 (any_uint_to_fp (i64 (PPCmfvsr f64:$src)))), 3855 (f128 (XSCVUDQP $src))>; 3856 3857// Convert (Un)Signed Word -> QP. 3858def : Pat<(f128 (any_sint_to_fp i32:$src)), 3859 (f128 (XSCVSDQP (MTVSRWA $src)))>; 3860def : Pat<(f128 (any_sint_to_fp (i32 (load ForceXForm:$src)))), 3861 (f128 (XSCVSDQP (LIWAX ForceXForm:$src)))>; 3862def : Pat<(f128 (any_uint_to_fp i32:$src)), 3863 (f128 (XSCVUDQP (MTVSRWZ $src)))>; 3864def : Pat<(f128 (any_uint_to_fp (i32 (load ForceXForm:$src)))), 3865 (f128 (XSCVUDQP (LIWZX ForceXForm:$src)))>; 3866 3867// Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a 3868// separate pattern so that it can convert the input register class from 3869// VRRC(v8i16) to VSRC. 3870def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)), 3871 (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>; 3872 3873// Use current rounding mode 3874def : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>; 3875// Round to nearest, ties away from zero 3876def : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>; 3877// Round towards Zero 3878def : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>; 3879// Round towards +Inf 3880def : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>; 3881// Round towards -Inf 3882def : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>; 3883// Use current rounding mode, [with Inexact] 3884def : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>; 3885 3886def : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)), 3887 (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>; 3888 3889def : Pat<(i64 (int_ppc_scalar_extract_expq f128:$vA)), 3890 (i64 (MFVSRD (EXTRACT_SUBREG 3891 (v2i64 (XSXEXPQP $vA)), sub_64)))>; 3892 3893// Extra patterns expanding to vector Extract Word/Insert Word 3894def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)), 3895 (v4i32 (XXINSERTW $A, $B, imm:$IMM))>; 3896def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)), 3897 (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>; 3898 3899// Vector Reverse 3900def : Pat<(v8i16 (bswap v8i16 :$A)), 3901 (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; 3902def : Pat<(v1i128 (bswap v1i128 :$A)), 3903 (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; 3904 3905// D-Form Load/Store 3906foreach Ty = [v4i32, v4f32, v2i64, v2f64] in { 3907 def : Pat<(Ty (load DQForm:$src)), (LXV memrix16:$src)>; 3908 def : Pat<(Ty (load XForm:$src)), (LXVX XForm:$src)>; 3909 def : Pat<(store Ty:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; 3910 def : Pat<(store Ty:$rS, XForm:$dst), (STXVX $rS, XForm:$dst)>; 3911} 3912 3913def : Pat<(f128 (load DQForm:$src)), 3914 (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>; 3915def : Pat<(f128 (load XForm:$src)), 3916 (COPY_TO_REGCLASS (LXVX XForm:$src), VRRC)>; 3917def : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>; 3918def : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>; 3919def : Pat<(v4i32 (int_ppc_vsx_lxvw4x XForm:$src)), (LXVX XForm:$src)>; 3920def : Pat<(v2f64 (int_ppc_vsx_lxvd2x XForm:$src)), (LXVX XForm:$src)>; 3921 3922def : Pat<(store f128:$rS, DQForm:$dst), 3923 (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>; 3924def : Pat<(store f128:$rS, XForm:$dst), 3925 (STXVX (COPY_TO_REGCLASS $rS, VSRC), XForm:$dst)>; 3926def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst), 3927 (STXV $rS, memrix16:$dst)>; 3928def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst), 3929 (STXV $rS, memrix16:$dst)>; 3930def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst), 3931 (STXVX $rS, XForm:$dst)>; 3932def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst), 3933 (STXVX $rS, XForm:$dst)>; 3934 3935// Build vectors from i8 loads 3936defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8, 3937 (VSPLTHs 3, (LXSIBZX ForceXForm:$src)), 3938 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 3939defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8, 3940 (XXSPLTWs (LXSIBZX ForceXForm:$src), 1), 3941 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 3942defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64, 3943 (XXPERMDIs (LXSIBZX ForceXForm:$src), 0), 3944 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 3945defm : ScalToVecWPermute< 3946 v4i32, ScalarLoads.SELi8, 3947 (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1), 3948 (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>; 3949defm : ScalToVecWPermute< 3950 v2i64, ScalarLoads.SELi8i64, 3951 (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0), 3952 (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>; 3953 3954// Build vectors from i16 loads 3955defm : ScalToVecWPermute< 3956 v4i32, ScalarLoads.ZELi16, 3957 (XXSPLTWs (LXSIHZX ForceXForm:$src), 1), 3958 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 3959defm : ScalToVecWPermute< 3960 v2i64, ScalarLoads.ZELi16i64, 3961 (XXPERMDIs (LXSIHZX ForceXForm:$src), 0), 3962 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 3963defm : ScalToVecWPermute< 3964 v4i32, ScalarLoads.SELi16, 3965 (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1), 3966 (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>; 3967defm : ScalToVecWPermute< 3968 v2i64, ScalarLoads.SELi16i64, 3969 (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0), 3970 (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>; 3971 3972// Load/convert and convert/store patterns for f16. 3973def : Pat<(f64 (extloadf16 ForceXForm:$src)), 3974 (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>; 3975def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst), 3976 (STXSIHX (XSCVDPHP $src), ForceXForm:$dst)>; 3977def : Pat<(f32 (extloadf16 ForceXForm:$src)), 3978 (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)), VSSRC))>; 3979def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst), 3980 (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), ForceXForm:$dst)>; 3981def : Pat<(f64 (f16_to_fp i32:$A)), 3982 (f64 (XSCVHPDP (MTVSRWZ $A)))>; 3983def : Pat<(f32 (f16_to_fp i32:$A)), 3984 (f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>; 3985def : Pat<(i32 (fp_to_f16 f32:$A)), 3986 (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>; 3987def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>; 3988 3989// Vector sign extensions 3990def : Pat<(f64 (PPCVexts f64:$A, 1)), 3991 (f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>; 3992def : Pat<(f64 (PPCVexts f64:$A, 2)), 3993 (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>; 3994 3995def : Pat<(f64 (extloadf32 DSForm:$src)), 3996 (COPY_TO_REGCLASS (DFLOADf32 DSForm:$src), VSFRC)>; 3997def : Pat<(f32 (fpround (f64 (extloadf32 DSForm:$src)))), 3998 (f32 (DFLOADf32 DSForm:$src))>; 3999 4000def : Pat<(v4f32 (PPCldvsxlh XForm:$src)), 4001 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; 4002def : Pat<(v4f32 (PPCldvsxlh DSForm:$src)), 4003 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; 4004 4005// Convert (Un)Signed DWord in memory -> QP 4006def : Pat<(f128 (sint_to_fp (i64 (load XForm:$src)))), 4007 (f128 (XSCVSDQP (LXSDX XForm:$src)))>; 4008def : Pat<(f128 (sint_to_fp (i64 (load DSForm:$src)))), 4009 (f128 (XSCVSDQP (LXSD DSForm:$src)))>; 4010def : Pat<(f128 (uint_to_fp (i64 (load XForm:$src)))), 4011 (f128 (XSCVUDQP (LXSDX XForm:$src)))>; 4012def : Pat<(f128 (uint_to_fp (i64 (load DSForm:$src)))), 4013 (f128 (XSCVUDQP (LXSD DSForm:$src)))>; 4014 4015// Convert Unsigned HWord in memory -> QP 4016def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)), 4017 (f128 (XSCVUDQP (LXSIHZX XForm:$src)))>; 4018 4019// Convert Unsigned Byte in memory -> QP 4020def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)), 4021 (f128 (XSCVUDQP (LXSIBZX ForceXForm:$src)))>; 4022 4023// Truncate & Convert QP -> (Un)Signed (D)Word. 4024def : Pat<(i64 (any_fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>; 4025def : Pat<(i64 (any_fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>; 4026def : Pat<(i32 (any_fp_to_sint f128:$src)), 4027 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>; 4028def : Pat<(i32 (any_fp_to_uint f128:$src)), 4029 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>; 4030 4031// Instructions for store(fptosi). 4032// The 8-byte version is repeated here due to availability of D-Form STXSD. 4033def : Pat<(PPCstore_scal_int_from_vsr 4034 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), XForm:$dst, 8), 4035 (STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), 4036 XForm:$dst)>; 4037def : Pat<(PPCstore_scal_int_from_vsr 4038 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), DSForm:$dst, 8), 4039 (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), 4040 DSForm:$dst)>; 4041def : Pat<(PPCstore_scal_int_from_vsr 4042 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 4), 4043 (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>; 4044def : Pat<(PPCstore_scal_int_from_vsr 4045 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 2), 4046 (STXSIHX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>; 4047def : Pat<(PPCstore_scal_int_from_vsr 4048 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 1), 4049 (STXSIBX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>; 4050def : Pat<(PPCstore_scal_int_from_vsr 4051 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), XForm:$dst, 8), 4052 (STXSDX (XSCVDPSXDS f64:$src), XForm:$dst)>; 4053def : Pat<(PPCstore_scal_int_from_vsr 4054 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), DSForm:$dst, 8), 4055 (STXSD (XSCVDPSXDS f64:$src), DSForm:$dst)>; 4056def : Pat<(PPCstore_scal_int_from_vsr 4057 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 2), 4058 (STXSIHX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>; 4059def : Pat<(PPCstore_scal_int_from_vsr 4060 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 1), 4061 (STXSIBX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>; 4062 4063// Instructions for store(fptoui). 4064def : Pat<(PPCstore_scal_int_from_vsr 4065 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), XForm:$dst, 8), 4066 (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), 4067 XForm:$dst)>; 4068def : Pat<(PPCstore_scal_int_from_vsr 4069 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), DSForm:$dst, 8), 4070 (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), 4071 DSForm:$dst)>; 4072def : Pat<(PPCstore_scal_int_from_vsr 4073 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 4), 4074 (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>; 4075def : Pat<(PPCstore_scal_int_from_vsr 4076 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 2), 4077 (STXSIHX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>; 4078def : Pat<(PPCstore_scal_int_from_vsr 4079 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 1), 4080 (STXSIBX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>; 4081def : Pat<(PPCstore_scal_int_from_vsr 4082 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), XForm:$dst, 8), 4083 (STXSDX (XSCVDPUXDS f64:$src), XForm:$dst)>; 4084def : Pat<(PPCstore_scal_int_from_vsr 4085 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), DSForm:$dst, 8), 4086 (STXSD (XSCVDPUXDS f64:$src), DSForm:$dst)>; 4087def : Pat<(PPCstore_scal_int_from_vsr 4088 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 2), 4089 (STXSIHX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>; 4090def : Pat<(PPCstore_scal_int_from_vsr 4091 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 1), 4092 (STXSIBX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>; 4093 4094// Round & Convert QP -> DP/SP 4095def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>; 4096def : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>; 4097 4098// Convert SP -> QP 4099def : Pat<(f128 (any_fpextend f32:$src)), 4100 (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>; 4101 4102def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)), 4103 (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC), 4104 (COPY_TO_REGCLASS $XB, VSSRC)), 4105 VSSRC))>; 4106def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)), 4107 (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC), 4108 (COPY_TO_REGCLASS $XB, VSSRC)), 4109 VSSRC))>; 4110 4111// Endianness-neutral patterns for const splats with ISA 3.0 instructions. 4112defm : ScalToVecWPermute<v4i32, (i32 i32:$A), (MTVSRWS $A), 4113 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 4114def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 4115 (v4i32 (MTVSRWS $A))>; 4116def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4117 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4118 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4119 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4120 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4121 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4122 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 4123 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)), 4124 (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>; 4125defm : ScalToVecWPermute< 4126 v4i32, FltToIntLoad.A, 4127 (XVCVSPSXWS (LXVWSX ForceXForm:$A)), 4128 (XVCVSPSXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; 4129defm : ScalToVecWPermute< 4130 v4i32, FltToUIntLoad.A, 4131 (XVCVSPUXWS (LXVWSX ForceXForm:$A)), 4132 (XVCVSPUXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; 4133defm : ScalToVecWPermute< 4134 v4i32, DblToIntLoadP9.A, 4135 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1), 4136 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>; 4137defm : ScalToVecWPermute< 4138 v4i32, DblToUIntLoadP9.A, 4139 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1), 4140 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>; 4141defm : ScalToVecWPermute< 4142 v2i64, FltToLongLoadP9.A, 4143 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), 4144 (SUBREG_TO_REG 4145 (i64 1), 4146 (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; 4147defm : ScalToVecWPermute< 4148 v2i64, FltToULongLoadP9.A, 4149 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), 4150 (SUBREG_TO_REG 4151 (i64 1), 4152 (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; 4153def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), 4154 (v4f32 (LXVWSX ForceXForm:$A))>; 4155def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)), 4156 (v4i32 (LXVWSX ForceXForm:$A))>; 4157def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)), 4158 (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>; 4159def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)), 4160 (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>; 4161def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)), 4162 (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>; 4163} // HasVSX, HasP9Vector 4164 4165// Any Power9 VSX subtarget with equivalent length but better Power10 VSX 4166// patterns. 4167// Two identical blocks are required due to the slightly different predicates: 4168// One without P10 instructions, the other is BigEndian only with P10 instructions. 4169let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in { 4170// Little endian Power10 subtargets produce a shorter pattern but require a 4171// COPY_TO_REGCLASS. The COPY_TO_REGCLASS makes it appear to need two instructions 4172// to perform the operation, when only one instruction is produced in practice. 4173// The NoP10Vector predicate excludes these patterns from Power10 VSX subtargets. 4174defm : ScalToVecWPermute< 4175 v16i8, ScalarLoads.Li8, 4176 (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), 4177 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 4178// Build vectors from i16 loads 4179defm : ScalToVecWPermute< 4180 v8i16, ScalarLoads.Li16, 4181 (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), 4182 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 4183} // HasVSX, HasP9Vector, NoP10Vector 4184 4185// Any big endian Power9 VSX subtarget 4186let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in { 4187// Power10 VSX subtargets produce a shorter pattern for little endian targets 4188// but this is still the best pattern for Power9 and Power10 VSX big endian 4189// Build vectors from i8 loads 4190defm : ScalToVecWPermute< 4191 v16i8, ScalarLoads.Li8, 4192 (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), 4193 (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; 4194// Build vectors from i16 loads 4195defm : ScalToVecWPermute< 4196 v8i16, ScalarLoads.Li16, 4197 (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), 4198 (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; 4199 4200def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 4201 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 4202def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 4203 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 4204def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 4205 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 4206def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 4207 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 4208def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 4209 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>; 4210def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 4211 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>; 4212def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 4213 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>; 4214def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 4215 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>; 4216def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 4217 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 4218def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), 4219 (v4i32 (XXINSERTW v4i32:$A, 4220 (SUBREG_TO_REG (i64 1), 4221 (XSCVDPSXWS f64:$B), sub_64), 4222 0))>; 4223def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), 4224 (v4i32 (XXINSERTW v4i32:$A, 4225 (SUBREG_TO_REG (i64 1), 4226 (XSCVDPUXWS f64:$B), sub_64), 4227 0))>; 4228def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 4229 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 4230def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), 4231 (v4i32 (XXINSERTW v4i32:$A, 4232 (SUBREG_TO_REG (i64 1), 4233 (XSCVDPSXWS f64:$B), sub_64), 4234 4))>; 4235def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), 4236 (v4i32 (XXINSERTW v4i32:$A, 4237 (SUBREG_TO_REG (i64 1), 4238 (XSCVDPUXWS f64:$B), sub_64), 4239 4))>; 4240def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 4241 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 4242def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), 4243 (v4i32 (XXINSERTW v4i32:$A, 4244 (SUBREG_TO_REG (i64 1), 4245 (XSCVDPSXWS f64:$B), sub_64), 4246 8))>; 4247def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), 4248 (v4i32 (XXINSERTW v4i32:$A, 4249 (SUBREG_TO_REG (i64 1), 4250 (XSCVDPUXWS f64:$B), sub_64), 4251 8))>; 4252def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 4253 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 4254def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), 4255 (v4i32 (XXINSERTW v4i32:$A, 4256 (SUBREG_TO_REG (i64 1), 4257 (XSCVDPSXWS f64:$B), sub_64), 4258 12))>; 4259def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), 4260 (v4i32 (XXINSERTW v4i32:$A, 4261 (SUBREG_TO_REG (i64 1), 4262 (XSCVDPUXWS f64:$B), sub_64), 4263 12))>; 4264def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 4265 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 4266def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 4267 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 4268def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 4269 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 4270def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 4271 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 4272 4273def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), 4274 (v4f32 (XXINSERTW v4f32:$A, 4275 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; 4276def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), 4277 (v4f32 (XXINSERTW v4f32:$A, 4278 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; 4279def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), 4280 (v4f32 (XXINSERTW v4f32:$A, 4281 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; 4282def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), 4283 (v4f32 (XXINSERTW v4f32:$A, 4284 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; 4285 4286// Scalar stores of i8 4287def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst), 4288 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>; 4289def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst), 4290 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4291def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst), 4292 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>; 4293def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst), 4294 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4295def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst), 4296 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>; 4297def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst), 4298 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4299def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst), 4300 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>; 4301def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst), 4302 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4303def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst), 4304 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>; 4305def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst), 4306 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4307def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst), 4308 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>; 4309def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst), 4310 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4311def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst), 4312 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>; 4313def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst), 4314 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4315def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst), 4316 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>; 4317def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst), 4318 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4319 4320// Scalar stores of i16 4321def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst), 4322 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4323def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst), 4324 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4325def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst), 4326 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4327def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst), 4328 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4329def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst), 4330 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4331def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst), 4332 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4333def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst), 4334 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4335def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), 4336 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4337} // HasVSX, HasP9Vector, IsBigEndian 4338 4339// Big endian 64Bit Power9 subtarget. 4340let Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in { 4341def : Pat<(v2i64 (scalar_to_vector (i64 (load DSForm:$src)))), 4342 (v2i64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; 4343def : Pat<(v2i64 (scalar_to_vector (i64 (load XForm:$src)))), 4344 (v2i64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; 4345 4346def : Pat<(v2f64 (scalar_to_vector (f64 (load DSForm:$src)))), 4347 (v2f64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; 4348def : Pat<(v2f64 (scalar_to_vector (f64 (load XForm:$src)))), 4349 (v2f64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; 4350def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src), 4351 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4352 sub_64), XForm:$src)>; 4353def : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src), 4354 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4355 sub_64), XForm:$src)>; 4356def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src), 4357 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4358def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src), 4359 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4360def : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src), 4361 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4362 sub_64), DSForm:$src)>; 4363def : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src), 4364 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4365 sub_64), DSForm:$src)>; 4366def : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src), 4367 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 4368def : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src), 4369 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 4370 4371// (Un)Signed DWord vector extract -> QP 4372def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4373 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4374def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4375 (f128 (XSCVSDQP 4376 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4377def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4378 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4379def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4380 (f128 (XSCVUDQP 4381 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4382 4383// (Un)Signed Word vector extract -> QP 4384def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))), 4385 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>; 4386foreach Idx = [0,2,3] in { 4387 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))), 4388 (f128 (XSCVSDQP (EXTRACT_SUBREG 4389 (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>; 4390} 4391foreach Idx = 0-3 in { 4392 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))), 4393 (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>; 4394} 4395 4396// (Un)Signed HWord vector extract -> QP/DP/SP 4397foreach Idx = 0-7 in { 4398 def : Pat<(f128 (sint_to_fp 4399 (i32 (sext_inreg 4400 (vector_extract v8i16:$src, Idx), i16)))), 4401 (f128 (XSCVSDQP (EXTRACT_SUBREG 4402 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 4403 sub_64)))>; 4404 // The SDAG adds the `and` since an `i16` is being extracted as an `i32`. 4405 def : Pat<(f128 (uint_to_fp 4406 (and (i32 (vector_extract v8i16:$src, Idx)), 65535))), 4407 (f128 (XSCVUDQP (EXTRACT_SUBREG 4408 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4409 def : Pat<(f32 (PPCfcfidus 4410 (f64 (PPCmtvsrz (and (i32 (vector_extract v8i16:$src, Idx)), 4411 65535))))), 4412 (f32 (XSCVUXDSP (EXTRACT_SUBREG 4413 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4414 def : Pat<(f32 (PPCfcfids 4415 (f64 (PPCmtvsra 4416 (i32 (sext_inreg (vector_extract v8i16:$src, Idx), 4417 i16)))))), 4418 (f32 (XSCVSXDSP (EXTRACT_SUBREG 4419 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 4420 sub_64)))>; 4421 def : Pat<(f64 (PPCfcfidu 4422 (f64 (PPCmtvsrz 4423 (and (i32 (vector_extract v8i16:$src, Idx)), 4424 65535))))), 4425 (f64 (XSCVUXDDP (EXTRACT_SUBREG 4426 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4427 def : Pat<(f64 (PPCfcfid 4428 (f64 (PPCmtvsra 4429 (i32 (sext_inreg (vector_extract v8i16:$src, Idx), 4430 i16)))))), 4431 (f64 (XSCVSXDDP (EXTRACT_SUBREG 4432 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 4433 sub_64)))>; 4434} 4435 4436// (Un)Signed Byte vector extract -> QP 4437foreach Idx = 0-15 in { 4438 def : Pat<(f128 (sint_to_fp 4439 (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 4440 i8)))), 4441 (f128 (XSCVSDQP (EXTRACT_SUBREG 4442 (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>; 4443 def : Pat<(f128 (uint_to_fp 4444 (and (i32 (vector_extract v16i8:$src, Idx)), 255))), 4445 (f128 (XSCVUDQP 4446 (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>; 4447 4448 def : Pat<(f32 (PPCfcfidus 4449 (f64 (PPCmtvsrz 4450 (and (i32 (vector_extract v16i8:$src, Idx)), 4451 255))))), 4452 (f32 (XSCVUXDSP (EXTRACT_SUBREG 4453 (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>; 4454 def : Pat<(f32 (PPCfcfids 4455 (f64 (PPCmtvsra 4456 (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 4457 i8)))))), 4458 (f32 (XSCVSXDSP (EXTRACT_SUBREG 4459 (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)), 4460 sub_64)))>; 4461 def : Pat<(f64 (PPCfcfidu 4462 (f64 (PPCmtvsrz 4463 (and (i32 (vector_extract v16i8:$src, Idx)), 4464 255))))), 4465 (f64 (XSCVUXDDP (EXTRACT_SUBREG 4466 (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>; 4467 def : Pat<(f64 (PPCfcfid 4468 (f64 (PPCmtvsra 4469 (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 4470 i8)))))), 4471 (f64 (XSCVSXDDP (EXTRACT_SUBREG 4472 (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)), 4473 sub_64)))>; 4474} 4475 4476// Unsiged int in vsx register -> QP 4477def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), 4478 (f128 (XSCVUDQP 4479 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>; 4480} // HasVSX, HasP9Vector, IsBigEndian, IsPPC64 4481 4482// Little endian Power9 subtarget. 4483let Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in { 4484def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 4485 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 4486def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 4487 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 4488def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 4489 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 4490def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 4491 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 4492def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 4493 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>; 4494def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 4495 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>; 4496def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 4497 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>; 4498def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 4499 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>; 4500def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 4501 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 4502def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), 4503 (v4i32 (XXINSERTW v4i32:$A, 4504 (SUBREG_TO_REG (i64 1), 4505 (XSCVDPSXWS f64:$B), sub_64), 4506 12))>; 4507def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), 4508 (v4i32 (XXINSERTW v4i32:$A, 4509 (SUBREG_TO_REG (i64 1), 4510 (XSCVDPUXWS f64:$B), sub_64), 4511 12))>; 4512def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 4513 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 4514def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), 4515 (v4i32 (XXINSERTW v4i32:$A, 4516 (SUBREG_TO_REG (i64 1), 4517 (XSCVDPSXWS f64:$B), sub_64), 4518 8))>; 4519def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), 4520 (v4i32 (XXINSERTW v4i32:$A, 4521 (SUBREG_TO_REG (i64 1), 4522 (XSCVDPUXWS f64:$B), sub_64), 4523 8))>; 4524def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 4525 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 4526def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), 4527 (v4i32 (XXINSERTW v4i32:$A, 4528 (SUBREG_TO_REG (i64 1), 4529 (XSCVDPSXWS f64:$B), sub_64), 4530 4))>; 4531def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), 4532 (v4i32 (XXINSERTW v4i32:$A, 4533 (SUBREG_TO_REG (i64 1), 4534 (XSCVDPUXWS f64:$B), sub_64), 4535 4))>; 4536def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 4537 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 4538def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), 4539 (v4i32 (XXINSERTW v4i32:$A, 4540 (SUBREG_TO_REG (i64 1), 4541 (XSCVDPSXWS f64:$B), sub_64), 4542 0))>; 4543def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), 4544 (v4i32 (XXINSERTW v4i32:$A, 4545 (SUBREG_TO_REG (i64 1), 4546 (XSCVDPUXWS f64:$B), sub_64), 4547 0))>; 4548def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 4549 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 4550def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 4551 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 4552def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 4553 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 4554def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 4555 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 4556 4557def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), 4558 (v4f32 (XXINSERTW v4f32:$A, 4559 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; 4560def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), 4561 (v4f32 (XXINSERTW v4f32:$A, 4562 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; 4563def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), 4564 (v4f32 (XXINSERTW v4f32:$A, 4565 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; 4566def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), 4567 (v4f32 (XXINSERTW v4f32:$A, 4568 (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; 4569 4570def : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)), 4571 (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>; 4572def : Pat<(PPCst_vec_be v8i16:$rS, ForceXForm:$dst), 4573 (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>; 4574 4575def : Pat<(v16i8 (PPCld_vec_be ForceXForm:$src)), 4576 (COPY_TO_REGCLASS (LXVB16X ForceXForm:$src), VRRC)>; 4577def : Pat<(PPCst_vec_be v16i8:$rS, ForceXForm:$dst), 4578 (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>; 4579 4580// Scalar stores of i8 4581def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst), 4582 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4583def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst), 4584 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), ForceXForm:$dst)>; 4585def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst), 4586 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4587def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst), 4588 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), ForceXForm:$dst)>; 4589def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), ForceXForm:$dst), 4590 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4591def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), ForceXForm:$dst), 4592 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), ForceXForm:$dst)>; 4593def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), ForceXForm:$dst), 4594 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4595def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), ForceXForm:$dst), 4596 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), ForceXForm:$dst)>; 4597def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), ForceXForm:$dst), 4598 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4599def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), ForceXForm:$dst), 4600 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), ForceXForm:$dst)>; 4601def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), ForceXForm:$dst), 4602 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4603def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), ForceXForm:$dst), 4604 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), ForceXForm:$dst)>; 4605def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), ForceXForm:$dst), 4606 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4607def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), ForceXForm:$dst), 4608 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>; 4609def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), ForceXForm:$dst), 4610 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4611def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), ForceXForm:$dst), 4612 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>; 4613 4614// Scalar stores of i16 4615def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), ForceXForm:$dst), 4616 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), ForceXForm:$dst)>; 4617def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), ForceXForm:$dst), 4618 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), ForceXForm:$dst)>; 4619def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), ForceXForm:$dst), 4620 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), ForceXForm:$dst)>; 4621def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), ForceXForm:$dst), 4622 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), ForceXForm:$dst)>; 4623def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), ForceXForm:$dst), 4624 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), ForceXForm:$dst)>; 4625def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst), 4626 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>; 4627def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst), 4628 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>; 4629def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), 4630 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>; 4631 4632defm : ScalToVecWPermute< 4633 v2i64, (i64 (load DSForm:$src)), 4634 (XXPERMDIs (DFLOADf64 DSForm:$src), 2), 4635 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; 4636defm : ScalToVecWPermute< 4637 v2i64, (i64 (load XForm:$src)), 4638 (XXPERMDIs (XFLOADf64 XForm:$src), 2), 4639 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; 4640defm : ScalToVecWPermute< 4641 v2f64, (f64 (load DSForm:$src)), 4642 (XXPERMDIs (DFLOADf64 DSForm:$src), 2), 4643 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; 4644defm : ScalToVecWPermute< 4645 v2f64, (f64 (load XForm:$src)), 4646 (XXPERMDIs (XFLOADf64 XForm:$src), 2), 4647 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; 4648 4649def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src), 4650 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4651 sub_64), XForm:$src)>; 4652def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src), 4653 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4654 sub_64), XForm:$src)>; 4655def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src), 4656 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4657def : Pat<(store (f64 (extractelt v2f64:$A, 1)), XForm:$src), 4658 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), XForm:$src)>; 4659def : Pat<(store (i64 (extractelt v2i64:$A, 0)), DSForm:$src), 4660 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4661 sub_64), DSForm:$src)>; 4662def : Pat<(store (f64 (extractelt v2f64:$A, 0)), DSForm:$src), 4663 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 4664 DSForm:$src)>; 4665def : Pat<(store (i64 (extractelt v2i64:$A, 1)), DSForm:$src), 4666 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 4667def : Pat<(store (f64 (extractelt v2f64:$A, 1)), DSForm:$src), 4668 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), DSForm:$src)>; 4669 4670// (Un)Signed DWord vector extract -> QP 4671def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4672 (f128 (XSCVSDQP 4673 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4674def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4675 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4676def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4677 (f128 (XSCVUDQP 4678 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4679def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4680 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4681 4682// (Un)Signed Word vector extract -> QP 4683foreach Idx = [[0,3],[1,2],[3,0]] in { 4684 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))), 4685 (f128 (XSCVSDQP (EXTRACT_SUBREG 4686 (VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)), 4687 sub_64)))>; 4688} 4689def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))), 4690 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>; 4691 4692foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in { 4693 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))), 4694 (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>; 4695} 4696 4697// (Un)Signed HWord vector extract -> QP/DP/SP 4698// The Nested foreach lists identifies the vector element and corresponding 4699// register byte location. 4700foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in { 4701 def : Pat<(f128 (sint_to_fp 4702 (i32 (sext_inreg 4703 (vector_extract v8i16:$src, !head(Idx)), i16)))), 4704 (f128 (XSCVSDQP 4705 (EXTRACT_SUBREG (VEXTSH2D 4706 (VEXTRACTUH !head(!tail(Idx)), $src)), 4707 sub_64)))>; 4708 def : Pat<(f128 (uint_to_fp 4709 (and (i32 (vector_extract v8i16:$src, !head(Idx))), 4710 65535))), 4711 (f128 (XSCVUDQP (EXTRACT_SUBREG 4712 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4713 def : Pat<(f32 (PPCfcfidus 4714 (f64 (PPCmtvsrz 4715 (and (i32 (vector_extract v8i16:$src, !head(Idx))), 4716 65535))))), 4717 (f32 (XSCVUXDSP (EXTRACT_SUBREG 4718 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4719 def : Pat<(f32 (PPCfcfids 4720 (f64 (PPCmtvsra 4721 (i32 (sext_inreg (vector_extract v8i16:$src, 4722 !head(Idx)), i16)))))), 4723 (f32 (XSCVSXDSP 4724 (EXTRACT_SUBREG 4725 (VEXTSH2D (VEXTRACTUH !head(!tail(Idx)), $src)), 4726 sub_64)))>; 4727 def : Pat<(f64 (PPCfcfidu 4728 (f64 (PPCmtvsrz 4729 (and (i32 (vector_extract v8i16:$src, !head(Idx))), 4730 65535))))), 4731 (f64 (XSCVUXDDP (EXTRACT_SUBREG 4732 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4733 def : Pat<(f64 (PPCfcfid 4734 (f64 (PPCmtvsra 4735 (i32 (sext_inreg 4736 (vector_extract v8i16:$src, !head(Idx)), i16)))))), 4737 (f64 (XSCVSXDDP 4738 (EXTRACT_SUBREG (VEXTSH2D 4739 (VEXTRACTUH !head(!tail(Idx)), $src)), 4740 sub_64)))>; 4741} 4742 4743// (Un)Signed Byte vector extract -> QP/DP/SP 4744foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7], 4745 [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in { 4746 def : Pat<(f128 (sint_to_fp 4747 (i32 (sext_inreg 4748 (vector_extract v16i8:$src, !head(Idx)), i8)))), 4749 (f128 (XSCVSDQP 4750 (EXTRACT_SUBREG 4751 (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)), 4752 sub_64)))>; 4753 def : Pat<(f128 (uint_to_fp 4754 (and (i32 (vector_extract v16i8:$src, !head(Idx))), 4755 255))), 4756 (f128 (XSCVUDQP 4757 (EXTRACT_SUBREG 4758 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4759 4760 def : Pat<(f32 (PPCfcfidus 4761 (f64 (PPCmtvsrz 4762 (and (i32 (vector_extract v16i8:$src, !head(Idx))), 4763 255))))), 4764 (f32 (XSCVUXDSP (EXTRACT_SUBREG 4765 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4766 def : Pat<(f32 (PPCfcfids 4767 (f64 (PPCmtvsra 4768 (i32 (sext_inreg 4769 (vector_extract v16i8:$src, !head(Idx)), i8)))))), 4770 (f32 (XSCVSXDSP 4771 (EXTRACT_SUBREG (VEXTSH2D 4772 (VEXTRACTUB !head(!tail(Idx)), $src)), 4773 sub_64)))>; 4774 def : Pat<(f64 (PPCfcfidu 4775 (f64 (PPCmtvsrz 4776 (and (i32 4777 (vector_extract v16i8:$src, !head(Idx))), 255))))), 4778 (f64 (XSCVUXDDP (EXTRACT_SUBREG 4779 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4780 def : Pat<(f64 (PPCfcfidu 4781 (f64 (PPCmtvsra 4782 (i32 (sext_inreg 4783 (vector_extract v16i8:$src, !head(Idx)), i8)))))), 4784 (f64 (XSCVSXDDP 4785 (EXTRACT_SUBREG (VEXTSH2D 4786 (VEXTRACTUB !head(!tail(Idx)), $src)), 4787 sub_64)))>; 4788 4789 def : Pat<(f64 (PPCfcfid 4790 (f64 (PPCmtvsra 4791 (i32 (sext_inreg 4792 (vector_extract v16i8:$src, !head(Idx)), i8)))))), 4793 (f64 (XSCVSXDDP 4794 (EXTRACT_SUBREG (VEXTSH2D 4795 (VEXTRACTUH !head(!tail(Idx)), $src)), 4796 sub_64)))>; 4797} 4798 4799// Unsiged int in vsx register -> QP 4800def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), 4801 (f128 (XSCVUDQP 4802 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; 4803} // HasVSX, HasP9Vector, IsLittleEndian 4804 4805// Any Power9 VSX subtarget that supports Power9 Altivec. 4806let Predicates = [HasVSX, HasP9Altivec] in { 4807// Unsigned absolute-difference. 4808def : Pat<(v4i32 (abdu v4i32:$A, v4i32:$B)), 4809 (v4i32 (VABSDUW $A, $B))>; 4810 4811def : Pat<(v8i16 (abdu v8i16:$A, v8i16:$B)), 4812 (v8i16 (VABSDUH $A, $B))>; 4813 4814def : Pat<(v16i8 (abdu v16i8:$A, v16i8:$B)), 4815 (v16i8 (VABSDUB $A, $B))>; 4816 4817// Signed absolute-difference. 4818// Power9 VABSD* instructions are designed to support unsigned integer 4819// vectors (byte/halfword/word), if we want to make use of them for signed 4820// integer vectors, we have to flip their sign bits first. To flip sign bit 4821// for byte/halfword integer vector would become inefficient, but for word 4822// integer vector, we can leverage XVNEGSP to make it efficiently. 4823def : Pat<(v4i32 (abds v4i32:$A, v4i32:$B)), 4824 (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>; 4825} // HasVSX, HasP9Altivec 4826 4827// Big endian Power9 64Bit VSX subtargets with P9 Altivec support. 4828let Predicates = [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] in { 4829def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), 4830 (VEXTUBLX $Idx, $S)>; 4831 4832def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))), 4833 (VEXTUHLX (RLWINM8 $Idx, 1, 28, 30), $S)>; 4834def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))), 4835 (VEXTUHLX (LI8 0), $S)>; 4836def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))), 4837 (VEXTUHLX (LI8 2), $S)>; 4838def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))), 4839 (VEXTUHLX (LI8 4), $S)>; 4840def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))), 4841 (VEXTUHLX (LI8 6), $S)>; 4842def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))), 4843 (VEXTUHLX (LI8 8), $S)>; 4844def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))), 4845 (VEXTUHLX (LI8 10), $S)>; 4846def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))), 4847 (VEXTUHLX (LI8 12), $S)>; 4848def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))), 4849 (VEXTUHLX (LI8 14), $S)>; 4850 4851def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4852 (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S)>; 4853def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))), 4854 (VEXTUWLX (LI8 0), $S)>; 4855 4856// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 4857def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))), 4858 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4859 (i32 VectorExtractions.LE_WORD_2), sub_32)>; 4860def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))), 4861 (VEXTUWLX (LI8 8), $S)>; 4862def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))), 4863 (VEXTUWLX (LI8 12), $S)>; 4864 4865def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4866 (EXTSW (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S))>; 4867def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))), 4868 (EXTSW (VEXTUWLX (LI8 0), $S))>; 4869// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 4870def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))), 4871 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4872 (i32 VectorExtractions.LE_WORD_2), sub_32))>; 4873def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))), 4874 (EXTSW (VEXTUWLX (LI8 8), $S))>; 4875def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))), 4876 (EXTSW (VEXTUWLX (LI8 12), $S))>; 4877 4878def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 4879 (i32 (EXTRACT_SUBREG (VEXTUBLX $Idx, $S), sub_32))>; 4880def : Pat<(i32 (vector_extract v16i8:$S, 0)), 4881 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 0), $S), sub_32))>; 4882def : Pat<(i32 (vector_extract v16i8:$S, 1)), 4883 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 1), $S), sub_32))>; 4884def : Pat<(i32 (vector_extract v16i8:$S, 2)), 4885 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 2), $S), sub_32))>; 4886def : Pat<(i32 (vector_extract v16i8:$S, 3)), 4887 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 3), $S), sub_32))>; 4888def : Pat<(i32 (vector_extract v16i8:$S, 4)), 4889 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 4), $S), sub_32))>; 4890def : Pat<(i32 (vector_extract v16i8:$S, 5)), 4891 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 5), $S), sub_32))>; 4892def : Pat<(i32 (vector_extract v16i8:$S, 6)), 4893 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 6), $S), sub_32))>; 4894def : Pat<(i32 (vector_extract v16i8:$S, 7)), 4895 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 7), $S), sub_32))>; 4896def : Pat<(i32 (vector_extract v16i8:$S, 8)), 4897 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 8), $S), sub_32))>; 4898def : Pat<(i32 (vector_extract v16i8:$S, 9)), 4899 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 9), $S), sub_32))>; 4900def : Pat<(i32 (vector_extract v16i8:$S, 10)), 4901 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 10), $S), sub_32))>; 4902def : Pat<(i32 (vector_extract v16i8:$S, 11)), 4903 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 11), $S), sub_32))>; 4904def : Pat<(i32 (vector_extract v16i8:$S, 12)), 4905 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 12), $S), sub_32))>; 4906def : Pat<(i32 (vector_extract v16i8:$S, 13)), 4907 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 13), $S), sub_32))>; 4908def : Pat<(i32 (vector_extract v16i8:$S, 14)), 4909 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 14), $S), sub_32))>; 4910def : Pat<(i32 (vector_extract v16i8:$S, 15)), 4911 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 15), $S), sub_32))>; 4912 4913def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 4914 (i32 (EXTRACT_SUBREG (VEXTUHLX 4915 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>; 4916def : Pat<(i32 (vector_extract v8i16:$S, 0)), 4917 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 0), $S), sub_32))>; 4918def : Pat<(i32 (vector_extract v8i16:$S, 1)), 4919 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 2), $S), sub_32))>; 4920def : Pat<(i32 (vector_extract v8i16:$S, 2)), 4921 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 4), $S), sub_32))>; 4922def : Pat<(i32 (vector_extract v8i16:$S, 3)), 4923 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 6), $S), sub_32))>; 4924def : Pat<(i32 (vector_extract v8i16:$S, 4)), 4925 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 8), $S), sub_32))>; 4926def : Pat<(i32 (vector_extract v8i16:$S, 5)), 4927 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 10), $S), sub_32))>; 4928def : Pat<(i32 (vector_extract v8i16:$S, 6)), 4929 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 12), $S), sub_32))>; 4930def : Pat<(i32 (vector_extract v8i16:$S, 6)), 4931 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 14), $S), sub_32))>; 4932 4933def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 4934 (i32 (EXTRACT_SUBREG (VEXTUWLX 4935 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>; 4936def : Pat<(i32 (vector_extract v4i32:$S, 0)), 4937 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 0), $S), sub_32))>; 4938// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 4939def : Pat<(i32 (vector_extract v4i32:$S, 1)), 4940 (i32 VectorExtractions.LE_WORD_2)>; 4941def : Pat<(i32 (vector_extract v4i32:$S, 2)), 4942 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 8), $S), sub_32))>; 4943def : Pat<(i32 (vector_extract v4i32:$S, 3)), 4944 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 12), $S), sub_32))>; 4945 4946// P9 Altivec instructions that can be used to build vectors. 4947// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete 4948// with complexities of existing build vector patterns in this file. 4949def : Pat<(v2i64 (build_vector WordToDWord.BE_A0, WordToDWord.BE_A1)), 4950 (v2i64 (VEXTSW2D $A))>; 4951def : Pat<(v2i64 (build_vector HWordToDWord.BE_A0, HWordToDWord.BE_A1)), 4952 (v2i64 (VEXTSH2D $A))>; 4953def : Pat<(v4i32 (build_vector HWordToWord.BE_A0, HWordToWord.BE_A1, 4954 HWordToWord.BE_A2, HWordToWord.BE_A3)), 4955 (v4i32 (VEXTSH2W $A))>; 4956def : Pat<(v4i32 (build_vector ByteToWord.BE_A0, ByteToWord.BE_A1, 4957 ByteToWord.BE_A2, ByteToWord.BE_A3)), 4958 (v4i32 (VEXTSB2W $A))>; 4959def : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)), 4960 (v2i64 (VEXTSB2D $A))>; 4961} // HasVSX, HasP9Altivec, IsBigEndian, IsPPC64 4962 4963// Little endian Power9 VSX subtargets with P9 Altivec support. 4964let Predicates = [HasVSX, HasP9Altivec, IsLittleEndian] in { 4965def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), 4966 (VEXTUBRX $Idx, $S)>; 4967 4968def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))), 4969 (VEXTUHRX (RLWINM8 $Idx, 1, 28, 30), $S)>; 4970def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))), 4971 (VEXTUHRX (LI8 0), $S)>; 4972def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))), 4973 (VEXTUHRX (LI8 2), $S)>; 4974def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))), 4975 (VEXTUHRX (LI8 4), $S)>; 4976def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))), 4977 (VEXTUHRX (LI8 6), $S)>; 4978def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))), 4979 (VEXTUHRX (LI8 8), $S)>; 4980def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))), 4981 (VEXTUHRX (LI8 10), $S)>; 4982def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))), 4983 (VEXTUHRX (LI8 12), $S)>; 4984def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))), 4985 (VEXTUHRX (LI8 14), $S)>; 4986 4987def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4988 (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S)>; 4989def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))), 4990 (VEXTUWRX (LI8 0), $S)>; 4991def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))), 4992 (VEXTUWRX (LI8 4), $S)>; 4993// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 4994def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))), 4995 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4996 (i32 VectorExtractions.LE_WORD_2), sub_32)>; 4997def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))), 4998 (VEXTUWRX (LI8 12), $S)>; 4999 5000def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 5001 (EXTSW (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S))>; 5002def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))), 5003 (EXTSW (VEXTUWRX (LI8 0), $S))>; 5004def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))), 5005 (EXTSW (VEXTUWRX (LI8 4), $S))>; 5006// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 5007def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))), 5008 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 5009 (i32 VectorExtractions.LE_WORD_2), sub_32))>; 5010def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))), 5011 (EXTSW (VEXTUWRX (LI8 12), $S))>; 5012 5013def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 5014 (i32 (EXTRACT_SUBREG (VEXTUBRX $Idx, $S), sub_32))>; 5015def : Pat<(i32 (vector_extract v16i8:$S, 0)), 5016 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 0), $S), sub_32))>; 5017def : Pat<(i32 (vector_extract v16i8:$S, 1)), 5018 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 1), $S), sub_32))>; 5019def : Pat<(i32 (vector_extract v16i8:$S, 2)), 5020 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 2), $S), sub_32))>; 5021def : Pat<(i32 (vector_extract v16i8:$S, 3)), 5022 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 3), $S), sub_32))>; 5023def : Pat<(i32 (vector_extract v16i8:$S, 4)), 5024 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 4), $S), sub_32))>; 5025def : Pat<(i32 (vector_extract v16i8:$S, 5)), 5026 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 5), $S), sub_32))>; 5027def : Pat<(i32 (vector_extract v16i8:$S, 6)), 5028 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 6), $S), sub_32))>; 5029def : Pat<(i32 (vector_extract v16i8:$S, 7)), 5030 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 7), $S), sub_32))>; 5031def : Pat<(i32 (vector_extract v16i8:$S, 8)), 5032 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 8), $S), sub_32))>; 5033def : Pat<(i32 (vector_extract v16i8:$S, 9)), 5034 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 9), $S), sub_32))>; 5035def : Pat<(i32 (vector_extract v16i8:$S, 10)), 5036 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 10), $S), sub_32))>; 5037def : Pat<(i32 (vector_extract v16i8:$S, 11)), 5038 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 11), $S), sub_32))>; 5039def : Pat<(i32 (vector_extract v16i8:$S, 12)), 5040 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 12), $S), sub_32))>; 5041def : Pat<(i32 (vector_extract v16i8:$S, 13)), 5042 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 13), $S), sub_32))>; 5043def : Pat<(i32 (vector_extract v16i8:$S, 14)), 5044 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 14), $S), sub_32))>; 5045def : Pat<(i32 (vector_extract v16i8:$S, 15)), 5046 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 15), $S), sub_32))>; 5047 5048def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 5049 (i32 (EXTRACT_SUBREG (VEXTUHRX 5050 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>; 5051def : Pat<(i32 (vector_extract v8i16:$S, 0)), 5052 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 0), $S), sub_32))>; 5053def : Pat<(i32 (vector_extract v8i16:$S, 1)), 5054 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 2), $S), sub_32))>; 5055def : Pat<(i32 (vector_extract v8i16:$S, 2)), 5056 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 4), $S), sub_32))>; 5057def : Pat<(i32 (vector_extract v8i16:$S, 3)), 5058 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 6), $S), sub_32))>; 5059def : Pat<(i32 (vector_extract v8i16:$S, 4)), 5060 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 8), $S), sub_32))>; 5061def : Pat<(i32 (vector_extract v8i16:$S, 5)), 5062 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 10), $S), sub_32))>; 5063def : Pat<(i32 (vector_extract v8i16:$S, 6)), 5064 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 12), $S), sub_32))>; 5065def : Pat<(i32 (vector_extract v8i16:$S, 6)), 5066 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 14), $S), sub_32))>; 5067 5068def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 5069 (i32 (EXTRACT_SUBREG (VEXTUWRX 5070 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>; 5071def : Pat<(i32 (vector_extract v4i32:$S, 0)), 5072 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 0), $S), sub_32))>; 5073def : Pat<(i32 (vector_extract v4i32:$S, 1)), 5074 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 4), $S), sub_32))>; 5075// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 5076def : Pat<(i32 (vector_extract v4i32:$S, 2)), 5077 (i32 VectorExtractions.LE_WORD_2)>; 5078def : Pat<(i32 (vector_extract v4i32:$S, 3)), 5079 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 12), $S), sub_32))>; 5080 5081// P9 Altivec instructions that can be used to build vectors. 5082// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete 5083// with complexities of existing build vector patterns in this file. 5084def : Pat<(v2i64 (build_vector WordToDWord.LE_A0, WordToDWord.LE_A1)), 5085 (v2i64 (VEXTSW2D $A))>; 5086def : Pat<(v2i64 (build_vector HWordToDWord.LE_A0, HWordToDWord.LE_A1)), 5087 (v2i64 (VEXTSH2D $A))>; 5088def : Pat<(v4i32 (build_vector HWordToWord.LE_A0, HWordToWord.LE_A1, 5089 HWordToWord.LE_A2, HWordToWord.LE_A3)), 5090 (v4i32 (VEXTSH2W $A))>; 5091def : Pat<(v4i32 (build_vector ByteToWord.LE_A0, ByteToWord.LE_A1, 5092 ByteToWord.LE_A2, ByteToWord.LE_A3)), 5093 (v4i32 (VEXTSB2W $A))>; 5094def : Pat<(v2i64 (build_vector ByteToDWord.LE_A0, ByteToDWord.LE_A1)), 5095 (v2i64 (VEXTSB2D $A))>; 5096} // HasVSX, HasP9Altivec, IsLittleEndian 5097 5098// Big endian 64Bit VSX subtarget that supports additional direct moves from 5099// ISA3.0. 5100let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64] in { 5101def : Pat<(i64 (extractelt v2i64:$A, 1)), 5102 (i64 (MFVSRLD $A))>; 5103// Better way to build integer vectors if we have MTVSRDD. Big endian. 5104def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)), 5105 (v2i64 (MTVSRDD $rB, $rA))>; 5106def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 5107 (MTVSRDD 5108 (RLDIMI AnyExts.B, AnyExts.A, 32, 0), 5109 (RLDIMI AnyExts.D, AnyExts.C, 32, 0))>; 5110 5111def : Pat<(f128 (PPCbuild_fp128 i64:$rB, i64:$rA)), 5112 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>; 5113} // HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64 5114 5115// Little endian VSX subtarget that supports direct moves from ISA3.0. 5116let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] in { 5117def : Pat<(i64 (extractelt v2i64:$A, 0)), 5118 (i64 (MFVSRLD $A))>; 5119// Better way to build integer vectors if we have MTVSRDD. Little endian. 5120def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)), 5121 (v2i64 (MTVSRDD $rB, $rA))>; 5122def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 5123 (MTVSRDD 5124 (RLDIMI AnyExts.C, AnyExts.D, 32, 0), 5125 (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>; 5126 5127def : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)), 5128 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>; 5129} // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian 5130} // AddedComplexity = 400 5131 5132//---------------------------- Instruction aliases ---------------------------// 5133def : InstAlias<"xvmovdp $XT, $XB", 5134 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 5135def : InstAlias<"xvmovsp $XT, $XB", 5136 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 5137 5138// Certain versions of the AIX assembler may missassemble these mnemonics. 5139let Predicates = [ModernAs] in { 5140 def : InstAlias<"xxspltd $XT, $XB, 0", 5141 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>; 5142 def : InstAlias<"xxspltd $XT, $XB, 1", 5143 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>; 5144 def : InstAlias<"xxspltd $XT, $XB, 0", 5145 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>; 5146 def : InstAlias<"xxspltd $XT, $XB, 1", 5147 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>; 5148} 5149 5150def : InstAlias<"xxmrghd $XT, $XA, $XB", 5151 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>; 5152def : InstAlias<"xxmrgld $XT, $XA, $XB", 5153 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>; 5154def : InstAlias<"xxswapd $XT, $XB", 5155 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>; 5156def : InstAlias<"xxswapd $XT, $XB", 5157 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>; 5158def : InstAlias<"mfvrd $rA, $XT", 5159 (MFVRD g8rc:$rA, vrrc:$XT), 0>; 5160def : InstAlias<"mffprd $rA, $src", 5161 (MFVSRD g8rc:$rA, f8rc:$src)>; 5162def : InstAlias<"mtvrd $XT, $rA", 5163 (MTVRD vrrc:$XT, g8rc:$rA), 0>; 5164def : InstAlias<"mtfprd $dst, $rA", 5165 (MTVSRD f8rc:$dst, g8rc:$rA)>; 5166def : InstAlias<"mfvrwz $rA, $XT", 5167 (MFVRWZ gprc:$rA, vrrc:$XT), 0>; 5168def : InstAlias<"mffprwz $rA, $src", 5169 (MFVSRWZ gprc:$rA, f8rc:$src)>; 5170def : InstAlias<"mtvrwa $XT, $rA", 5171 (MTVRWA vrrc:$XT, gprc:$rA), 0>; 5172def : InstAlias<"mtfprwa $dst, $rA", 5173 (MTVSRWA f8rc:$dst, gprc:$rA)>; 5174def : InstAlias<"mtvrwz $XT, $rA", 5175 (MTVRWZ vrrc:$XT, gprc:$rA), 0>; 5176def : InstAlias<"mtfprwz $dst, $rA", 5177 (MTVSRWZ f8rc:$dst, gprc:$rA)>; 5178