1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8// 9//===----------------------------------------------------------------------===// 10// 11// This file describes the instructions introduced for the Power10 CPU. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Naming convention for future instruction formats 17// 18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+ 19// 20// Where: 21// <INSTR_FORM> - name of instruction format as per the ISA 22// (X-Form, VX-Form, etc.) 23// <OP_TYPE> - operand type 24// * FRT/RT/VT/XT/BT - target register 25// (FPR, GPR, VR, VSR, CR-bit respectively) 26// In some situations, the 'T' is replaced by 27// 'D' when describing the target register. 28// * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.) 29// * IMM - immediate (where signedness matters, 30// this is SI/UI for signed/unsigned) 31// * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp) 32// * R - PC-Relative bit 33// (denotes that the address is computed pc-relative) 34// * VRM - Masked Registers 35// * AT - target accumulator 36// * N - the Nth bit in a VSR 37// * Additional 1-bit operands may be required for certain 38// instruction formats such as: MC, P, MP 39// * X / Y / P - mask values. In the instruction encoding, this is 40// represented as XMSK, YMSK and PMSK. 41// * MEM - indicates if the instruction format requires any memory 42// accesses. This does not have <OP_LENGTH> attached to it. 43// <OP_LENGTH> - the length of each operand in bits. 44// For operands that are 1 bit, the '1' is omitted from the name. 45// 46// Example: 8RR_XX4Form_IMM8_XTAB6 47// 8RR_XX4Form is the instruction format. 48// The operand is an 8-bit immediate (IMM), the destination (XT) 49// and sources (XA, XB) that are all 6-bits. The destination and 50// source registers are combined if they are of the same length. 51// Moreover, the order of operands reflects the order of operands 52// in the encoding. 53 54//-------------------------- Predicate definitions ---------------------------// 55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; 56 57 58//===----------------------------------------------------------------------===// 59// PowerPC ISA 3.1 specific type constraints. 60// 61 62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>, 63 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3> 64]>; 65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [ 66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>, 67 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32> 68]>; 69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ 70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> 71]>; 72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ 73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2> 74]>; 75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ 76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2> 77]>; 78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ 79 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> 80]>; 81 82//===----------------------------------------------------------------------===// 83// ISA 3.1 specific PPCISD nodes. 84// 85 86def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>; 87def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>; 88def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>; 89def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx, 90 []>; 91def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx, 92 []>; 93def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>; 94 95//===----------------------------------------------------------------------===// 96 97// PC Relative flag (for instructions that use the address of the prefix for 98// address computations). 99class isPCRel { bit PCRel = 1; } 100 101// PowerPC specific type constraints. 102def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [ 103 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 104]>; 105 106// PPC Specific DAG Nodes. 107def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, 108 [SDNPHasChain, SDNPMayLoad]>; 109 110// Top-level class for prefixed instructions. 111class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr, 112 InstrItinClass itin> : Instruction { 113 field bits<64> Inst; 114 field bits<64> SoftFail = 0; 115 bit PCRel = 0; // Default value, set by isPCRel. 116 let Size = 8; 117 118 let Namespace = "PPC"; 119 let OutOperandList = OOL; 120 let InOperandList = IOL; 121 let AsmString = asmstr; 122 let Itinerary = itin; 123 let Inst{0-5} = pref; 124 let Inst{32-37} = opcode; 125 126 bits<1> PPC970_First = 0; 127 bits<1> PPC970_Single = 0; 128 bits<1> PPC970_Cracked = 0; 129 bits<3> PPC970_Unit = 0; 130 131 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 132 /// these must be reflected there! See comments there for what these are. 133 let TSFlags{0} = PPC970_First; 134 let TSFlags{1} = PPC970_Single; 135 let TSFlags{2} = PPC970_Cracked; 136 let TSFlags{5-3} = PPC970_Unit; 137 138 bits<1> Prefixed = 1; // This is a prefixed instruction. 139 let TSFlags{7} = Prefixed; 140 141 // For cases where multiple instruction definitions really represent the 142 // same underlying instruction but with one definition for 64-bit arguments 143 // and one for 32-bit arguments, this bit breaks the degeneracy between 144 // the two forms and allows TableGen to generate mapping tables. 145 bit Interpretation64Bit = 0; 146 147 // Fields used for relation models. 148 string BaseName = ""; 149} 150 151// VX-Form: [ PO VT R VB RC XO ] 152class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr, 153 InstrItinClass itin, list<dag> pattern> 154 : I<4, OOL, IOL, asmstr, itin> { 155 bits<5> VT; 156 bits<5> VB; 157 bit RC = 0; 158 159 let Pattern = pattern; 160 161 let Inst{6-10} = VT; 162 let Inst{11-15} = R; 163 let Inst{16-20} = VB; 164 let Inst{21} = RC; 165 let Inst{22-31} = xo; 166} 167 168// Multiclass definition to account for record and non-record form 169// instructions of VXRForm. 170multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL, 171 string asmbase, string asmstr, 172 InstrItinClass itin, list<dag> pattern> { 173 let BaseName = asmbase in { 174 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL, 175 !strconcat(asmbase, !strconcat(" ", asmstr)), 176 itin, pattern>, RecFormRel; 177 let Defs = [CR6] in 178 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL, 179 !strconcat(asmbase, !strconcat(". ", asmstr)), 180 itin, []>, isRecordForm, RecFormRel; 181 } 182} 183 184class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 185 InstrItinClass itin, list<dag> pattern> 186 : PI<1, opcode, OOL, IOL, asmstr, itin> { 187 bits<5> FRS; 188 bits<39> D_RA; 189 190 let Pattern = pattern; 191 192 // The prefix. 193 let Inst{6-7} = 2; 194 let Inst{8-10} = 0; 195 let Inst{11} = PCRel; 196 let Inst{12-13} = 0; 197 let Inst{14-31} = D_RA{33-16}; // d0 198 199 // The instruction. 200 let Inst{38-42} = FRS{4-0}; 201 let Inst{43-47} = D_RA{38-34}; // RA 202 let Inst{48-63} = D_RA{15-0}; // d1 203} 204 205class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 206 InstrItinClass itin, list<dag> pattern> 207 : PI<1, opcode, OOL, IOL, asmstr, itin> { 208 bits<5> RT; 209 bits<5> RA; 210 bits<34> SI; 211 212 let Pattern = pattern; 213 214 // The prefix. 215 let Inst{6-7} = 2; 216 let Inst{8-10} = 0; 217 let Inst{11} = PCRel; 218 let Inst{12-13} = 0; 219 let Inst{14-31} = SI{33-16}; 220 221 // The instruction. 222 let Inst{38-42} = RT; 223 let Inst{43-47} = RA; 224 let Inst{48-63} = SI{15-0}; 225} 226 227class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 228 InstrItinClass itin, list<dag> pattern> 229 : PI<1, opcode, OOL, IOL, asmstr, itin> { 230 bits<5> RT; 231 bits<34> SI; 232 233 let Pattern = pattern; 234 235 // The prefix. 236 let Inst{6-7} = 2; 237 let Inst{8-10} = 0; 238 let Inst{11} = 0; 239 let Inst{12-13} = 0; 240 let Inst{14-31} = SI{33-16}; 241 242 // The instruction. 243 let Inst{38-42} = RT; 244 let Inst{43-47} = 0; 245 let Inst{48-63} = SI{15-0}; 246} 247 248multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 249 dag PCRel_IOL, string asmstr, 250 InstrItinClass itin> { 251 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 252 !strconcat(asmstr, ", 0"), itin, []>; 253 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 254 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 255} 256 257class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : PI<1, opcode, OOL, IOL, asmstr, itin> { 260 bits<5> RT; 261 bits<39> D_RA; 262 263 let Pattern = pattern; 264 265 // The prefix. 266 let Inst{6-10} = 0; 267 let Inst{11} = PCRel; 268 let Inst{12-13} = 0; 269 let Inst{14-31} = D_RA{33-16}; // d0 270 271 // The instruction. 272 let Inst{38-42} = RT{4-0}; 273 let Inst{43-47} = D_RA{38-34}; // RA 274 let Inst{48-63} = D_RA{15-0}; // d1 275} 276 277// 8LS:D-Form: [ 1 0 0 // R // d0 278// PO TX T RA d1 ] 279class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL, 280 string asmstr, InstrItinClass itin, 281 list<dag> pattern> 282 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { 283 bits<6> XT; 284 bits<39> D_RA; 285 286 let Pattern = pattern; 287 288 // The prefix. 289 let Inst{6-7} = 0; 290 let Inst{8} = 0; 291 let Inst{9-10} = 0; // reserved 292 let Inst{11} = PCRel; 293 let Inst{12-13} = 0; // reserved 294 let Inst{14-31} = D_RA{33-16}; // d0 295 296 // The instruction. 297 let Inst{37} = XT{5}; 298 let Inst{38-42} = XT{4-0}; 299 let Inst{43-47} = D_RA{38-34}; // RA 300 let Inst{48-63} = D_RA{15-0}; // d1 301} 302 303// X-Form: [PO T IMM VRB XO TX] 304class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 305 string asmstr, InstrItinClass itin, list<dag> pattern> 306 : I<opcode, OOL, IOL, asmstr, itin> { 307 bits<6> XT; 308 bits<5> VRB; 309 bits<5> IMM; 310 311 let Pattern = pattern; 312 let Inst{6-10} = XT{4-0}; 313 let Inst{11-15} = IMM; 314 let Inst{16-20} = VRB; 315 let Inst{21-30} = xo; 316 let Inst{31} = XT{5}; 317} 318 319class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo, 320 dag OOL, dag IOL, string asmstr, 321 InstrItinClass itin, list<dag> pattern> 322 : PI<1, opcode, OOL, IOL, asmstr, itin> { 323 bits<6> XT; 324 bits<6> XA; 325 bits<6> XB; 326 bits<6> XC; 327 bits<8> IMM; 328 329 let Pattern = pattern; 330 331 // The prefix. 332 let Inst{6-7} = 1; 333 let Inst{8} = 0; 334 let Inst{9-11} = 0; 335 let Inst{12-13} = 0; 336 let Inst{14-23} = 0; 337 let Inst{24-31} = IMM; 338 339 // The instruction. 340 let Inst{38-42} = XT{4-0}; 341 let Inst{43-47} = XA{4-0}; 342 let Inst{48-52} = XB{4-0}; 343 let Inst{53-57} = XC{4-0}; 344 let Inst{58-59} = xo; 345 let Inst{60} = XC{5}; 346 let Inst{61} = XA{5}; 347 let Inst{62} = XB{5}; 348 let Inst{63} = XT{5}; 349} 350 351class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 352 InstrItinClass itin, list<dag> pattern> 353 : I<4, OOL, IOL, asmstr, itin> { 354 bits<5> RD; 355 bits<5> VB; 356 bits<3> N; 357 358 let Pattern = pattern; 359 360 let Inst{6-10} = RD; 361 let Inst{11-12} = 0; 362 let Inst{13-15} = N; 363 let Inst{16-20} = VB; 364 let Inst{21-31} = xo; 365} 366 367 368// VX-Form: [PO VRT RA VRB XO]. 369// Destructive (insert) forms are suffixed with _ins. 370class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> 371 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB), 372 !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>, 373 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 374 375// VX-Form: [PO VRT RA RB XO]. 376// Destructive (insert) forms are suffixed with _ins. 377class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> 378 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB), 379 !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>, 380 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 381 382// VX-Form: [ PO BF // VRA VRB XO ] 383class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 384 InstrItinClass itin, list<dag> pattern> 385 : I<4, OOL, IOL, asmstr, itin> { 386 bits<3> BF; 387 bits<5> VA; 388 bits<5> VB; 389 390 let Pattern = pattern; 391 392 let Inst{6-8} = BF; 393 let Inst{9-10} = 0; 394 let Inst{11-15} = VA; 395 let Inst{16-20} = VB; 396 let Inst{21-31} = xo; 397} 398 399// VN-Form: [PO VRT VRA VRB PS SD XO] 400// SD is "Shift Direction" 401class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, 402 InstrItinClass itin, list<dag> pattern> 403 : I<4, OOL, IOL, asmstr, itin> { 404 bits<5> VRT; 405 bits<5> VRA; 406 bits<5> VRB; 407 bits<3> SD; 408 409 let Pattern = pattern; 410 411 let Inst{6-10} = VRT; 412 let Inst{11-15} = VRA; 413 let Inst{16-20} = VRB; 414 let Inst{21-22} = ps; 415 let Inst{23-25} = SD; 416 let Inst{26-31} = xo; 417} 418 419class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 420 string asmstr, InstrItinClass itin, list<dag> pattern> 421 : I<4, OOL, IOL, asmstr, itin> { 422 bits<5> RD; 423 bits<5> VB; 424 bit MP; 425 426 let Pattern = pattern; 427 428 let Inst{6-10} = RD; 429 let Inst{11-14} = eo; 430 let Inst{15} = MP; 431 let Inst{16-20} = VB; 432 let Inst{21-31} = xo; 433} 434 435// 8RR:D-Form: [ 1 1 0 // // imm0 436// PO T XO TX imm1 ]. 437class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 438 string asmstr, InstrItinClass itin, 439 list<dag> pattern> 440 : PI<1, opcode, OOL, IOL, asmstr, itin> { 441 bits<6> XT; 442 bits<32> IMM32; 443 444 let Pattern = pattern; 445 446 // The prefix. 447 let Inst{6-7} = 1; 448 let Inst{8-11} = 0; 449 let Inst{12-13} = 0; // reserved 450 let Inst{14-15} = 0; // reserved 451 let Inst{16-31} = IMM32{31-16}; 452 453 // The instruction. 454 let Inst{38-42} = XT{4-0}; 455 let Inst{43-46} = xo; 456 let Inst{47} = XT{5}; 457 let Inst{48-63} = IMM32{15-0}; 458} 459 460// 8RR:D-Form: [ 1 1 0 // // imm0 461// PO T XO IX TX imm1 ]. 462class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 463 string asmstr, InstrItinClass itin, 464 list<dag> pattern> 465 : PI<1, opcode, OOL, IOL, asmstr, itin> { 466 bits<6> XT; 467 bit IX; 468 bits<32> IMM32; 469 470 let Pattern = pattern; 471 472 // The prefix. 473 let Inst{6-7} = 1; 474 let Inst{8-11} = 0; 475 let Inst{12-13} = 0; // reserved 476 let Inst{14-15} = 0; // reserved 477 let Inst{16-31} = IMM32{31-16}; 478 479 // The instruction. 480 let Inst{38-42} = XT{4-0}; 481 let Inst{43-45} = xo; 482 let Inst{46} = IX; 483 let Inst{47} = XT{5}; 484 let Inst{48-63} = IMM32{15-0}; 485} 486 487class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 488 string asmstr, InstrItinClass itin, list<dag> pattern> 489 : PI<1, opcode, OOL, IOL, asmstr, itin> { 490 bits<6> XT; 491 bits<6> XA; 492 bits<6> XB; 493 bits<6> XC; 494 495 let Pattern = pattern; 496 497 // The prefix. 498 let Inst{6-7} = 1; 499 let Inst{8-11} = 0; 500 let Inst{12-13} = 0; 501 let Inst{14-31} = 0; 502 503 // The instruction. 504 let Inst{38-42} = XT{4-0}; 505 let Inst{43-47} = XA{4-0}; 506 let Inst{48-52} = XB{4-0}; 507 let Inst{53-57} = XC{4-0}; 508 let Inst{58-59} = xo; 509 let Inst{60} = XC{5}; 510 let Inst{61} = XA{5}; 511 let Inst{62} = XB{5}; 512 let Inst{63} = XT{5}; 513} 514 515class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 516 string asmstr, InstrItinClass itin, 517 list<dag> pattern> 518 : PI<1, opcode, OOL, IOL, asmstr, itin> { 519 bits<6> XT; 520 bits<6> XA; 521 bits<6> XB; 522 bits<6> XC; 523 bits<3> IMM; 524 525 let Pattern = pattern; 526 527 // The prefix. 528 let Inst{6-7} = 1; 529 let Inst{8-11} = 0; 530 let Inst{12-13} = 0; 531 let Inst{14-28} = 0; 532 let Inst{29-31} = IMM; 533 534 // The instruction. 535 let Inst{38-42} = XT{4-0}; 536 let Inst{43-47} = XA{4-0}; 537 let Inst{48-52} = XB{4-0}; 538 let Inst{53-57} = XC{4-0}; 539 let Inst{58-59} = xo; 540 let Inst{60} = XC{5}; 541 let Inst{61} = XA{5}; 542 let Inst{62} = XB{5}; 543 let Inst{63} = XT{5}; 544} 545 546// [PO BF / XO2 B XO BX /] 547class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, 548 dag IOL, string asmstr, InstrItinClass itin, 549 list<dag> pattern> 550 : I<opcode, OOL, IOL, asmstr, itin> { 551 bits<3> BF; 552 bits<6> XB; 553 554 let Pattern = pattern; 555 556 let Inst{6-8} = BF; 557 let Inst{9-10} = 0; 558 let Inst{11-15} = xo2; 559 let Inst{16-20} = XB{4-0}; 560 let Inst{21-29} = xo; 561 let Inst{30} = XB{5}; 562 let Inst{31} = 0; 563} 564 565// X-Form: [ PO RT BI /// XO / ] 566class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 567 string asmstr, InstrItinClass itin, list<dag> pattern> 568 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 569 let B = 0; 570} 571 572multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 573 dag PCRel_IOL, string asmstr, 574 InstrItinClass itin> { 575 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 576 !strconcat(asmstr, ", 0"), itin, []>; 577 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 578 !strconcat(asmstr, ", 1"), itin, []>, 579 isPCRel; 580} 581 582multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 583 dag PCRel_IOL, string asmstr, 584 InstrItinClass itin> { 585 def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 586 !strconcat(asmstr, ", 0"), itin, []>; 587 def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 588 !strconcat(asmstr, ", 1"), itin, []>, 589 isPCRel; 590} 591 592multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL, 593 dag PCRel_IOL, string asmstr, 594 InstrItinClass itin> { 595 def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, 596 !strconcat(asmstr, ", 0"), itin, []>; 597 def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL, 598 !strconcat(asmstr, ", 1"), itin, []>, 599 isPCRel; 600} 601 602def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; 603def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; 604def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; 605def RCCp { 606 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); 607 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); 608} 609 610let Predicates = [PrefixInstrs] in { 611 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 612 defm PADDI8 : 613 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI), 614 (ins immZero:$RA, s34imm_pcrel:$SI), 615 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 616 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 617 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 618 (ins s34imm:$SI), 619 "pli $RT, $SI", IIC_IntSimple, []>; 620 } 621 } 622 defm PADDI : 623 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI), 624 (ins immZero:$RA, s34imm_pcrel:$SI), 625 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 626 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 627 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 628 (ins s34imm:$SI), 629 "pli $RT, $SI", IIC_IntSimple, []>; 630 } 631 632 let mayLoad = 1, mayStore = 0 in { 633 defm PLXV : 634 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XT), (ins memri34:$D_RA), 635 (ins memri34_pcrel:$D_RA), 636 "plxv $XT, $D_RA", IIC_LdStLFD>; 637 defm PLFS : 638 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA), 639 (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA", 640 IIC_LdStLFD>; 641 defm PLFD : 642 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA), 643 (ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA", 644 IIC_LdStLFD>; 645 defm PLXSSP : 646 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA), 647 (ins memri34_pcrel:$D_RA), 648 "plxssp $VRT, $D_RA", IIC_LdStLFD>; 649 defm PLXSD : 650 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA), 651 (ins memri34_pcrel:$D_RA), 652 "plxsd $VRT, $D_RA", IIC_LdStLFD>; 653 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 654 defm PLBZ8 : 655 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA), 656 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", 657 IIC_LdStLFD>; 658 defm PLHZ8 : 659 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA), 660 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", 661 IIC_LdStLFD>; 662 defm PLHA8 : 663 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA), 664 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", 665 IIC_LdStLFD>; 666 defm PLWA8 : 667 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RT), (ins memri34:$D_RA), 668 (ins memri34_pcrel:$D_RA), 669 "plwa $RT, $D_RA", IIC_LdStLFD>; 670 defm PLWZ8 : 671 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA), 672 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", 673 IIC_LdStLFD>; 674 } 675 defm PLBZ : 676 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA), 677 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", 678 IIC_LdStLFD>; 679 defm PLHZ : 680 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA), 681 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", 682 IIC_LdStLFD>; 683 defm PLHA : 684 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA), 685 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", 686 IIC_LdStLFD>; 687 defm PLWZ : 688 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA), 689 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", 690 IIC_LdStLFD>; 691 defm PLWA : 692 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RT), (ins memri34:$D_RA), 693 (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", 694 IIC_LdStLFD>; 695 defm PLD : 696 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RT), (ins memri34:$D_RA), 697 (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA", 698 IIC_LdStLFD>; 699 } 700 701 let mayStore = 1, mayLoad = 0 in { 702 defm PSTXV : 703 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA), 704 (ins vsrc:$XS, memri34_pcrel:$D_RA), 705 "pstxv $XS, $D_RA", IIC_LdStLFD>; 706 defm PSTFS : 707 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA), 708 (ins f4rc:$FRS, memri34_pcrel:$D_RA), 709 "pstfs $FRS, $D_RA", IIC_LdStLFD>; 710 defm PSTFD : 711 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA), 712 (ins f8rc:$FRS, memri34_pcrel:$D_RA), 713 "pstfd $FRS, $D_RA", IIC_LdStLFD>; 714 defm PSTXSSP : 715 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA), 716 (ins vfrc:$VRS, memri34_pcrel:$D_RA), 717 "pstxssp $VRS, $D_RA", IIC_LdStLFD>; 718 defm PSTXSD : 719 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA), 720 (ins vfrc:$VRS, memri34_pcrel:$D_RA), 721 "pstxsd $VRS, $D_RA", IIC_LdStLFD>; 722 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 723 defm PSTB8 : 724 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA), 725 (ins g8rc:$RS, memri34_pcrel:$D_RA), 726 "pstb $RS, $D_RA", IIC_LdStLFD>; 727 defm PSTH8 : 728 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA), 729 (ins g8rc:$RS, memri34_pcrel:$D_RA), 730 "psth $RS, $D_RA", IIC_LdStLFD>; 731 defm PSTW8 : 732 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA), 733 (ins g8rc:$RS, memri34_pcrel:$D_RA), 734 "pstw $RS, $D_RA", IIC_LdStLFD>; 735 } 736 defm PSTB : 737 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA), 738 (ins gprc:$RS, memri34_pcrel:$D_RA), 739 "pstb $RS, $D_RA", IIC_LdStLFD>; 740 defm PSTH : 741 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA), 742 (ins gprc:$RS, memri34_pcrel:$D_RA), 743 "psth $RS, $D_RA", IIC_LdStLFD>; 744 defm PSTW : 745 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA), 746 (ins gprc:$RS, memri34_pcrel:$D_RA), 747 "pstw $RS, $D_RA", IIC_LdStLFD>; 748 defm PSTD : 749 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA), 750 (ins g8rc:$RS, memri34_pcrel:$D_RA), 751 "pstd $RS, $D_RA", IIC_LdStLFD>; 752 } 753} 754 755class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 756 string asmstr, InstrItinClass itin, list<dag> pattern> 757 : I<opcode, OOL, IOL, asmstr, itin> { 758 bits<5> XTp; 759 bits<17> DQ_RA; 760 let Pattern = pattern; 761 762 let Inst{6-9} = XTp{3-0}; 763 let Inst{10} = XTp{4}; 764 let Inst{11-15} = DQ_RA{16-12}; // Register # 765 let Inst{16-27} = DQ_RA{11-0}; // Displacement. 766 let Inst{28-31} = xo; 767} 768 769class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 770 string asmstr, InstrItinClass itin, list<dag> pattern> 771 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { 772 bits<5> XTp; 773 bits<5> A; 774 bits<5> B; 775 776 let Pattern = pattern; 777 let Inst{6-9} = XTp{3-0}; 778 let Inst{10} = XTp{4}; 779 let Inst{11-15} = A; 780 let Inst{16-20} = B; 781 let Inst{21-30} = xo; 782 let Inst{31} = 0; 783} 784 785class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 786 InstrItinClass itin, list<dag> pattern> 787 : PI<1, opcode, OOL, IOL, asmstr, itin> { 788 bits<5> XTp; 789 bits<39> D_RA; 790 791 let Pattern = pattern; 792 793 // The prefix. 794 let Inst{6-10} = 0; 795 let Inst{11} = PCRel; 796 let Inst{12-13} = 0; 797 let Inst{14-31} = D_RA{33-16}; // Imm18 798 799 // The instruction. 800 let Inst{38-41} = XTp{3-0}; 801 let Inst{42} = XTp{4}; 802 let Inst{43-47} = D_RA{38-34}; // Register # 803 let Inst{48-63} = D_RA{15-0}; // D 804} 805 806multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL, 807 dag IOL, dag PCRel_IOL, 808 string asmstr, InstrItinClass itin> { 809 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, 810 !strconcat(asmstr, ", 0"), itin, []>; 811 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL, 812 !strconcat(asmstr, ", 1"), itin, []>, 813 isPCRel; 814} 815 816 817 818// [PO AS XO2 XO] 819class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 820 string asmstr, InstrItinClass itin, list<dag> pattern> 821 : I<opcode, OOL, IOL, asmstr, itin> { 822 bits<3> AT; 823 824 let Pattern = pattern; 825 826 let Inst{6-8} = AT; 827 let Inst{9-10} = 0; 828 let Inst{11-15} = xo2; 829 let Inst{16-20} = 0; 830 let Inst{21-30} = xo; 831 let Inst{31} = 0; 832} 833 834// X-Form: [ PO T EO UIM XO TX ] 835class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL, 836 string asmstr, InstrItinClass itin, list<dag> pattern> 837 : I<opcode, OOL, IOL, asmstr, itin> { 838 bits<6> XT; 839 bits<5> UIM; 840 841 let Pattern = pattern; 842 843 let Inst{6-10} = XT{4-0}; 844 let Inst{11-15} = eo; 845 let Inst{16-20} = UIM; 846 let Inst{21-30} = xo; 847 let Inst{31} = XT{5}; 848} 849 850class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 851 string asmstr, InstrItinClass itin, 852 list<dag> pattern> 853 : I<opcode, OOL, IOL, asmstr, itin> { 854 bits<3> AT; 855 bits<6> XA; 856 bits<6> XB; 857 858 let Pattern = pattern; 859 860 let Inst{6-8} = AT; 861 let Inst{9-10} = 0; 862 let Inst{11-15} = XA{4-0}; 863 let Inst{16-20} = XB{4-0}; 864 let Inst{21-28} = xo; 865 let Inst{29} = XA{5}; 866 let Inst{30} = XB{5}; 867 let Inst{31} = 0; 868} 869 870class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 871 string asmstr, InstrItinClass itin, 872 list<dag> pattern> 873 : PI<1, opcode, OOL, IOL, asmstr, itin> { 874 bits<3> AT; 875 bits<6> XA; 876 bits<6> XB; 877 bits<4> XMSK; 878 bits<4> YMSK; 879 bits<2> PMSK; 880 881 let Pattern = pattern; 882 883 // The prefix. 884 let Inst{6-7} = 3; 885 let Inst{8-11} = 9; 886 let Inst{12-15} = 0; 887 let Inst{16-17} = PMSK; 888 let Inst{18-23} = 0; 889 let Inst{24-27} = XMSK; 890 let Inst{28-31} = YMSK; 891 892 // The instruction. 893 let Inst{38-40} = AT; 894 let Inst{41-42} = 0; 895 let Inst{43-47} = XA{4-0}; 896 let Inst{48-52} = XB{4-0}; 897 let Inst{53-60} = xo; 898 let Inst{61} = XA{5}; 899 let Inst{62} = XB{5}; 900 let Inst{63} = 0; 901} 902 903class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 904 string asmstr, InstrItinClass itin, 905 list<dag> pattern> 906 : PI<1, opcode, OOL, IOL, asmstr, itin> { 907 bits<3> AT; 908 bits<6> XA; 909 bits<6> XB; 910 bits<4> XMSK; 911 bits<4> YMSK; 912 913 let Pattern = pattern; 914 915 // The prefix. 916 let Inst{6-7} = 3; 917 let Inst{8-11} = 9; 918 let Inst{12-23} = 0; 919 let Inst{24-27} = XMSK; 920 let Inst{28-31} = YMSK; 921 922 // The instruction. 923 let Inst{38-40} = AT; 924 let Inst{41-42} = 0; 925 let Inst{43-47} = XA{4-0}; 926 let Inst{48-52} = XB{4-0}; 927 let Inst{53-60} = xo; 928 let Inst{61} = XA{5}; 929 let Inst{62} = XB{5}; 930 let Inst{63} = 0; 931} 932 933class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 934 string asmstr, InstrItinClass itin, 935 list<dag> pattern> 936 : PI<1, opcode, OOL, IOL, asmstr, itin> { 937 bits<3> AT; 938 bits<6> XA; 939 bits<6> XB; 940 bits<4> XMSK; 941 bits<2> YMSK; 942 943 let Pattern = pattern; 944 945 // The prefix. 946 let Inst{6-7} = 3; 947 let Inst{8-11} = 9; 948 let Inst{12-23} = 0; 949 let Inst{24-27} = XMSK; 950 let Inst{28-29} = YMSK; 951 let Inst{30-31} = 0; 952 953 // The instruction. 954 let Inst{38-40} = AT; 955 let Inst{41-42} = 0; 956 let Inst{43-47} = XA{4-0}; 957 let Inst{48-52} = XB{4-0}; 958 let Inst{53-60} = xo; 959 let Inst{61} = XA{5}; 960 let Inst{62} = XB{5}; 961 let Inst{63} = 0; 962} 963 964class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 965 string asmstr, InstrItinClass itin, 966 list<dag> pattern> 967 : PI<1, opcode, OOL, IOL, asmstr, itin> { 968 bits<3> AT; 969 bits<6> XA; 970 bits<6> XB; 971 bits<4> XMSK; 972 bits<4> YMSK; 973 bits<8> PMSK; 974 975 let Pattern = pattern; 976 977 // The prefix. 978 let Inst{6-7} = 3; 979 let Inst{8-11} = 9; 980 let Inst{12-15} = 0; 981 let Inst{16-23} = PMSK; 982 let Inst{24-27} = XMSK; 983 let Inst{28-31} = YMSK; 984 985 // The instruction. 986 let Inst{38-40} = AT; 987 let Inst{41-42} = 0; 988 let Inst{43-47} = XA{4-0}; 989 let Inst{48-52} = XB{4-0}; 990 let Inst{53-60} = xo; 991 let Inst{61} = XA{5}; 992 let Inst{62} = XB{5}; 993 let Inst{63} = 0; 994} 995 996class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 997 string asmstr, InstrItinClass itin, 998 list<dag> pattern> 999 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1000 bits<3> AT; 1001 bits<6> XA; 1002 bits<6> XB; 1003 bits<4> XMSK; 1004 bits<4> YMSK; 1005 bits<4> PMSK; 1006 1007 let Pattern = pattern; 1008 1009 // The prefix. 1010 let Inst{6-7} = 3; 1011 let Inst{8-11} = 9; 1012 let Inst{12-15} = 0; 1013 let Inst{16-19} = PMSK; 1014 let Inst{20-23} = 0; 1015 let Inst{24-27} = XMSK; 1016 let Inst{28-31} = YMSK; 1017 1018 // The instruction. 1019 let Inst{38-40} = AT; 1020 let Inst{41-42} = 0; 1021 let Inst{43-47} = XA{4-0}; 1022 let Inst{48-52} = XB{4-0}; 1023 let Inst{53-60} = xo; 1024 let Inst{61} = XA{5}; 1025 let Inst{62} = XB{5}; 1026 let Inst{63} = 0; 1027} 1028 1029 1030 1031def Concats { 1032 dag VecsToVecPair0 = 1033 (v256i1 (INSERT_SUBREG 1034 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1035 $vs1, sub_vsx0)); 1036 dag VecsToVecPair1 = 1037 (v256i1 (INSERT_SUBREG 1038 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1039 $vs3, sub_vsx0)); 1040} 1041 1042let Predicates = [PairedVectorMemops] in { 1043 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)), 1044 Concats.VecsToVecPair0>; 1045 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), 1046 Concats.VecsToVecPair0>; 1047 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)), 1048 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; 1049 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), 1050 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; 1051} 1052 1053let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in { 1054 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), 1055 (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA", 1056 IIC_LdStLFD, []>; 1057 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src), 1058 "lxvpx $XTp, $src", IIC_LdStLFD, 1059 []>; 1060} 1061 1062let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in { 1063 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, 1064 memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA", 1065 IIC_LdStLFD, []>; 1066 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst), 1067 "stxvpx $XTp, $dst", IIC_LdStLFD, 1068 []>; 1069} 1070 1071let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1072 defm PLXVP : 1073 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA), 1074 (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA", 1075 IIC_LdStLFD>; 1076} 1077 1078let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1079 defm PSTXVP : 1080 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, memri34:$D_RA), 1081 (ins vsrprc:$XTp, memri34_pcrel:$D_RA), 1082 "pstxvp $XTp, $D_RA", IIC_LdStLFD>; 1083} 1084 1085let Predicates = [PairedVectorMemops] in { 1086 // Intrinsics for Paired Vector Loads. 1087 def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>; 1088 def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>; 1089 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1090 def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>; 1091 } 1092 // Intrinsics for Paired Vector Stores. 1093 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst), 1094 (STXVP $XSp, memrix16:$dst)>; 1095 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst), 1096 (STXVPX $XSp, XForm:$dst)>; 1097 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1098 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst), 1099 (PSTXVP $XSp, memri34:$dst)>; 1100 } 1101} 1102 1103let Predicates = [PCRelativeMemops] in { 1104 // Load i32 1105 def : Pat<(i32 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1106 (PLBZpc $ga, 0)>; 1107 def : Pat<(i32 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1108 (PLBZpc $ga, 0)>; 1109 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1110 (PLBZpc $ga, 0)>; 1111 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1112 (PLBZpc $ga, 0)>; 1113 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1114 (PLHApc $ga, 0)>; 1115 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1116 (PLHZpc $ga, 0)>; 1117 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1118 (PLHZpc $ga, 0)>; 1119 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>; 1120 1121 // Store i32 1122 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1123 (PSTBpc $RS, $ga, 0)>; 1124 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1125 (PSTHpc $RS, $ga, 0)>; 1126 def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1127 (PSTWpc $RS, $ga, 0)>; 1128 1129 // Load i64 1130 def : Pat<(i64 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1131 (PLBZ8pc $ga, 0)>; 1132 def : Pat<(i64 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1133 (PLBZ8pc $ga, 0)>; 1134 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1135 (PLBZ8pc $ga, 0)>; 1136 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1137 (PLBZ8pc $ga, 0)>; 1138 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1139 (PLHA8pc $ga, 0)>; 1140 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1141 (PLHZ8pc $ga, 0)>; 1142 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1143 (PLHZ8pc $ga, 0)>; 1144 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1145 (PLWZ8pc $ga, 0)>; 1146 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1147 (PLWA8pc $ga, 0)>; 1148 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1149 (PLWZ8pc $ga, 0)>; 1150 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>; 1151 1152 // Store i64 1153 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1154 (PSTB8pc $RS, $ga, 0)>; 1155 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1156 (PSTH8pc $RS, $ga, 0)>; 1157 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1158 (PSTW8pc $RS, $ga, 0)>; 1159 def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1160 (PSTDpc $RS, $ga, 0)>; 1161 1162 // Load f32 1163 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>; 1164 1165 // Store f32 1166 def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1167 (PSTFSpc $FRS, $ga, 0)>; 1168 1169 // Load f64 1170 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))), 1171 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>; 1172 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>; 1173 1174 // Store f64 1175 def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1176 (PSTFDpc $FRS, $ga, 0)>; 1177 1178 // Load f128 1179 def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))), 1180 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>; 1181 1182 // Store f128 1183 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1184 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>; 1185 1186 // Load v4i32 1187 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1188 1189 // Store v4i32 1190 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1191 (PSTXVpc $XS, $ga, 0)>; 1192 1193 // Load v2i64 1194 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1195 1196 // Store v2i64 1197 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1198 (PSTXVpc $XS, $ga, 0)>; 1199 1200 // Load v4f32 1201 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1202 1203 // Store v4f32 1204 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1205 (PSTXVpc $XS, $ga, 0)>; 1206 1207 // Load v2f64 1208 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1209 1210 // Store v2f64 1211 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1212 (PSTXVpc $XS, $ga, 0)>; 1213 1214 // Atomic Load 1215 def : Pat<(atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga)), 1216 (PLBZpc $ga, 0)>; 1217 def : Pat<(atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga)), 1218 (PLHZpc $ga, 0)>; 1219 def : Pat<(atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga)), 1220 (PLWZpc $ga, 0)>; 1221 def : Pat<(atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga)), 1222 (PLDpc $ga, 0)>; 1223 1224 // Atomic Store 1225 def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS), 1226 (PSTBpc $RS, $ga, 0)>; 1227 def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS), 1228 (PSTHpc $RS, $ga, 0)>; 1229 def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS), 1230 (PSTWpc $RS, $ga, 0)>; 1231 def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1232 (PSTB8pc $RS, $ga, 0)>; 1233 def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1234 (PSTH8pc $RS, $ga, 0)>; 1235 def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1236 (PSTW8pc $RS, $ga, 0)>; 1237 def : Pat<(atomic_store_64 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1238 (PSTDpc $RS, $ga, 0)>; 1239 1240 // Special Cases For PPCstore_scal_int_from_vsr 1241 def : Pat<(PPCstore_scal_int_from_vsr 1242 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), 1243 (PPCmatpcreladdr PCRelForm:$dst), 8), 1244 (PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>; 1245 def : Pat<(PPCstore_scal_int_from_vsr 1246 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), 1247 (PPCmatpcreladdr PCRelForm:$dst), 8), 1248 (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>; 1249 1250 def : Pat<(PPCstore_scal_int_from_vsr 1251 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), 1252 (PPCmatpcreladdr PCRelForm:$dst), 8), 1253 (PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>; 1254 def : Pat<(PPCstore_scal_int_from_vsr 1255 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), 1256 (PPCmatpcreladdr PCRelForm:$dst), 8), 1257 (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>; 1258 1259 def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), 1260 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; 1261 1262 // If the PPCmatpcreladdr node is not caught by any other pattern it should be 1263 // caught here and turned into a paddi instruction to materialize the address. 1264 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1265 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize 1266 // tls global address with paddi instruction. 1267 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1268 // PPCtlslocalexecmataddr node is used for TLS local exec models to 1269 // materialize tls global address with paddi instruction. 1270 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), 1271 (PADDI8 $in, $addr)>; 1272} 1273 1274let Predicates = [PrefixInstrs] in { 1275 def XXPERMX : 1276 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1277 vsrc:$XC, u3imm:$UIM), 1278 "xxpermx $XT, $XA, $XB, $XC, $UIM", 1279 IIC_VecPerm, []>; 1280 def XXBLENDVB : 1281 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1282 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", 1283 IIC_VecGeneral, []>; 1284 def XXBLENDVH : 1285 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1286 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", 1287 IIC_VecGeneral, []>; 1288 def XXBLENDVW : 1289 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1290 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC", 1291 IIC_VecGeneral, []>; 1292 def XXBLENDVD : 1293 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1294 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC", 1295 IIC_VecGeneral, []>; 1296} 1297 1298// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt 1299// to spill part of the instruction when the values are similar. 1300let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in { 1301 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT), 1302 (ins i32imm:$IMM32), 1303 "xxspltiw $XT, $IMM32", IIC_VecGeneral, 1304 []>; 1305 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT), 1306 (ins i32imm:$IMM32), 1307 "xxspltidp $XT, $IMM32", IIC_VecGeneral, 1308 [(set v2f64:$XT, 1309 (PPCxxspltidp i32:$IMM32))]>; 1310 def XXSPLTI32DX : 1311 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT), 1312 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32), 1313 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, 1314 [(set v2i64:$XT, 1315 (PPCxxsplti32dx v2i64:$XTi, i32:$IX, 1316 i32:$IMM32))]>, 1317 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1318} 1319 1320let Predicates = [IsISA3_1] in { 1321 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI), 1322 "setbc $RT, $BI", IIC_IntCompare, []>; 1323 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI), 1324 "setbcr $RT, $BI", IIC_IntCompare, []>; 1325 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI), 1326 "setnbc $RT, $BI", IIC_IntCompare, []>; 1327 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI), 1328 "setnbcr $RT, $BI", IIC_IntCompare, []>; 1329 1330 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1331 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI), 1332 "setbc $RT, $BI", IIC_IntCompare, []>; 1333 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI), 1334 "setbcr $RT, $BI", IIC_IntCompare, []>; 1335 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI), 1336 "setnbc $RT, $BI", IIC_IntCompare, []>; 1337 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI), 1338 "setnbcr $RT, $BI", IIC_IntCompare, []>; 1339 } 1340 1341 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), 1342 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), 1343 "vsldbi $VRT, $VRA, $VRB, $SH", 1344 IIC_VecGeneral, 1345 [(set v16i8:$VRT, 1346 (int_ppc_altivec_vsldbi v16i8:$VRA, 1347 v16i8:$VRB, 1348 timm:$SH))]>; 1349 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), 1350 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), 1351 "vsrdbi $VRT, $VRA, $VRB, $SH", 1352 IIC_VecGeneral, 1353 [(set v16i8:$VRT, 1354 (int_ppc_altivec_vsrdbi v16i8:$VRA, 1355 v16i8:$VRB, 1356 timm:$SH))]>; 1357 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB), 1358 "vstribr", "$vT, $vB", IIC_VecGeneral, 1359 [(set v16i8:$vT, 1360 (int_ppc_altivec_vstribr v16i8:$vB))]>; 1361 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB), 1362 "vstribl", "$vT, $vB", IIC_VecGeneral, 1363 [(set v16i8:$vT, 1364 (int_ppc_altivec_vstribl v16i8:$vB))]>; 1365 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB), 1366 "vstrihr", "$vT, $vB", IIC_VecGeneral, 1367 [(set v8i16:$vT, 1368 (int_ppc_altivec_vstrihr v8i16:$vB))]>; 1369 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB), 1370 "vstrihl", "$vT, $vB", IIC_VecGeneral, 1371 [(set v8i16:$vT, 1372 (int_ppc_altivec_vstrihl v8i16:$vB))]>; 1373 def VINSW : 1374 VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB), 1375 "vinsw $vD, $rB, $UIM", IIC_VecGeneral, 1376 [(set v4i32:$vD, 1377 (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>, 1378 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1379 def VINSD : 1380 VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB), 1381 "vinsd $vD, $rB, $UIM", IIC_VecGeneral, 1382 [(set v2i64:$vD, 1383 (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>, 1384 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1385 def VINSBVLX : 1386 VXForm_VTB5_RA5_ins<15, "vinsbvlx", 1387 [(set v16i8:$vD, 1388 (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA, 1389 v16i8:$vB))]>; 1390 def VINSBVRX : 1391 VXForm_VTB5_RA5_ins<271, "vinsbvrx", 1392 [(set v16i8:$vD, 1393 (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA, 1394 v16i8:$vB))]>; 1395 def VINSHVLX : 1396 VXForm_VTB5_RA5_ins<79, "vinshvlx", 1397 [(set v8i16:$vD, 1398 (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA, 1399 v8i16:$vB))]>; 1400 def VINSHVRX : 1401 VXForm_VTB5_RA5_ins<335, "vinshvrx", 1402 [(set v8i16:$vD, 1403 (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA, 1404 v8i16:$vB))]>; 1405 def VINSWVLX : 1406 VXForm_VTB5_RA5_ins<143, "vinswvlx", 1407 [(set v4i32:$vD, 1408 (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA, 1409 v4i32:$vB))]>; 1410 def VINSWVRX : 1411 VXForm_VTB5_RA5_ins<399, "vinswvrx", 1412 [(set v4i32:$vD, 1413 (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA, 1414 v4i32:$vB))]>; 1415 def VINSBLX : 1416 VXForm_VRT5_RAB5_ins<527, "vinsblx", 1417 [(set v16i8:$vD, 1418 (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA, 1419 i32:$rB))]>; 1420 def VINSBRX : 1421 VXForm_VRT5_RAB5_ins<783, "vinsbrx", 1422 [(set v16i8:$vD, 1423 (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA, 1424 i32:$rB))]>; 1425 def VINSHLX : 1426 VXForm_VRT5_RAB5_ins<591, "vinshlx", 1427 [(set v8i16:$vD, 1428 (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA, 1429 i32:$rB))]>; 1430 def VINSHRX : 1431 VXForm_VRT5_RAB5_ins<847, "vinshrx", 1432 [(set v8i16:$vD, 1433 (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA, 1434 i32:$rB))]>; 1435 def VINSWLX : 1436 VXForm_VRT5_RAB5_ins<655, "vinswlx", 1437 [(set v4i32:$vD, 1438 (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA, 1439 i32:$rB))]>; 1440 def VINSWRX : 1441 VXForm_VRT5_RAB5_ins<911, "vinswrx", 1442 [(set v4i32:$vD, 1443 (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA, 1444 i32:$rB))]>; 1445 def VINSDLX : 1446 VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), 1447 "vinsdlx $vD, $rA, $rB", IIC_VecGeneral, 1448 [(set v2i64:$vD, 1449 (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>, 1450 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1451 def VINSDRX : 1452 VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), 1453 "vinsdrx $vD, $rA, $rB", IIC_VecGeneral, 1454 [(set v2i64:$vD, 1455 (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>, 1456 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1457 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB), 1458 "vextractbm $rD, $vB", IIC_VecGeneral, 1459 [(set i32:$rD, 1460 (int_ppc_altivec_vextractbm v16i8:$vB))]>; 1461 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB), 1462 "vextracthm $rD, $vB", IIC_VecGeneral, 1463 [(set i32:$rD, 1464 (int_ppc_altivec_vextracthm v8i16:$vB))]>; 1465 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB), 1466 "vextractwm $rD, $vB", IIC_VecGeneral, 1467 [(set i32:$rD, 1468 (int_ppc_altivec_vextractwm v4i32:$vB))]>; 1469 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB), 1470 "vextractdm $rD, $vB", IIC_VecGeneral, 1471 [(set i32:$rD, 1472 (int_ppc_altivec_vextractdm v2i64:$vB))]>; 1473 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB), 1474 "vextractqm $rD, $vB", IIC_VecGeneral, 1475 [(set i32:$rD, 1476 (int_ppc_altivec_vextractqm v1i128:$vB))]>; 1477 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), 1478 "vexpandbm $vD, $vB", IIC_VecGeneral, 1479 [(set v16i8:$vD, (int_ppc_altivec_vexpandbm 1480 v16i8:$vB))]>; 1481 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), 1482 "vexpandhm $vD, $vB", IIC_VecGeneral, 1483 [(set v8i16:$vD, (int_ppc_altivec_vexpandhm 1484 v8i16:$vB))]>; 1485 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), 1486 "vexpandwm $vD, $vB", IIC_VecGeneral, 1487 [(set v4i32:$vD, (int_ppc_altivec_vexpandwm 1488 v4i32:$vB))]>; 1489 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), 1490 "vexpanddm $vD, $vB", IIC_VecGeneral, 1491 [(set v2i64:$vD, (int_ppc_altivec_vexpanddm 1492 v2i64:$vB))]>; 1493 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), 1494 "vexpandqm $vD, $vB", IIC_VecGeneral, 1495 [(set v1i128:$vD, (int_ppc_altivec_vexpandqm 1496 v1i128:$vB))]>; 1497 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), 1498 "mtvsrbm $vD, $rB", IIC_VecGeneral, 1499 [(set v16i8:$vD, 1500 (int_ppc_altivec_mtvsrbm i64:$rB))]>; 1501 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB), 1502 "mtvsrhm $vD, $rB", IIC_VecGeneral, 1503 [(set v8i16:$vD, 1504 (int_ppc_altivec_mtvsrhm i64:$rB))]>; 1505 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB), 1506 "mtvsrwm $vD, $rB", IIC_VecGeneral, 1507 [(set v4i32:$vD, 1508 (int_ppc_altivec_mtvsrwm i64:$rB))]>; 1509 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB), 1510 "mtvsrdm $vD, $rB", IIC_VecGeneral, 1511 [(set v2i64:$vD, 1512 (int_ppc_altivec_mtvsrdm i64:$rB))]>; 1513 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB), 1514 "mtvsrqm $vD, $rB", IIC_VecGeneral, 1515 [(set v1i128:$vD, 1516 (int_ppc_altivec_mtvsrqm i64:$rB))]>; 1517 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D), 1518 "mtvsrbmi $vD, $D", IIC_VecGeneral, 1519 [(set v16i8:$vD, 1520 (int_ppc_altivec_mtvsrbm imm:$D))]>; 1521 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD), 1522 (ins vrrc:$vB, u1imm:$MP), 1523 "vcntmbb $rD, $vB, $MP", IIC_VecGeneral, 1524 [(set i64:$rD, (int_ppc_altivec_vcntmbb 1525 v16i8:$vB, timm:$MP))]>; 1526 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD), 1527 (ins vrrc:$vB, u1imm:$MP), 1528 "vcntmbh $rD, $vB, $MP", IIC_VecGeneral, 1529 [(set i64:$rD, (int_ppc_altivec_vcntmbh 1530 v8i16:$vB, timm:$MP))]>; 1531 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD), 1532 (ins vrrc:$vB, u1imm:$MP), 1533 "vcntmbw $rD, $vB, $MP", IIC_VecGeneral, 1534 [(set i64:$rD, (int_ppc_altivec_vcntmbw 1535 v4i32:$vB, timm:$MP))]>; 1536 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD), 1537 (ins vrrc:$vB, u1imm:$MP), 1538 "vcntmbd $rD, $vB, $MP", IIC_VecGeneral, 1539 [(set i64:$rD, (int_ppc_altivec_vcntmbd 1540 v2i64:$vB, timm:$MP))]>; 1541 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD), 1542 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1543 "vextdubvlx $vD, $vA, $vB, $rC", 1544 IIC_VecGeneral, 1545 [(set v2i64:$vD, 1546 (int_ppc_altivec_vextdubvlx v16i8:$vA, 1547 v16i8:$vB, 1548 i32:$rC))]>; 1549 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD), 1550 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1551 "vextdubvrx $vD, $vA, $vB, $rC", 1552 IIC_VecGeneral, 1553 [(set v2i64:$vD, 1554 (int_ppc_altivec_vextdubvrx v16i8:$vA, 1555 v16i8:$vB, 1556 i32:$rC))]>; 1557 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD), 1558 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1559 "vextduhvlx $vD, $vA, $vB, $rC", 1560 IIC_VecGeneral, 1561 [(set v2i64:$vD, 1562 (int_ppc_altivec_vextduhvlx v8i16:$vA, 1563 v8i16:$vB, 1564 i32:$rC))]>; 1565 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD), 1566 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1567 "vextduhvrx $vD, $vA, $vB, $rC", 1568 IIC_VecGeneral, 1569 [(set v2i64:$vD, 1570 (int_ppc_altivec_vextduhvrx v8i16:$vA, 1571 v8i16:$vB, 1572 i32:$rC))]>; 1573 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD), 1574 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1575 "vextduwvlx $vD, $vA, $vB, $rC", 1576 IIC_VecGeneral, 1577 [(set v2i64:$vD, 1578 (int_ppc_altivec_vextduwvlx v4i32:$vA, 1579 v4i32:$vB, 1580 i32:$rC))]>; 1581 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD), 1582 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1583 "vextduwvrx $vD, $vA, $vB, $rC", 1584 IIC_VecGeneral, 1585 [(set v2i64:$vD, 1586 (int_ppc_altivec_vextduwvrx v4i32:$vA, 1587 v4i32:$vB, 1588 i32:$rC))]>; 1589 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD), 1590 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1591 "vextddvlx $vD, $vA, $vB, $rC", 1592 IIC_VecGeneral, 1593 [(set v2i64:$vD, 1594 (int_ppc_altivec_vextddvlx v2i64:$vA, 1595 v2i64:$vB, 1596 i32:$rC))]>; 1597 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD), 1598 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1599 "vextddvrx $vD, $vA, $vB, $rC", 1600 IIC_VecGeneral, 1601 [(set v2i64:$vD, 1602 (int_ppc_altivec_vextddvrx v2i64:$vA, 1603 v2i64:$vB, 1604 i32:$rC))]>; 1605 def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1606 "vpdepd $vD, $vA, $vB", IIC_VecGeneral, 1607 [(set v2i64:$vD, 1608 (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; 1609 def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1610 "vpextd $vD, $vA, $vB", IIC_VecGeneral, 1611 [(set v2i64:$vD, 1612 (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; 1613 def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1614 "pdepd $rA, $rS, $rB", IIC_IntGeneral, 1615 [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>; 1616 def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1617 "pextd $rA, $rS, $rB", IIC_IntGeneral, 1618 [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>; 1619 def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1620 "vcfuged $vD, $vA, $vB", IIC_VecGeneral, 1621 [(set v2i64:$vD, 1622 (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>; 1623 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N), 1624 "vgnb $rD, $vB, $N", IIC_VecGeneral, 1625 [(set i64:$rD, 1626 (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>; 1627 def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1628 "cfuged $rA, $rS, $rB", IIC_IntGeneral, 1629 [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>; 1630 def XXEVAL : 1631 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1632 vsrc:$XC, u8imm:$IMM), 1633 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, 1634 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, 1635 v2i64:$XB, v2i64:$XC, timm:$IMM))]>; 1636 def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1637 "vclzdm $vD, $vA, $vB", IIC_VecGeneral, 1638 [(set v2i64:$vD, 1639 (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>; 1640 def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1641 "vctzdm $vD, $vA, $vB", IIC_VecGeneral, 1642 [(set v2i64:$vD, 1643 (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>; 1644 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1645 "cntlzdm $rA, $rS, $rB", IIC_IntGeneral, 1646 [(set i64:$rA, 1647 (int_ppc_cntlzdm i64:$rS, i64:$rB))]>; 1648 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1649 "cnttzdm $rA, $rS, $rB", IIC_IntGeneral, 1650 [(set i64:$rA, 1651 (int_ppc_cnttzdm i64:$rS, i64:$rB))]>; 1652 def XXGENPCVBM : 1653 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1654 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1655 def XXGENPCVHM : 1656 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1657 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1658 def XXGENPCVWM : 1659 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1660 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1661 def XXGENPCVDM : 1662 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1663 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1664 def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), 1665 "vclrlb $vD, $vA, $rB", IIC_VecGeneral, 1666 [(set v16i8:$vD, 1667 (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; 1668 def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), 1669 "vclrrb $vD, $vA, $rB", IIC_VecGeneral, 1670 [(set v16i8:$vD, 1671 (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; 1672 def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1673 "vmulld $vD, $vA, $vB", IIC_VecGeneral, 1674 [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>; 1675 def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1676 "vmulhsw $vD, $vA, $vB", IIC_VecGeneral, 1677 [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>; 1678 def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1679 "vmulhuw $vD, $vA, $vB", IIC_VecGeneral, 1680 [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>; 1681 def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1682 "vmulhsd $vD, $vA, $vB", IIC_VecGeneral, 1683 [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>; 1684 def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1685 "vmulhud $vD, $vA, $vB", IIC_VecGeneral, 1686 [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>; 1687 def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1688 "vmodsw $vD, $vA, $vB", IIC_VecGeneral, 1689 [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>; 1690 def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1691 "vmoduw $vD, $vA, $vB", IIC_VecGeneral, 1692 [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>; 1693 def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1694 "vmodsd $vD, $vA, $vB", IIC_VecGeneral, 1695 [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>; 1696 def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1697 "vmodud $vD, $vA, $vB", IIC_VecGeneral, 1698 [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>; 1699 def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1700 "vdivsw $vD, $vA, $vB", IIC_VecGeneral, 1701 [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>; 1702 def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1703 "vdivuw $vD, $vA, $vB", IIC_VecGeneral, 1704 [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>; 1705 def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1706 "vdivsd $vD, $vA, $vB", IIC_VecGeneral, 1707 [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>; 1708 def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1709 "vdivud $vD, $vA, $vB", IIC_VecGeneral, 1710 [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>; 1711 def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1712 "vdivesw $vD, $vA, $vB", IIC_VecGeneral, 1713 [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA, 1714 v4i32:$vB))]>; 1715 def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1716 "vdiveuw $vD, $vA, $vB", IIC_VecGeneral, 1717 [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA, 1718 v4i32:$vB))]>; 1719 def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1720 "vdivesd $vD, $vA, $vB", IIC_VecGeneral, 1721 [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA, 1722 v2i64:$vB))]>; 1723 def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1724 "vdiveud $vD, $vA, $vB", IIC_VecGeneral, 1725 [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA, 1726 v2i64:$vB))]>; 1727 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), 1728 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; 1729 1730 // The XFormMemOp flag for the following 8 instructions is set on 1731 // the instruction format. 1732 let mayLoad = 1, mayStore = 0 in { 1733 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; 1734 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; 1735 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; 1736 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; 1737 } 1738 1739 let mayLoad = 0, mayStore = 1 in { 1740 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; 1741 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; 1742 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; 1743 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; 1744 } 1745 1746 def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1747 "vmulesd $vD, $vA, $vB", IIC_VecGeneral, 1748 [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA, 1749 v2i64:$vB))]>; 1750 def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1751 "vmuleud $vD, $vA, $vB", IIC_VecGeneral, 1752 [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA, 1753 v2i64:$vB))]>; 1754 def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1755 "vmulosd $vD, $vA, $vB", IIC_VecGeneral, 1756 [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA, 1757 v2i64:$vB))]>; 1758 def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1759 "vmuloud $vD, $vA, $vB", IIC_VecGeneral, 1760 [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA, 1761 v2i64:$vB))]>; 1762 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1763 "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral, 1764 [(set v1i128:$vD, (int_ppc_altivec_vmsumcud 1765 v2i64:$vA, v2i64:$vB, v1i128:$vC))]>; 1766 def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1767 "vdivsq $vD, $vA, $vB", IIC_VecGeneral, 1768 [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>; 1769 def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1770 "vdivuq $vD, $vA, $vB", IIC_VecGeneral, 1771 [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>; 1772 def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1773 "vdivesq $vD, $vA, $vB", IIC_VecGeneral, 1774 [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA, 1775 v1i128:$vB))]>; 1776 def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1777 "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, 1778 [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA, 1779 v1i128:$vB))]>; 1780 def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>; 1781 def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>; 1782 def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>; 1783 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>; 1784 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>; 1785 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>; 1786 def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1787 "vmodsq $vD, $vA, $vB", IIC_VecGeneral, 1788 [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>; 1789 def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1790 "vmoduq $vD, $vA, $vB", IIC_VecGeneral, 1791 [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>; 1792 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB), 1793 "vextsd2q $vD, $vB", IIC_VecGeneral, 1794 [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>; 1795 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), 1796 "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>; 1797 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), 1798 "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>; 1799 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", 1800 [(set v1i128:$vD, 1801 (int_ppc_altivec_vrlqnm v1i128:$vA, 1802 v1i128:$vB))]>; 1803 def VRLQMI : VXForm_1<69, (outs vrrc:$vD), 1804 (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1805 "vrlqmi $vD, $vA, $vB", IIC_VecFP, 1806 [(set v1i128:$vD, 1807 (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB, 1808 v1i128:$vDi))]>, 1809 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1810 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; 1811 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; 1812 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; 1813 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; 1814 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; 1815 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; 1816 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; 1817 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; 1818 def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM), 1819 "lxvkq $XT, $UIM", IIC_VecGeneral, []>; 1820} 1821 1822let Predicates = [IsISA3_1, HasVSX] in { 1823 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; 1824 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; 1825 def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", 1826 [(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>; 1827 def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", 1828 [(set f128:$vT, (PPCxsminc f128:$vA, f128:$vB))]>; 1829} 1830 1831// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. 1832// This is analogous to the CRNotPat multiclass but specifically for Power10 1833// and newer subtargets since the extended forms use Set Boolean instructions. 1834// The first two anonymous patterns defined are actually a duplicate of those 1835// in CRNotPat, but it is preferable to define both multiclasses as complete 1836// ones rather than pulling that small common section out. 1837multiclass P10ReverseSetBool<dag pattern, dag result> { 1838 def : Pat<pattern, (crnot result)>; 1839 def : Pat<(not pattern), result>; 1840 1841 def : Pat<(i32 (zext pattern)), 1842 (SETBCR result)>; 1843 def : Pat<(i64 (zext pattern)), 1844 (SETBCR8 result)>; 1845 1846 def : Pat<(i32 (sext pattern)), 1847 (SETNBCR result)>; 1848 def : Pat<(i64 (sext pattern)), 1849 (SETNBCR8 result)>; 1850 1851 def : Pat<(i32 (anyext pattern)), 1852 (SETBCR result)>; 1853 def : Pat<(i64 (anyext pattern)), 1854 (SETBCR8 result)>; 1855} 1856 1857multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy, 1858 ImmLeaf SExtTy, I Cmpi, I Cmpli, 1859 I Cmp, I Cmpl> { 1860 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1861 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>; 1862 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1863 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>; 1864 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1865 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>; 1866 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1867 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>; 1868 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1869 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>; 1870 1871 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)), 1872 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>; 1873 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)), 1874 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>; 1875 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)), 1876 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>; 1877 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)), 1878 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>; 1879 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)), 1880 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>; 1881 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)), 1882 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>; 1883} 1884 1885multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> { 1886 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1887 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1888 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1889 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1890 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1891 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 1892 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1893 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 1894 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 1895 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 1896 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1897 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 1898 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 1899 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 1900} 1901 1902let Predicates = [IsISA3_1] in { 1903 def : Pat<(i32 (zext i1:$in)), 1904 (SETBC $in)>; 1905 def : Pat<(i64 (zext i1:$in)), 1906 (SETBC8 $in)>; 1907 def : Pat<(i32 (sext i1:$in)), 1908 (SETNBC $in)>; 1909 def : Pat<(i64 (sext i1:$in)), 1910 (SETNBC8 $in)>; 1911 def : Pat<(i32 (anyext i1:$in)), 1912 (SETBC $in)>; 1913 def : Pat<(i64 (anyext i1:$in)), 1914 (SETBC8 $in)>; 1915 1916 // Instantiation of the set boolean reverse patterns for 32-bit integers. 1917 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16, 1918 CMPWI, CMPLWI, CMPW, CMPLW>; 1919 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 1920 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 1921 (LO16 imm:$imm)), sub_eq)>; 1922 1923 // Instantiation of the set boolean reverse patterns for 64-bit integers. 1924 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16, 1925 CMPDI, CMPLDI, CMPD, CMPLD>; 1926 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 1927 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 1928 (LO16 imm:$imm)), sub_eq)>; 1929} 1930 1931// Instantiation of the set boolean reverse patterns for f32, f64, f128. 1932let Predicates = [IsISA3_1, HasFPU] in { 1933 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>; 1934 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>; 1935 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>; 1936} 1937 1938//---------------------------- Anonymous Patterns ----------------------------// 1939let Predicates = [IsISA3_1] in { 1940 // Exploit the vector multiply high instructions using intrinsics. 1941 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), 1942 (v4i32 (VMULHSW $vA, $vB))>; 1943 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), 1944 (v4i32 (VMULHUW $vA, $vB))>; 1945 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), 1946 (v2i64 (VMULHSD $vA, $vB))>; 1947 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)), 1948 (v2i64 (VMULHUD $vA, $vB))>; 1949 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), 1950 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; 1951 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), 1952 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; 1953 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), 1954 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; 1955 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), 1956 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; 1957 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), 1958 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; 1959 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), 1960 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; 1961 1962 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)), 1963 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>; 1964 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)), 1965 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>; 1966 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)), 1967 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>; 1968 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)), 1969 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>; 1970 1971 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)), 1972 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>; 1973 1974 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)), 1975 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>; 1976} 1977 1978let Predicates = [IsISA3_1, HasVSX] in { 1979 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)), 1980 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>; 1981 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)), 1982 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>; 1983} 1984 1985let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in { 1986 // Store element 0 of a VSX register to memory 1987 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst), 1988 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>; 1989 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst), 1990 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>; 1991 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst), 1992 (STXVRWX $src, ForceXForm:$dst)>; 1993 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst), 1994 (STXVRWX $src, ForceXForm:$dst)>; 1995 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst), 1996 (STXVRDX $src, ForceXForm:$dst)>; 1997 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst), 1998 (STXVRDX $src, ForceXForm:$dst)>; 1999 // Load element 0 of a VSX register to memory 2000 def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))), 2001 (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>; 2002 def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))), 2003 (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>; 2004 } 2005 2006// FIXME: The swap is overkill when the shift amount is a constant. 2007// We should just fix the constant in the DAG. 2008let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { 2009 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)), 2010 (v1i128 (VSLQ v1i128:$VRA, 2011 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2012 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2013 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), 2014 (v1i128 (VSLQ v1i128:$VRA, 2015 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2016 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2017 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)), 2018 (v1i128 (VSRQ v1i128:$VRA, 2019 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2020 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2021 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)), 2022 (v1i128 (VSRQ v1i128:$VRA, 2023 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2024 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2025 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)), 2026 (v1i128 (VSRAQ v1i128:$VRA, 2027 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2028 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2029 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)), 2030 (v1i128 (VSRAQ v1i128:$VRA, 2031 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2032 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2033} 2034 2035class xxevalPattern <dag pattern, bits<8> imm> : 2036 Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} 2037 2038let AddedComplexity = 400, Predicates = [PrefixInstrs] in { 2039 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A, 2040 i32immNonAllOneNonZero:$A, 2041 i32immNonAllOneNonZero:$A, 2042 i32immNonAllOneNonZero:$A)), 2043 (v4i32 (XXSPLTIW imm:$A))>; 2044 def : Pat<(f32 nzFPImmAsi32:$A), 2045 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2046 VSFRC)>; 2047 def : Pat<(f64 nzFPImmAsi32:$A), 2048 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2049 VSFRC)>; 2050 2051// To replace constant pool with XXSPLTI32DX for scalars. 2052def : Pat<(f32 nzFPImmAsi64:$A), 2053 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0, 2054 (getFPAs64BitIntHi $A)), 2055 1, (getFPAs64BitIntLo $A)), 2056 VSSRC)>; 2057 2058def : Pat<(f64 nzFPImmAsi64:$A), 2059 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0, 2060 (getFPAs64BitIntHi $A)), 2061 1, (getFPAs64BitIntLo $A)), 2062 VSFRC)>; 2063 2064 // Anonymous patterns for XXEVAL 2065 // AND 2066 // and(A, B, C) 2067 def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; 2068 // and(A, xor(B, C)) 2069 def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; 2070 // and(A, or(B, C)) 2071 def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; 2072 // and(A, nor(B, C)) 2073 def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; 2074 // and(A, eqv(B, C)) 2075 def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; 2076 // and(A, nand(B, C)) 2077 def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; 2078 2079 // NAND 2080 // nand(A, B, C) 2081 def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 2082 !sub(255, 1)>; 2083 // nand(A, xor(B, C)) 2084 def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 2085 !sub(255, 6)>; 2086 // nand(A, or(B, C)) 2087 def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 2088 !sub(255, 7)>; 2089 // nand(A, nor(B, C)) 2090 def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 2091 !sub(255, 8)>; 2092 // nand(A, eqv(B, C)) 2093 def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 2094 !sub(255, 9)>; 2095 // nand(A, nand(B, C)) 2096 def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 2097 !sub(255, 14)>; 2098 2099 // Anonymous patterns to select prefixed VSX loads and stores. 2100 // Load / Store f128 2101 def : Pat<(f128 (load PDForm:$src)), 2102 (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>; 2103 def : Pat<(store f128:$XS, PDForm:$dst), 2104 (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>; 2105 2106 // Load / Store v4i32 2107 def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>; 2108 def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2109 2110 // Load / Store v2i64 2111 def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>; 2112 def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2113 2114 // Load / Store v4f32 2115 def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>; 2116 def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2117 2118 // Load / Store v2f64 2119 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>; 2120 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2121 2122 // Cases For PPCstore_scal_int_from_vsr 2123 def : Pat<(PPCstore_scal_int_from_vsr 2124 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), PDForm:$dst, 8), 2125 (PSTXSD (XSCVDPUXDS f64:$src), PDForm:$dst)>; 2126 def : Pat<(PPCstore_scal_int_from_vsr 2127 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), PDForm:$dst, 8), 2128 (PSTXSD (XSCVDPSXDS f64:$src), PDForm:$dst)>; 2129 def : Pat<(PPCstore_scal_int_from_vsr 2130 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), PDForm:$dst, 8), 2131 (PSTXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), 2132 PDForm:$dst)>; 2133 def : Pat<(PPCstore_scal_int_from_vsr 2134 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), PDForm:$dst, 8), 2135 (PSTXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), 2136 PDForm:$dst)>; 2137} 2138 2139let Predicates = [PrefixInstrs] in { 2140 def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>; 2141 def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>; 2142 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)), 2143 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC), 2144 (COPY_TO_REGCLASS $B, VSRC), 2145 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>; 2146 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)), 2147 (COPY_TO_REGCLASS 2148 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC), 2149 (COPY_TO_REGCLASS $B, VSRC), 2150 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2151 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)), 2152 (COPY_TO_REGCLASS 2153 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC), 2154 (COPY_TO_REGCLASS $B, VSRC), 2155 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2156 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C), 2157 (XXBLENDVW $A, $B, $C)>; 2158 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C), 2159 (XXBLENDVD $A, $B, $C)>; 2160 2161 // Anonymous patterns to select prefixed loads and stores. 2162 // Load i32 2163 def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2164 def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2165 def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2166 def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2167 def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2168 def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2169 def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>; 2170 def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>; 2171 2172 // Store i32 2173 def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>; 2174 def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>; 2175 def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>; 2176 2177 // Load i64 2178 def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2179 def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2180 def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2181 def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2182 def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2183 def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2184 def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>; 2185 def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2186 def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2187 def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>; 2188 def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>; 2189 2190 // Store i64 2191 def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>; 2192 def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>; 2193 def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>; 2194 def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>; 2195 2196 // Load / Store f32 2197 def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>; 2198 def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>; 2199 2200 // Load / Store f64 2201 def : Pat<(f64 (extloadf32 PDForm:$src)), 2202 (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>; 2203 def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>; 2204 def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; 2205 2206 // Atomic Load 2207 def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>; 2208 def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>; 2209 def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>; 2210 def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>; 2211 2212 // Atomic Store 2213 def : Pat<(atomic_store_8 PDForm:$dst, i32:$RS), (PSTB $RS, memri34:$dst)>; 2214 def : Pat<(atomic_store_16 PDForm:$dst, i32:$RS), (PSTH $RS, memri34:$dst)>; 2215 def : Pat<(atomic_store_32 PDForm:$dst, i32:$RS), (PSTW $RS, memri34:$dst)>; 2216 def : Pat<(atomic_store_64 PDForm:$dst, i64:$RS), (PSTD $RS, memri34:$dst)>; 2217 2218 // Prefixed fpext to v2f64 2219 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), 2220 (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; 2221} 2222 2223def InsertEltShift { 2224 dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32)); 2225 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30); 2226 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29); 2227 dag Left1 = (RLWINM $rB, 1, 0, 30); 2228 dag Left2 = (RLWINM $rB, 2, 0, 29); 2229 dag Left3 = (RLWINM8 $rB, 3, 0, 28); 2230} 2231 2232let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in { 2233 // Indexed vector insert element 2234 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2235 (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>; 2236 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2237 (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2238 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2239 (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2240 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2241 (VINSDRX $vDi, InsertEltShift.Left3, $rA)>; 2242 2243 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2244 (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2245 2246 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2247 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2248 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2249 (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2250 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2251 (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2252 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2253 (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2254 let AddedComplexity = 400 in { 2255 // Immediate vector insert element 2256 foreach Idx = [0, 1, 2, 3] in { 2257 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)), 2258 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>; 2259 } 2260 foreach i = [0, 1] in 2261 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))), 2262 (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>; 2263 } 2264} 2265 2266let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in { 2267 // Indexed vector insert element 2268 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)), 2269 (VINSBLX $vDi, $rB, $rA)>; 2270 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)), 2271 (VINSHLX $vDi, InsertEltShift.Left1, $rA)>; 2272 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)), 2273 (VINSWLX $vDi, InsertEltShift.Left2, $rA)>; 2274 2275 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i32:$rB)), 2276 (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>; 2277} 2278 2279let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in { 2280 // Indexed vector insert element 2281 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2282 (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>; 2283 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2284 (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2285 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2286 (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2287 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2288 (VINSDLX $vDi, InsertEltShift.Left3, $rA)>; 2289 2290 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2291 (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2292 2293 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2294 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2295 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2296 (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2297 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2298 (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2299 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2300 (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2301} 2302 2303let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in { 2304 // Immediate vector insert element 2305 foreach Ty = [i32, i64] in { 2306 foreach Idx = [0, 1, 2, 3] in { 2307 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))), 2308 (VINSW $vDi, !mul(Idx, 4), $rA)>; 2309 } 2310 } 2311 2312 foreach Idx = [0, 1] in 2313 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)), 2314 (VINSD $vDi, !mul(Idx, 8), $rA)>; 2315} 2316