xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrP10.td (revision da5432eda807c4b7232d030d5157d5b417ea4f52)
1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10//
11// This file describes the instructions introduced for the Power10 CPU.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Naming convention for future instruction formats
17//
18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+
19//
20// Where:
21// <INSTR_FORM> - name of instruction format as per the ISA
22//                (X-Form, VX-Form, etc.)
23// <OP_TYPE> - operand type
24//             * FRT/RT/VT/XT/BT - target register
25//                                 (FPR, GPR, VR, VSR, CR-bit respectively)
26//                                 In some situations, the 'T' is replaced by
27//                                 'D' when describing the target register.
28//             * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.)
29//             * IMM - immediate (where signedness matters,
30//                     this is SI/UI for signed/unsigned)
31//             * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp)
32//             * R - PC-Relative bit
33//                   (denotes that the address is computed pc-relative)
34//             * VRM - Masked Registers
35//             * AT - target accumulator
36//             * N - the Nth bit in a VSR
37//             * Additional 1-bit operands may be required for certain
38//               instruction formats such as: MC, P, MP
39//             * X / Y / P - mask values. In the instruction encoding, this is
40//                           represented as XMSK, YMSK and PMSK.
41//             * MEM - indicates if the instruction format requires any memory
42//                     accesses. This does not have <OP_LENGTH> attached to it.
43// <OP_LENGTH> - the length of each operand in bits.
44//               For operands that are 1 bit, the '1' is omitted from the name.
45//
46// Example: 8RR_XX4Form_IMM8_XTAB6
47//          8RR_XX4Form is the instruction format.
48//          The operand is an 8-bit immediate (IMM), the destination (XT)
49//          and sources (XA, XB) that are all 6-bits. The destination and
50//          source registers are combined if they are of the same length.
51//          Moreover, the order of operands reflects the order of operands
52//          in the encoding.
53
54//-------------------------- Predicate definitions ---------------------------//
55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
56
57
58//===----------------------------------------------------------------------===//
59// PowerPC ISA 3.1 specific type constraints.
60//
61
62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>,
63  SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3>
64]>;
65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [
66  SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
67                       SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>
68]>;
69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [
70  SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
71]>;
72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [
73  SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
74]>;
75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [
76  SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
77]>;
78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [
79  SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>
80]>;
81
82//===----------------------------------------------------------------------===//
83// ISA 3.1 specific PPCISD nodes.
84//
85
86def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>;
87def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>;
88def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>;
89def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx,
90                       []>;
91def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx,
92                        []>;
93def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>;
94
95//===----------------------------------------------------------------------===//
96
97// PC Relative flag (for instructions that use the address of the prefix for
98// address computations).
99class isPCRel { bit PCRel = 1; }
100
101// PowerPC specific type constraints.
102def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [
103  SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
104]>;
105
106// PPC Specific DAG Nodes.
107def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
108                       [SDNPHasChain, SDNPMayLoad]>;
109
110// Top-level class for prefixed instructions.
111class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
112         InstrItinClass itin> : Instruction {
113  field bits<64> Inst;
114  field bits<64> SoftFail = 0;
115  bit PCRel = 0; // Default value, set by isPCRel.
116  let Size = 8;
117
118  let Namespace = "PPC";
119  let OutOperandList = OOL;
120  let InOperandList = IOL;
121  let AsmString = asmstr;
122  let Itinerary = itin;
123  let Inst{0-5} = pref;
124  let Inst{32-37} = opcode;
125
126  bits<1> PPC970_First = 0;
127  bits<1> PPC970_Single = 0;
128  bits<1> PPC970_Cracked = 0;
129  bits<3> PPC970_Unit = 0;
130
131  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
132  /// these must be reflected there!  See comments there for what these are.
133  let TSFlags{0}   = PPC970_First;
134  let TSFlags{1}   = PPC970_Single;
135  let TSFlags{2}   = PPC970_Cracked;
136  let TSFlags{5-3} = PPC970_Unit;
137
138  bits<1> Prefixed = 1;  // This is a prefixed instruction.
139  let TSFlags{7}  = Prefixed;
140
141  // For cases where multiple instruction definitions really represent the
142  // same underlying instruction but with one definition for 64-bit arguments
143  // and one for 32-bit arguments, this bit breaks the degeneracy between
144  // the two forms and allows TableGen to generate mapping tables.
145  bit Interpretation64Bit = 0;
146
147  // Fields used for relation models.
148  string BaseName = "";
149}
150
151// VX-Form: [ PO VT R VB RC XO ]
152class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
153                      InstrItinClass itin, list<dag> pattern>
154  : I<4, OOL, IOL, asmstr, itin> {
155  bits<5> VT;
156  bits<5> VB;
157  bit RC = 0;
158
159  let Pattern = pattern;
160
161  let Inst{6-10} = VT;
162  let Inst{11-15} = R;
163  let Inst{16-20} = VB;
164  let Inst{21} = RC;
165  let Inst{22-31} = xo;
166}
167
168// Multiclass definition to account for record and non-record form
169// instructions of VXRForm.
170multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
171                            string asmbase, string asmstr,
172                            InstrItinClass itin, list<dag> pattern> {
173  let BaseName = asmbase in {
174    def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,
175                               !strconcat(asmbase, !strconcat(" ", asmstr)),
176                               itin, pattern>, RecFormRel;
177    let Defs = [CR6] in
178    def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
179                               !strconcat(asmbase, !strconcat(". ", asmstr)),
180                               itin, []>, isRecordForm, RecFormRel;
181  }
182}
183
184class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
185                                InstrItinClass itin, list<dag> pattern>
186  : PI<1, opcode, OOL, IOL, asmstr, itin> {
187  bits<5> FRS;
188  bits<39> D_RA;
189
190  let Pattern = pattern;
191
192  // The prefix.
193  let Inst{6-7} = 2;
194  let Inst{8-10} = 0;
195  let Inst{11} = PCRel;
196  let Inst{12-13} = 0;
197  let Inst{14-31} = D_RA{33-16}; // d0
198
199  // The instruction.
200  let Inst{38-42} = FRS{4-0};
201  let Inst{43-47} = D_RA{38-34}; // RA
202  let Inst{48-63} = D_RA{15-0}; // d1
203}
204
205class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
206                            InstrItinClass itin, list<dag> pattern>
207  : PI<1, opcode, OOL, IOL, asmstr, itin> {
208  bits<5> RT;
209  bits<5> RA;
210  bits<34> SI;
211
212  let Pattern = pattern;
213
214  // The prefix.
215  let Inst{6-7} = 2;
216  let Inst{8-10} = 0;
217  let Inst{11} = PCRel;
218  let Inst{12-13} = 0;
219  let Inst{14-31} = SI{33-16};
220
221  // The instruction.
222  let Inst{38-42} = RT;
223  let Inst{43-47} = RA;
224  let Inst{48-63} = SI{15-0};
225}
226
227class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228                         InstrItinClass itin, list<dag> pattern>
229  : PI<1, opcode, OOL, IOL, asmstr, itin> {
230  bits<5> RT;
231  bits<34> SI;
232
233  let Pattern = pattern;
234
235  // The prefix.
236  let Inst{6-7} = 2;
237  let Inst{8-10} = 0;
238  let Inst{11} = 0;
239  let Inst{12-13} = 0;
240  let Inst{14-31} = SI{33-16};
241
242  // The instruction.
243  let Inst{38-42} = RT;
244  let Inst{43-47} = 0;
245  let Inst{48-63} = SI{15-0};
246}
247
248multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
249                                   dag PCRel_IOL, string asmstr,
250                                   InstrItinClass itin> {
251  def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
252                                   !strconcat(asmstr, ", 0"), itin, []>;
253  def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
254                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
255}
256
257class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258                                InstrItinClass itin, list<dag> pattern>
259  : PI<1, opcode, OOL, IOL, asmstr, itin> {
260  bits<5> RT;
261  bits<39> D_RA;
262
263  let Pattern = pattern;
264
265  // The prefix.
266  let Inst{6-10} = 0;
267  let Inst{11} = PCRel;
268  let Inst{12-13} = 0;
269  let Inst{14-31} = D_RA{33-16}; // d0
270
271  // The instruction.
272  let Inst{38-42} = RT{4-0};
273  let Inst{43-47} = D_RA{38-34}; // RA
274  let Inst{48-63} = D_RA{15-0}; // d1
275}
276
277// 8LS:D-Form: [ 1 0 0 // R // d0
278//               PO TX T RA d1 ]
279class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
280                                   string asmstr, InstrItinClass itin,
281                                   list<dag> pattern>
282  : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
283  bits<6> XT;
284  bits<39> D_RA;
285
286  let Pattern = pattern;
287
288  // The prefix.
289  let Inst{6-7} = 0;
290  let Inst{8} = 0;
291  let Inst{9-10} = 0; // reserved
292  let Inst{11} = PCRel;
293  let Inst{12-13} = 0; // reserved
294  let Inst{14-31} = D_RA{33-16}; // d0
295
296  // The instruction.
297  let Inst{37} = XT{5};
298  let Inst{38-42} = XT{4-0};
299  let Inst{43-47} = D_RA{38-34}; // RA
300  let Inst{48-63} = D_RA{15-0}; // d1
301}
302
303// X-Form: [PO T IMM VRB XO TX]
304class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
305                         string asmstr, InstrItinClass itin, list<dag> pattern>
306  : I<opcode, OOL, IOL, asmstr, itin> {
307  bits<6> XT;
308  bits<5> VRB;
309  bits<5> IMM;
310
311  let Pattern = pattern;
312  let Inst{6-10} = XT{4-0};
313  let Inst{11-15} = IMM;
314  let Inst{16-20} = VRB;
315  let Inst{21-30} = xo;
316  let Inst{31} = XT{5};
317}
318
319class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,
320                             dag OOL, dag IOL, string asmstr,
321                             InstrItinClass itin, list<dag> pattern>
322  : PI<1, opcode, OOL, IOL, asmstr, itin> {
323    bits<6> XT;
324    bits<6> XA;
325    bits<6> XB;
326    bits<6> XC;
327    bits<8> IMM;
328
329    let Pattern = pattern;
330
331    // The prefix.
332    let Inst{6-7} = 1;
333    let Inst{8} = 0;
334    let Inst{9-11} = 0;
335    let Inst{12-13} = 0;
336    let Inst{14-23} = 0;
337    let Inst{24-31} = IMM;
338
339    // The instruction.
340    let Inst{38-42} = XT{4-0};
341    let Inst{43-47} = XA{4-0};
342    let Inst{48-52} = XB{4-0};
343    let Inst{53-57} = XC{4-0};
344    let Inst{58-59} = xo;
345    let Inst{60} = XC{5};
346    let Inst{61} = XA{5};
347    let Inst{62} = XB{5};
348    let Inst{63} = XT{5};
349}
350
351class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
352                        InstrItinClass itin, list<dag> pattern>
353  : I<4, OOL, IOL, asmstr, itin> {
354  bits<5> RD;
355  bits<5> VB;
356  bits<3> N;
357
358  let Pattern = pattern;
359
360  let Inst{6-10}  = RD;
361  let Inst{11-12} = 0;
362  let Inst{13-15} = N;
363  let Inst{16-20} = VB;
364  let Inst{21-31} = xo;
365}
366
367
368// VX-Form: [PO VRT RA VRB XO].
369// Destructive (insert) forms are suffixed with _ins.
370class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
371  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB),
372             !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
373             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
374
375// VX-Form: [PO VRT RA RB XO].
376// Destructive (insert) forms are suffixed with _ins.
377class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
378  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB),
379             !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
380             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
381
382// VX-Form: [ PO BF // VRA VRB XO ]
383class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
384                      InstrItinClass itin, list<dag> pattern>
385  : I<4, OOL, IOL, asmstr, itin> {
386  bits<3> BF;
387  bits<5> VA;
388  bits<5> VB;
389
390  let Pattern = pattern;
391
392  let Inst{6-8} = BF;
393  let Inst{9-10} = 0;
394  let Inst{11-15} = VA;
395  let Inst{16-20} = VB;
396  let Inst{21-31} = xo;
397}
398
399// VN-Form: [PO VRT VRA VRB PS SD XO]
400// SD is "Shift Direction"
401class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
402                       InstrItinClass itin, list<dag> pattern>
403    : I<4, OOL, IOL, asmstr, itin> {
404  bits<5> VRT;
405  bits<5> VRA;
406  bits<5> VRB;
407  bits<3> SD;
408
409  let Pattern = pattern;
410
411  let Inst{6-10}  = VRT;
412  let Inst{11-15} = VRA;
413  let Inst{16-20} = VRB;
414  let Inst{21-22} = ps;
415  let Inst{23-25} = SD;
416  let Inst{26-31} = xo;
417}
418
419class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
420                        string asmstr, InstrItinClass itin, list<dag> pattern>
421  : I<4, OOL, IOL, asmstr, itin> {
422  bits<5> RD;
423  bits<5> VB;
424  bit MP;
425
426  let Pattern = pattern;
427
428  let Inst{6-10}  = RD;
429  let Inst{11-14} = eo;
430  let Inst{15} = MP;
431  let Inst{16-20} = VB;
432  let Inst{21-31} = xo;
433}
434
435// 8RR:D-Form: [ 1 1 0 // // imm0
436//               PO T XO TX imm1 ].
437class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
438                          string asmstr, InstrItinClass itin,
439                          list<dag> pattern>
440  : PI<1, opcode, OOL, IOL, asmstr, itin> {
441  bits<6> XT;
442  bits<32> IMM32;
443
444  let Pattern = pattern;
445
446  // The prefix.
447  let Inst{6-7} = 1;
448  let Inst{8-11} = 0;
449  let Inst{12-13} = 0; // reserved
450  let Inst{14-15} = 0; // reserved
451  let Inst{16-31} = IMM32{31-16};
452
453  // The instruction.
454  let Inst{38-42} = XT{4-0};
455  let Inst{43-46} = xo;
456  let Inst{47} = XT{5};
457  let Inst{48-63} = IMM32{15-0};
458}
459
460// 8RR:D-Form: [ 1 1 0 // // imm0
461//               PO T XO IX TX imm1 ].
462class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
463                             string asmstr, InstrItinClass itin,
464                             list<dag> pattern>
465  : PI<1, opcode, OOL, IOL, asmstr, itin> {
466  bits<6> XT;
467  bit IX;
468  bits<32> IMM32;
469
470  let Pattern = pattern;
471
472  // The prefix.
473  let Inst{6-7} = 1;
474  let Inst{8-11} = 0;
475  let Inst{12-13} = 0; // reserved
476  let Inst{14-15} = 0; // reserved
477  let Inst{16-31} = IMM32{31-16};
478
479  // The instruction.
480  let Inst{38-42} = XT{4-0};
481  let Inst{43-45} = xo;
482  let Inst{46} = IX;
483  let Inst{47} = XT{5};
484  let Inst{48-63} = IMM32{15-0};
485}
486
487class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
488                         string asmstr, InstrItinClass itin, list<dag> pattern>
489  : PI<1, opcode, OOL, IOL, asmstr, itin> {
490  bits<6> XT;
491  bits<6> XA;
492  bits<6> XB;
493  bits<6> XC;
494
495  let Pattern = pattern;
496
497  // The prefix.
498  let Inst{6-7} = 1;
499  let Inst{8-11} = 0;
500  let Inst{12-13} = 0;
501  let Inst{14-31} = 0;
502
503  // The instruction.
504  let Inst{38-42} = XT{4-0};
505  let Inst{43-47} = XA{4-0};
506  let Inst{48-52} = XB{4-0};
507  let Inst{53-57} = XC{4-0};
508  let Inst{58-59} = xo;
509  let Inst{60} = XC{5};
510  let Inst{61} = XA{5};
511  let Inst{62} = XB{5};
512  let Inst{63} = XT{5};
513}
514
515class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
516                              string asmstr, InstrItinClass itin,
517                              list<dag> pattern>
518  : PI<1, opcode, OOL, IOL, asmstr, itin> {
519  bits<6> XT;
520  bits<6> XA;
521  bits<6> XB;
522  bits<6> XC;
523  bits<3> IMM;
524
525  let Pattern = pattern;
526
527  // The prefix.
528  let Inst{6-7} = 1;
529  let Inst{8-11} = 0;
530  let Inst{12-13} = 0;
531  let Inst{14-28} = 0;
532  let Inst{29-31} = IMM;
533
534  // The instruction.
535  let Inst{38-42} = XT{4-0};
536  let Inst{43-47} = XA{4-0};
537  let Inst{48-52} = XB{4-0};
538  let Inst{53-57} = XC{4-0};
539  let Inst{58-59} = xo;
540  let Inst{60} = XC{5};
541  let Inst{61} = XA{5};
542  let Inst{62} = XB{5};
543  let Inst{63} = XT{5};
544}
545
546// [PO BF / XO2 B XO BX /]
547class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
548                          dag IOL, string asmstr, InstrItinClass itin,
549                          list<dag> pattern>
550  : I<opcode, OOL, IOL, asmstr, itin> {
551  bits<3> BF;
552  bits<6> XB;
553
554  let Pattern = pattern;
555
556  let Inst{6-8}   = BF;
557  let Inst{9-10}  = 0;
558  let Inst{11-15} = xo2;
559  let Inst{16-20} = XB{4-0};
560  let Inst{21-29} = xo;
561  let Inst{30}    = XB{5};
562  let Inst{31}    = 0;
563}
564
565// X-Form: [ PO RT BI /// XO / ]
566class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
567                    string asmstr, InstrItinClass itin, list<dag> pattern>
568  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
569  let B = 0;
570}
571
572multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
573                                       dag PCRel_IOL, string asmstr,
574                                       InstrItinClass itin> {
575  def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
576                                       !strconcat(asmstr, ", 0"), itin, []>;
577  def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
578                                     !strconcat(asmstr, ", 1"), itin, []>,
579                                     isPCRel;
580}
581
582multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
583                                       dag PCRel_IOL, string asmstr,
584                                       InstrItinClass itin> {
585  def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
586                                       !strconcat(asmstr, ", 0"), itin, []>;
587  def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
588                                     !strconcat(asmstr, ", 1"), itin, []>,
589                                     isPCRel;
590}
591
592multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
593                                          dag PCRel_IOL, string asmstr,
594                                          InstrItinClass itin> {
595  def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL,
596                                          !strconcat(asmstr, ", 0"), itin, []>;
597  def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL,
598                                        !strconcat(asmstr, ", 1"), itin, []>,
599                                        isPCRel;
600}
601
602def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
603def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
604def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
605def RCCp {
606  dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
607  dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
608}
609
610let Predicates = [PrefixInstrs] in {
611  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
612    defm PADDI8 :
613      MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
614                              (ins immZero:$RA, s34imm_pcrel:$SI),
615                              "paddi $RT, $RA, $SI", IIC_LdStLFD>;
616    let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
617      def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
618                                    (ins s34imm:$SI),
619                                    "pli $RT, $SI", IIC_IntSimple, []>;
620    }
621  }
622  defm PADDI :
623    MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
624                            (ins immZero:$RA, s34imm_pcrel:$SI),
625                            "paddi $RT, $RA, $SI", IIC_LdStLFD>;
626  let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
627    def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
628                                 (ins s34imm:$SI),
629                                 "pli $RT, $SI", IIC_IntSimple, []>;
630  }
631
632  let mayLoad = 1, mayStore = 0 in {
633    defm PLXV :
634      8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
635                                     (ins memri34_pcrel:$D_RA),
636                                     "plxv $XT, $D_RA", IIC_LdStLFD>;
637    defm PLFS :
638      MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
639                                  (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
640                                  IIC_LdStLFD>;
641    defm PLFD :
642      MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
643                                  (ins  memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
644                                  IIC_LdStLFD>;
645    defm PLXSSP :
646      8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
647                                  (ins memri34_pcrel:$D_RA),
648                                  "plxssp $VRT, $D_RA", IIC_LdStLFD>;
649    defm PLXSD :
650      8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
651                                  (ins memri34_pcrel:$D_RA),
652                                  "plxsd $VRT, $D_RA", IIC_LdStLFD>;
653    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
654      defm PLBZ8 :
655        MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
656                                    (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
657                                    IIC_LdStLFD>;
658      defm PLHZ8 :
659        MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
660                                    (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
661                                    IIC_LdStLFD>;
662      defm PLHA8 :
663        MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
664                                    (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
665                                    IIC_LdStLFD>;
666      defm PLWA8 :
667        8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
668                                    (ins memri34_pcrel:$D_RA),
669                                    "plwa $RT, $D_RA", IIC_LdStLFD>;
670      defm PLWZ8 :
671        MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
672                                    (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
673                                    IIC_LdStLFD>;
674    }
675    defm PLBZ :
676      MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
677                                  (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
678                                  IIC_LdStLFD>;
679    defm PLHZ :
680      MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
681                                  (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
682                                  IIC_LdStLFD>;
683    defm PLHA :
684      MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
685                                  (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
686                                  IIC_LdStLFD>;
687    defm PLWZ :
688      MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
689                                  (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
690                                  IIC_LdStLFD>;
691    defm PLWA :
692      8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
693                                  (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
694                                  IIC_LdStLFD>;
695    defm PLD :
696      8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
697                                  (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
698                                  IIC_LdStLFD>;
699  }
700
701  let mayStore = 1, mayLoad = 0 in {
702    defm PSTXV :
703      8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
704                                     (ins vsrc:$XS, memri34_pcrel:$D_RA),
705                                     "pstxv $XS, $D_RA", IIC_LdStLFD>;
706    defm PSTFS :
707      MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
708                                  (ins f4rc:$FRS, memri34_pcrel:$D_RA),
709                                  "pstfs $FRS, $D_RA", IIC_LdStLFD>;
710    defm PSTFD :
711      MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
712                                  (ins f8rc:$FRS, memri34_pcrel:$D_RA),
713                                  "pstfd $FRS, $D_RA", IIC_LdStLFD>;
714    defm PSTXSSP :
715      8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
716                                  (ins vfrc:$VRS, memri34_pcrel:$D_RA),
717                                  "pstxssp $VRS, $D_RA", IIC_LdStLFD>;
718    defm PSTXSD :
719      8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
720                                  (ins vfrc:$VRS, memri34_pcrel:$D_RA),
721                                  "pstxsd $VRS, $D_RA", IIC_LdStLFD>;
722    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
723      defm PSTB8 :
724        MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
725                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
726                                    "pstb $RS, $D_RA", IIC_LdStLFD>;
727      defm PSTH8 :
728        MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
729                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
730                                    "psth $RS, $D_RA", IIC_LdStLFD>;
731      defm PSTW8 :
732        MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
733                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
734                                    "pstw $RS, $D_RA", IIC_LdStLFD>;
735    }
736    defm PSTB :
737      MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
738                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
739                                  "pstb $RS, $D_RA", IIC_LdStLFD>;
740    defm PSTH :
741      MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
742                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
743                                  "psth $RS, $D_RA", IIC_LdStLFD>;
744    defm PSTW :
745      MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
746                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
747                                  "pstw $RS, $D_RA", IIC_LdStLFD>;
748    defm PSTD :
749      8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
750                                  (ins g8rc:$RS, memri34_pcrel:$D_RA),
751                                  "pstd $RS, $D_RA", IIC_LdStLFD>;
752  }
753}
754
755class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
756                           string asmstr, InstrItinClass itin, list<dag> pattern>
757  : I<opcode, OOL, IOL, asmstr, itin> {
758  bits<5> XTp;
759  bits<17> DQ_RA;
760  let Pattern = pattern;
761
762  let Inst{6-9} = XTp{3-0};
763  let Inst{10} = XTp{4};
764  let Inst{11-15} = DQ_RA{16-12};  // Register #
765  let Inst{16-27} = DQ_RA{11-0};   // Displacement.
766  let Inst{28-31} = xo;
767}
768
769class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
770                      string asmstr, InstrItinClass itin, list<dag> pattern>
771  : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {
772  bits<5> XTp;
773  bits<5> A;
774  bits<5> B;
775
776  let Pattern = pattern;
777  let Inst{6-9} = XTp{3-0};
778  let Inst{10} = XTp{4};
779  let Inst{11-15} = A;
780  let Inst{16-20} = B;
781  let Inst{21-30} = xo;
782  let Inst{31} = 0;
783}
784
785class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
786                                InstrItinClass itin, list<dag> pattern>
787  : PI<1, opcode, OOL, IOL, asmstr, itin> {
788  bits<5> XTp;
789  bits<39> D_RA;
790
791  let Pattern = pattern;
792
793  // The prefix.
794  let Inst{6-10} = 0;
795  let Inst{11} = PCRel;
796  let Inst{12-13} = 0;
797  let Inst{14-31} = D_RA{33-16}; // Imm18
798
799  // The instruction.
800  let Inst{38-41} = XTp{3-0};
801  let Inst{42}    = XTp{4};
802  let Inst{43-47} = D_RA{38-34};   // Register #
803  let Inst{48-63} = D_RA{15-0};    // D
804}
805
806multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
807                                       dag IOL, dag PCRel_IOL,
808                                       string asmstr, InstrItinClass itin> {
809  def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,
810                                       !strconcat(asmstr, ", 0"), itin, []>;
811  def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,
812                                     !strconcat(asmstr, ", 1"), itin, []>,
813                                     isPCRel;
814}
815
816
817
818// [PO AS XO2 XO]
819class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
820                    string asmstr, InstrItinClass itin, list<dag> pattern>
821  : I<opcode, OOL, IOL, asmstr, itin> {
822  bits<3> AT;
823
824  let Pattern = pattern;
825
826  let Inst{6-8}  = AT;
827  let Inst{9-10}  = 0;
828  let Inst{11-15} = xo2;
829  let Inst{16-20} = 0;
830  let Inst{21-30} = xo;
831  let Inst{31} = 0;
832}
833
834// X-Form: [ PO T EO UIM XO TX ]
835class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,
836                     string asmstr, InstrItinClass itin, list<dag> pattern>
837  : I<opcode, OOL, IOL, asmstr, itin> {
838  bits<6> XT;
839  bits<5> UIM;
840
841  let Pattern = pattern;
842
843  let Inst{6-10} = XT{4-0};
844  let Inst{11-15} = eo;
845  let Inst{16-20} = UIM;
846  let Inst{21-30} = xo;
847  let Inst{31} = XT{5};
848}
849
850class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
851                           string asmstr, InstrItinClass itin,
852                           list<dag> pattern>
853  : I<opcode, OOL, IOL, asmstr, itin> {
854  bits<3> AT;
855  bits<6> XA;
856  bits<6> XB;
857
858  let Pattern = pattern;
859
860  let Inst{6-8} = AT;
861  let Inst{9-10} = 0;
862  let Inst{11-15} = XA{4-0};
863  let Inst{16-20} = XB{4-0};
864  let Inst{21-28} = xo;
865  let Inst{29}    = XA{5};
866  let Inst{30}    = XB{5};
867  let Inst{31} = 0;
868}
869
870class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
871                               string asmstr, InstrItinClass itin,
872                               list<dag> pattern>
873  : PI<1, opcode, OOL, IOL, asmstr, itin> {
874  bits<3> AT;
875  bits<6> XA;
876  bits<6> XB;
877  bits<4> XMSK;
878  bits<4> YMSK;
879  bits<2> PMSK;
880
881  let Pattern = pattern;
882
883  // The prefix.
884  let Inst{6-7} = 3;
885  let Inst{8-11} = 9;
886  let Inst{12-15} = 0;
887  let Inst{16-17} = PMSK;
888  let Inst{18-23} = 0;
889  let Inst{24-27} = XMSK;
890  let Inst{28-31} = YMSK;
891
892  // The instruction.
893  let Inst{38-40} = AT;
894  let Inst{41-42} = 0;
895  let Inst{43-47} = XA{4-0};
896  let Inst{48-52} = XB{4-0};
897  let Inst{53-60} = xo;
898  let Inst{61} = XA{5};
899  let Inst{62} = XB{5};
900  let Inst{63} = 0;
901}
902
903class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
904                             string asmstr, InstrItinClass itin,
905                             list<dag> pattern>
906  : PI<1, opcode, OOL, IOL, asmstr, itin> {
907  bits<3> AT;
908  bits<6> XA;
909  bits<6> XB;
910  bits<4> XMSK;
911  bits<4> YMSK;
912
913  let Pattern = pattern;
914
915  // The prefix.
916  let Inst{6-7} = 3;
917  let Inst{8-11} = 9;
918  let Inst{12-23} = 0;
919  let Inst{24-27} = XMSK;
920  let Inst{28-31} = YMSK;
921
922  // The instruction.
923  let Inst{38-40} = AT;
924  let Inst{41-42} = 0;
925  let Inst{43-47} = XA{4-0};
926  let Inst{48-52} = XB{4-0};
927  let Inst{53-60} = xo;
928  let Inst{61} = XA{5};
929  let Inst{62} = XB{5};
930  let Inst{63} = 0;
931}
932
933class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
934                              string asmstr, InstrItinClass itin,
935                              list<dag> pattern>
936  : PI<1, opcode, OOL, IOL, asmstr, itin> {
937  bits<3> AT;
938  bits<6> XA;
939  bits<6> XB;
940  bits<4> XMSK;
941  bits<2> YMSK;
942
943  let Pattern = pattern;
944
945  // The prefix.
946  let Inst{6-7} = 3;
947  let Inst{8-11} = 9;
948  let Inst{12-23} = 0;
949  let Inst{24-27} = XMSK;
950  let Inst{28-29} = YMSK;
951  let Inst{30-31} = 0;
952
953  // The instruction.
954  let Inst{38-40} = AT;
955  let Inst{41-42} = 0;
956  let Inst{43-47} = XA{4-0};
957  let Inst{48-52} = XB{4-0};
958  let Inst{53-60} = xo;
959  let Inst{61} = XA{5};
960  let Inst{62} = XB{5};
961  let Inst{63} = 0;
962}
963
964class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
965                               string asmstr, InstrItinClass itin,
966                               list<dag> pattern>
967  : PI<1, opcode, OOL, IOL, asmstr, itin> {
968  bits<3> AT;
969  bits<6> XA;
970  bits<6> XB;
971  bits<4> XMSK;
972  bits<4> YMSK;
973  bits<8> PMSK;
974
975  let Pattern = pattern;
976
977  // The prefix.
978  let Inst{6-7} = 3;
979  let Inst{8-11} = 9;
980  let Inst{12-15} = 0;
981  let Inst{16-23} = PMSK;
982  let Inst{24-27} = XMSK;
983  let Inst{28-31} = YMSK;
984
985  // The instruction.
986  let Inst{38-40} = AT;
987  let Inst{41-42} = 0;
988  let Inst{43-47} = XA{4-0};
989  let Inst{48-52} = XB{4-0};
990  let Inst{53-60} = xo;
991  let Inst{61} = XA{5};
992  let Inst{62} = XB{5};
993  let Inst{63} = 0;
994}
995
996class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
997                              string asmstr, InstrItinClass itin,
998                              list<dag> pattern>
999  : PI<1, opcode, OOL, IOL, asmstr, itin> {
1000  bits<3> AT;
1001  bits<6> XA;
1002  bits<6> XB;
1003  bits<4> XMSK;
1004  bits<4> YMSK;
1005  bits<4> PMSK;
1006
1007  let Pattern = pattern;
1008
1009  // The prefix.
1010  let Inst{6-7} = 3;
1011  let Inst{8-11} = 9;
1012  let Inst{12-15} = 0;
1013  let Inst{16-19} = PMSK;
1014  let Inst{20-23} = 0;
1015  let Inst{24-27} = XMSK;
1016  let Inst{28-31} = YMSK;
1017
1018  // The instruction.
1019  let Inst{38-40} = AT;
1020  let Inst{41-42} = 0;
1021  let Inst{43-47} = XA{4-0};
1022  let Inst{48-52} = XB{4-0};
1023  let Inst{53-60} = xo;
1024  let Inst{61} = XA{5};
1025  let Inst{62} = XB{5};
1026  let Inst{63} = 0;
1027}
1028
1029
1030
1031def Concats {
1032  dag VecsToVecPair0 =
1033    (v256i1 (INSERT_SUBREG
1034      (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
1035      $vs1, sub_vsx0));
1036  dag VecsToVecPair1 =
1037    (v256i1 (INSERT_SUBREG
1038      (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1039      $vs3, sub_vsx0));
1040}
1041
1042let Predicates = [PairedVectorMemops] in {
1043  def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1044            Concats.VecsToVecPair0>;
1045  def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
1046            Concats.VecsToVecPair0>;
1047  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
1048            (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
1049  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
1050            (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
1051}
1052
1053let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
1054  def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
1055                                  (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA",
1056                                  IIC_LdStLFD, []>;
1057  def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src),
1058                              "lxvpx $XTp, $src", IIC_LdStLFD,
1059                              []>;
1060}
1061
1062let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
1063  def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
1064                                   memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA",
1065                                   IIC_LdStLFD, []>;
1066  def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst),
1067                               "stxvpx $XTp, $dst", IIC_LdStLFD,
1068                               []>;
1069}
1070
1071let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1072  defm PLXVP :
1073    8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
1074                                (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA",
1075                                IIC_LdStLFD>;
1076}
1077
1078let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1079  defm PSTXVP :
1080    8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),
1081                                (ins vsrprc:$XTp, memri34_pcrel:$D_RA),
1082                                "pstxvp $XTp, $D_RA", IIC_LdStLFD>;
1083}
1084
1085let Predicates = [PairedVectorMemops] in {
1086  // Intrinsics for Paired Vector Loads.
1087  def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
1088  def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
1089  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1090    def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;
1091  }
1092  // Intrinsics for Paired Vector Stores.
1093  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst),
1094            (STXVP $XSp, memrix16:$dst)>;
1095  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),
1096            (STXVPX $XSp, XForm:$dst)>;
1097  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1098    def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),
1099              (PSTXVP $XSp, memri34:$dst)>;
1100  }
1101}
1102
1103let Predicates = [IsISA3_1] in {
1104  def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>;
1105  def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>;
1106  def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>;
1107}
1108
1109let Predicates = [PCRelativeMemops] in {
1110  // Load i32
1111  def : Pat<(i32 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1112            (PLBZpc $ga, 0)>;
1113  def : Pat<(i32 (extloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1114            (PLBZpc $ga, 0)>;
1115  def : Pat<(i32 (zextloadi8  (PPCmatpcreladdr PCRelForm:$ga))),
1116            (PLBZpc $ga, 0)>;
1117  def : Pat<(i32 (extloadi8   (PPCmatpcreladdr PCRelForm:$ga))),
1118            (PLBZpc $ga, 0)>;
1119  def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1120            (PLHApc $ga, 0)>;
1121  def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1122            (PLHZpc $ga, 0)>;
1123  def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1124            (PLHZpc $ga, 0)>;
1125  def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>;
1126
1127  // Store i32
1128  def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1129            (PSTBpc $RS, $ga, 0)>;
1130  def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1131            (PSTHpc $RS, $ga, 0)>;
1132  def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1133            (PSTWpc $RS, $ga, 0)>;
1134
1135  // Load i64
1136  def : Pat<(i64 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1137            (PLBZ8pc $ga, 0)>;
1138  def : Pat<(i64 (extloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1139            (PLBZ8pc $ga, 0)>;
1140  def : Pat<(i64 (zextloadi8  (PPCmatpcreladdr PCRelForm:$ga))),
1141            (PLBZ8pc $ga, 0)>;
1142  def : Pat<(i64 (extloadi8   (PPCmatpcreladdr PCRelForm:$ga))),
1143            (PLBZ8pc $ga, 0)>;
1144  def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1145            (PLHA8pc $ga, 0)>;
1146  def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1147            (PLHZ8pc $ga, 0)>;
1148  def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1149            (PLHZ8pc $ga, 0)>;
1150  def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1151            (PLWZ8pc $ga, 0)>;
1152  def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1153            (PLWA8pc $ga, 0)>;
1154  def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1155            (PLWZ8pc $ga, 0)>;
1156  def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>;
1157
1158  // Store i64
1159  def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1160            (PSTB8pc $RS, $ga, 0)>;
1161  def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1162            (PSTH8pc $RS, $ga, 0)>;
1163  def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1164            (PSTW8pc $RS, $ga, 0)>;
1165  def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1166            (PSTDpc $RS, $ga, 0)>;
1167
1168  // Load f32
1169  def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;
1170
1171  // Store f32
1172  def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
1173            (PSTFSpc $FRS, $ga, 0)>;
1174
1175  // Load f64
1176  def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))),
1177            (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
1178  def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>;
1179
1180  // Store f64
1181  def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
1182            (PSTFDpc $FRS, $ga, 0)>;
1183
1184  // Load f128
1185  def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))),
1186            (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
1187
1188  // Store f128
1189  def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1190            (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
1191
1192  // Load v4i32
1193  def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1194
1195  // Store v4i32
1196  def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1197            (PSTXVpc $XS, $ga, 0)>;
1198
1199  // Load v2i64
1200  def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1201
1202  // Store v2i64
1203  def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1204            (PSTXVpc $XS, $ga, 0)>;
1205
1206  // Load v4f32
1207  def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1208
1209  // Store v4f32
1210  def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1211            (PSTXVpc $XS, $ga, 0)>;
1212
1213  // Load v2f64
1214  def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1215
1216  // Store v2f64
1217  def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1218            (PSTXVpc $XS, $ga, 0)>;
1219
1220  // Atomic Load
1221  def : Pat<(atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga)),
1222            (PLBZpc $ga, 0)>;
1223  def : Pat<(atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga)),
1224            (PLHZpc $ga, 0)>;
1225  def : Pat<(atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga)),
1226            (PLWZpc $ga, 0)>;
1227  def : Pat<(atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga)),
1228            (PLDpc $ga, 0)>;
1229
1230  // Atomic Store
1231  def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1232            (PSTBpc $RS, $ga, 0)>;
1233  def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1234            (PSTHpc $RS, $ga, 0)>;
1235  def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1236            (PSTWpc $RS, $ga, 0)>;
1237  def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1238            (PSTB8pc $RS, $ga, 0)>;
1239  def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1240            (PSTH8pc $RS, $ga, 0)>;
1241  def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1242            (PSTW8pc $RS, $ga, 0)>;
1243  def : Pat<(atomic_store_64 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1244            (PSTDpc $RS, $ga, 0)>;
1245
1246  // Special Cases For PPCstore_scal_int_from_vsr
1247  def : Pat<(PPCstore_scal_int_from_vsr
1248              (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)),
1249              (PPCmatpcreladdr PCRelForm:$dst), 8),
1250            (PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>;
1251  def : Pat<(PPCstore_scal_int_from_vsr
1252              (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)),
1253              (PPCmatpcreladdr PCRelForm:$dst), 8),
1254            (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>;
1255
1256  def : Pat<(PPCstore_scal_int_from_vsr
1257              (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)),
1258              (PPCmatpcreladdr PCRelForm:$dst), 8),
1259            (PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>;
1260  def : Pat<(PPCstore_scal_int_from_vsr
1261              (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)),
1262              (PPCmatpcreladdr PCRelForm:$dst), 8),
1263            (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
1264
1265  def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
1266            (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
1267
1268  // If the PPCmatpcreladdr node is not caught by any other pattern it should be
1269  // caught here and turned into a paddi instruction to materialize the address.
1270  def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1271  // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize
1272  // tls global address with paddi instruction.
1273  def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1274  // PPCtlslocalexecmataddr node is used for TLS local exec models to
1275  // materialize tls global address with paddi instruction.
1276  def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),
1277            (PADDI8 $in, $addr)>;
1278}
1279
1280let Predicates = [PrefixInstrs] in {
1281  def XXPERMX :
1282    8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1283                            vsrc:$XC, u3imm:$UIM),
1284                            "xxpermx $XT, $XA, $XB, $XC, $UIM",
1285                            IIC_VecPerm, []>;
1286  def XXBLENDVB :
1287    8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1288                       vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
1289                       IIC_VecGeneral, []>;
1290  def XXBLENDVH :
1291    8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1292                       vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
1293                       IIC_VecGeneral, []>;
1294  def XXBLENDVW :
1295    8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1296                       vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
1297                       IIC_VecGeneral, []>;
1298  def XXBLENDVD :
1299    8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1300                       vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
1301                       IIC_VecGeneral, []>;
1302}
1303
1304// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt
1305// to spill part of the instruction when the values are similar.
1306let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
1307  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
1308                                     (ins i32imm:$IMM32),
1309                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
1310                                     []>;
1311  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
1312                                      (ins i32imm:$IMM32),
1313                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
1314                                      [(set v2f64:$XT,
1315                                            (PPCxxspltidp i32:$IMM32))]>;
1316  def XXSPLTI32DX :
1317      8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
1318                             (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),
1319                             "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
1320                             [(set v2i64:$XT,
1321                                   (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
1322                                                   i32:$IMM32))]>,
1323                             RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1324}
1325
1326let Predicates = [IsISA3_1] in {
1327  def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
1328                            "setbc $RT, $BI", IIC_IntCompare, []>,
1329                            SExt32To64, ZExt32To64;
1330  def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
1331                             "setbcr $RT, $BI", IIC_IntCompare, []>,
1332                             SExt32To64, ZExt32To64;
1333  def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
1334                             "setnbc $RT, $BI", IIC_IntCompare, []>,
1335                             SExt32To64;
1336  def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
1337                              "setnbcr $RT, $BI", IIC_IntCompare, []>,
1338                              SExt32To64;
1339
1340  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1341    def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
1342                               "setbc $RT, $BI", IIC_IntCompare, []>,
1343                               SExt32To64, ZExt32To64;
1344    def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
1345                                "setbcr $RT, $BI", IIC_IntCompare, []>,
1346                                SExt32To64, ZExt32To64;
1347    def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
1348                                "setnbc $RT, $BI", IIC_IntCompare, []>,
1349                                SExt32To64;
1350    def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
1351                                 "setnbcr $RT, $BI", IIC_IntCompare, []>,
1352                                 SExt32To64;
1353  }
1354
1355  def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
1356                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
1357                                "vsldbi $VRT, $VRA, $VRB, $SH",
1358                                IIC_VecGeneral,
1359                                [(set v16i8:$VRT,
1360                                      (int_ppc_altivec_vsldbi v16i8:$VRA,
1361                                                              v16i8:$VRB,
1362                                                              timm:$SH))]>;
1363  def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
1364                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
1365                                "vsrdbi $VRT, $VRA, $VRB, $SH",
1366                                IIC_VecGeneral,
1367                                [(set v16i8:$VRT,
1368                                      (int_ppc_altivec_vsrdbi v16i8:$VRA,
1369                                                              v16i8:$VRB,
1370                                                              timm:$SH))]>;
1371  defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB),
1372                                 "vstribr", "$vT, $vB", IIC_VecGeneral,
1373				 [(set v16i8:$vT,
1374                                       (int_ppc_altivec_vstribr v16i8:$vB))]>;
1375  defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB),
1376                                 "vstribl", "$vT, $vB", IIC_VecGeneral,
1377                                 [(set v16i8:$vT,
1378                                       (int_ppc_altivec_vstribl v16i8:$vB))]>;
1379  defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB),
1380                                 "vstrihr", "$vT, $vB", IIC_VecGeneral,
1381                                 [(set v8i16:$vT,
1382                                       (int_ppc_altivec_vstrihr v8i16:$vB))]>;
1383  defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB),
1384                                 "vstrihl", "$vT, $vB", IIC_VecGeneral,
1385                                 [(set v8i16:$vT,
1386                                       (int_ppc_altivec_vstrihl v8i16:$vB))]>;
1387  def VINSW :
1388    VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
1389             "vinsw $vD, $rB, $UIM", IIC_VecGeneral,
1390             [(set v4i32:$vD,
1391                   (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>,
1392             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1393  def VINSD :
1394    VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
1395             "vinsd $vD, $rB, $UIM", IIC_VecGeneral,
1396             [(set v2i64:$vD,
1397                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>,
1398             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1399  def VINSBVLX :
1400    VXForm_VTB5_RA5_ins<15, "vinsbvlx",
1401                        [(set v16i8:$vD,
1402                              (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA,
1403                                                        v16i8:$vB))]>;
1404  def VINSBVRX :
1405    VXForm_VTB5_RA5_ins<271, "vinsbvrx",
1406                        [(set v16i8:$vD,
1407                              (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA,
1408                                                        v16i8:$vB))]>;
1409  def VINSHVLX :
1410    VXForm_VTB5_RA5_ins<79, "vinshvlx",
1411                        [(set v8i16:$vD,
1412                              (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA,
1413                                                        v8i16:$vB))]>;
1414  def VINSHVRX :
1415    VXForm_VTB5_RA5_ins<335, "vinshvrx",
1416                        [(set v8i16:$vD,
1417                              (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA,
1418                                                        v8i16:$vB))]>;
1419  def VINSWVLX :
1420    VXForm_VTB5_RA5_ins<143, "vinswvlx",
1421                        [(set v4i32:$vD,
1422                              (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA,
1423                                                        v4i32:$vB))]>;
1424  def VINSWVRX :
1425    VXForm_VTB5_RA5_ins<399, "vinswvrx",
1426                        [(set v4i32:$vD,
1427                              (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA,
1428                                                        v4i32:$vB))]>;
1429  def VINSBLX :
1430    VXForm_VRT5_RAB5_ins<527, "vinsblx",
1431                         [(set v16i8:$vD,
1432                               (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA,
1433                                                        i32:$rB))]>;
1434  def VINSBRX :
1435    VXForm_VRT5_RAB5_ins<783, "vinsbrx",
1436                         [(set v16i8:$vD,
1437                               (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA,
1438                                                        i32:$rB))]>;
1439  def VINSHLX :
1440    VXForm_VRT5_RAB5_ins<591, "vinshlx",
1441                         [(set v8i16:$vD,
1442                               (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA,
1443                                                        i32:$rB))]>;
1444  def VINSHRX :
1445    VXForm_VRT5_RAB5_ins<847, "vinshrx",
1446                         [(set v8i16:$vD,
1447                               (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA,
1448                                                        i32:$rB))]>;
1449  def VINSWLX :
1450    VXForm_VRT5_RAB5_ins<655, "vinswlx",
1451                         [(set v4i32:$vD,
1452                               (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA,
1453                                                        i32:$rB))]>;
1454  def VINSWRX :
1455    VXForm_VRT5_RAB5_ins<911, "vinswrx",
1456                         [(set v4i32:$vD,
1457                               (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA,
1458                                                        i32:$rB))]>;
1459  def VINSDLX :
1460    VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
1461             "vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
1462              [(set v2i64:$vD,
1463                    (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>,
1464              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1465  def VINSDRX :
1466    VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
1467             "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
1468              [(set v2i64:$vD,
1469                    (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
1470              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1471  def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
1472                                      "vextractbm $rD, $vB", IIC_VecGeneral,
1473                                      [(set i32:$rD,
1474                                      (int_ppc_altivec_vextractbm v16i8:$vB))]>,
1475                                      ZExt32To64;
1476  def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
1477                                      "vextracthm $rD, $vB", IIC_VecGeneral,
1478                                      [(set i32:$rD,
1479                                      (int_ppc_altivec_vextracthm v8i16:$vB))]>,
1480                                      ZExt32To64;
1481  def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
1482                                      "vextractwm $rD, $vB", IIC_VecGeneral,
1483                                      [(set i32:$rD,
1484                                      (int_ppc_altivec_vextractwm v4i32:$vB))]>,
1485                                      ZExt32To64;
1486  def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
1487                                      "vextractdm $rD, $vB", IIC_VecGeneral,
1488                                      [(set i32:$rD,
1489                                      (int_ppc_altivec_vextractdm v2i64:$vB))]>,
1490                                      ZExt32To64;
1491  def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
1492                                      "vextractqm $rD, $vB", IIC_VecGeneral,
1493                                      [(set i32:$rD,
1494                                      (int_ppc_altivec_vextractqm v1i128:$vB))]>;
1495  def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
1496                                     "vexpandbm $vD, $vB", IIC_VecGeneral,
1497                                     [(set v16i8:$vD, (int_ppc_altivec_vexpandbm
1498                                           v16i8:$vB))]>;
1499  def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB),
1500                                     "vexpandhm $vD, $vB", IIC_VecGeneral,
1501                                     [(set v8i16:$vD, (int_ppc_altivec_vexpandhm
1502                                           v8i16:$vB))]>;
1503  def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB),
1504                                     "vexpandwm $vD, $vB", IIC_VecGeneral,
1505                                     [(set v4i32:$vD, (int_ppc_altivec_vexpandwm
1506                                           v4i32:$vB))]>;
1507  def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
1508                                     "vexpanddm $vD, $vB", IIC_VecGeneral,
1509                                     [(set v2i64:$vD, (int_ppc_altivec_vexpanddm
1510                                           v2i64:$vB))]>;
1511  def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
1512                                     "vexpandqm $vD, $vB", IIC_VecGeneral,
1513                                     [(set v1i128:$vD, (int_ppc_altivec_vexpandqm
1514                                           v1i128:$vB))]>;
1515  def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
1516                                   "mtvsrbm $vD, $rB", IIC_VecGeneral,
1517                                   [(set v16i8:$vD,
1518                                         (int_ppc_altivec_mtvsrbm i64:$rB))]>;
1519  def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB),
1520                                   "mtvsrhm $vD, $rB", IIC_VecGeneral,
1521                                   [(set v8i16:$vD,
1522                                         (int_ppc_altivec_mtvsrhm i64:$rB))]>;
1523  def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB),
1524                                   "mtvsrwm $vD, $rB", IIC_VecGeneral,
1525                                   [(set v4i32:$vD,
1526                                         (int_ppc_altivec_mtvsrwm i64:$rB))]>;
1527  def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB),
1528                                   "mtvsrdm $vD, $rB", IIC_VecGeneral,
1529                                   [(set v2i64:$vD,
1530                                         (int_ppc_altivec_mtvsrdm i64:$rB))]>;
1531  def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB),
1532                                   "mtvsrqm $vD, $rB", IIC_VecGeneral,
1533                                   [(set v1i128:$vD,
1534                                         (int_ppc_altivec_mtvsrqm i64:$rB))]>;
1535  def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D),
1536                        "mtvsrbmi $vD, $D", IIC_VecGeneral,
1537                        [(set v16i8:$vD,
1538                              (int_ppc_altivec_mtvsrbm imm:$D))]>;
1539  def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
1540                                  (ins vrrc:$vB, u1imm:$MP),
1541                                  "vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
1542                                  [(set i64:$rD, (int_ppc_altivec_vcntmbb
1543                                        v16i8:$vB, timm:$MP))]>;
1544  def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD),
1545                                  (ins vrrc:$vB, u1imm:$MP),
1546                                  "vcntmbh $rD, $vB, $MP", IIC_VecGeneral,
1547                                  [(set i64:$rD, (int_ppc_altivec_vcntmbh
1548                                        v8i16:$vB, timm:$MP))]>;
1549  def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD),
1550                                  (ins vrrc:$vB, u1imm:$MP),
1551                                  "vcntmbw $rD, $vB, $MP", IIC_VecGeneral,
1552                                  [(set i64:$rD, (int_ppc_altivec_vcntmbw
1553                                        v4i32:$vB, timm:$MP))]>;
1554  def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD),
1555                                  (ins vrrc:$vB, u1imm:$MP),
1556                                  "vcntmbd $rD, $vB, $MP", IIC_VecGeneral,
1557                                  [(set i64:$rD, (int_ppc_altivec_vcntmbd
1558                                        v2i64:$vB, timm:$MP))]>;
1559  def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD),
1560                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1561                             "vextdubvlx $vD, $vA, $vB, $rC",
1562                             IIC_VecGeneral,
1563                             [(set v2i64:$vD,
1564                                   (int_ppc_altivec_vextdubvlx v16i8:$vA,
1565                                                               v16i8:$vB,
1566                                                               i32:$rC))]>;
1567  def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD),
1568                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1569                             "vextdubvrx $vD, $vA, $vB, $rC",
1570                             IIC_VecGeneral,
1571                             [(set v2i64:$vD,
1572                                   (int_ppc_altivec_vextdubvrx v16i8:$vA,
1573                                                               v16i8:$vB,
1574                                                               i32:$rC))]>;
1575  def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD),
1576                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1577                             "vextduhvlx $vD, $vA, $vB, $rC",
1578                             IIC_VecGeneral,
1579                             [(set v2i64:$vD,
1580                                   (int_ppc_altivec_vextduhvlx v8i16:$vA,
1581                                                               v8i16:$vB,
1582                                                               i32:$rC))]>;
1583  def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD),
1584                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1585                             "vextduhvrx $vD, $vA, $vB, $rC",
1586                             IIC_VecGeneral,
1587                             [(set v2i64:$vD,
1588                                   (int_ppc_altivec_vextduhvrx v8i16:$vA,
1589                                                               v8i16:$vB,
1590                                                               i32:$rC))]>;
1591  def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD),
1592                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1593                             "vextduwvlx $vD, $vA, $vB, $rC",
1594                             IIC_VecGeneral,
1595                             [(set v2i64:$vD,
1596                                   (int_ppc_altivec_vextduwvlx v4i32:$vA,
1597                                                               v4i32:$vB,
1598                                                               i32:$rC))]>;
1599  def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD),
1600                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1601                             "vextduwvrx $vD, $vA, $vB, $rC",
1602                             IIC_VecGeneral,
1603                             [(set v2i64:$vD,
1604                                   (int_ppc_altivec_vextduwvrx v4i32:$vA,
1605                                                               v4i32:$vB,
1606                                                               i32:$rC))]>;
1607  def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD),
1608                            (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1609                            "vextddvlx $vD, $vA, $vB, $rC",
1610                            IIC_VecGeneral,
1611                            [(set v2i64:$vD,
1612                                  (int_ppc_altivec_vextddvlx v2i64:$vA,
1613                                                             v2i64:$vB,
1614                                                             i32:$rC))]>;
1615  def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD),
1616                            (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
1617                            "vextddvrx $vD, $vA, $vB, $rC",
1618                            IIC_VecGeneral,
1619                            [(set v2i64:$vD,
1620                                  (int_ppc_altivec_vextddvrx v2i64:$vA,
1621                                                             v2i64:$vB,
1622                                                             i32:$rC))]>;
1623   def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1624                         "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
1625                         [(set v2i64:$vD,
1626                         (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
1627   def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1628                         "vpextd $vD, $vA, $vB", IIC_VecGeneral,
1629                         [(set v2i64:$vD,
1630                         (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
1631   def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
1632                       "pdepd $rA, $rS, $rB", IIC_IntGeneral,
1633                       [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>;
1634   def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
1635                       "pextd $rA, $rS, $rB", IIC_IntGeneral,
1636                       [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
1637   def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1638                          "vcfuged $vD, $vA, $vB", IIC_VecGeneral,
1639                          [(set v2i64:$vD,
1640                          (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>;
1641   def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N),
1642                                "vgnb $rD, $vB, $N", IIC_VecGeneral,
1643                                [(set i64:$rD,
1644                                (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>;
1645   def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
1646                        "cfuged $rA, $rS, $rB", IIC_IntGeneral,
1647                        [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>;
1648   def XXEVAL :
1649     8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1650                            vsrc:$XC, u8imm:$IMM),
1651                            "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
1652                            [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
1653                                  v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
1654   def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1655                         "vclzdm $vD, $vA, $vB", IIC_VecGeneral,
1656                         [(set v2i64:$vD,
1657                         (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>;
1658   def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1659                         "vctzdm $vD, $vA, $vB", IIC_VecGeneral,
1660                         [(set v2i64:$vD,
1661                         (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>;
1662   def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
1663                         "cntlzdm $rA, $rS, $rB", IIC_IntGeneral,
1664                         [(set i64:$rA,
1665                         (int_ppc_cntlzdm i64:$rS, i64:$rB))]>;
1666   def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
1667                         "cnttzdm $rA, $rS, $rB", IIC_IntGeneral,
1668                         [(set i64:$rA,
1669                         (int_ppc_cnttzdm i64:$rS, i64:$rB))]>;
1670   def XXGENPCVBM :
1671     XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1672                        "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1673   def XXGENPCVHM :
1674     XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1675                        "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1676   def XXGENPCVWM :
1677     XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1678                        "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1679   def XXGENPCVDM :
1680     XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1681                        "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1682   def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
1683                         "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
1684                         [(set v16i8:$vD,
1685                               (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
1686   def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
1687                         "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
1688                         [(set v16i8:$vD,
1689                               (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
1690  def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1691                        "vmulld $vD, $vA, $vB", IIC_VecGeneral,
1692                        [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>;
1693  def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1694                         "vmulhsw $vD, $vA, $vB", IIC_VecGeneral,
1695                         [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>;
1696  def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1697                         "vmulhuw $vD, $vA, $vB", IIC_VecGeneral,
1698                         [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>;
1699  def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1700                         "vmulhsd $vD, $vA, $vB", IIC_VecGeneral,
1701                         [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>;
1702  def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1703                         "vmulhud $vD, $vA, $vB", IIC_VecGeneral,
1704                         [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>;
1705  def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1706                        "vmodsw $vD, $vA, $vB", IIC_VecGeneral,
1707                        [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>;
1708  def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1709                        "vmoduw $vD, $vA, $vB", IIC_VecGeneral,
1710                        [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>;
1711  def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1712                        "vmodsd $vD, $vA, $vB", IIC_VecGeneral,
1713                        [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>;
1714  def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1715                        "vmodud $vD, $vA, $vB", IIC_VecGeneral,
1716                        [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>;
1717  def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1718                        "vdivsw $vD, $vA, $vB", IIC_VecGeneral,
1719                        [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>;
1720  def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1721                        "vdivuw $vD, $vA, $vB", IIC_VecGeneral,
1722                        [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>;
1723  def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1724                        "vdivsd $vD, $vA, $vB", IIC_VecGeneral,
1725                        [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>;
1726  def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1727                        "vdivud $vD, $vA, $vB", IIC_VecGeneral,
1728                        [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>;
1729  def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1730                         "vdivesw $vD, $vA, $vB", IIC_VecGeneral,
1731                         [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA,
1732                               v4i32:$vB))]>;
1733  def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1734                         "vdiveuw $vD, $vA, $vB", IIC_VecGeneral,
1735                         [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA,
1736                               v4i32:$vB))]>;
1737  def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1738                         "vdivesd $vD, $vA, $vB", IIC_VecGeneral,
1739                         [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA,
1740                               v2i64:$vB))]>;
1741  def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1742                         "vdiveud $vD, $vA, $vB", IIC_VecGeneral,
1743                         [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA,
1744                               v2i64:$vB))]>;
1745  def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
1746                                    "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
1747  def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RS),
1748                     "brh $RA, $RS", IIC_IntRotate, []>;
1749  def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RS),
1750                     "brw $RA, $RS", IIC_IntRotate,
1751                     [(set i32:$RA, (bswap i32:$RS))]>;
1752  let isCodeGenOnly = 1 in {
1753    def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RS),
1754                        "brh $RA, $RS", IIC_IntRotate, []>;
1755    def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RS),
1756                        "brw $RA, $RS", IIC_IntRotate, []>;
1757  }
1758  def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RS),
1759                     "brd $RA, $RS", IIC_IntRotate,
1760                     [(set i64:$RA, (bswap i64:$RS))]>;
1761
1762  // The XFormMemOp flag for the following 8 instructions is set on
1763  // the instruction format.
1764  let mayLoad = 1, mayStore = 0 in {
1765    def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
1766    def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
1767    def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
1768    def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
1769  }
1770
1771  let mayLoad = 0, mayStore = 1 in {
1772    def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
1773    def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
1774    def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
1775    def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
1776  }
1777
1778  def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1779                         "vmulesd $vD, $vA, $vB", IIC_VecGeneral,
1780                         [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA,
1781                               v2i64:$vB))]>;
1782  def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1783                         "vmuleud $vD, $vA, $vB", IIC_VecGeneral,
1784                         [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA,
1785                               v2i64:$vB))]>;
1786  def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1787                         "vmulosd $vD, $vA, $vB", IIC_VecGeneral,
1788                         [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA,
1789                               v2i64:$vB))]>;
1790  def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1791                         "vmuloud $vD, $vA, $vB", IIC_VecGeneral,
1792                         [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA,
1793                               v2i64:$vB))]>;
1794  def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
1795                           "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral,
1796                           [(set v1i128:$vD, (int_ppc_altivec_vmsumcud
1797                                 v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
1798  def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1799                        "vdivsq $vD, $vA, $vB", IIC_VecGeneral,
1800                        [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
1801  def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1802                        "vdivuq $vD, $vA, $vB", IIC_VecGeneral,
1803                        [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
1804  def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1805                         "vdivesq $vD, $vA, $vB", IIC_VecGeneral,
1806                         [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA,
1807			       v1i128:$vB))]>;
1808  def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1809                         "vdiveuq $vD, $vA, $vB", IIC_VecGeneral,
1810                         [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA,
1811			       v1i128:$vB))]>;
1812  def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
1813  def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
1814  def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
1815  def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;
1816  def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
1817  def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
1818  def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1819                        "vmodsq $vD, $vA, $vB", IIC_VecGeneral,
1820                        [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>;
1821  def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1822                        "vmoduq $vD, $vA, $vB", IIC_VecGeneral,
1823                        [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>;
1824  def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB),
1825                               "vextsd2q $vD, $vB", IIC_VecGeneral,
1826                               [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>;
1827  def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
1828                               "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
1829  def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
1830                               "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>;
1831  def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
1832                               [(set v1i128:$vD,
1833                                   (int_ppc_altivec_vrlqnm v1i128:$vA,
1834                                                           v1i128:$vB))]>;
1835  def VRLQMI : VXForm_1<69, (outs vrrc:$vD),
1836                        (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
1837                        "vrlqmi $vD, $vA, $vB", IIC_VecFP,
1838                        [(set v1i128:$vD,
1839                          (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB,
1840                                                  v1i128:$vDi))]>,
1841                        RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1842  def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
1843  def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
1844  def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
1845  def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
1846  def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
1847  def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
1848  def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
1849  def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
1850  def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),
1851                             "lxvkq $XT, $UIM", IIC_VecGeneral, []>;
1852}
1853
1854let Predicates = [IsISA3_1, HasVSX] in {
1855  def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
1856  def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
1857  def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp",
1858                               [(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>;
1859  def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp",
1860                               [(set f128:$vT, (PPCxsminc f128:$vA, f128:$vB))]>;
1861}
1862
1863// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
1864// This is analogous to the CRNotPat multiclass but specifically for Power10
1865// and newer subtargets since the extended forms use Set Boolean instructions.
1866// The first two anonymous patterns defined are actually a duplicate of those
1867// in CRNotPat, but it is preferable to define both multiclasses as complete
1868// ones rather than pulling that small common section out.
1869multiclass P10ReverseSetBool<dag pattern, dag result> {
1870  def : Pat<pattern, (crnot result)>;
1871  def : Pat<(not pattern), result>;
1872
1873  def : Pat<(i32 (zext pattern)),
1874            (SETBCR result)>;
1875  def : Pat<(i64 (zext pattern)),
1876            (SETBCR8 result)>;
1877
1878  def : Pat<(i32 (sext pattern)),
1879            (SETNBCR result)>;
1880  def : Pat<(i64 (sext pattern)),
1881            (SETNBCR8 result)>;
1882
1883  def : Pat<(i32 (anyext pattern)),
1884            (SETBCR result)>;
1885  def : Pat<(i64 (anyext pattern)),
1886            (SETBCR8 result)>;
1887}
1888
1889multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
1890                               ImmLeaf SExtTy, I Cmpi, I Cmpli,
1891                               I Cmp, I Cmpl> {
1892  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1893                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>;
1894  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1895                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>;
1896  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1897                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>;
1898  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1899                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>;
1900  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1901                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>;
1902
1903  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
1904                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>;
1905  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
1906                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>;
1907  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
1908                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>;
1909  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
1910                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>;
1911  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
1912                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>;
1913  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
1914                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>;
1915}
1916
1917multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> {
1918  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1919                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
1920  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1921                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
1922  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1923                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
1924  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1925                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
1926  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
1927                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
1928  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1929                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
1930  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
1931                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
1932}
1933
1934let Predicates = [IsISA3_1] in {
1935  def : Pat<(i32 (zext i1:$in)),
1936            (SETBC $in)>;
1937  def : Pat<(i64 (zext i1:$in)),
1938            (SETBC8 $in)>;
1939  def : Pat<(i32 (sext i1:$in)),
1940            (SETNBC $in)>;
1941  def : Pat<(i64 (sext i1:$in)),
1942            (SETNBC8 $in)>;
1943  def : Pat<(i32 (anyext i1:$in)),
1944            (SETBC $in)>;
1945  def : Pat<(i64 (anyext i1:$in)),
1946            (SETBC8 $in)>;
1947
1948  // Instantiation of the set boolean reverse patterns for 32-bit integers.
1949  defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,
1950                             CMPWI, CMPLWI, CMPW, CMPLW>;
1951  defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
1952                           (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
1953                                           (LO16 imm:$imm)), sub_eq)>;
1954
1955  // Instantiation of the set boolean reverse patterns for 64-bit integers.
1956  defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,
1957                             CMPDI, CMPLDI, CMPD, CMPLD>;
1958  defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
1959                           (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
1960                                           (LO16 imm:$imm)), sub_eq)>;
1961}
1962
1963// Instantiation of the set boolean reverse patterns for f32, f64, f128.
1964let Predicates = [IsISA3_1, HasFPU] in {
1965  defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;
1966  defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;
1967  defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;
1968}
1969
1970//---------------------------- Anonymous Patterns ----------------------------//
1971let Predicates = [IsISA3_1] in {
1972  // Exploit the vector multiply high instructions using intrinsics.
1973  def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),
1974            (v4i32 (VMULHSW $vA, $vB))>;
1975  def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)),
1976            (v4i32 (VMULHUW $vA, $vB))>;
1977  def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)),
1978            (v2i64 (VMULHSD $vA, $vB))>;
1979  def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)),
1980            (v2i64 (VMULHUD $vA, $vB))>;
1981  def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
1982            (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
1983  def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
1984            (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
1985  def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
1986            (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
1987  def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
1988            (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
1989  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
1990            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
1991  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
1992            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
1993  def : Pat<(srl (bswap i32:$RS), (i32 16)),
1994            (RLDICL_32 (BRH $RS), 0, 48)>;
1995  def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))),
1996            (RLDICL_32_64 (BRH $RS), 0, 48)>;
1997  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),
1998             (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;
1999  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),
2000             (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;
2001  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)),
2002             (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;
2003  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)),
2004             (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;
2005
2006  def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
2007            (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
2008
2009  def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
2010             (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;
2011}
2012
2013let Predicates = [IsISA3_1, HasVSX] in {
2014  def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
2015            (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;
2016  def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
2017            (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
2018}
2019
2020let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
2021  // Store element 0 of a VSX register to memory
2022  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst),
2023            (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>;
2024  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst),
2025            (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>;
2026  def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst),
2027            (STXVRWX $src, ForceXForm:$dst)>;
2028  def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst),
2029            (STXVRWX $src, ForceXForm:$dst)>;
2030  def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst),
2031            (STXVRDX $src, ForceXForm:$dst)>;
2032  def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),
2033            (STXVRDX $src, ForceXForm:$dst)>;
2034  // Load element 0 of a VSX register to memory
2035  def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))),
2036            (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>;
2037  def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))),
2038            (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>;
2039 }
2040
2041// FIXME: The swap is overkill when the shift amount is a constant.
2042// We should just fix the constant in the DAG.
2043let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
2044  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
2045            (v1i128 (VSLQ v1i128:$VRA,
2046                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2047                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2048  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
2049            (v1i128 (VSLQ v1i128:$VRA,
2050                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2051                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2052  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
2053            (v1i128 (VSRQ v1i128:$VRA,
2054                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2055                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2056  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
2057            (v1i128 (VSRQ v1i128:$VRA,
2058                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2059                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2060  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
2061            (v1i128 (VSRAQ v1i128:$VRA,
2062                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2063                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2064  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
2065            (v1i128 (VSRAQ v1i128:$VRA,
2066                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2067                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2068}
2069
2070class xxevalPattern <dag pattern, bits<8> imm> :
2071  Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
2072
2073let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
2074 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
2075                                i32immNonAllOneNonZero:$A,
2076                                i32immNonAllOneNonZero:$A,
2077                                i32immNonAllOneNonZero:$A)),
2078           (v4i32 (XXSPLTIW imm:$A))>;
2079 def : Pat<(f32 nzFPImmAsi32:$A),
2080           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2081                             VSFRC)>;
2082 def : Pat<(f64 nzFPImmAsi32:$A),
2083           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2084                             VSFRC)>;
2085
2086// To replace constant pool with XXSPLTI32DX for scalars.
2087def : Pat<(f32 nzFPImmAsi64:$A),
2088          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0,
2089                                        (getFPAs64BitIntHi $A)),
2090                                        1, (getFPAs64BitIntLo $A)),
2091                            VSSRC)>;
2092
2093def : Pat<(f64 nzFPImmAsi64:$A),
2094          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0,
2095                                        (getFPAs64BitIntHi $A)),
2096                                        1, (getFPAs64BitIntLo $A)),
2097                            VSFRC)>;
2098
2099  // Anonymous patterns for XXEVAL
2100  // AND
2101  // and(A, B, C)
2102  def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
2103  // and(A, xor(B, C))
2104  def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
2105  // and(A, or(B, C))
2106  def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
2107  // and(A, nor(B, C))
2108  def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
2109  // and(A, eqv(B, C))
2110  def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
2111  // and(A, nand(B, C))
2112  def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
2113
2114  // NAND
2115  // nand(A, B, C)
2116  def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
2117                       !sub(255, 1)>;
2118  // nand(A, xor(B, C))
2119  def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
2120                       !sub(255, 6)>;
2121  // nand(A, or(B, C))
2122  def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
2123                       !sub(255, 7)>;
2124  // nand(A, nor(B, C))
2125  def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
2126                       !sub(255, 8)>;
2127  // nand(A, eqv(B, C))
2128  def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
2129                       !sub(255, 9)>;
2130  // nand(A, nand(B, C))
2131  def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
2132                       !sub(255, 14)>;
2133
2134  // EQV
2135  // (eqv A, B, C)
2136  def : xxevalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),
2137                          (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))),
2138                       150>;
2139  // (eqv A, (and B, C))
2140  def : xxevalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;
2141  // (eqv A, (or B, C))
2142  def : xxevalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;
2143
2144  // NOR
2145  // (nor A, B, C)
2146  def : xxevalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;
2147  // (nor A, (and B, C))
2148  def : xxevalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;
2149  // (nor A, (eqv B, C))
2150  def : xxevalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;
2151  // (nor A, (nand B, C))
2152  def : xxevalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;
2153  // (nor A, (nor B, C))
2154  def : xxevalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;
2155  // (nor A, (xor B, C))
2156  def : xxevalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;
2157
2158  // OR
2159  // (or A, B, C)
2160  def : xxevalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;
2161  // (or A, (and B, C))
2162  def : xxevalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;
2163  // (or A, (eqv B, C))
2164  def : xxevalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;
2165  // (or A, (nand B, C))
2166  def : xxevalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;
2167  // (or A, (nor B, C))
2168  def : xxevalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;
2169  // (or A, (xor B, C))
2170  def : xxevalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;
2171
2172  // XOR
2173  // (xor A, B, C)
2174  def : xxevalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;
2175  // (xor A, (and B, C))
2176  def : xxevalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;
2177  // (xor A, (or B, C))
2178  def : xxevalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;
2179
2180  // Anonymous patterns to select prefixed VSX loads and stores.
2181  // Load / Store f128
2182  def : Pat<(f128 (load PDForm:$src)),
2183            (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>;
2184  def : Pat<(store f128:$XS, PDForm:$dst),
2185            (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>;
2186
2187  // Load / Store v4i32
2188  def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>;
2189  def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2190
2191  // Load / Store v2i64
2192  def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>;
2193  def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2194
2195  // Load / Store v4f32
2196  def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>;
2197  def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2198
2199  // Load / Store v2f64
2200  def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>;
2201  def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2202
2203  // Cases For PPCstore_scal_int_from_vsr
2204  def : Pat<(PPCstore_scal_int_from_vsr
2205            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), PDForm:$dst, 8),
2206            (PSTXSD (XSCVDPUXDS f64:$src), PDForm:$dst)>;
2207  def : Pat<(PPCstore_scal_int_from_vsr
2208            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), PDForm:$dst, 8),
2209            (PSTXSD (XSCVDPSXDS f64:$src), PDForm:$dst)>;
2210  def : Pat<(PPCstore_scal_int_from_vsr
2211            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), PDForm:$dst, 8),
2212            (PSTXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
2213                     PDForm:$dst)>;
2214  def : Pat<(PPCstore_scal_int_from_vsr
2215            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), PDForm:$dst, 8),
2216            (PSTXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
2217                     PDForm:$dst)>;
2218}
2219
2220let Predicates = [PrefixInstrs] in {
2221  def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
2222  def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
2223  def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
2224            (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
2225                                       (COPY_TO_REGCLASS $B, VSRC),
2226                                       (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
2227  def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),
2228            (COPY_TO_REGCLASS
2229                   (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC),
2230                              (COPY_TO_REGCLASS $B, VSRC),
2231                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2232  def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)),
2233            (COPY_TO_REGCLASS
2234                   (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC),
2235                              (COPY_TO_REGCLASS $B, VSRC),
2236                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2237  def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C),
2238            (XXBLENDVW $A, $B, $C)>;
2239  def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
2240            (XXBLENDVD $A, $B, $C)>;
2241
2242  // Anonymous patterns to select prefixed loads and stores.
2243  // Load i32
2244  def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2245  def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2246  def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2247  def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2248  def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2249  def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2250  def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>;
2251  def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>;
2252
2253  // Store i32
2254  def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>;
2255  def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>;
2256  def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>;
2257
2258  // Load i64
2259  def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2260  def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2261  def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2262  def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2263  def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2264  def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2265  def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>;
2266  def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2267  def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2268  def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>;
2269  def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>;
2270
2271  // Store i64
2272  def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>;
2273  def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;
2274  def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;
2275  def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;
2276
2277  // Load / Store f32
2278  def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;
2279  def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;
2280
2281  // Load / Store f64
2282  def : Pat<(f64 (extloadf32 PDForm:$src)),
2283            (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;
2284  def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;
2285  def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;
2286
2287  // Atomic Load
2288  def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>;
2289  def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>;
2290  def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>;
2291  def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>;
2292
2293  // Atomic Store
2294  def : Pat<(atomic_store_8 PDForm:$dst, i32:$RS), (PSTB $RS, memri34:$dst)>;
2295  def : Pat<(atomic_store_16 PDForm:$dst, i32:$RS), (PSTH $RS, memri34:$dst)>;
2296  def : Pat<(atomic_store_32 PDForm:$dst, i32:$RS), (PSTW $RS, memri34:$dst)>;
2297  def : Pat<(atomic_store_64 PDForm:$dst, i64:$RS), (PSTD $RS, memri34:$dst)>;
2298
2299  // Prefixed fpext to v2f64
2300  def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
2301            (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
2302}
2303
2304def InsertEltShift {
2305  dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32));
2306  dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30);
2307  dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29);
2308  dag Left1 = (RLWINM $rB, 1, 0, 30);
2309  dag Left2 = (RLWINM $rB, 2, 0, 29);
2310  dag Left3 = (RLWINM8 $rB, 3, 0, 28);
2311}
2312
2313let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
2314  // Indexed vector insert element
2315  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
2316            (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>;
2317  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
2318            (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2319  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2320            (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2321  def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2322            (VINSDRX $vDi, InsertEltShift.Left3, $rA)>;
2323
2324  def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)),
2325            (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
2326
2327  def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2328            (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2329  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
2330            (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2331  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
2332            (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2333  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
2334            (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2335  let AddedComplexity = 400 in {
2336    // Immediate vector insert element
2337    foreach Idx = [0, 1, 2, 3] in {
2338      def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)),
2339                (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>;
2340    }
2341    foreach i = [0, 1] in
2342     def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))),
2343               (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>;
2344  }
2345}
2346
2347let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
2348  // Indexed vector insert element
2349  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)),
2350            (VINSBLX $vDi, $rB, $rA)>;
2351  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)),
2352            (VINSHLX $vDi, InsertEltShift.Left1, $rA)>;
2353  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)),
2354            (VINSWLX $vDi, InsertEltShift.Left2, $rA)>;
2355
2356  def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i32:$rB)),
2357            (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>;
2358}
2359
2360let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
2361  // Indexed vector insert element
2362  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
2363            (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>;
2364  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
2365            (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2366  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2367            (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2368  def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2369            (VINSDLX $vDi, InsertEltShift.Left3, $rA)>;
2370
2371  def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i64:$rB)),
2372            (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
2373
2374  def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2375            (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2376  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
2377            (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2378  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
2379            (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2380  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
2381            (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2382}
2383
2384let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
2385  // Immediate vector insert element
2386  foreach Ty = [i32, i64] in {
2387    foreach Idx = [0, 1, 2, 3] in {
2388      def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))),
2389               (VINSW $vDi, !mul(Idx, 4), $rA)>;
2390    }
2391  }
2392
2393  foreach Idx = [0, 1] in
2394    def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)),
2395              (VINSD $vDi, !mul(Idx, 8), $rA)>;
2396}
2397