1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8// 9//===----------------------------------------------------------------------===// 10// 11// This file describes the instructions introduced for the Power10 CPU. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Naming convention for future instruction formats 17// 18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+ 19// 20// Where: 21// <INSTR_FORM> - name of instruction format as per the ISA 22// (X-Form, VX-Form, etc.) 23// <OP_TYPE> - operand type 24// * FRT/RT/VT/XT/BT - target register 25// (FPR, GPR, VR, VSR, CR-bit respectively) 26// In some situations, the 'T' is replaced by 27// 'D' when describing the target register. 28// * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.) 29// * IMM - immediate (where signedness matters, 30// this is SI/UI for signed/unsigned) 31// * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp) 32// * R - PC-Relative bit 33// (denotes that the address is computed pc-relative) 34// * VRM - Masked Registers 35// * AT - target accumulator 36// * N - the Nth bit in a VSR 37// * Additional 1-bit operands may be required for certain 38// instruction formats such as: MC, P, MP 39// * X / Y / P - mask values. In the instruction encoding, this is 40// represented as XMSK, YMSK and PMSK. 41// * MEM - indicates if the instruction format requires any memory 42// accesses. This does not have <OP_LENGTH> attached to it. 43// <OP_LENGTH> - the length of each operand in bits. 44// For operands that are 1 bit, the '1' is omitted from the name. 45// 46// Example: 8RR_XX4Form_IMM8_XTAB6 47// 8RR_XX4Form is the instruction format. 48// The operand is an 8-bit immediate (IMM), the destination (XT) 49// and sources (XA, XB) that are all 6-bits. The destination and 50// source registers are combined if they are of the same length. 51// Moreover, the order of operands reflects the order of operands 52// in the encoding. 53 54//-------------------------- Predicate definitions ---------------------------// 55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; 56 57 58//===----------------------------------------------------------------------===// 59// PowerPC ISA 3.1 specific type constraints. 60// 61 62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>, 63 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3> 64]>; 65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [ 66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>, 67 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32> 68]>; 69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ 70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> 71]>; 72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ 73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2> 74]>; 75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ 76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2> 77]>; 78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ 79 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> 80]>; 81 82//===----------------------------------------------------------------------===// 83// ISA 3.1 specific PPCISD nodes. 84// 85 86def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>; 87def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>; 88def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>; 89def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx, 90 []>; 91def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx, 92 []>; 93def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>; 94 95//===----------------------------------------------------------------------===// 96 97// PC Relative flag (for instructions that use the address of the prefix for 98// address computations). 99class isPCRel { bit PCRel = 1; } 100 101// PowerPC specific type constraints. 102def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [ 103 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 104]>; 105 106// PPC Specific DAG Nodes. 107def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, 108 [SDNPHasChain, SDNPMayLoad]>; 109 110// Top-level class for prefixed instructions. 111class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr, 112 InstrItinClass itin> : Instruction { 113 field bits<64> Inst; 114 field bits<64> SoftFail = 0; 115 bit PCRel = 0; // Default value, set by isPCRel. 116 let Size = 8; 117 118 let Namespace = "PPC"; 119 let OutOperandList = OOL; 120 let InOperandList = IOL; 121 let AsmString = asmstr; 122 let Itinerary = itin; 123 let Inst{0-5} = pref; 124 let Inst{32-37} = opcode; 125 126 bits<1> PPC970_First = 0; 127 bits<1> PPC970_Single = 0; 128 bits<1> PPC970_Cracked = 0; 129 bits<3> PPC970_Unit = 0; 130 131 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 132 /// these must be reflected there! See comments there for what these are. 133 let TSFlags{0} = PPC970_First; 134 let TSFlags{1} = PPC970_Single; 135 let TSFlags{2} = PPC970_Cracked; 136 let TSFlags{5-3} = PPC970_Unit; 137 138 bits<1> Prefixed = 1; // This is a prefixed instruction. 139 let TSFlags{7} = Prefixed; 140 141 // For cases where multiple instruction definitions really represent the 142 // same underlying instruction but with one definition for 64-bit arguments 143 // and one for 32-bit arguments, this bit breaks the degeneracy between 144 // the two forms and allows TableGen to generate mapping tables. 145 bit Interpretation64Bit = 0; 146 147 // Fields used for relation models. 148 string BaseName = ""; 149} 150 151// VX-Form: [ PO VT R VB RC XO ] 152class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr, 153 InstrItinClass itin, list<dag> pattern> 154 : I<4, OOL, IOL, asmstr, itin> { 155 bits<5> VT; 156 bits<5> VB; 157 bit RC = 0; 158 159 let Pattern = pattern; 160 161 let Inst{6-10} = VT; 162 let Inst{11-15} = R; 163 let Inst{16-20} = VB; 164 let Inst{21} = RC; 165 let Inst{22-31} = xo; 166} 167 168// Multiclass definition to account for record and non-record form 169// instructions of VXRForm. 170multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL, 171 string asmbase, string asmstr, 172 InstrItinClass itin, list<dag> pattern> { 173 let BaseName = asmbase in { 174 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL, 175 !strconcat(asmbase, !strconcat(" ", asmstr)), 176 itin, pattern>, RecFormRel; 177 let Defs = [CR6] in 178 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL, 179 !strconcat(asmbase, !strconcat(". ", asmstr)), 180 itin, []>, isRecordForm, RecFormRel; 181 } 182} 183 184class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 185 InstrItinClass itin, list<dag> pattern> 186 : PI<1, opcode, OOL, IOL, asmstr, itin> { 187 bits<5> RST; 188 bits<5> RA; 189 bits<34> D; 190 191 let Pattern = pattern; 192 193 // The prefix. 194 let Inst{6-7} = 2; 195 let Inst{8-10} = 0; 196 let Inst{11} = PCRel; 197 let Inst{12-13} = 0; 198 let Inst{14-31} = D{33-16}; // d0 199 200 // The instruction. 201 let Inst{38-42} = RST{4-0}; 202 let Inst{43-47} = RA; 203 let Inst{48-63} = D{15-0}; // d1 204} 205 206class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 207 InstrItinClass itin, list<dag> pattern> 208 : PI<1, opcode, OOL, IOL, asmstr, itin> { 209 bits<5> RT; 210 bits<5> RA; 211 bits<34> SI; 212 213 let Pattern = pattern; 214 215 // The prefix. 216 let Inst{6-7} = 2; 217 let Inst{8-10} = 0; 218 let Inst{11} = PCRel; 219 let Inst{12-13} = 0; 220 let Inst{14-31} = SI{33-16}; 221 222 // The instruction. 223 let Inst{38-42} = RT; 224 let Inst{43-47} = RA; 225 let Inst{48-63} = SI{15-0}; 226} 227 228class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 229 InstrItinClass itin, list<dag> pattern> 230 : PI<1, opcode, OOL, IOL, asmstr, itin> { 231 bits<5> RT; 232 bits<34> SI; 233 234 let Pattern = pattern; 235 236 // The prefix. 237 let Inst{6-7} = 2; 238 let Inst{8-10} = 0; 239 let Inst{11} = 0; 240 let Inst{12-13} = 0; 241 let Inst{14-31} = SI{33-16}; 242 243 // The instruction. 244 let Inst{38-42} = RT; 245 let Inst{43-47} = 0; 246 let Inst{48-63} = SI{15-0}; 247} 248 249multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 250 dag PCRel_IOL, string asmstr, 251 InstrItinClass itin> { 252 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 253 !strconcat(asmstr, ", 0"), itin, []>; 254 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 255 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 256} 257 258class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 259 InstrItinClass itin, list<dag> pattern> 260 : PI<1, opcode, OOL, IOL, asmstr, itin> { 261 bits<5> RST; 262 bits<5> RA; 263 bits<34> D; 264 265 let Pattern = pattern; 266 267 // The prefix. 268 let Inst{6-10} = 0; 269 let Inst{11} = PCRel; 270 let Inst{12-13} = 0; 271 let Inst{14-31} = D{33-16}; // d0 272 273 // The instruction. 274 let Inst{38-42} = RST{4-0}; 275 let Inst{43-47} = RA; 276 let Inst{48-63} = D{15-0}; // d1 277} 278 279// 8LS:D-Form: [ 1 0 0 // R // d0 280// PO TX T RA d1 ] 281class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL, 282 string asmstr, InstrItinClass itin, 283 list<dag> pattern> 284 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { 285 bits<6> XST; 286 bits<5> RA; 287 bits<34> D; 288 289 let Pattern = pattern; 290 291 // The prefix. 292 let Inst{6-7} = 0; 293 let Inst{8} = 0; 294 let Inst{9-10} = 0; // reserved 295 let Inst{11} = PCRel; 296 let Inst{12-13} = 0; // reserved 297 let Inst{14-31} = D{33-16}; // d0 298 299 // The instruction. 300 let Inst{37} = XST{5}; 301 let Inst{38-42} = XST{4-0}; 302 let Inst{43-47} = RA; 303 let Inst{48-63} = D{15-0}; // d1 304} 305 306// X-Form: [PO T IMM VRB XO TX] 307class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 308 string asmstr, InstrItinClass itin, list<dag> pattern> 309 : I<opcode, OOL, IOL, asmstr, itin> { 310 bits<6> XT; 311 bits<5> VRB; 312 bits<5> IMM; 313 314 let Pattern = pattern; 315 let Inst{6-10} = XT{4-0}; 316 let Inst{11-15} = IMM; 317 let Inst{16-20} = VRB; 318 let Inst{21-30} = xo; 319 let Inst{31} = XT{5}; 320} 321 322class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo, 323 dag OOL, dag IOL, string asmstr, 324 InstrItinClass itin, list<dag> pattern> 325 : PI<1, opcode, OOL, IOL, asmstr, itin> { 326 bits<6> XT; 327 bits<6> XA; 328 bits<6> XB; 329 bits<6> XC; 330 bits<8> IMM; 331 332 let Pattern = pattern; 333 334 // The prefix. 335 let Inst{6-7} = 1; 336 let Inst{8} = 0; 337 let Inst{9-11} = 0; 338 let Inst{12-13} = 0; 339 let Inst{14-23} = 0; 340 let Inst{24-31} = IMM; 341 342 // The instruction. 343 let Inst{38-42} = XT{4-0}; 344 let Inst{43-47} = XA{4-0}; 345 let Inst{48-52} = XB{4-0}; 346 let Inst{53-57} = XC{4-0}; 347 let Inst{58-59} = xo; 348 let Inst{60} = XC{5}; 349 let Inst{61} = XA{5}; 350 let Inst{62} = XB{5}; 351 let Inst{63} = XT{5}; 352} 353 354class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 355 InstrItinClass itin, list<dag> pattern> 356 : I<4, OOL, IOL, asmstr, itin> { 357 bits<5> RD; 358 bits<5> VB; 359 bits<3> N; 360 361 let Pattern = pattern; 362 363 let Inst{6-10} = RD; 364 let Inst{11-12} = 0; 365 let Inst{13-15} = N; 366 let Inst{16-20} = VB; 367 let Inst{21-31} = xo; 368} 369 370 371// VX-Form: [PO VRT RA VRB XO]. 372// Destructive (insert) forms are suffixed with _ins. 373class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> 374 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB), 375 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>, 376 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 377 378// VX-Form: [PO VRT RA RB XO]. 379// Destructive (insert) forms are suffixed with _ins. 380class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> 381 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB), 382 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>, 383 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 384 385// VX-Form: [ PO BF // VRA VRB XO ] 386class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 387 InstrItinClass itin, list<dag> pattern> 388 : I<4, OOL, IOL, asmstr, itin> { 389 bits<3> BF; 390 bits<5> VA; 391 bits<5> VB; 392 393 let Pattern = pattern; 394 395 let Inst{6-8} = BF; 396 let Inst{9-10} = 0; 397 let Inst{11-15} = VA; 398 let Inst{16-20} = VB; 399 let Inst{21-31} = xo; 400} 401 402// VN-Form: [PO VRT VRA VRB PS SD XO] 403// SD is "Shift Direction" 404class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, 405 InstrItinClass itin, list<dag> pattern> 406 : I<4, OOL, IOL, asmstr, itin> { 407 bits<5> VRT; 408 bits<5> VRA; 409 bits<5> VRB; 410 bits<3> SD; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = VRT; 415 let Inst{11-15} = VRA; 416 let Inst{16-20} = VRB; 417 let Inst{21-22} = ps; 418 let Inst{23-25} = SD; 419 let Inst{26-31} = xo; 420} 421 422class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 423 string asmstr, InstrItinClass itin, list<dag> pattern> 424 : I<4, OOL, IOL, asmstr, itin> { 425 bits<5> RD; 426 bits<5> VB; 427 bit MP; 428 429 let Pattern = pattern; 430 431 let Inst{6-10} = RD; 432 let Inst{11-14} = eo; 433 let Inst{15} = MP; 434 let Inst{16-20} = VB; 435 let Inst{21-31} = xo; 436} 437 438// 8RR:D-Form: [ 1 1 0 // // imm0 439// PO T XO TX imm1 ]. 440class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 441 string asmstr, InstrItinClass itin, 442 list<dag> pattern> 443 : PI<1, opcode, OOL, IOL, asmstr, itin> { 444 bits<6> XT; 445 bits<32> IMM32; 446 447 let Pattern = pattern; 448 449 // The prefix. 450 let Inst{6-7} = 1; 451 let Inst{8-11} = 0; 452 let Inst{12-13} = 0; // reserved 453 let Inst{14-15} = 0; // reserved 454 let Inst{16-31} = IMM32{31-16}; 455 456 // The instruction. 457 let Inst{38-42} = XT{4-0}; 458 let Inst{43-46} = xo; 459 let Inst{47} = XT{5}; 460 let Inst{48-63} = IMM32{15-0}; 461} 462 463// 8RR:D-Form: [ 1 1 0 // // imm0 464// PO T XO IX TX imm1 ]. 465class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 466 string asmstr, InstrItinClass itin, 467 list<dag> pattern> 468 : PI<1, opcode, OOL, IOL, asmstr, itin> { 469 bits<6> XT; 470 bit IX; 471 bits<32> IMM32; 472 473 let Pattern = pattern; 474 475 // The prefix. 476 let Inst{6-7} = 1; 477 let Inst{8-11} = 0; 478 let Inst{12-13} = 0; // reserved 479 let Inst{14-15} = 0; // reserved 480 let Inst{16-31} = IMM32{31-16}; 481 482 // The instruction. 483 let Inst{38-42} = XT{4-0}; 484 let Inst{43-45} = xo; 485 let Inst{46} = IX; 486 let Inst{47} = XT{5}; 487 let Inst{48-63} = IMM32{15-0}; 488} 489 490class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 491 string asmstr, InstrItinClass itin, list<dag> pattern> 492 : PI<1, opcode, OOL, IOL, asmstr, itin> { 493 bits<6> XT; 494 bits<6> XA; 495 bits<6> XB; 496 bits<6> XC; 497 498 let Pattern = pattern; 499 500 // The prefix. 501 let Inst{6-7} = 1; 502 let Inst{8-11} = 0; 503 let Inst{12-13} = 0; 504 let Inst{14-31} = 0; 505 506 // The instruction. 507 let Inst{38-42} = XT{4-0}; 508 let Inst{43-47} = XA{4-0}; 509 let Inst{48-52} = XB{4-0}; 510 let Inst{53-57} = XC{4-0}; 511 let Inst{58-59} = xo; 512 let Inst{60} = XC{5}; 513 let Inst{61} = XA{5}; 514 let Inst{62} = XB{5}; 515 let Inst{63} = XT{5}; 516} 517 518class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 519 string asmstr, InstrItinClass itin, 520 list<dag> pattern> 521 : PI<1, opcode, OOL, IOL, asmstr, itin> { 522 bits<6> XT; 523 bits<6> XA; 524 bits<6> XB; 525 bits<6> XC; 526 bits<3> IMM; 527 528 let Pattern = pattern; 529 530 // The prefix. 531 let Inst{6-7} = 1; 532 let Inst{8-11} = 0; 533 let Inst{12-13} = 0; 534 let Inst{14-28} = 0; 535 let Inst{29-31} = IMM; 536 537 // The instruction. 538 let Inst{38-42} = XT{4-0}; 539 let Inst{43-47} = XA{4-0}; 540 let Inst{48-52} = XB{4-0}; 541 let Inst{53-57} = XC{4-0}; 542 let Inst{58-59} = xo; 543 let Inst{60} = XC{5}; 544 let Inst{61} = XA{5}; 545 let Inst{62} = XB{5}; 546 let Inst{63} = XT{5}; 547} 548 549// [PO BF / XO2 B XO BX /] 550class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, 551 dag IOL, string asmstr, InstrItinClass itin, 552 list<dag> pattern> 553 : I<opcode, OOL, IOL, asmstr, itin> { 554 bits<3> BF; 555 bits<6> XB; 556 557 let Pattern = pattern; 558 559 let Inst{6-8} = BF; 560 let Inst{9-10} = 0; 561 let Inst{11-15} = xo2; 562 let Inst{16-20} = XB{4-0}; 563 let Inst{21-29} = xo; 564 let Inst{30} = XB{5}; 565 let Inst{31} = 0; 566} 567 568// X-Form: [ PO RT BI /// XO / ] 569class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 570 string asmstr, InstrItinClass itin, list<dag> pattern> 571 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 572 bits<5> BI; 573 let RA = BI; 574 let RB = 0; 575} 576 577multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 578 dag PCRel_IOL, dag PCRelOnly_IOL, 579 string asmstr, string asmstr_pcext, 580 InstrItinClass itin> { 581 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 582 !strconcat(asmstr, ", 0"), itin, []>; 583 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 584 !strconcat(asmstr, ", 1"), itin, []>, 585 isPCRel; 586 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 587 def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 588 let RA = 0 in 589 def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL, 590 asmstr_pcext, itin, []>, isPCRel; 591 } 592} 593 594multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 595 dag PCRel_IOL, dag PCRelOnly_IOL, 596 string asmstr, string asmstr_pcext, 597 InstrItinClass itin> { 598 def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 599 !strconcat(asmstr, ", 0"), itin, []>; 600 def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 601 !strconcat(asmstr, ", 1"), itin, []>, 602 isPCRel; 603 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 604 def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 605 let RA = 0 in 606 def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL, 607 asmstr_pcext, itin, []>, isPCRel; 608 } 609} 610 611multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL, 612 dag PCRel_IOL, dag PCRelOnly_IOL, 613 string asmstr, string asmstr_pcext, 614 InstrItinClass itin> { 615 def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, 616 !strconcat(asmstr, ", 0"), itin, []>; 617 def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL, 618 !strconcat(asmstr, ", 1"), itin, []>, 619 isPCRel; 620 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 621 def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 622 let RA = 0 in 623 def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL, 624 asmstr_pcext, itin, []>, isPCRel; 625 } 626} 627 628def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; 629def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; 630def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; 631def RCCp { 632 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); 633 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); 634} 635 636let Predicates = [PrefixInstrs] in { 637 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 638 defm PADDI8 : 639 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI), 640 (ins immZero:$RA, s34imm_pcrel:$SI), 641 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 642 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 643 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 644 (ins s34imm:$SI), 645 "pli $RT, $SI", IIC_IntSimple, []>; 646 } 647 } 648 defm PADDI : 649 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI), 650 (ins immZero:$RA, s34imm_pcrel:$SI), 651 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 652 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 653 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 654 (ins s34imm:$SI), 655 "pli $RT, $SI", IIC_IntSimple, []>; 656 } 657 658 let mayLoad = 1, mayStore = 0 in { 659 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 660 defm PLBZ8 : 661 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 662 (ins (memri34_pcrel $D, $RA):$addr), 663 (ins s34imm_pcrel:$D), "plbz $RST, $addr", 664 "plbz $RST, $D", IIC_LdStLFD>; 665 defm PLHZ8 : 666 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 667 (ins (memri34_pcrel $D, $RA):$addr), 668 (ins s34imm_pcrel:$D), "plhz $RST, $addr", 669 "plhz $RST, $D", IIC_LdStLFD>; 670 defm PLHA8 : 671 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 672 (ins (memri34_pcrel $D, $RA):$addr), 673 (ins s34imm_pcrel:$D), "plha $RST, $addr", 674 "plha $RST, $D", IIC_LdStLFD>; 675 defm PLWA8 : 676 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 677 (ins (memri34_pcrel $D, $RA):$addr), 678 (ins s34imm_pcrel:$D), 679 "plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>; 680 defm PLWZ8 : 681 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 682 (ins (memri34_pcrel $D, $RA):$addr), 683 (ins s34imm_pcrel:$D), "plwz $RST, $addr", 684 "plwz $RST, $D", IIC_LdStLFD>; 685 } 686 defm PLBZ : 687 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 688 (ins (memri34_pcrel $D, $RA):$addr), 689 (ins s34imm_pcrel:$D), "plbz $RST, $addr", 690 "plbz $RST, $D", IIC_LdStLFD>; 691 defm PLHZ : 692 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 693 (ins (memri34_pcrel $D, $RA):$addr), 694 (ins s34imm_pcrel:$D), "plhz $RST, $addr", 695 "plhz $RST, $D", IIC_LdStLFD>; 696 defm PLHA : 697 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 698 (ins (memri34_pcrel $D, $RA):$addr), 699 (ins s34imm_pcrel:$D), "plha $RST, $addr", 700 "plha $RST, $D", IIC_LdStLFD>; 701 defm PLWZ : 702 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 703 (ins (memri34_pcrel $D, $RA):$addr), 704 (ins s34imm_pcrel:$D), "plwz $RST, $addr", 705 "plwz $RST, $D", IIC_LdStLFD>; 706 defm PLWA : 707 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 708 (ins (memri34_pcrel $D, $RA):$addr), 709 (ins s34imm_pcrel:$D), 710 "plwa $RST, $addr", "plwa $RST, $D", 711 IIC_LdStLFD>; 712 defm PLD : 713 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 714 (ins (memri34_pcrel $D, $RA):$addr), 715 (ins s34imm_pcrel:$D), 716 "pld $RST, $addr", "pld $RST, $D", 717 IIC_LdStLFD>; 718 } 719 720 let mayStore = 1, mayLoad = 0 in { 721 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 722 defm PSTB8 : 723 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 724 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 725 (ins g8rc:$RST, s34imm_pcrel:$D), 726 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>; 727 defm PSTH8 : 728 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 729 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 730 (ins g8rc:$RST, s34imm_pcrel:$D), 731 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>; 732 defm PSTW8 : 733 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 734 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 735 (ins g8rc:$RST, s34imm_pcrel:$D), 736 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>; 737 } 738 defm PSTB : 739 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 740 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 741 (ins gprc:$RST, s34imm_pcrel:$D), 742 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>; 743 defm PSTH : 744 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 745 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 746 (ins gprc:$RST, s34imm_pcrel:$D), 747 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>; 748 defm PSTW : 749 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 750 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 751 (ins gprc:$RST, s34imm_pcrel:$D), 752 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>; 753 defm PSTD : 754 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 755 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 756 (ins g8rc:$RST, s34imm_pcrel:$D), 757 "pstd $RST, $addr", "pstd $RST, $D", IIC_LdStLFD>; 758 } 759} 760 761let Predicates = [PrefixInstrs, HasFPU] in { 762 let mayLoad = 1, mayStore = 0 in { 763 defm PLFS : 764 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr), 765 (ins (memri34_pcrel $D, $RA):$addr), 766 (ins s34imm_pcrel:$D), "plfs $RST, $addr", 767 "plfs $RST, $D", IIC_LdStLFD>; 768 defm PLFD : 769 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr), 770 (ins (memri34_pcrel $D, $RA):$addr), 771 (ins s34imm_pcrel:$D), "plfd $RST, $addr", 772 "plfd $RST, $D", IIC_LdStLFD>; 773 } 774 let mayStore = 1, mayLoad = 0 in { 775 defm PSTFS : 776 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr), 777 (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr), 778 (ins f4rc:$RST, s34imm_pcrel:$D), 779 "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>; 780 defm PSTFD : 781 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr), 782 (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr), 783 (ins f8rc:$RST, s34imm_pcrel:$D), 784 "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>; 785 } 786} 787 788let Predicates = [PrefixInstrs, HasP10Vector] in { 789 let mayLoad = 1, mayStore = 0 in { 790 defm PLXV : 791 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr), 792 (ins (memri34_pcrel $D, $RA):$addr), 793 (ins s34imm_pcrel:$D), 794 "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>; 795 defm PLXSSP : 796 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr), 797 (ins (memri34_pcrel $D, $RA):$addr), 798 (ins s34imm_pcrel:$D), 799 "plxssp $RST, $addr", "plxssp $RST, $D", 800 IIC_LdStLFD>; 801 defm PLXSD : 802 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr), 803 (ins (memri34_pcrel $D, $RA):$addr), 804 (ins s34imm_pcrel:$D), 805 "plxsd $RST, $addr", "plxsd $RST, $D", 806 IIC_LdStLFD>; 807 } 808 let mayStore = 1, mayLoad = 0 in { 809 defm PSTXV : 810 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr), 811 (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr), 812 (ins vsrc:$XST, s34imm_pcrel:$D), 813 "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>; 814 defm PSTXSSP : 815 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr), 816 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr), 817 (ins vfrc:$RST, s34imm_pcrel:$D), 818 "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>; 819 defm PSTXSD : 820 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr), 821 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr), 822 (ins vfrc:$RST, s34imm_pcrel:$D), 823 "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>; 824 } 825 def XXPERMX : 826 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 827 vsrc:$XC, u3imm:$IMM), 828 "xxpermx $XT, $XA, $XB, $XC, $IMM", 829 IIC_VecPerm, []>; 830 def XXBLENDVB : 831 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 832 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", 833 IIC_VecGeneral, []>; 834 def XXBLENDVH : 835 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 836 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", 837 IIC_VecGeneral, []>; 838 def XXBLENDVW : 839 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 840 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC", 841 IIC_VecGeneral, []>; 842 def XXBLENDVD : 843 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 844 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC", 845 IIC_VecGeneral, []>; 846} 847 848class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 849 string asmstr, InstrItinClass itin, list<dag> pattern> 850 : I<opcode, OOL, IOL, asmstr, itin> { 851 bits<5> XTp; 852 bits<5> RA; 853 bits<12> DQ; 854 855 let Pattern = pattern; 856 857 let Inst{6-9} = XTp{3-0}; 858 let Inst{10} = XTp{4}; 859 let Inst{11-15} = RA; 860 let Inst{16-27} = DQ; 861 let Inst{28-31} = xo; 862} 863 864class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 865 string asmstr, InstrItinClass itin, list<dag> pattern> 866 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { 867 bits<5> XTp; 868 bits<5> RA; 869 bits<5> RB; 870 871 let Pattern = pattern; 872 let Inst{6-9} = XTp{3-0}; 873 let Inst{10} = XTp{4}; 874 let Inst{11-15} = RA; 875 let Inst{16-20} = RB; 876 let Inst{21-30} = xo; 877 let Inst{31} = 0; 878} 879 880class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 881 InstrItinClass itin, list<dag> pattern> 882 : PI<1, opcode, OOL, IOL, asmstr, itin> { 883 bits<5> XTp; 884 bits<5> RA; 885 bits<34> D; 886 887 let Pattern = pattern; 888 889 // The prefix. 890 let Inst{6-10} = 0; 891 let Inst{11} = PCRel; 892 let Inst{12-13} = 0; 893 let Inst{14-31} = D{33-16}; // Imm18 894 895 // The instruction. 896 let Inst{38-41} = XTp{3-0}; 897 let Inst{42} = XTp{4}; 898 let Inst{43-47} = RA; 899 let Inst{48-63} = D{15-0}; 900} 901 902multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL, 903 dag IOL, dag PCRel_IOL, dag PCRelOnly_IOL, 904 string asmstr, string asmstr_pcext, 905 InstrItinClass itin> { 906 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, 907 !strconcat(asmstr, ", 0"), itin, []>; 908 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL, 909 !strconcat(asmstr, ", 1"), itin, []>, 910 isPCRel; 911 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 912 def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>; 913 let RA = 0 in 914 def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL, 915 asmstr_pcext, itin, []>, isPCRel; 916 } 917} 918 919 920 921// [PO AS XO2 XO] 922class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 923 string asmstr, InstrItinClass itin, list<dag> pattern> 924 : I<opcode, OOL, IOL, asmstr, itin> { 925 bits<3> AT; 926 927 let Pattern = pattern; 928 929 let Inst{6-8} = AT; 930 let Inst{9-10} = 0; 931 let Inst{11-15} = xo2; 932 let Inst{16-20} = 0; 933 let Inst{21-30} = xo; 934 let Inst{31} = 0; 935} 936 937// X-Form: [ PO T EO UIM XO TX ] 938class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL, 939 string asmstr, InstrItinClass itin, list<dag> pattern> 940 : I<opcode, OOL, IOL, asmstr, itin> { 941 bits<6> XT; 942 bits<5> UIM; 943 944 let Pattern = pattern; 945 946 let Inst{6-10} = XT{4-0}; 947 let Inst{11-15} = eo; 948 let Inst{16-20} = UIM; 949 let Inst{21-30} = xo; 950 let Inst{31} = XT{5}; 951} 952 953class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 954 string asmstr, InstrItinClass itin, 955 list<dag> pattern> 956 : I<opcode, OOL, IOL, asmstr, itin> { 957 bits<3> AT; 958 bits<6> XA; 959 bits<6> XB; 960 961 let Pattern = pattern; 962 963 let Inst{6-8} = AT; 964 let Inst{9-10} = 0; 965 let Inst{11-15} = XA{4-0}; 966 let Inst{16-20} = XB{4-0}; 967 let Inst{21-28} = xo; 968 let Inst{29} = XA{5}; 969 let Inst{30} = XB{5}; 970 let Inst{31} = 0; 971} 972 973class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 974 string asmstr, InstrItinClass itin, 975 list<dag> pattern> 976 : PI<1, opcode, OOL, IOL, asmstr, itin> { 977 bits<3> AT; 978 bits<6> XA; 979 bits<6> XB; 980 bits<4> XMSK; 981 bits<4> YMSK; 982 bits<2> PMSK; 983 984 let Pattern = pattern; 985 986 // The prefix. 987 let Inst{6-7} = 3; 988 let Inst{8-11} = 9; 989 let Inst{12-15} = 0; 990 let Inst{16-17} = PMSK; 991 let Inst{18-23} = 0; 992 let Inst{24-27} = XMSK; 993 let Inst{28-31} = YMSK; 994 995 // The instruction. 996 let Inst{38-40} = AT; 997 let Inst{41-42} = 0; 998 let Inst{43-47} = XA{4-0}; 999 let Inst{48-52} = XB{4-0}; 1000 let Inst{53-60} = xo; 1001 let Inst{61} = XA{5}; 1002 let Inst{62} = XB{5}; 1003 let Inst{63} = 0; 1004} 1005 1006class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1007 string asmstr, InstrItinClass itin, 1008 list<dag> pattern> 1009 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1010 bits<3> AT; 1011 bits<6> XA; 1012 bits<6> XB; 1013 bits<4> XMSK; 1014 bits<4> YMSK; 1015 1016 let Pattern = pattern; 1017 1018 // The prefix. 1019 let Inst{6-7} = 3; 1020 let Inst{8-11} = 9; 1021 let Inst{12-23} = 0; 1022 let Inst{24-27} = XMSK; 1023 let Inst{28-31} = YMSK; 1024 1025 // The instruction. 1026 let Inst{38-40} = AT; 1027 let Inst{41-42} = 0; 1028 let Inst{43-47} = XA{4-0}; 1029 let Inst{48-52} = XB{4-0}; 1030 let Inst{53-60} = xo; 1031 let Inst{61} = XA{5}; 1032 let Inst{62} = XB{5}; 1033 let Inst{63} = 0; 1034} 1035 1036class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1037 string asmstr, InstrItinClass itin, 1038 list<dag> pattern> 1039 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1040 bits<3> AT; 1041 bits<6> XA; 1042 bits<6> XB; 1043 bits<4> XMSK; 1044 bits<2> YMSK; 1045 1046 let Pattern = pattern; 1047 1048 // The prefix. 1049 let Inst{6-7} = 3; 1050 let Inst{8-11} = 9; 1051 let Inst{12-23} = 0; 1052 let Inst{24-27} = XMSK; 1053 let Inst{28-29} = YMSK; 1054 let Inst{30-31} = 0; 1055 1056 // The instruction. 1057 let Inst{38-40} = AT; 1058 let Inst{41-42} = 0; 1059 let Inst{43-47} = XA{4-0}; 1060 let Inst{48-52} = XB{4-0}; 1061 let Inst{53-60} = xo; 1062 let Inst{61} = XA{5}; 1063 let Inst{62} = XB{5}; 1064 let Inst{63} = 0; 1065} 1066 1067class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1068 string asmstr, InstrItinClass itin, 1069 list<dag> pattern> 1070 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1071 bits<3> AT; 1072 bits<6> XA; 1073 bits<6> XB; 1074 bits<4> XMSK; 1075 bits<4> YMSK; 1076 bits<8> PMSK; 1077 1078 let Pattern = pattern; 1079 1080 // The prefix. 1081 let Inst{6-7} = 3; 1082 let Inst{8-11} = 9; 1083 let Inst{12-15} = 0; 1084 let Inst{16-23} = PMSK; 1085 let Inst{24-27} = XMSK; 1086 let Inst{28-31} = YMSK; 1087 1088 // The instruction. 1089 let Inst{38-40} = AT; 1090 let Inst{41-42} = 0; 1091 let Inst{43-47} = XA{4-0}; 1092 let Inst{48-52} = XB{4-0}; 1093 let Inst{53-60} = xo; 1094 let Inst{61} = XA{5}; 1095 let Inst{62} = XB{5}; 1096 let Inst{63} = 0; 1097} 1098 1099class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1100 string asmstr, InstrItinClass itin, 1101 list<dag> pattern> 1102 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1103 bits<3> AT; 1104 bits<6> XA; 1105 bits<6> XB; 1106 bits<4> XMSK; 1107 bits<4> YMSK; 1108 bits<4> PMSK; 1109 1110 let Pattern = pattern; 1111 1112 // The prefix. 1113 let Inst{6-7} = 3; 1114 let Inst{8-11} = 9; 1115 let Inst{12-15} = 0; 1116 let Inst{16-19} = PMSK; 1117 let Inst{20-23} = 0; 1118 let Inst{24-27} = XMSK; 1119 let Inst{28-31} = YMSK; 1120 1121 // The instruction. 1122 let Inst{38-40} = AT; 1123 let Inst{41-42} = 0; 1124 let Inst{43-47} = XA{4-0}; 1125 let Inst{48-52} = XB{4-0}; 1126 let Inst{53-60} = xo; 1127 let Inst{61} = XA{5}; 1128 let Inst{62} = XB{5}; 1129 let Inst{63} = 0; 1130} 1131 1132 1133 1134def Concats { 1135 dag VecsToVecPair0 = 1136 (v256i1 (INSERT_SUBREG 1137 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1138 $vs1, sub_vsx0)); 1139 dag VecsToVecPair1 = 1140 (v256i1 (INSERT_SUBREG 1141 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1142 $vs3, sub_vsx0)); 1143} 1144 1145let Predicates = [PairedVectorMemops] in { 1146 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)), 1147 Concats.VecsToVecPair0>; 1148 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), 1149 Concats.VecsToVecPair0>; 1150 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)), 1151 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; 1152 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), 1153 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; 1154 1155 let mayLoad = 1, mayStore = 0 in { 1156 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), 1157 (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr", 1158 IIC_LdStLFD, []>; 1159 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr), 1160 "lxvpx $XTp, $addr", IIC_LdStLFD, 1161 []>; 1162 } 1163 1164 let mayLoad = 0, mayStore = 1 in { 1165 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, 1166 (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr", 1167 IIC_LdStLFD, []>; 1168 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr), 1169 "stxvpx $XTp, $addr", IIC_LdStLFD, 1170 []>; 1171 } 1172} 1173let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1174 defm PLXVP : 1175 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr), 1176 (ins (memri34_pcrel $D, $RA):$addr), 1177 (ins s34imm_pcrel:$D), 1178 "plxvp $XTp, $addr", "plxvp $XTp, $D", 1179 IIC_LdStLFD>; 1180} 1181 1182let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1183 defm PSTXVP : 1184 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr), 1185 (ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr), 1186 (ins vsrprc:$XTp, s34imm_pcrel:$D), 1187 "pstxvp $XTp, $addr", "pstxvp $XTp, $D", IIC_LdStLFD>; 1188} 1189 1190let Predicates = [PairedVectorMemops] in { 1191 // Intrinsics for Paired Vector Loads. 1192 def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>; 1193 def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>; 1194 let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1195 def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>; 1196 } 1197 // Intrinsics for Paired Vector Stores. 1198 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst), 1199 (STXVP $XSp, memrix16:$dst)>; 1200 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst), 1201 (STXVPX $XSp, XForm:$dst)>; 1202 let Predicates = [PairedVectorMemops, PrefixInstrs, HasP10Vector] in { 1203 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst), 1204 (PSTXVP $XSp, memri34:$dst)>; 1205 } 1206} 1207 1208let Predicates = [IsISA3_1] in { 1209 def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>; 1210 def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>; 1211 def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>; 1212} 1213 1214let Predicates = [PCRelativeMemops] in { 1215 // Load i32 1216 def : Pat<(i32 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1217 (PLBZpc $ga, 0)>; 1218 def : Pat<(i32 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1219 (PLBZpc $ga, 0)>; 1220 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1221 (PLBZpc $ga, 0)>; 1222 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1223 (PLBZpc $ga, 0)>; 1224 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1225 (PLHApc $ga, 0)>; 1226 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1227 (PLHZpc $ga, 0)>; 1228 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1229 (PLHZpc $ga, 0)>; 1230 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>; 1231 1232 // Store i32 1233 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1234 (PSTBpc $RS, $ga, 0)>; 1235 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1236 (PSTHpc $RS, $ga, 0)>; 1237 def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1238 (PSTWpc $RS, $ga, 0)>; 1239 1240 // Load i64 1241 def : Pat<(i64 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1242 (PLBZ8pc $ga, 0)>; 1243 def : Pat<(i64 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1244 (PLBZ8pc $ga, 0)>; 1245 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1246 (PLBZ8pc $ga, 0)>; 1247 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1248 (PLBZ8pc $ga, 0)>; 1249 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1250 (PLHA8pc $ga, 0)>; 1251 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1252 (PLHZ8pc $ga, 0)>; 1253 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1254 (PLHZ8pc $ga, 0)>; 1255 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1256 (PLWZ8pc $ga, 0)>; 1257 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1258 (PLWA8pc $ga, 0)>; 1259 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1260 (PLWZ8pc $ga, 0)>; 1261 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>; 1262 1263 // Store i64 1264 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1265 (PSTB8pc $RS, $ga, 0)>; 1266 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1267 (PSTH8pc $RS, $ga, 0)>; 1268 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1269 (PSTW8pc $RS, $ga, 0)>; 1270 def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1271 (PSTDpc $RS, $ga, 0)>; 1272 1273 // Atomic Load 1274 def : Pat<(i32 (atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga))), 1275 (PLBZpc $ga, 0)>; 1276 def : Pat<(i32 (atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga))), 1277 (PLHZpc $ga, 0)>; 1278 def : Pat<(i32 (atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga))), 1279 (PLWZpc $ga, 0)>; 1280 def : Pat<(i64 (atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga))), 1281 (PLDpc $ga, 0)>; 1282 1283 // Atomic Store 1284 def : Pat<(atomic_store_8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1285 (PSTBpc $RS, $ga, 0)>; 1286 def : Pat<(atomic_store_16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1287 (PSTHpc $RS, $ga, 0)>; 1288 def : Pat<(atomic_store_32 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1289 (PSTWpc $RS, $ga, 0)>; 1290 def : Pat<(atomic_store_8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1291 (PSTB8pc $RS, $ga, 0)>; 1292 def : Pat<(atomic_store_16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1293 (PSTH8pc $RS, $ga, 0)>; 1294 def : Pat<(atomic_store_32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1295 (PSTW8pc $RS, $ga, 0)>; 1296 def : Pat<(atomic_store_64 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1297 (PSTDpc $RS, $ga, 0)>; 1298 1299 // If the PPCmatpcreladdr node is not caught by any other pattern it should be 1300 // caught here and turned into a paddi instruction to materialize the address. 1301 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1302 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize 1303 // tls global address with paddi instruction. 1304 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1305 // PPCtlslocalexecmataddr node is used for TLS local exec models to 1306 // materialize tls global address with paddi instruction. 1307 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), 1308 (PADDI8 $in, $addr)>; 1309} 1310 1311let Predicates = [PCRelativeMemops, HasFPU] in { 1312 // Load f32 1313 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>; 1314 1315 // Store f32 1316 def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1317 (PSTFSpc $FRS, $ga, 0)>; 1318 1319 // Load f64 1320 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))), 1321 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>; 1322 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>; 1323 1324 // Store f64 1325 def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1326 (PSTFDpc $FRS, $ga, 0)>; 1327 1328 def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), 1329 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; 1330} 1331 1332let Predicates = [PCRelativeMemops, HasP10Vector] in { 1333 // Load f128 1334 def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))), 1335 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>; 1336 1337 // Store f128 1338 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1339 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>; 1340 1341 // Load v4i32 1342 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1343 1344 // Store v4i32 1345 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1346 (PSTXVpc $XS, $ga, 0)>; 1347 1348 // Load v2i64 1349 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1350 1351 // Store v2i64 1352 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1353 (PSTXVpc $XS, $ga, 0)>; 1354 1355 // Load v4f32 1356 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1357 1358 // Store v4f32 1359 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1360 (PSTXVpc $XS, $ga, 0)>; 1361 1362 // Load v2f64 1363 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1364 1365 // Store v2f64 1366 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1367 (PSTXVpc $XS, $ga, 0)>; 1368 1369 // Special Cases For PPCstore_scal_int_from_vsr 1370 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8), 1371 (PSTXSDpc $src, $dst, 0)>; 1372 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8), 1373 (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>; 1374} 1375 1376// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt 1377// to spill part of the instruction when the values are similar. 1378let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in { 1379 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT), 1380 (ins i32imm:$IMM32), 1381 "xxspltiw $XT, $IMM32", IIC_VecGeneral, 1382 []>; 1383 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT), 1384 (ins i32imm:$IMM32), 1385 "xxspltidp $XT, $IMM32", IIC_VecGeneral, 1386 [(set v2f64:$XT, 1387 (PPCxxspltidp i32:$IMM32))]>; 1388 def XXSPLTI32DX : 1389 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT), 1390 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32), 1391 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, 1392 [(set v2i64:$XT, 1393 (PPCxxsplti32dx v2i64:$XTi, i32:$IX, 1394 i32:$IMM32))]>, 1395 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1396} 1397 1398let Predicates = [IsISA3_1] in { 1399 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI), 1400 "setbc $RST, $BI", IIC_IntCompare, []>, 1401 SExt32To64, ZExt32To64; 1402 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI), 1403 "setbcr $RST, $BI", IIC_IntCompare, []>, 1404 SExt32To64, ZExt32To64; 1405 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI), 1406 "setnbc $RST, $BI", IIC_IntCompare, []>, 1407 SExt32To64; 1408 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI), 1409 "setnbcr $RST, $BI", IIC_IntCompare, []>, 1410 SExt32To64; 1411 1412 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1413 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI), 1414 "setbc $RST, $BI", IIC_IntCompare, []>, 1415 SExt32To64, ZExt32To64; 1416 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI), 1417 "setbcr $RST, $BI", IIC_IntCompare, []>, 1418 SExt32To64, ZExt32To64; 1419 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI), 1420 "setnbc $RST, $BI", IIC_IntCompare, []>, 1421 SExt32To64; 1422 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI), 1423 "setnbcr $RST, $BI", IIC_IntCompare, []>, 1424 SExt32To64; 1425 } 1426 1427 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), 1428 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), 1429 "vsldbi $VRT, $VRA, $VRB, $SD", 1430 IIC_VecGeneral, 1431 [(set v16i8:$VRT, 1432 (int_ppc_altivec_vsldbi v16i8:$VRA, 1433 v16i8:$VRB, 1434 timm:$SD))]>; 1435 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), 1436 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), 1437 "vsrdbi $VRT, $VRA, $VRB, $SD", 1438 IIC_VecGeneral, 1439 [(set v16i8:$VRT, 1440 (int_ppc_altivec_vsrdbi v16i8:$VRA, 1441 v16i8:$VRB, 1442 timm:$SD))]>; 1443 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB), 1444 "vstribr", "$VT, $VB", IIC_VecGeneral, 1445 [(set v16i8:$VT, 1446 (int_ppc_altivec_vstribr v16i8:$VB))]>; 1447 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB), 1448 "vstribl", "$VT, $VB", IIC_VecGeneral, 1449 [(set v16i8:$VT, 1450 (int_ppc_altivec_vstribl v16i8:$VB))]>; 1451 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB), 1452 "vstrihr", "$VT, $VB", IIC_VecGeneral, 1453 [(set v8i16:$VT, 1454 (int_ppc_altivec_vstrihr v8i16:$VB))]>; 1455 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB), 1456 "vstrihl", "$VT, $VB", IIC_VecGeneral, 1457 [(set v8i16:$VT, 1458 (int_ppc_altivec_vstrihl v8i16:$VB))]>; 1459 def VINSW : 1460 VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB), 1461 "vinsw $VD, $VB, $VA", IIC_VecGeneral, 1462 [(set v4i32:$VD, 1463 (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>, 1464 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1465 def VINSD : 1466 VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB), 1467 "vinsd $VD, $VB, $VA", IIC_VecGeneral, 1468 [(set v2i64:$VD, 1469 (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>, 1470 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1471 def VINSBVLX : 1472 VXForm_VTB5_RA5_ins<15, "vinsbvlx", 1473 [(set v16i8:$VD, 1474 (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA, 1475 v16i8:$VB))]>; 1476 def VINSBVRX : 1477 VXForm_VTB5_RA5_ins<271, "vinsbvrx", 1478 [(set v16i8:$VD, 1479 (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA, 1480 v16i8:$VB))]>; 1481 def VINSHVLX : 1482 VXForm_VTB5_RA5_ins<79, "vinshvlx", 1483 [(set v8i16:$VD, 1484 (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA, 1485 v8i16:$VB))]>; 1486 def VINSHVRX : 1487 VXForm_VTB5_RA5_ins<335, "vinshvrx", 1488 [(set v8i16:$VD, 1489 (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA, 1490 v8i16:$VB))]>; 1491 def VINSWVLX : 1492 VXForm_VTB5_RA5_ins<143, "vinswvlx", 1493 [(set v4i32:$VD, 1494 (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA, 1495 v4i32:$VB))]>; 1496 def VINSWVRX : 1497 VXForm_VTB5_RA5_ins<399, "vinswvrx", 1498 [(set v4i32:$VD, 1499 (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA, 1500 v4i32:$VB))]>; 1501 def VINSBLX : 1502 VXForm_VRT5_RAB5_ins<527, "vinsblx", 1503 [(set v16i8:$VD, 1504 (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA, 1505 i32:$VB))]>; 1506 def VINSBRX : 1507 VXForm_VRT5_RAB5_ins<783, "vinsbrx", 1508 [(set v16i8:$VD, 1509 (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA, 1510 i32:$VB))]>; 1511 def VINSHLX : 1512 VXForm_VRT5_RAB5_ins<591, "vinshlx", 1513 [(set v8i16:$VD, 1514 (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA, 1515 i32:$VB))]>; 1516 def VINSHRX : 1517 VXForm_VRT5_RAB5_ins<847, "vinshrx", 1518 [(set v8i16:$VD, 1519 (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA, 1520 i32:$VB))]>; 1521 def VINSWLX : 1522 VXForm_VRT5_RAB5_ins<655, "vinswlx", 1523 [(set v4i32:$VD, 1524 (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA, 1525 i32:$VB))]>; 1526 def VINSWRX : 1527 VXForm_VRT5_RAB5_ins<911, "vinswrx", 1528 [(set v4i32:$VD, 1529 (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA, 1530 i32:$VB))]>; 1531 def VINSDLX : 1532 VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), 1533 "vinsdlx $VD, $VA, $VB", IIC_VecGeneral, 1534 [(set v2i64:$VD, 1535 (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>, 1536 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1537 def VINSDRX : 1538 VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), 1539 "vinsdrx $VD, $VA, $VB", IIC_VecGeneral, 1540 [(set v2i64:$VD, 1541 (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>, 1542 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1543 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB), 1544 "vextractbm $VD, $VB", IIC_VecGeneral, 1545 [(set i32:$VD, 1546 (int_ppc_altivec_vextractbm v16i8:$VB))]>, 1547 ZExt32To64; 1548 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB), 1549 "vextracthm $VD, $VB", IIC_VecGeneral, 1550 [(set i32:$VD, 1551 (int_ppc_altivec_vextracthm v8i16:$VB))]>, 1552 ZExt32To64; 1553 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB), 1554 "vextractwm $VD, $VB", IIC_VecGeneral, 1555 [(set i32:$VD, 1556 (int_ppc_altivec_vextractwm v4i32:$VB))]>, 1557 ZExt32To64; 1558 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB), 1559 "vextractdm $VD, $VB", IIC_VecGeneral, 1560 [(set i32:$VD, 1561 (int_ppc_altivec_vextractdm v2i64:$VB))]>, 1562 ZExt32To64; 1563 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB), 1564 "vextractqm $VD, $VB", IIC_VecGeneral, 1565 [(set i32:$VD, 1566 (int_ppc_altivec_vextractqm v1i128:$VB))]>; 1567 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB), 1568 "vexpandbm $VD, $VB", IIC_VecGeneral, 1569 [(set v16i8:$VD, (int_ppc_altivec_vexpandbm 1570 v16i8:$VB))]>; 1571 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB), 1572 "vexpandhm $VD, $VB", IIC_VecGeneral, 1573 [(set v8i16:$VD, (int_ppc_altivec_vexpandhm 1574 v8i16:$VB))]>; 1575 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB), 1576 "vexpandwm $VD, $VB", IIC_VecGeneral, 1577 [(set v4i32:$VD, (int_ppc_altivec_vexpandwm 1578 v4i32:$VB))]>; 1579 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB), 1580 "vexpanddm $VD, $VB", IIC_VecGeneral, 1581 [(set v2i64:$VD, (int_ppc_altivec_vexpanddm 1582 v2i64:$VB))]>; 1583 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB), 1584 "vexpandqm $VD, $VB", IIC_VecGeneral, 1585 [(set v1i128:$VD, (int_ppc_altivec_vexpandqm 1586 v1i128:$VB))]>; 1587 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB), 1588 "mtvsrbm $VD, $VB", IIC_VecGeneral, 1589 [(set v16i8:$VD, 1590 (int_ppc_altivec_mtvsrbm i64:$VB))]>; 1591 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB), 1592 "mtvsrhm $VD, $VB", IIC_VecGeneral, 1593 [(set v8i16:$VD, 1594 (int_ppc_altivec_mtvsrhm i64:$VB))]>; 1595 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB), 1596 "mtvsrwm $VD, $VB", IIC_VecGeneral, 1597 [(set v4i32:$VD, 1598 (int_ppc_altivec_mtvsrwm i64:$VB))]>; 1599 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB), 1600 "mtvsrdm $VD, $VB", IIC_VecGeneral, 1601 [(set v2i64:$VD, 1602 (int_ppc_altivec_mtvsrdm i64:$VB))]>; 1603 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB), 1604 "mtvsrqm $VD, $VB", IIC_VecGeneral, 1605 [(set v1i128:$VD, 1606 (int_ppc_altivec_mtvsrqm i64:$VB))]>; 1607 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D), 1608 "mtvsrbmi $RT, $D", IIC_VecGeneral, 1609 [(set v16i8:$RT, 1610 (int_ppc_altivec_mtvsrbm imm:$D))]>; 1611 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD), 1612 (ins vrrc:$VB, u1imm:$MP), 1613 "vcntmbb $RD, $VB, $MP", IIC_VecGeneral, 1614 [(set i64:$RD, (int_ppc_altivec_vcntmbb 1615 v16i8:$VB, timm:$MP))]>; 1616 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD), 1617 (ins vrrc:$VB, u1imm:$MP), 1618 "vcntmbh $RD, $VB, $MP", IIC_VecGeneral, 1619 [(set i64:$RD, (int_ppc_altivec_vcntmbh 1620 v8i16:$VB, timm:$MP))]>; 1621 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD), 1622 (ins vrrc:$VB, u1imm:$MP), 1623 "vcntmbw $RD, $VB, $MP", IIC_VecGeneral, 1624 [(set i64:$RD, (int_ppc_altivec_vcntmbw 1625 v4i32:$VB, timm:$MP))]>; 1626 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD), 1627 (ins vrrc:$VB, u1imm:$MP), 1628 "vcntmbd $RD, $VB, $MP", IIC_VecGeneral, 1629 [(set i64:$RD, (int_ppc_altivec_vcntmbd 1630 v2i64:$VB, timm:$MP))]>; 1631 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT), 1632 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1633 "vextdubvlx $RT, $RA, $RB, $RC", 1634 IIC_VecGeneral, 1635 [(set v2i64:$RT, 1636 (int_ppc_altivec_vextdubvlx v16i8:$RA, 1637 v16i8:$RB, 1638 i32:$RC))]>; 1639 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT), 1640 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1641 "vextdubvrx $RT, $RA, $RB, $RC", 1642 IIC_VecGeneral, 1643 [(set v2i64:$RT, 1644 (int_ppc_altivec_vextdubvrx v16i8:$RA, 1645 v16i8:$RB, 1646 i32:$RC))]>; 1647 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT), 1648 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1649 "vextduhvlx $RT, $RA, $RB, $RC", 1650 IIC_VecGeneral, 1651 [(set v2i64:$RT, 1652 (int_ppc_altivec_vextduhvlx v8i16:$RA, 1653 v8i16:$RB, 1654 i32:$RC))]>; 1655 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT), 1656 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1657 "vextduhvrx $RT, $RA, $RB, $RC", 1658 IIC_VecGeneral, 1659 [(set v2i64:$RT, 1660 (int_ppc_altivec_vextduhvrx v8i16:$RA, 1661 v8i16:$RB, 1662 i32:$RC))]>; 1663 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT), 1664 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1665 "vextduwvlx $RT, $RA, $RB, $RC", 1666 IIC_VecGeneral, 1667 [(set v2i64:$RT, 1668 (int_ppc_altivec_vextduwvlx v4i32:$RA, 1669 v4i32:$RB, 1670 i32:$RC))]>; 1671 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT), 1672 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1673 "vextduwvrx $RT, $RA, $RB, $RC", 1674 IIC_VecGeneral, 1675 [(set v2i64:$RT, 1676 (int_ppc_altivec_vextduwvrx v4i32:$RA, 1677 v4i32:$RB, 1678 i32:$RC))]>; 1679 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT), 1680 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1681 "vextddvlx $RT, $RA, $RB, $RC", 1682 IIC_VecGeneral, 1683 [(set v2i64:$RT, 1684 (int_ppc_altivec_vextddvlx v2i64:$RA, 1685 v2i64:$RB, 1686 i32:$RC))]>; 1687 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT), 1688 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1689 "vextddvrx $RT, $RA, $RB, $RC", 1690 IIC_VecGeneral, 1691 [(set v2i64:$RT, 1692 (int_ppc_altivec_vextddvrx v2i64:$RA, 1693 v2i64:$RB, 1694 i32:$RC))]>; 1695 def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1696 "vpdepd $VD, $VA, $VB", IIC_VecGeneral, 1697 [(set v2i64:$VD, 1698 (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>; 1699 def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1700 "vpextd $VD, $VA, $VB", IIC_VecGeneral, 1701 [(set v2i64:$VD, 1702 (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>; 1703 def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1704 "pdepd $RA, $RST, $RB", IIC_IntGeneral, 1705 [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>; 1706 def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1707 "pextd $RA, $RST, $RB", IIC_IntGeneral, 1708 [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>; 1709 def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1710 "vcfuged $VD, $VA, $VB", IIC_VecGeneral, 1711 [(set v2i64:$VD, 1712 (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>; 1713 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N), 1714 "vgnb $RD, $VB, $N", IIC_VecGeneral, 1715 [(set i64:$RD, 1716 (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>; 1717 def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1718 "cfuged $RA, $RST, $RB", IIC_IntGeneral, 1719 [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>; 1720 def XXEVAL : 1721 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1722 vsrc:$XC, u8imm:$IMM), 1723 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, 1724 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, 1725 v2i64:$XB, v2i64:$XC, timm:$IMM))]>; 1726 def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1727 "vclzdm $VD, $VA, $VB", IIC_VecGeneral, 1728 [(set v2i64:$VD, 1729 (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>; 1730 def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1731 "vctzdm $VD, $VA, $VB", IIC_VecGeneral, 1732 [(set v2i64:$VD, 1733 (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>; 1734 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1735 "cntlzdm $RA, $RST, $RB", IIC_IntGeneral, 1736 [(set i64:$RA, 1737 (int_ppc_cntlzdm i64:$RST, i64:$RB))]>; 1738 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1739 "cnttzdm $RA, $RST, $RB", IIC_IntGeneral, 1740 [(set i64:$RA, 1741 (int_ppc_cnttzdm i64:$RST, i64:$RB))]>; 1742 def XXGENPCVBM : 1743 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1744 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1745 def XXGENPCVHM : 1746 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1747 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1748 def XXGENPCVWM : 1749 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1750 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1751 def XXGENPCVDM : 1752 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1753 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1754 def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), 1755 "vclrlb $VD, $VA, $VB", IIC_VecGeneral, 1756 [(set v16i8:$VD, 1757 (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>; 1758 def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), 1759 "vclrrb $VD, $VA, $VB", IIC_VecGeneral, 1760 [(set v16i8:$VD, 1761 (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>; 1762 def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1763 "vmulld $VD, $VA, $VB", IIC_VecGeneral, 1764 [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>; 1765 def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1766 "vmulhsw $VD, $VA, $VB", IIC_VecGeneral, 1767 [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>; 1768 def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1769 "vmulhuw $VD, $VA, $VB", IIC_VecGeneral, 1770 [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>; 1771 def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1772 "vmulhsd $VD, $VA, $VB", IIC_VecGeneral, 1773 [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>; 1774 def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1775 "vmulhud $VD, $VA, $VB", IIC_VecGeneral, 1776 [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>; 1777 def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1778 "vmodsw $VD, $VA, $VB", IIC_VecGeneral, 1779 [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>; 1780 def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1781 "vmoduw $VD, $VA, $VB", IIC_VecGeneral, 1782 [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>; 1783 def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1784 "vmodsd $VD, $VA, $VB", IIC_VecGeneral, 1785 [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>; 1786 def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1787 "vmodud $VD, $VA, $VB", IIC_VecGeneral, 1788 [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>; 1789 def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1790 "vdivsw $VD, $VA, $VB", IIC_VecGeneral, 1791 [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>; 1792 def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1793 "vdivuw $VD, $VA, $VB", IIC_VecGeneral, 1794 [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>; 1795 def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1796 "vdivsd $VD, $VA, $VB", IIC_VecGeneral, 1797 [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>; 1798 def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1799 "vdivud $VD, $VA, $VB", IIC_VecGeneral, 1800 [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>; 1801 def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1802 "vdivesw $VD, $VA, $VB", IIC_VecGeneral, 1803 [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA, 1804 v4i32:$VB))]>; 1805 def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1806 "vdiveuw $VD, $VA, $VB", IIC_VecGeneral, 1807 [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA, 1808 v4i32:$VB))]>; 1809 def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1810 "vdivesd $VD, $VA, $VB", IIC_VecGeneral, 1811 [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA, 1812 v2i64:$VB))]>; 1813 def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1814 "vdiveud $VD, $VA, $VB", IIC_VecGeneral, 1815 [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA, 1816 v2i64:$VB))]>; 1817 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), 1818 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; 1819 def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RST), 1820 "brh $RA, $RST", IIC_IntRotate, []>; 1821 def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RST), 1822 "brw $RA, $RST", IIC_IntRotate, 1823 [(set i32:$RA, (bswap i32:$RST))]>; 1824 let isCodeGenOnly = 1 in { 1825 def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RST), 1826 "brh $RA, $RST", IIC_IntRotate, []>; 1827 def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RST), 1828 "brw $RA, $RST", IIC_IntRotate, []>; 1829 } 1830 def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RST), 1831 "brd $RA, $RST", IIC_IntRotate, 1832 [(set i64:$RA, (bswap i64:$RST))]>; 1833 1834 // The XFormMemOp flag for the following 8 instructions is set on 1835 // the instruction format. 1836 let mayLoad = 1, mayStore = 0 in { 1837 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; 1838 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; 1839 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; 1840 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; 1841 } 1842 1843 let mayLoad = 0, mayStore = 1 in { 1844 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; 1845 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; 1846 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; 1847 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; 1848 } 1849 1850 def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1851 "vmulesd $VD, $VA, $VB", IIC_VecGeneral, 1852 [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA, 1853 v2i64:$VB))]>; 1854 def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1855 "vmuleud $VD, $VA, $VB", IIC_VecGeneral, 1856 [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA, 1857 v2i64:$VB))]>; 1858 def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1859 "vmulosd $VD, $VA, $VB", IIC_VecGeneral, 1860 [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA, 1861 v2i64:$VB))]>; 1862 def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1863 "vmuloud $VD, $VA, $VB", IIC_VecGeneral, 1864 [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA, 1865 v2i64:$VB))]>; 1866 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC), 1867 "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral, 1868 [(set v1i128:$RT, (int_ppc_altivec_vmsumcud 1869 v2i64:$RA, v2i64:$RB, v1i128:$RC))]>; 1870 def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1871 "vdivsq $VD, $VA, $VB", IIC_VecGeneral, 1872 [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>; 1873 def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1874 "vdivuq $VD, $VA, $VB", IIC_VecGeneral, 1875 [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>; 1876 def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1877 "vdivesq $VD, $VA, $VB", IIC_VecGeneral, 1878 [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA, 1879 v1i128:$VB))]>; 1880 def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1881 "vdiveuq $VD, $VA, $VB", IIC_VecGeneral, 1882 [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA, 1883 v1i128:$VB))]>; 1884 def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>; 1885 def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>; 1886 def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>; 1887 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>; 1888 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>; 1889 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>; 1890 def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1891 "vmodsq $VD, $VA, $VB", IIC_VecGeneral, 1892 [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>; 1893 def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1894 "vmoduq $VD, $VA, $VB", IIC_VecGeneral, 1895 [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>; 1896 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB), 1897 "vextsd2q $VD, $VB", IIC_VecGeneral, 1898 [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>; 1899 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), 1900 "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>; 1901 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), 1902 "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>; 1903 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", 1904 [(set v1i128:$VD, 1905 (int_ppc_altivec_vrlqnm v1i128:$VA, 1906 v1i128:$VB))]>; 1907 def VRLQMI : VXForm_1<69, (outs vrrc:$VD), 1908 (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi), 1909 "vrlqmi $VD, $VA, $VB", IIC_VecFP, 1910 [(set v1i128:$VD, 1911 (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB, 1912 v1i128:$VDi))]>, 1913 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1914 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; 1915 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; 1916 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; 1917 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; 1918 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; 1919 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; 1920 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; 1921 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; 1922 def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM), 1923 "lxvkq $XT, $UIM", IIC_VecGeneral, []>; 1924} 1925 1926let Predicates = [IsISA3_1, HasVSX] in { 1927 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; 1928 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; 1929 def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", 1930 [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>; 1931 def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", 1932 [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>; 1933} 1934 1935let Predicates = [IsISA3_1] in { 1936 def WAITP10 : XForm_IMM2_IMM2<31, 30, (outs), (ins u2imm:$L, u2imm:$PL), 1937 "wait $L $PL", IIC_LdStLoad, []>; 1938 def SYNCP10 : XForm_IMM3_IMM2<31, 598, (outs), (ins u3imm:$L, u2imm:$SC), 1939 "sync $L, $SC", IIC_LdStSync, []>; 1940} 1941 1942// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. 1943// This is analogous to the CRNotPat multiclass but specifically for Power10 1944// and newer subtargets since the extended forms use Set Boolean instructions. 1945// The first two anonymous patterns defined are actually a duplicate of those 1946// in CRNotPat, but it is preferable to define both multiclasses as complete 1947// ones rather than pulling that small common section out. 1948multiclass P10ReverseSetBool<dag pattern, dag result> { 1949 def : Pat<pattern, (crnot result)>; 1950 def : Pat<(not pattern), result>; 1951 1952 def : Pat<(i32 (zext pattern)), 1953 (SETBCR result)>; 1954 def : Pat<(i64 (zext pattern)), 1955 (SETBCR8 result)>; 1956 1957 def : Pat<(i32 (sext pattern)), 1958 (SETNBCR result)>; 1959 def : Pat<(i64 (sext pattern)), 1960 (SETNBCR8 result)>; 1961 1962 def : Pat<(i32 (anyext pattern)), 1963 (SETBCR result)>; 1964 def : Pat<(i64 (anyext pattern)), 1965 (SETBCR8 result)>; 1966} 1967 1968multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy, 1969 ImmLeaf SExtTy, I Cmpi, I Cmpli, 1970 I Cmp, I Cmpl> { 1971 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1972 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>; 1973 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1974 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>; 1975 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1976 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>; 1977 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1978 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>; 1979 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1980 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>; 1981 1982 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)), 1983 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>; 1984 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)), 1985 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>; 1986 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)), 1987 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>; 1988 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)), 1989 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>; 1990 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)), 1991 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>; 1992 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)), 1993 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>; 1994} 1995 1996multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> { 1997 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1998 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1999 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 2000 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 2001 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 2002 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 2003 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 2004 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 2005 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 2006 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 2007 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 2008 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 2009 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 2010 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 2011} 2012 2013let Predicates = [IsISA3_1] in { 2014 def : Pat<(i32 (zext i1:$in)), 2015 (SETBC $in)>; 2016 def : Pat<(i64 (zext i1:$in)), 2017 (SETBC8 $in)>; 2018 def : Pat<(i32 (sext i1:$in)), 2019 (SETNBC $in)>; 2020 def : Pat<(i64 (sext i1:$in)), 2021 (SETNBC8 $in)>; 2022 def : Pat<(i32 (anyext i1:$in)), 2023 (SETBC $in)>; 2024 def : Pat<(i64 (anyext i1:$in)), 2025 (SETBC8 $in)>; 2026 2027 // Instantiation of the set boolean reverse patterns for 32-bit integers. 2028 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16, 2029 CMPWI, CMPLWI, CMPW, CMPLW>; 2030 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 2031 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2032 (LO16 imm:$imm)), sub_eq)>; 2033 2034 // Instantiation of the set boolean reverse patterns for 64-bit integers. 2035 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16, 2036 CMPDI, CMPLDI, CMPD, CMPLD>; 2037 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 2038 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2039 (LO16 imm:$imm)), sub_eq)>; 2040} 2041 2042// Instantiation of the set boolean reverse patterns for f32, f64, f128. 2043let Predicates = [IsISA3_1, HasFPU] in { 2044 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>; 2045 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>; 2046 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>; 2047} 2048 2049//---------------------------- Anonymous Patterns ----------------------------// 2050let Predicates = [IsISA3_1] in { 2051 // Exploit the vector multiply high instructions using intrinsics. 2052 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), 2053 (v4i32 (VMULHSW $vA, $vB))>; 2054 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), 2055 (v4i32 (VMULHUW $vA, $vB))>; 2056 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), 2057 (v2i64 (VMULHSD $vA, $vB))>; 2058 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)), 2059 (v2i64 (VMULHUD $vA, $vB))>; 2060 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), 2061 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; 2062 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), 2063 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; 2064 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), 2065 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; 2066 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), 2067 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; 2068 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), 2069 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; 2070 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), 2071 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; 2072 def : Pat<(srl (bswap i32:$RS), (i32 16)), 2073 (RLDICL_32 (BRH $RS), 0, 48)>; 2074 def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))), 2075 (RLDICL_32_64 (BRH $RS), 0, 48)>; 2076 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)), 2077 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>; 2078 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)), 2079 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>; 2080 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)), 2081 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>; 2082 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)), 2083 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>; 2084 2085 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)), 2086 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>; 2087 2088 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)), 2089 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>; 2090} 2091 2092let Predicates = [IsISA3_1, HasVSX] in { 2093 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)), 2094 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>; 2095 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)), 2096 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>; 2097} 2098 2099let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in { 2100 // Store element 0 of a VSX register to memory 2101 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst), 2102 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>; 2103 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst), 2104 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>; 2105 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst), 2106 (STXVRWX $src, ForceXForm:$dst)>; 2107 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst), 2108 (STXVRWX $src, ForceXForm:$dst)>; 2109 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst), 2110 (STXVRDX $src, ForceXForm:$dst)>; 2111 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst), 2112 (STXVRDX $src, ForceXForm:$dst)>; 2113 // Load element 0 of a VSX register to memory 2114 def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))), 2115 (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>; 2116 def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))), 2117 (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>; 2118 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 2119 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 2120 } 2121 2122let Predicates = [IsISA3_1, IsBigEndian] in { 2123 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 2124 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 2125} 2126 2127// FIXME: The swap is overkill when the shift amount is a constant. 2128// We should just fix the constant in the DAG. 2129let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { 2130 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)), 2131 (v1i128 (VSLQ v1i128:$VRA, 2132 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2133 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2134 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), 2135 (v1i128 (VSLQ v1i128:$VRA, 2136 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2137 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2138 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)), 2139 (v1i128 (VSRQ v1i128:$VRA, 2140 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2141 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2142 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)), 2143 (v1i128 (VSRQ v1i128:$VRA, 2144 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2145 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2146 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)), 2147 (v1i128 (VSRAQ v1i128:$VRA, 2148 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2149 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2150 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)), 2151 (v1i128 (VSRAQ v1i128:$VRA, 2152 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2153 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2154} 2155 2156class xxevalPattern <dag pattern, bits<8> imm> : 2157 Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} 2158 2159let Predicates = [PrefixInstrs, HasP10Vector] in { 2160 let AddedComplexity = 400 in { 2161 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A, 2162 i32immNonAllOneNonZero:$A, 2163 i32immNonAllOneNonZero:$A, 2164 i32immNonAllOneNonZero:$A)), 2165 (v4i32 (XXSPLTIW imm:$A))>; 2166 def : Pat<(f32 nzFPImmAsi32:$A), 2167 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2168 VSFRC)>; 2169 def : Pat<(f64 nzFPImmAsi32:$A), 2170 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2171 VSFRC)>; 2172 2173 // To replace constant pool with XXSPLTI32DX for scalars. 2174 def : Pat<(f32 nzFPImmAsi64:$A), 2175 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0, 2176 (getFPAs64BitIntHi $A)), 2177 1, (getFPAs64BitIntLo $A)), 2178 VSSRC)>; 2179 2180 def : Pat<(f64 nzFPImmAsi64:$A), 2181 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0, 2182 (getFPAs64BitIntHi $A)), 2183 1, (getFPAs64BitIntLo $A)), 2184 VSFRC)>; 2185 2186 // Anonymous patterns for XXEVAL 2187 // AND 2188 // and(A, B, C) 2189 def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; 2190 // and(A, xor(B, C)) 2191 def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; 2192 // and(A, or(B, C)) 2193 def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; 2194 // and(A, nor(B, C)) 2195 def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; 2196 // and(A, eqv(B, C)) 2197 def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; 2198 // and(A, nand(B, C)) 2199 def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; 2200 2201 // NAND 2202 // nand(A, B, C) 2203 def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 2204 !sub(255, 1)>; 2205 // nand(A, xor(B, C)) 2206 def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 2207 !sub(255, 6)>; 2208 // nand(A, or(B, C)) 2209 def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 2210 !sub(255, 7)>; 2211 // nand(A, nor(B, C)) 2212 def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 2213 !sub(255, 8)>; 2214 // nand(A, eqv(B, C)) 2215 def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 2216 !sub(255, 9)>; 2217 // nand(A, nand(B, C)) 2218 def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 2219 !sub(255, 14)>; 2220 2221 // EQV 2222 // (eqv A, B, C) 2223 def : xxevalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 2224 (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), 2225 150>; 2226 // (eqv A, (and B, C)) 2227 def : xxevalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>; 2228 // (eqv A, (or B, C)) 2229 def : xxevalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>; 2230 2231 // NOR 2232 // (nor A, B, C) 2233 def : xxevalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>; 2234 // (nor A, (and B, C)) 2235 def : xxevalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>; 2236 // (nor A, (eqv B, C)) 2237 def : xxevalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>; 2238 // (nor A, (nand B, C)) 2239 def : xxevalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>; 2240 // (nor A, (nor B, C)) 2241 def : xxevalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>; 2242 // (nor A, (xor B, C)) 2243 def : xxevalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>; 2244 2245 // OR 2246 // (or A, B, C) 2247 def : xxevalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>; 2248 // (or A, (and B, C)) 2249 def : xxevalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>; 2250 // (or A, (eqv B, C)) 2251 def : xxevalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>; 2252 // (or A, (nand B, C)) 2253 def : xxevalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>; 2254 // (or A, (nor B, C)) 2255 def : xxevalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>; 2256 // (or A, (xor B, C)) 2257 def : xxevalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>; 2258 2259 // XOR 2260 // (xor A, B, C) 2261 def : xxevalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>; 2262 // (xor A, (and B, C)) 2263 def : xxevalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>; 2264 // (xor A, (or B, C)) 2265 def : xxevalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>; 2266 2267 // Anonymous patterns to select prefixed VSX loads and stores. 2268 // Load / Store f128 2269 def : Pat<(f128 (load PDForm:$src)), 2270 (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>; 2271 def : Pat<(store f128:$XS, PDForm:$dst), 2272 (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>; 2273 2274 // Load / Store v4i32 2275 def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>; 2276 def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2277 2278 // Load / Store v2i64 2279 def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>; 2280 def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2281 2282 // Load / Store v4f32 2283 def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>; 2284 def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2285 2286 // Load / Store v2f64 2287 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>; 2288 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2289 2290 // Cases For PPCstore_scal_int_from_vsr 2291 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, PDForm:$dst, 8), 2292 (PSTXSD $src, PDForm:$dst)>; 2293 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, PDForm:$dst, 8), 2294 (PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>; 2295 } 2296 2297 2298 def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>; 2299 def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>; 2300 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)), 2301 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC), 2302 (COPY_TO_REGCLASS $B, VSRC), 2303 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>; 2304 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)), 2305 (COPY_TO_REGCLASS 2306 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC), 2307 (COPY_TO_REGCLASS $B, VSRC), 2308 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2309 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)), 2310 (COPY_TO_REGCLASS 2311 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC), 2312 (COPY_TO_REGCLASS $B, VSRC), 2313 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2314 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C), 2315 (XXBLENDVW $A, $B, $C)>; 2316 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C), 2317 (XXBLENDVD $A, $B, $C)>; 2318} 2319 2320let Predicates = [PrefixInstrs] in { 2321 // Anonymous patterns to select prefixed loads and stores. 2322 // Load i32 2323 def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2324 def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2325 def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2326 def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2327 def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2328 def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2329 def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>; 2330 def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>; 2331 2332 // Store i32 2333 def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>; 2334 def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>; 2335 def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>; 2336 2337 // Load i64 2338 def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2339 def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2340 def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2341 def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2342 def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2343 def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2344 def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>; 2345 def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2346 def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2347 def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>; 2348 def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>; 2349 2350 // Store i64 2351 def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>; 2352 def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>; 2353 def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>; 2354 def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>; 2355 2356 // Atomic Load 2357 def : Pat<(i32 (atomic_load_8 PDForm:$src)), (PLBZ memri34:$src)>; 2358 def : Pat<(i32 (atomic_load_16 PDForm:$src)), (PLHZ memri34:$src)>; 2359 def : Pat<(i32 (atomic_load_32 PDForm:$src)), (PLWZ memri34:$src)>; 2360 def : Pat<(i64 (atomic_load_64 PDForm:$src)), (PLD memri34:$src)>; 2361 2362 // Atomic Store 2363 def : Pat<(atomic_store_8 i32:$RS, PDForm:$dst), (PSTB $RS, memri34:$dst)>; 2364 def : Pat<(atomic_store_16 i32:$RS, PDForm:$dst), (PSTH $RS, memri34:$dst)>; 2365 def : Pat<(atomic_store_32 i32:$RS, PDForm:$dst), (PSTW $RS, memri34:$dst)>; 2366 def : Pat<(atomic_store_64 i64:$RS, PDForm:$dst), (PSTD $RS, memri34:$dst)>; 2367} 2368 2369let Predicates = [PrefixInstrs, HasFPU] in { 2370 // Load / Store f32 2371 def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>; 2372 def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>; 2373 2374 // Load / Store f64 2375 def : Pat<(f64 (extloadf32 PDForm:$src)), 2376 (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>; 2377 def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>; 2378 def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; 2379 // Prefixed fpext to v2f64 2380 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), 2381 (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; 2382 2383} 2384 2385def InsertEltShift { 2386 dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32)); 2387 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30); 2388 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29); 2389 dag Left1 = (RLWINM $rB, 1, 0, 30); 2390 dag Left2 = (RLWINM $rB, 2, 0, 29); 2391 dag Left3 = (RLWINM8 $rB, 3, 0, 28); 2392} 2393 2394let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in { 2395 // Indexed vector insert element 2396 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2397 (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>; 2398 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2399 (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2400 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2401 (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2402 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2403 (VINSDRX $vDi, InsertEltShift.Left3, $rA)>; 2404 2405 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2406 (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2407 2408 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2409 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2410 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2411 (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2412 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2413 (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2414 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2415 (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2416 let AddedComplexity = 400 in { 2417 // Immediate vector insert element 2418 foreach Idx = [0, 1, 2, 3] in { 2419 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)), 2420 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>; 2421 } 2422 foreach i = [0, 1] in 2423 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))), 2424 (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>; 2425 } 2426} 2427 2428let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in { 2429 // Indexed vector insert element 2430 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)), 2431 (VINSBLX $vDi, $rB, $rA)>; 2432 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)), 2433 (VINSHLX $vDi, InsertEltShift.Left1, $rA)>; 2434 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)), 2435 (VINSWLX $vDi, InsertEltShift.Left2, $rA)>; 2436 2437 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i32:$rB)), 2438 (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>; 2439} 2440 2441let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in { 2442 // Indexed vector insert element 2443 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2444 (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>; 2445 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2446 (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2447 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2448 (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2449 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2450 (VINSDLX $vDi, InsertEltShift.Left3, $rA)>; 2451 2452 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2453 (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2454 2455 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2456 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2457 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2458 (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2459 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2460 (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2461 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2462 (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2463} 2464 2465let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in { 2466 // Immediate vector insert element 2467 foreach Ty = [i32, i64] in { 2468 foreach Idx = [0, 1, 2, 3] in { 2469 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))), 2470 (VINSW $vDi, !mul(Idx, 4), $rA)>; 2471 } 2472 } 2473 2474 foreach Idx = [0, 1] in 2475 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)), 2476 (VINSD $vDi, !mul(Idx, 8), $rA)>; 2477} 2478 2479 2480//===----------------------------------------------------------------------===// 2481// PowerPC ISA 3.1 Extended Mnemonics. 2482// 2483 2484let Predicates = [IsISA3_1] in { 2485 def : InstAlias<"wait", (WAITP10 0, 0)>; 2486 def : InstAlias<"wait 0", (WAITP10 0, 0), 0>; 2487 def : InstAlias<"wait 1", (WAITP10 1, 0), 0>; 2488 def : InstAlias<"waitrsv", (WAITP10 1, 0)>; 2489 def : InstAlias<"pause_short", (WAITP10 2, 0), 0>; 2490 2491 def : InstAlias<"sync", (SYNCP10 0, 0)>; 2492 def : InstAlias<"hwsync", (SYNCP10 0, 0), 0>; 2493 def : InstAlias<"wsync", (SYNCP10 1, 0), 0>; 2494 def : InstAlias<"ptesync", (SYNCP10 2, 0)>; 2495 def : InstAlias<"phwsync", (SYNCP10 4, 0)>; 2496 def : InstAlias<"plwsync", (SYNCP10 5, 0)>; 2497 def : InstAlias<"sync $L", (SYNCP10 u3imm:$L, 0)>; 2498 def : InstAlias<"stncisync", (SYNCP10 1, 1)>; 2499 def : InstAlias<"stcisync", (SYNCP10 0, 2)>; 2500 def : InstAlias<"stsync", (SYNCP10 0, 3)>; 2501 2502 def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>; 2503} 2504 2505let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 2506 let Interpretation64Bit = 1 in { 2507 def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 2508 (ins g8rc_nox0:$RA, s34imm:$SI), 2509 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>; 2510 def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 2511 (ins s34imm_pcrel:$SI), 2512 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel; 2513 } 2514 2515 def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI", 2516 (ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>; 2517 2518 def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 2519 (ins gprc_nor0:$RA, s34imm:$SI), 2520 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>; 2521 def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 2522 (ins s34imm_pcrel:$SI), 2523 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel; 2524} 2525