xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrP10.td (revision 5fb307d29b364982acbde82cbf77db3cae486f8c)
1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10//
11// This file describes the instructions introduced for the Power10 CPU.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Naming convention for future instruction formats
17//
18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+
19//
20// Where:
21// <INSTR_FORM> - name of instruction format as per the ISA
22//                (X-Form, VX-Form, etc.)
23// <OP_TYPE> - operand type
24//             * FRT/RT/VT/XT/BT - target register
25//                                 (FPR, GPR, VR, VSR, CR-bit respectively)
26//                                 In some situations, the 'T' is replaced by
27//                                 'D' when describing the target register.
28//             * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.)
29//             * IMM - immediate (where signedness matters,
30//                     this is SI/UI for signed/unsigned)
31//             * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp)
32//             * R - PC-Relative bit
33//                   (denotes that the address is computed pc-relative)
34//             * VRM - Masked Registers
35//             * AT - target accumulator
36//             * N - the Nth bit in a VSR
37//             * Additional 1-bit operands may be required for certain
38//               instruction formats such as: MC, P, MP
39//             * X / Y / P - mask values. In the instruction encoding, this is
40//                           represented as XMSK, YMSK and PMSK.
41//             * MEM - indicates if the instruction format requires any memory
42//                     accesses. This does not have <OP_LENGTH> attached to it.
43// <OP_LENGTH> - the length of each operand in bits.
44//               For operands that are 1 bit, the '1' is omitted from the name.
45//
46// Example: 8RR_XX4Form_IMM8_XTAB6
47//          8RR_XX4Form is the instruction format.
48//          The operand is an 8-bit immediate (IMM), the destination (XT)
49//          and sources (XA, XB) that are all 6-bits. The destination and
50//          source registers are combined if they are of the same length.
51//          Moreover, the order of operands reflects the order of operands
52//          in the encoding.
53
54//-------------------------- Predicate definitions ---------------------------//
55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
56
57
58//===----------------------------------------------------------------------===//
59// PowerPC ISA 3.1 specific type constraints.
60//
61
62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>,
63  SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3>
64]>;
65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [
66  SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
67                       SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>
68]>;
69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [
70  SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
71]>;
72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [
73  SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
74]>;
75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [
76  SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
77]>;
78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [
79  SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>
80]>;
81
82//===----------------------------------------------------------------------===//
83// ISA 3.1 specific PPCISD nodes.
84//
85
86def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>;
87def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>;
88def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>;
89def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx,
90                       []>;
91def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx,
92                        []>;
93def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>;
94
95//===----------------------------------------------------------------------===//
96
97// PC Relative flag (for instructions that use the address of the prefix for
98// address computations).
99class isPCRel { bit PCRel = 1; }
100
101// PowerPC specific type constraints.
102def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [
103  SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
104]>;
105
106// PPC Specific DAG Nodes.
107def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
108                       [SDNPHasChain, SDNPMayLoad]>;
109
110// Top-level class for prefixed instructions.
111class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
112         InstrItinClass itin> : Instruction {
113  field bits<64> Inst;
114  field bits<64> SoftFail = 0;
115  bit PCRel = 0; // Default value, set by isPCRel.
116  let Size = 8;
117
118  let Namespace = "PPC";
119  let OutOperandList = OOL;
120  let InOperandList = IOL;
121  let AsmString = asmstr;
122  let Itinerary = itin;
123  let Inst{0-5} = pref;
124  let Inst{32-37} = opcode;
125
126  bits<1> PPC970_First = 0;
127  bits<1> PPC970_Single = 0;
128  bits<1> PPC970_Cracked = 0;
129  bits<3> PPC970_Unit = 0;
130
131  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
132  /// these must be reflected there!  See comments there for what these are.
133  let TSFlags{0}   = PPC970_First;
134  let TSFlags{1}   = PPC970_Single;
135  let TSFlags{2}   = PPC970_Cracked;
136  let TSFlags{5-3} = PPC970_Unit;
137
138  bits<1> Prefixed = 1;  // This is a prefixed instruction.
139  let TSFlags{7}  = Prefixed;
140
141  // For cases where multiple instruction definitions really represent the
142  // same underlying instruction but with one definition for 64-bit arguments
143  // and one for 32-bit arguments, this bit breaks the degeneracy between
144  // the two forms and allows TableGen to generate mapping tables.
145  bit Interpretation64Bit = 0;
146
147  // Fields used for relation models.
148  string BaseName = "";
149}
150
151// VX-Form: [ PO VT R VB RC XO ]
152class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
153                      InstrItinClass itin, list<dag> pattern>
154  : I<4, OOL, IOL, asmstr, itin> {
155  bits<5> VT;
156  bits<5> VB;
157  bit RC = 0;
158
159  let Pattern = pattern;
160
161  let Inst{6-10} = VT;
162  let Inst{11-15} = R;
163  let Inst{16-20} = VB;
164  let Inst{21} = RC;
165  let Inst{22-31} = xo;
166}
167
168// Multiclass definition to account for record and non-record form
169// instructions of VXRForm.
170multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
171                            string asmbase, string asmstr,
172                            InstrItinClass itin, list<dag> pattern> {
173  let BaseName = asmbase in {
174    def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,
175                               !strconcat(asmbase, !strconcat(" ", asmstr)),
176                               itin, pattern>, RecFormRel;
177    let Defs = [CR6] in
178    def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
179                               !strconcat(asmbase, !strconcat(". ", asmstr)),
180                               itin, []>, isRecordForm, RecFormRel;
181  }
182}
183
184class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
185                                InstrItinClass itin, list<dag> pattern>
186  : PI<1, opcode, OOL, IOL, asmstr, itin> {
187  bits<5> RST;
188  bits<5> RA;
189  bits<34> D;
190
191  let Pattern = pattern;
192
193  // The prefix.
194  let Inst{6-7} = 2;
195  let Inst{8-10} = 0;
196  let Inst{11} = PCRel;
197  let Inst{12-13} = 0;
198  let Inst{14-31} = D{33-16}; // d0
199
200  // The instruction.
201  let Inst{38-42} = RST{4-0};
202  let Inst{43-47} = RA;
203  let Inst{48-63} = D{15-0}; // d1
204}
205
206class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
207                            InstrItinClass itin, list<dag> pattern>
208  : PI<1, opcode, OOL, IOL, asmstr, itin> {
209  bits<5> RT;
210  bits<5> RA;
211  bits<34> SI;
212
213  let Pattern = pattern;
214
215  // The prefix.
216  let Inst{6-7} = 2;
217  let Inst{8-10} = 0;
218  let Inst{11} = PCRel;
219  let Inst{12-13} = 0;
220  let Inst{14-31} = SI{33-16};
221
222  // The instruction.
223  let Inst{38-42} = RT;
224  let Inst{43-47} = RA;
225  let Inst{48-63} = SI{15-0};
226}
227
228class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
229                         InstrItinClass itin, list<dag> pattern>
230  : PI<1, opcode, OOL, IOL, asmstr, itin> {
231  bits<5> RT;
232  bits<34> SI;
233
234  let Pattern = pattern;
235
236  // The prefix.
237  let Inst{6-7} = 2;
238  let Inst{8-10} = 0;
239  let Inst{11} = 0;
240  let Inst{12-13} = 0;
241  let Inst{14-31} = SI{33-16};
242
243  // The instruction.
244  let Inst{38-42} = RT;
245  let Inst{43-47} = 0;
246  let Inst{48-63} = SI{15-0};
247}
248
249multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
250                                   dag PCRel_IOL, string asmstr,
251                                   InstrItinClass itin> {
252  def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
253                                   !strconcat(asmstr, ", 0"), itin, []>;
254  def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
255                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
256}
257
258class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
259                                InstrItinClass itin, list<dag> pattern>
260  : PI<1, opcode, OOL, IOL, asmstr, itin> {
261  bits<5> RST;
262  bits<5> RA;
263  bits<34> D;
264
265  let Pattern = pattern;
266
267  // The prefix.
268  let Inst{6-10} = 0;
269  let Inst{11} = PCRel;
270  let Inst{12-13} = 0;
271  let Inst{14-31} = D{33-16}; // d0
272
273  // The instruction.
274  let Inst{38-42} = RST{4-0};
275  let Inst{43-47} = RA;
276  let Inst{48-63} = D{15-0}; // d1
277}
278
279// 8LS:D-Form: [ 1 0 0 // R // d0
280//               PO TX T RA d1 ]
281class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
282                                   string asmstr, InstrItinClass itin,
283                                   list<dag> pattern>
284  : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
285  bits<6> XST;
286  bits<5> RA;
287  bits<34> D;
288
289  let Pattern = pattern;
290
291  // The prefix.
292  let Inst{6-7} = 0;
293  let Inst{8} = 0;
294  let Inst{9-10} = 0; // reserved
295  let Inst{11} = PCRel;
296  let Inst{12-13} = 0; // reserved
297  let Inst{14-31} = D{33-16}; // d0
298
299  // The instruction.
300  let Inst{37} = XST{5};
301  let Inst{38-42} = XST{4-0};
302  let Inst{43-47} = RA;
303  let Inst{48-63} = D{15-0}; // d1
304}
305
306// X-Form: [PO T IMM VRB XO TX]
307class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
308                         string asmstr, InstrItinClass itin, list<dag> pattern>
309  : I<opcode, OOL, IOL, asmstr, itin> {
310  bits<6> XT;
311  bits<5> VRB;
312  bits<5> IMM;
313
314  let Pattern = pattern;
315  let Inst{6-10} = XT{4-0};
316  let Inst{11-15} = IMM;
317  let Inst{16-20} = VRB;
318  let Inst{21-30} = xo;
319  let Inst{31} = XT{5};
320}
321
322class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,
323                             dag OOL, dag IOL, string asmstr,
324                             InstrItinClass itin, list<dag> pattern>
325  : PI<1, opcode, OOL, IOL, asmstr, itin> {
326    bits<6> XT;
327    bits<6> XA;
328    bits<6> XB;
329    bits<6> XC;
330    bits<8> IMM;
331
332    let Pattern = pattern;
333
334    // The prefix.
335    let Inst{6-7} = 1;
336    let Inst{8} = 0;
337    let Inst{9-11} = 0;
338    let Inst{12-13} = 0;
339    let Inst{14-23} = 0;
340    let Inst{24-31} = IMM;
341
342    // The instruction.
343    let Inst{38-42} = XT{4-0};
344    let Inst{43-47} = XA{4-0};
345    let Inst{48-52} = XB{4-0};
346    let Inst{53-57} = XC{4-0};
347    let Inst{58-59} = xo;
348    let Inst{60} = XC{5};
349    let Inst{61} = XA{5};
350    let Inst{62} = XB{5};
351    let Inst{63} = XT{5};
352}
353
354class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
355                        InstrItinClass itin, list<dag> pattern>
356  : I<4, OOL, IOL, asmstr, itin> {
357  bits<5> RD;
358  bits<5> VB;
359  bits<3> N;
360
361  let Pattern = pattern;
362
363  let Inst{6-10}  = RD;
364  let Inst{11-12} = 0;
365  let Inst{13-15} = N;
366  let Inst{16-20} = VB;
367  let Inst{21-31} = xo;
368}
369
370
371// VX-Form: [PO VRT RA VRB XO].
372// Destructive (insert) forms are suffixed with _ins.
373class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
374  : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB),
375             !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
376             RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
377
378// VX-Form: [PO VRT RA RB XO].
379// Destructive (insert) forms are suffixed with _ins.
380class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
381  : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB),
382             !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
383             RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
384
385// VX-Form: [ PO BF // VRA VRB XO ]
386class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
387                      InstrItinClass itin, list<dag> pattern>
388  : I<4, OOL, IOL, asmstr, itin> {
389  bits<3> BF;
390  bits<5> VA;
391  bits<5> VB;
392
393  let Pattern = pattern;
394
395  let Inst{6-8} = BF;
396  let Inst{9-10} = 0;
397  let Inst{11-15} = VA;
398  let Inst{16-20} = VB;
399  let Inst{21-31} = xo;
400}
401
402// VN-Form: [PO VRT VRA VRB PS SD XO]
403// SD is "Shift Direction"
404class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
405                       InstrItinClass itin, list<dag> pattern>
406    : I<4, OOL, IOL, asmstr, itin> {
407  bits<5> VRT;
408  bits<5> VRA;
409  bits<5> VRB;
410  bits<3> SD;
411
412  let Pattern = pattern;
413
414  let Inst{6-10}  = VRT;
415  let Inst{11-15} = VRA;
416  let Inst{16-20} = VRB;
417  let Inst{21-22} = ps;
418  let Inst{23-25} = SD;
419  let Inst{26-31} = xo;
420}
421
422class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
423                        string asmstr, InstrItinClass itin, list<dag> pattern>
424  : I<4, OOL, IOL, asmstr, itin> {
425  bits<5> RD;
426  bits<5> VB;
427  bit MP;
428
429  let Pattern = pattern;
430
431  let Inst{6-10}  = RD;
432  let Inst{11-14} = eo;
433  let Inst{15} = MP;
434  let Inst{16-20} = VB;
435  let Inst{21-31} = xo;
436}
437
438// 8RR:D-Form: [ 1 1 0 // // imm0
439//               PO T XO TX imm1 ].
440class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
441                          string asmstr, InstrItinClass itin,
442                          list<dag> pattern>
443  : PI<1, opcode, OOL, IOL, asmstr, itin> {
444  bits<6> XT;
445  bits<32> IMM32;
446
447  let Pattern = pattern;
448
449  // The prefix.
450  let Inst{6-7} = 1;
451  let Inst{8-11} = 0;
452  let Inst{12-13} = 0; // reserved
453  let Inst{14-15} = 0; // reserved
454  let Inst{16-31} = IMM32{31-16};
455
456  // The instruction.
457  let Inst{38-42} = XT{4-0};
458  let Inst{43-46} = xo;
459  let Inst{47} = XT{5};
460  let Inst{48-63} = IMM32{15-0};
461}
462
463// 8RR:D-Form: [ 1 1 0 // // imm0
464//               PO T XO IX TX imm1 ].
465class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
466                             string asmstr, InstrItinClass itin,
467                             list<dag> pattern>
468  : PI<1, opcode, OOL, IOL, asmstr, itin> {
469  bits<6> XT;
470  bit IX;
471  bits<32> IMM32;
472
473  let Pattern = pattern;
474
475  // The prefix.
476  let Inst{6-7} = 1;
477  let Inst{8-11} = 0;
478  let Inst{12-13} = 0; // reserved
479  let Inst{14-15} = 0; // reserved
480  let Inst{16-31} = IMM32{31-16};
481
482  // The instruction.
483  let Inst{38-42} = XT{4-0};
484  let Inst{43-45} = xo;
485  let Inst{46} = IX;
486  let Inst{47} = XT{5};
487  let Inst{48-63} = IMM32{15-0};
488}
489
490class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
491                         string asmstr, InstrItinClass itin, list<dag> pattern>
492  : PI<1, opcode, OOL, IOL, asmstr, itin> {
493  bits<6> XT;
494  bits<6> XA;
495  bits<6> XB;
496  bits<6> XC;
497
498  let Pattern = pattern;
499
500  // The prefix.
501  let Inst{6-7} = 1;
502  let Inst{8-11} = 0;
503  let Inst{12-13} = 0;
504  let Inst{14-31} = 0;
505
506  // The instruction.
507  let Inst{38-42} = XT{4-0};
508  let Inst{43-47} = XA{4-0};
509  let Inst{48-52} = XB{4-0};
510  let Inst{53-57} = XC{4-0};
511  let Inst{58-59} = xo;
512  let Inst{60} = XC{5};
513  let Inst{61} = XA{5};
514  let Inst{62} = XB{5};
515  let Inst{63} = XT{5};
516}
517
518class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
519                              string asmstr, InstrItinClass itin,
520                              list<dag> pattern>
521  : PI<1, opcode, OOL, IOL, asmstr, itin> {
522  bits<6> XT;
523  bits<6> XA;
524  bits<6> XB;
525  bits<6> XC;
526  bits<3> IMM;
527
528  let Pattern = pattern;
529
530  // The prefix.
531  let Inst{6-7} = 1;
532  let Inst{8-11} = 0;
533  let Inst{12-13} = 0;
534  let Inst{14-28} = 0;
535  let Inst{29-31} = IMM;
536
537  // The instruction.
538  let Inst{38-42} = XT{4-0};
539  let Inst{43-47} = XA{4-0};
540  let Inst{48-52} = XB{4-0};
541  let Inst{53-57} = XC{4-0};
542  let Inst{58-59} = xo;
543  let Inst{60} = XC{5};
544  let Inst{61} = XA{5};
545  let Inst{62} = XB{5};
546  let Inst{63} = XT{5};
547}
548
549// [PO BF / XO2 B XO BX /]
550class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
551                          dag IOL, string asmstr, InstrItinClass itin,
552                          list<dag> pattern>
553  : I<opcode, OOL, IOL, asmstr, itin> {
554  bits<3> BF;
555  bits<6> XB;
556
557  let Pattern = pattern;
558
559  let Inst{6-8}   = BF;
560  let Inst{9-10}  = 0;
561  let Inst{11-15} = xo2;
562  let Inst{16-20} = XB{4-0};
563  let Inst{21-29} = xo;
564  let Inst{30}    = XB{5};
565  let Inst{31}    = 0;
566}
567
568// X-Form: [ PO RT BI /// XO / ]
569class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
570                    string asmstr, InstrItinClass itin, list<dag> pattern>
571  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
572  bits<5> BI;
573  let RA = BI;
574  let RB = 0;
575}
576
577multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
578                                       dag PCRel_IOL, string asmstr,
579                                       InstrItinClass itin> {
580  def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
581                                       !strconcat(asmstr, ", 0"), itin, []>;
582  def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
583                                     !strconcat(asmstr, ", 1"), itin, []>,
584                                     isPCRel;
585}
586
587multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
588                                       dag PCRel_IOL, string asmstr,
589                                       InstrItinClass itin> {
590  def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
591                                       !strconcat(asmstr, ", 0"), itin, []>;
592  def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
593                                     !strconcat(asmstr, ", 1"), itin, []>,
594                                     isPCRel;
595}
596
597multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
598                                          dag PCRel_IOL, string asmstr,
599                                          InstrItinClass itin> {
600  def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL,
601                                          !strconcat(asmstr, ", 0"), itin, []>;
602  def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL,
603                                        !strconcat(asmstr, ", 1"), itin, []>,
604                                        isPCRel;
605}
606
607def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
608def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
609def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
610def RCCp {
611  dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
612  dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
613}
614
615let Predicates = [PrefixInstrs] in {
616  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
617    defm PADDI8 :
618      MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
619                              (ins immZero:$RA, s34imm_pcrel:$SI),
620                              "paddi $RT, $RA, $SI", IIC_LdStLFD>;
621    let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
622      def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
623                                    (ins s34imm:$SI),
624                                    "pli $RT, $SI", IIC_IntSimple, []>;
625    }
626  }
627  defm PADDI :
628    MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
629                            (ins immZero:$RA, s34imm_pcrel:$SI),
630                            "paddi $RT, $RA, $SI", IIC_LdStLFD>;
631  let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
632    def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
633                                 (ins s34imm:$SI),
634                                 "pli $RT, $SI", IIC_IntSimple, []>;
635  }
636
637  let mayLoad = 1, mayStore = 0 in {
638    defm PLXV :
639      8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
640                                     (ins (memri34_pcrel $D, $RA):$addr),
641                                     "plxv $XST, $addr", IIC_LdStLFD>;
642    defm PLFS :
643      MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
644                                  (ins (memri34_pcrel $D, $RA):$addr), "plfs $RST, $addr",
645                                  IIC_LdStLFD>;
646    defm PLFD :
647      MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr),
648                                  (ins  (memri34_pcrel $D, $RA):$addr), "plfd $RST, $addr",
649                                  IIC_LdStLFD>;
650    defm PLXSSP :
651      8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
652                                  (ins (memri34_pcrel $D, $RA):$addr),
653                                  "plxssp $RST, $addr", IIC_LdStLFD>;
654    defm PLXSD :
655      8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
656                                  (ins (memri34_pcrel $D, $RA):$addr),
657                                  "plxsd $RST, $addr", IIC_LdStLFD>;
658    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
659      defm PLBZ8 :
660        MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
661                                    (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
662                                    IIC_LdStLFD>;
663      defm PLHZ8 :
664        MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
665                                    (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
666                                    IIC_LdStLFD>;
667      defm PLHA8 :
668        MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
669                                    (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
670                                    IIC_LdStLFD>;
671      defm PLWA8 :
672        8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
673                                    (ins (memri34_pcrel $D, $RA):$addr),
674                                    "plwa $RST, $addr", IIC_LdStLFD>;
675      defm PLWZ8 :
676        MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
677                                    (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
678                                    IIC_LdStLFD>;
679    }
680    defm PLBZ :
681      MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
682                                  (ins (memri34_pcrel $D, $RA):$addr), "plbz $RST, $addr",
683                                  IIC_LdStLFD>;
684    defm PLHZ :
685      MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
686                                  (ins (memri34_pcrel $D, $RA):$addr), "plhz $RST, $addr",
687                                  IIC_LdStLFD>;
688    defm PLHA :
689      MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
690                                  (ins (memri34_pcrel $D, $RA):$addr), "plha $RST, $addr",
691                                  IIC_LdStLFD>;
692    defm PLWZ :
693      MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
694                                  (ins (memri34_pcrel $D, $RA):$addr), "plwz $RST, $addr",
695                                  IIC_LdStLFD>;
696    defm PLWA :
697      8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
698                                  (ins (memri34_pcrel $D, $RA):$addr), "plwa $RST, $addr",
699                                  IIC_LdStLFD>;
700    defm PLD :
701      8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
702                                  (ins (memri34_pcrel $D, $RA):$addr), "pld $RST, $addr",
703                                  IIC_LdStLFD>;
704  }
705
706  let mayStore = 1, mayLoad = 0 in {
707    defm PSTXV :
708      8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
709                                     (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
710                                     "pstxv $XST, $addr", IIC_LdStLFD>;
711    defm PSTFS :
712      MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
713                                  (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
714                                  "pstfs $RST, $addr", IIC_LdStLFD>;
715    defm PSTFD :
716      MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
717                                  (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
718                                  "pstfd $RST, $addr", IIC_LdStLFD>;
719    defm PSTXSSP :
720      8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
721                                  (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
722                                  "pstxssp $RST, $addr", IIC_LdStLFD>;
723    defm PSTXSD :
724      8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
725                                  (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
726                                  "pstxsd $RST, $addr", IIC_LdStLFD>;
727    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
728      defm PSTB8 :
729        MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
730                                    (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
731                                    "pstb $RST, $addr", IIC_LdStLFD>;
732      defm PSTH8 :
733        MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
734                                    (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
735                                    "psth $RST, $addr", IIC_LdStLFD>;
736      defm PSTW8 :
737        MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
738                                    (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
739                                    "pstw $RST, $addr", IIC_LdStLFD>;
740    }
741    defm PSTB :
742      MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
743                                  (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
744                                  "pstb $RST, $addr", IIC_LdStLFD>;
745    defm PSTH :
746      MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
747                                  (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
748                                  "psth $RST, $addr", IIC_LdStLFD>;
749    defm PSTW :
750      MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
751                                  (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
752                                  "pstw $RST, $addr", IIC_LdStLFD>;
753    defm PSTD :
754      8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
755                                  (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
756                                  "pstd $RST, $addr", IIC_LdStLFD>;
757  }
758}
759
760class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
761                           string asmstr, InstrItinClass itin, list<dag> pattern>
762  : I<opcode, OOL, IOL, asmstr, itin> {
763  bits<5> XTp;
764  bits<5> RA;
765  bits<12> DQ;
766
767  let Pattern = pattern;
768
769  let Inst{6-9} = XTp{3-0};
770  let Inst{10} = XTp{4};
771  let Inst{11-15} = RA;
772  let Inst{16-27} = DQ;
773  let Inst{28-31} = xo;
774}
775
776class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
777                      string asmstr, InstrItinClass itin, list<dag> pattern>
778  : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {
779  bits<5> XTp;
780  bits<5> RA;
781  bits<5> RB;
782
783  let Pattern = pattern;
784  let Inst{6-9} = XTp{3-0};
785  let Inst{10} = XTp{4};
786  let Inst{11-15} = RA;
787  let Inst{16-20} = RB;
788  let Inst{21-30} = xo;
789  let Inst{31} = 0;
790}
791
792class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
793                                InstrItinClass itin, list<dag> pattern>
794  : PI<1, opcode, OOL, IOL, asmstr, itin> {
795  bits<5> XTp;
796  bits<5> RA;
797  bits<34> D;
798
799  let Pattern = pattern;
800
801  // The prefix.
802  let Inst{6-10} = 0;
803  let Inst{11} = PCRel;
804  let Inst{12-13} = 0;
805  let Inst{14-31} = D{33-16}; // Imm18
806
807  // The instruction.
808  let Inst{38-41} = XTp{3-0};
809  let Inst{42}    = XTp{4};
810  let Inst{43-47} = RA;
811  let Inst{48-63} = D{15-0};
812}
813
814multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
815                                       dag IOL, dag PCRel_IOL,
816                                       string asmstr, InstrItinClass itin> {
817  def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,
818                                       !strconcat(asmstr, ", 0"), itin, []>;
819  def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,
820                                     !strconcat(asmstr, ", 1"), itin, []>,
821                                     isPCRel;
822}
823
824
825
826// [PO AS XO2 XO]
827class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
828                    string asmstr, InstrItinClass itin, list<dag> pattern>
829  : I<opcode, OOL, IOL, asmstr, itin> {
830  bits<3> AT;
831
832  let Pattern = pattern;
833
834  let Inst{6-8}  = AT;
835  let Inst{9-10}  = 0;
836  let Inst{11-15} = xo2;
837  let Inst{16-20} = 0;
838  let Inst{21-30} = xo;
839  let Inst{31} = 0;
840}
841
842// X-Form: [ PO T EO UIM XO TX ]
843class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,
844                     string asmstr, InstrItinClass itin, list<dag> pattern>
845  : I<opcode, OOL, IOL, asmstr, itin> {
846  bits<6> XT;
847  bits<5> UIM;
848
849  let Pattern = pattern;
850
851  let Inst{6-10} = XT{4-0};
852  let Inst{11-15} = eo;
853  let Inst{16-20} = UIM;
854  let Inst{21-30} = xo;
855  let Inst{31} = XT{5};
856}
857
858class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
859                           string asmstr, InstrItinClass itin,
860                           list<dag> pattern>
861  : I<opcode, OOL, IOL, asmstr, itin> {
862  bits<3> AT;
863  bits<6> XA;
864  bits<6> XB;
865
866  let Pattern = pattern;
867
868  let Inst{6-8} = AT;
869  let Inst{9-10} = 0;
870  let Inst{11-15} = XA{4-0};
871  let Inst{16-20} = XB{4-0};
872  let Inst{21-28} = xo;
873  let Inst{29}    = XA{5};
874  let Inst{30}    = XB{5};
875  let Inst{31} = 0;
876}
877
878class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
879                               string asmstr, InstrItinClass itin,
880                               list<dag> pattern>
881  : PI<1, opcode, OOL, IOL, asmstr, itin> {
882  bits<3> AT;
883  bits<6> XA;
884  bits<6> XB;
885  bits<4> XMSK;
886  bits<4> YMSK;
887  bits<2> PMSK;
888
889  let Pattern = pattern;
890
891  // The prefix.
892  let Inst{6-7} = 3;
893  let Inst{8-11} = 9;
894  let Inst{12-15} = 0;
895  let Inst{16-17} = PMSK;
896  let Inst{18-23} = 0;
897  let Inst{24-27} = XMSK;
898  let Inst{28-31} = YMSK;
899
900  // The instruction.
901  let Inst{38-40} = AT;
902  let Inst{41-42} = 0;
903  let Inst{43-47} = XA{4-0};
904  let Inst{48-52} = XB{4-0};
905  let Inst{53-60} = xo;
906  let Inst{61} = XA{5};
907  let Inst{62} = XB{5};
908  let Inst{63} = 0;
909}
910
911class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
912                             string asmstr, InstrItinClass itin,
913                             list<dag> pattern>
914  : PI<1, opcode, OOL, IOL, asmstr, itin> {
915  bits<3> AT;
916  bits<6> XA;
917  bits<6> XB;
918  bits<4> XMSK;
919  bits<4> YMSK;
920
921  let Pattern = pattern;
922
923  // The prefix.
924  let Inst{6-7} = 3;
925  let Inst{8-11} = 9;
926  let Inst{12-23} = 0;
927  let Inst{24-27} = XMSK;
928  let Inst{28-31} = YMSK;
929
930  // The instruction.
931  let Inst{38-40} = AT;
932  let Inst{41-42} = 0;
933  let Inst{43-47} = XA{4-0};
934  let Inst{48-52} = XB{4-0};
935  let Inst{53-60} = xo;
936  let Inst{61} = XA{5};
937  let Inst{62} = XB{5};
938  let Inst{63} = 0;
939}
940
941class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
942                              string asmstr, InstrItinClass itin,
943                              list<dag> pattern>
944  : PI<1, opcode, OOL, IOL, asmstr, itin> {
945  bits<3> AT;
946  bits<6> XA;
947  bits<6> XB;
948  bits<4> XMSK;
949  bits<2> YMSK;
950
951  let Pattern = pattern;
952
953  // The prefix.
954  let Inst{6-7} = 3;
955  let Inst{8-11} = 9;
956  let Inst{12-23} = 0;
957  let Inst{24-27} = XMSK;
958  let Inst{28-29} = YMSK;
959  let Inst{30-31} = 0;
960
961  // The instruction.
962  let Inst{38-40} = AT;
963  let Inst{41-42} = 0;
964  let Inst{43-47} = XA{4-0};
965  let Inst{48-52} = XB{4-0};
966  let Inst{53-60} = xo;
967  let Inst{61} = XA{5};
968  let Inst{62} = XB{5};
969  let Inst{63} = 0;
970}
971
972class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
973                               string asmstr, InstrItinClass itin,
974                               list<dag> pattern>
975  : PI<1, opcode, OOL, IOL, asmstr, itin> {
976  bits<3> AT;
977  bits<6> XA;
978  bits<6> XB;
979  bits<4> XMSK;
980  bits<4> YMSK;
981  bits<8> PMSK;
982
983  let Pattern = pattern;
984
985  // The prefix.
986  let Inst{6-7} = 3;
987  let Inst{8-11} = 9;
988  let Inst{12-15} = 0;
989  let Inst{16-23} = PMSK;
990  let Inst{24-27} = XMSK;
991  let Inst{28-31} = YMSK;
992
993  // The instruction.
994  let Inst{38-40} = AT;
995  let Inst{41-42} = 0;
996  let Inst{43-47} = XA{4-0};
997  let Inst{48-52} = XB{4-0};
998  let Inst{53-60} = xo;
999  let Inst{61} = XA{5};
1000  let Inst{62} = XB{5};
1001  let Inst{63} = 0;
1002}
1003
1004class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
1005                              string asmstr, InstrItinClass itin,
1006                              list<dag> pattern>
1007  : PI<1, opcode, OOL, IOL, asmstr, itin> {
1008  bits<3> AT;
1009  bits<6> XA;
1010  bits<6> XB;
1011  bits<4> XMSK;
1012  bits<4> YMSK;
1013  bits<4> PMSK;
1014
1015  let Pattern = pattern;
1016
1017  // The prefix.
1018  let Inst{6-7} = 3;
1019  let Inst{8-11} = 9;
1020  let Inst{12-15} = 0;
1021  let Inst{16-19} = PMSK;
1022  let Inst{20-23} = 0;
1023  let Inst{24-27} = XMSK;
1024  let Inst{28-31} = YMSK;
1025
1026  // The instruction.
1027  let Inst{38-40} = AT;
1028  let Inst{41-42} = 0;
1029  let Inst{43-47} = XA{4-0};
1030  let Inst{48-52} = XB{4-0};
1031  let Inst{53-60} = xo;
1032  let Inst{61} = XA{5};
1033  let Inst{62} = XB{5};
1034  let Inst{63} = 0;
1035}
1036
1037
1038
1039def Concats {
1040  dag VecsToVecPair0 =
1041    (v256i1 (INSERT_SUBREG
1042      (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
1043      $vs1, sub_vsx0));
1044  dag VecsToVecPair1 =
1045    (v256i1 (INSERT_SUBREG
1046      (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1047      $vs3, sub_vsx0));
1048}
1049
1050let Predicates = [PairedVectorMemops] in {
1051  def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1052            Concats.VecsToVecPair0>;
1053  def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
1054            Concats.VecsToVecPair0>;
1055  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
1056            (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
1057  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
1058            (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
1059}
1060
1061let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
1062  def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
1063                                  (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr",
1064                                  IIC_LdStLFD, []>;
1065  def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr),
1066                              "lxvpx $XTp, $addr", IIC_LdStLFD,
1067                              []>;
1068}
1069
1070let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
1071  def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
1072                                   (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr",
1073                                   IIC_LdStLFD, []>;
1074  def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr),
1075                               "stxvpx $XTp, $addr", IIC_LdStLFD,
1076                               []>;
1077}
1078
1079let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1080  defm PLXVP :
1081    8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),
1082                                (ins (memri34_pcrel $D, $RA):$addr), "plxvp $XTp, $addr",
1083                                IIC_LdStLFD>;
1084}
1085
1086let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1087  defm PSTXVP :
1088    8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),
1089                                (ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),
1090                                "pstxvp $XTp, $addr", IIC_LdStLFD>;
1091}
1092
1093let Predicates = [PairedVectorMemops] in {
1094  // Intrinsics for Paired Vector Loads.
1095  def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
1096  def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
1097  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1098    def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;
1099  }
1100  // Intrinsics for Paired Vector Stores.
1101  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst),
1102            (STXVP $XSp, memrix16:$dst)>;
1103  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),
1104            (STXVPX $XSp, XForm:$dst)>;
1105  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1106    def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),
1107              (PSTXVP $XSp, memri34:$dst)>;
1108  }
1109}
1110
1111let Predicates = [IsISA3_1] in {
1112  def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>;
1113  def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>;
1114  def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>;
1115}
1116
1117let Predicates = [PCRelativeMemops] in {
1118  // Load i32
1119  def : Pat<(i32 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1120            (PLBZpc $ga, 0)>;
1121  def : Pat<(i32 (extloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1122            (PLBZpc $ga, 0)>;
1123  def : Pat<(i32 (zextloadi8  (PPCmatpcreladdr PCRelForm:$ga))),
1124            (PLBZpc $ga, 0)>;
1125  def : Pat<(i32 (extloadi8   (PPCmatpcreladdr PCRelForm:$ga))),
1126            (PLBZpc $ga, 0)>;
1127  def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1128            (PLHApc $ga, 0)>;
1129  def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1130            (PLHZpc $ga, 0)>;
1131  def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1132            (PLHZpc $ga, 0)>;
1133  def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>;
1134
1135  // Store i32
1136  def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1137            (PSTBpc $RS, $ga, 0)>;
1138  def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1139            (PSTHpc $RS, $ga, 0)>;
1140  def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1141            (PSTWpc $RS, $ga, 0)>;
1142
1143  // Load i64
1144  def : Pat<(i64 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1145            (PLBZ8pc $ga, 0)>;
1146  def : Pat<(i64 (extloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1147            (PLBZ8pc $ga, 0)>;
1148  def : Pat<(i64 (zextloadi8  (PPCmatpcreladdr PCRelForm:$ga))),
1149            (PLBZ8pc $ga, 0)>;
1150  def : Pat<(i64 (extloadi8   (PPCmatpcreladdr PCRelForm:$ga))),
1151            (PLBZ8pc $ga, 0)>;
1152  def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1153            (PLHA8pc $ga, 0)>;
1154  def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1155            (PLHZ8pc $ga, 0)>;
1156  def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1157            (PLHZ8pc $ga, 0)>;
1158  def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1159            (PLWZ8pc $ga, 0)>;
1160  def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1161            (PLWA8pc $ga, 0)>;
1162  def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1163            (PLWZ8pc $ga, 0)>;
1164  def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>;
1165
1166  // Store i64
1167  def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1168            (PSTB8pc $RS, $ga, 0)>;
1169  def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1170            (PSTH8pc $RS, $ga, 0)>;
1171  def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1172            (PSTW8pc $RS, $ga, 0)>;
1173  def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1174            (PSTDpc $RS, $ga, 0)>;
1175
1176  // Load f32
1177  def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;
1178
1179  // Store f32
1180  def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
1181            (PSTFSpc $FRS, $ga, 0)>;
1182
1183  // Load f64
1184  def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))),
1185            (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
1186  def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>;
1187
1188  // Store f64
1189  def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
1190            (PSTFDpc $FRS, $ga, 0)>;
1191
1192  // Load f128
1193  def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))),
1194            (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
1195
1196  // Store f128
1197  def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1198            (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
1199
1200  // Load v4i32
1201  def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1202
1203  // Store v4i32
1204  def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1205            (PSTXVpc $XS, $ga, 0)>;
1206
1207  // Load v2i64
1208  def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1209
1210  // Store v2i64
1211  def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1212            (PSTXVpc $XS, $ga, 0)>;
1213
1214  // Load v4f32
1215  def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1216
1217  // Store v4f32
1218  def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1219            (PSTXVpc $XS, $ga, 0)>;
1220
1221  // Load v2f64
1222  def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1223
1224  // Store v2f64
1225  def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1226            (PSTXVpc $XS, $ga, 0)>;
1227
1228  // Atomic Load
1229  def : Pat<(atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga)),
1230            (PLBZpc $ga, 0)>;
1231  def : Pat<(atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga)),
1232            (PLHZpc $ga, 0)>;
1233  def : Pat<(atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga)),
1234            (PLWZpc $ga, 0)>;
1235  def : Pat<(atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga)),
1236            (PLDpc $ga, 0)>;
1237
1238  // Atomic Store
1239  def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1240            (PSTBpc $RS, $ga, 0)>;
1241  def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1242            (PSTHpc $RS, $ga, 0)>;
1243  def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1244            (PSTWpc $RS, $ga, 0)>;
1245  def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1246            (PSTB8pc $RS, $ga, 0)>;
1247  def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1248            (PSTH8pc $RS, $ga, 0)>;
1249  def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1250            (PSTW8pc $RS, $ga, 0)>;
1251  def : Pat<(atomic_store_64 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1252            (PSTDpc $RS, $ga, 0)>;
1253
1254  // Special Cases For PPCstore_scal_int_from_vsr
1255  def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1256            (PSTXSDpc $src, $dst, 0)>;
1257  def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1258            (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
1259
1260  def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
1261            (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
1262
1263  // If the PPCmatpcreladdr node is not caught by any other pattern it should be
1264  // caught here and turned into a paddi instruction to materialize the address.
1265  def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1266  // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize
1267  // tls global address with paddi instruction.
1268  def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1269  // PPCtlslocalexecmataddr node is used for TLS local exec models to
1270  // materialize tls global address with paddi instruction.
1271  def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),
1272            (PADDI8 $in, $addr)>;
1273}
1274
1275let Predicates = [PrefixInstrs] in {
1276  def XXPERMX :
1277    8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1278                            vsrc:$XC, u3imm:$IMM),
1279                            "xxpermx $XT, $XA, $XB, $XC, $IMM",
1280                            IIC_VecPerm, []>;
1281  def XXBLENDVB :
1282    8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1283                       vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
1284                       IIC_VecGeneral, []>;
1285  def XXBLENDVH :
1286    8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1287                       vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
1288                       IIC_VecGeneral, []>;
1289  def XXBLENDVW :
1290    8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1291                       vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
1292                       IIC_VecGeneral, []>;
1293  def XXBLENDVD :
1294    8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1295                       vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
1296                       IIC_VecGeneral, []>;
1297}
1298
1299// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt
1300// to spill part of the instruction when the values are similar.
1301let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
1302  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
1303                                     (ins i32imm:$IMM32),
1304                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
1305                                     []>;
1306  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
1307                                      (ins i32imm:$IMM32),
1308                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
1309                                      [(set v2f64:$XT,
1310                                            (PPCxxspltidp i32:$IMM32))]>;
1311  def XXSPLTI32DX :
1312      8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
1313                             (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),
1314                             "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
1315                             [(set v2i64:$XT,
1316                                   (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
1317                                                   i32:$IMM32))]>,
1318                             RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1319}
1320
1321let Predicates = [IsISA3_1] in {
1322  def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI),
1323                            "setbc $RST, $BI", IIC_IntCompare, []>,
1324                            SExt32To64, ZExt32To64;
1325  def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI),
1326                             "setbcr $RST, $BI", IIC_IntCompare, []>,
1327                             SExt32To64, ZExt32To64;
1328  def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI),
1329                             "setnbc $RST, $BI", IIC_IntCompare, []>,
1330                             SExt32To64;
1331  def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI),
1332                              "setnbcr $RST, $BI", IIC_IntCompare, []>,
1333                              SExt32To64;
1334
1335  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1336    def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI),
1337                               "setbc $RST, $BI", IIC_IntCompare, []>,
1338                               SExt32To64, ZExt32To64;
1339    def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI),
1340                                "setbcr $RST, $BI", IIC_IntCompare, []>,
1341                                SExt32To64, ZExt32To64;
1342    def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI),
1343                                "setnbc $RST, $BI", IIC_IntCompare, []>,
1344                                SExt32To64;
1345    def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI),
1346                                 "setnbcr $RST, $BI", IIC_IntCompare, []>,
1347                                 SExt32To64;
1348  }
1349
1350  def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
1351                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),
1352                                "vsldbi $VRT, $VRA, $VRB, $SD",
1353                                IIC_VecGeneral,
1354                                [(set v16i8:$VRT,
1355                                      (int_ppc_altivec_vsldbi v16i8:$VRA,
1356                                                              v16i8:$VRB,
1357                                                              timm:$SD))]>;
1358  def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
1359                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),
1360                                "vsrdbi $VRT, $VRA, $VRB, $SD",
1361                                IIC_VecGeneral,
1362                                [(set v16i8:$VRT,
1363                                      (int_ppc_altivec_vsrdbi v16i8:$VRA,
1364                                                              v16i8:$VRB,
1365                                                              timm:$SD))]>;
1366  defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB),
1367                                 "vstribr", "$VT, $VB", IIC_VecGeneral,
1368				 [(set v16i8:$VT,
1369                                       (int_ppc_altivec_vstribr v16i8:$VB))]>;
1370  defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB),
1371                                 "vstribl", "$VT, $VB", IIC_VecGeneral,
1372                                 [(set v16i8:$VT,
1373                                       (int_ppc_altivec_vstribl v16i8:$VB))]>;
1374  defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB),
1375                                 "vstrihr", "$VT, $VB", IIC_VecGeneral,
1376                                 [(set v8i16:$VT,
1377                                       (int_ppc_altivec_vstrihr v8i16:$VB))]>;
1378  defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB),
1379                                 "vstrihl", "$VT, $VB", IIC_VecGeneral,
1380                                 [(set v8i16:$VT,
1381                                       (int_ppc_altivec_vstrihl v8i16:$VB))]>;
1382  def VINSW :
1383    VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB),
1384             "vinsw $VD, $VB, $VA", IIC_VecGeneral,
1385             [(set v4i32:$VD,
1386                   (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>,
1387             RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
1388  def VINSD :
1389    VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB),
1390             "vinsd $VD, $VB, $VA", IIC_VecGeneral,
1391             [(set v2i64:$VD,
1392                   (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>,
1393             RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
1394  def VINSBVLX :
1395    VXForm_VTB5_RA5_ins<15, "vinsbvlx",
1396                        [(set v16i8:$VD,
1397                              (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA,
1398                                                        v16i8:$VB))]>;
1399  def VINSBVRX :
1400    VXForm_VTB5_RA5_ins<271, "vinsbvrx",
1401                        [(set v16i8:$VD,
1402                              (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA,
1403                                                        v16i8:$VB))]>;
1404  def VINSHVLX :
1405    VXForm_VTB5_RA5_ins<79, "vinshvlx",
1406                        [(set v8i16:$VD,
1407                              (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA,
1408                                                        v8i16:$VB))]>;
1409  def VINSHVRX :
1410    VXForm_VTB5_RA5_ins<335, "vinshvrx",
1411                        [(set v8i16:$VD,
1412                              (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA,
1413                                                        v8i16:$VB))]>;
1414  def VINSWVLX :
1415    VXForm_VTB5_RA5_ins<143, "vinswvlx",
1416                        [(set v4i32:$VD,
1417                              (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA,
1418                                                        v4i32:$VB))]>;
1419  def VINSWVRX :
1420    VXForm_VTB5_RA5_ins<399, "vinswvrx",
1421                        [(set v4i32:$VD,
1422                              (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA,
1423                                                        v4i32:$VB))]>;
1424  def VINSBLX :
1425    VXForm_VRT5_RAB5_ins<527, "vinsblx",
1426                         [(set v16i8:$VD,
1427                               (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA,
1428                                                        i32:$VB))]>;
1429  def VINSBRX :
1430    VXForm_VRT5_RAB5_ins<783, "vinsbrx",
1431                         [(set v16i8:$VD,
1432                               (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA,
1433                                                        i32:$VB))]>;
1434  def VINSHLX :
1435    VXForm_VRT5_RAB5_ins<591, "vinshlx",
1436                         [(set v8i16:$VD,
1437                               (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA,
1438                                                        i32:$VB))]>;
1439  def VINSHRX :
1440    VXForm_VRT5_RAB5_ins<847, "vinshrx",
1441                         [(set v8i16:$VD,
1442                               (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA,
1443                                                        i32:$VB))]>;
1444  def VINSWLX :
1445    VXForm_VRT5_RAB5_ins<655, "vinswlx",
1446                         [(set v4i32:$VD,
1447                               (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA,
1448                                                        i32:$VB))]>;
1449  def VINSWRX :
1450    VXForm_VRT5_RAB5_ins<911, "vinswrx",
1451                         [(set v4i32:$VD,
1452                               (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA,
1453                                                        i32:$VB))]>;
1454  def VINSDLX :
1455    VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),
1456             "vinsdlx $VD, $VA, $VB", IIC_VecGeneral,
1457              [(set v2i64:$VD,
1458                    (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>,
1459              RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
1460  def VINSDRX :
1461    VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),
1462             "vinsdrx $VD, $VA, $VB", IIC_VecGeneral,
1463              [(set v2i64:$VD,
1464                    (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>,
1465              RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
1466  def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB),
1467                                      "vextractbm $VD, $VB", IIC_VecGeneral,
1468                                      [(set i32:$VD,
1469                                      (int_ppc_altivec_vextractbm v16i8:$VB))]>,
1470                                      ZExt32To64;
1471  def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB),
1472                                      "vextracthm $VD, $VB", IIC_VecGeneral,
1473                                      [(set i32:$VD,
1474                                      (int_ppc_altivec_vextracthm v8i16:$VB))]>,
1475                                      ZExt32To64;
1476  def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB),
1477                                      "vextractwm $VD, $VB", IIC_VecGeneral,
1478                                      [(set i32:$VD,
1479                                      (int_ppc_altivec_vextractwm v4i32:$VB))]>,
1480                                      ZExt32To64;
1481  def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB),
1482                                      "vextractdm $VD, $VB", IIC_VecGeneral,
1483                                      [(set i32:$VD,
1484                                      (int_ppc_altivec_vextractdm v2i64:$VB))]>,
1485                                      ZExt32To64;
1486  def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB),
1487                                      "vextractqm $VD, $VB", IIC_VecGeneral,
1488                                      [(set i32:$VD,
1489                                      (int_ppc_altivec_vextractqm v1i128:$VB))]>;
1490  def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB),
1491                                     "vexpandbm $VD, $VB", IIC_VecGeneral,
1492                                     [(set v16i8:$VD, (int_ppc_altivec_vexpandbm
1493                                           v16i8:$VB))]>;
1494  def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB),
1495                                     "vexpandhm $VD, $VB", IIC_VecGeneral,
1496                                     [(set v8i16:$VD, (int_ppc_altivec_vexpandhm
1497                                           v8i16:$VB))]>;
1498  def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB),
1499                                     "vexpandwm $VD, $VB", IIC_VecGeneral,
1500                                     [(set v4i32:$VD, (int_ppc_altivec_vexpandwm
1501                                           v4i32:$VB))]>;
1502  def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB),
1503                                     "vexpanddm $VD, $VB", IIC_VecGeneral,
1504                                     [(set v2i64:$VD, (int_ppc_altivec_vexpanddm
1505                                           v2i64:$VB))]>;
1506  def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB),
1507                                     "vexpandqm $VD, $VB", IIC_VecGeneral,
1508                                     [(set v1i128:$VD, (int_ppc_altivec_vexpandqm
1509                                           v1i128:$VB))]>;
1510  def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB),
1511                                   "mtvsrbm $VD, $VB", IIC_VecGeneral,
1512                                   [(set v16i8:$VD,
1513                                         (int_ppc_altivec_mtvsrbm i64:$VB))]>;
1514  def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB),
1515                                   "mtvsrhm $VD, $VB", IIC_VecGeneral,
1516                                   [(set v8i16:$VD,
1517                                         (int_ppc_altivec_mtvsrhm i64:$VB))]>;
1518  def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB),
1519                                   "mtvsrwm $VD, $VB", IIC_VecGeneral,
1520                                   [(set v4i32:$VD,
1521                                         (int_ppc_altivec_mtvsrwm i64:$VB))]>;
1522  def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB),
1523                                   "mtvsrdm $VD, $VB", IIC_VecGeneral,
1524                                   [(set v2i64:$VD,
1525                                         (int_ppc_altivec_mtvsrdm i64:$VB))]>;
1526  def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB),
1527                                   "mtvsrqm $VD, $VB", IIC_VecGeneral,
1528                                   [(set v1i128:$VD,
1529                                         (int_ppc_altivec_mtvsrqm i64:$VB))]>;
1530  def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D),
1531                        "mtvsrbmi $RT, $D", IIC_VecGeneral,
1532                        [(set v16i8:$RT,
1533                              (int_ppc_altivec_mtvsrbm imm:$D))]>;
1534  def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD),
1535                                  (ins vrrc:$VB, u1imm:$MP),
1536                                  "vcntmbb $RD, $VB, $MP", IIC_VecGeneral,
1537                                  [(set i64:$RD, (int_ppc_altivec_vcntmbb
1538                                        v16i8:$VB, timm:$MP))]>;
1539  def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD),
1540                                  (ins vrrc:$VB, u1imm:$MP),
1541                                  "vcntmbh $RD, $VB, $MP", IIC_VecGeneral,
1542                                  [(set i64:$RD, (int_ppc_altivec_vcntmbh
1543                                        v8i16:$VB, timm:$MP))]>;
1544  def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD),
1545                                  (ins vrrc:$VB, u1imm:$MP),
1546                                  "vcntmbw $RD, $VB, $MP", IIC_VecGeneral,
1547                                  [(set i64:$RD, (int_ppc_altivec_vcntmbw
1548                                        v4i32:$VB, timm:$MP))]>;
1549  def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD),
1550                                  (ins vrrc:$VB, u1imm:$MP),
1551                                  "vcntmbd $RD, $VB, $MP", IIC_VecGeneral,
1552                                  [(set i64:$RD, (int_ppc_altivec_vcntmbd
1553                                        v2i64:$VB, timm:$MP))]>;
1554  def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT),
1555                             (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1556                             "vextdubvlx $RT, $RA, $RB, $RC",
1557                             IIC_VecGeneral,
1558                             [(set v2i64:$RT,
1559                                   (int_ppc_altivec_vextdubvlx v16i8:$RA,
1560                                                               v16i8:$RB,
1561                                                               i32:$RC))]>;
1562  def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT),
1563                             (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1564                             "vextdubvrx $RT, $RA, $RB, $RC",
1565                             IIC_VecGeneral,
1566                             [(set v2i64:$RT,
1567                                   (int_ppc_altivec_vextdubvrx v16i8:$RA,
1568                                                               v16i8:$RB,
1569                                                               i32:$RC))]>;
1570  def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT),
1571                             (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1572                             "vextduhvlx $RT, $RA, $RB, $RC",
1573                             IIC_VecGeneral,
1574                             [(set v2i64:$RT,
1575                                   (int_ppc_altivec_vextduhvlx v8i16:$RA,
1576                                                               v8i16:$RB,
1577                                                               i32:$RC))]>;
1578  def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT),
1579                             (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1580                             "vextduhvrx $RT, $RA, $RB, $RC",
1581                             IIC_VecGeneral,
1582                             [(set v2i64:$RT,
1583                                   (int_ppc_altivec_vextduhvrx v8i16:$RA,
1584                                                               v8i16:$RB,
1585                                                               i32:$RC))]>;
1586  def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT),
1587                             (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1588                             "vextduwvlx $RT, $RA, $RB, $RC",
1589                             IIC_VecGeneral,
1590                             [(set v2i64:$RT,
1591                                   (int_ppc_altivec_vextduwvlx v4i32:$RA,
1592                                                               v4i32:$RB,
1593                                                               i32:$RC))]>;
1594  def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT),
1595                             (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1596                             "vextduwvrx $RT, $RA, $RB, $RC",
1597                             IIC_VecGeneral,
1598                             [(set v2i64:$RT,
1599                                   (int_ppc_altivec_vextduwvrx v4i32:$RA,
1600                                                               v4i32:$RB,
1601                                                               i32:$RC))]>;
1602  def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT),
1603                            (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1604                            "vextddvlx $RT, $RA, $RB, $RC",
1605                            IIC_VecGeneral,
1606                            [(set v2i64:$RT,
1607                                  (int_ppc_altivec_vextddvlx v2i64:$RA,
1608                                                             v2i64:$RB,
1609                                                             i32:$RC))]>;
1610  def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT),
1611                            (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1612                            "vextddvrx $RT, $RA, $RB, $RC",
1613                            IIC_VecGeneral,
1614                            [(set v2i64:$RT,
1615                                  (int_ppc_altivec_vextddvrx v2i64:$RA,
1616                                                             v2i64:$RB,
1617                                                             i32:$RC))]>;
1618   def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1619                         "vpdepd $VD, $VA, $VB", IIC_VecGeneral,
1620                         [(set v2i64:$VD,
1621                         (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>;
1622   def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1623                         "vpextd $VD, $VA, $VB", IIC_VecGeneral,
1624                         [(set v2i64:$VD,
1625                         (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>;
1626   def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1627                       "pdepd $RA, $RST, $RB", IIC_IntGeneral,
1628                       [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>;
1629   def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1630                       "pextd $RA, $RST, $RB", IIC_IntGeneral,
1631                       [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>;
1632   def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1633                          "vcfuged $VD, $VA, $VB", IIC_VecGeneral,
1634                          [(set v2i64:$VD,
1635                          (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>;
1636   def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N),
1637                                "vgnb $RD, $VB, $N", IIC_VecGeneral,
1638                                [(set i64:$RD,
1639                                (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>;
1640   def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1641                        "cfuged $RA, $RST, $RB", IIC_IntGeneral,
1642                        [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>;
1643   def XXEVAL :
1644     8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1645                            vsrc:$XC, u8imm:$IMM),
1646                            "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
1647                            [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
1648                                  v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
1649   def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1650                         "vclzdm $VD, $VA, $VB", IIC_VecGeneral,
1651                         [(set v2i64:$VD,
1652                         (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>;
1653   def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1654                         "vctzdm $VD, $VA, $VB", IIC_VecGeneral,
1655                         [(set v2i64:$VD,
1656                         (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>;
1657   def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1658                         "cntlzdm $RA, $RST, $RB", IIC_IntGeneral,
1659                         [(set i64:$RA,
1660                         (int_ppc_cntlzdm i64:$RST, i64:$RB))]>;
1661   def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1662                         "cnttzdm $RA, $RST, $RB", IIC_IntGeneral,
1663                         [(set i64:$RA,
1664                         (int_ppc_cnttzdm i64:$RST, i64:$RB))]>;
1665   def XXGENPCVBM :
1666     XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1667                        "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1668   def XXGENPCVHM :
1669     XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1670                        "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1671   def XXGENPCVWM :
1672     XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1673                        "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1674   def XXGENPCVDM :
1675     XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1676                        "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1677   def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB),
1678                         "vclrlb $VD, $VA, $VB", IIC_VecGeneral,
1679                         [(set v16i8:$VD,
1680                               (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>;
1681   def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB),
1682                         "vclrrb $VD, $VA, $VB", IIC_VecGeneral,
1683                         [(set v16i8:$VD,
1684                               (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>;
1685  def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1686                        "vmulld $VD, $VA, $VB", IIC_VecGeneral,
1687                        [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>;
1688  def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1689                         "vmulhsw $VD, $VA, $VB", IIC_VecGeneral,
1690                         [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>;
1691  def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1692                         "vmulhuw $VD, $VA, $VB", IIC_VecGeneral,
1693                         [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>;
1694  def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1695                         "vmulhsd $VD, $VA, $VB", IIC_VecGeneral,
1696                         [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>;
1697  def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1698                         "vmulhud $VD, $VA, $VB", IIC_VecGeneral,
1699                         [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>;
1700  def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1701                        "vmodsw $VD, $VA, $VB", IIC_VecGeneral,
1702                        [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>;
1703  def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1704                        "vmoduw $VD, $VA, $VB", IIC_VecGeneral,
1705                        [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>;
1706  def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1707                        "vmodsd $VD, $VA, $VB", IIC_VecGeneral,
1708                        [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>;
1709  def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1710                        "vmodud $VD, $VA, $VB", IIC_VecGeneral,
1711                        [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>;
1712  def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1713                        "vdivsw $VD, $VA, $VB", IIC_VecGeneral,
1714                        [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>;
1715  def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1716                        "vdivuw $VD, $VA, $VB", IIC_VecGeneral,
1717                        [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>;
1718  def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1719                        "vdivsd $VD, $VA, $VB", IIC_VecGeneral,
1720                        [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>;
1721  def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1722                        "vdivud $VD, $VA, $VB", IIC_VecGeneral,
1723                        [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>;
1724  def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1725                         "vdivesw $VD, $VA, $VB", IIC_VecGeneral,
1726                         [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA,
1727                               v4i32:$VB))]>;
1728  def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1729                         "vdiveuw $VD, $VA, $VB", IIC_VecGeneral,
1730                         [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA,
1731                               v4i32:$VB))]>;
1732  def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1733                         "vdivesd $VD, $VA, $VB", IIC_VecGeneral,
1734                         [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA,
1735                               v2i64:$VB))]>;
1736  def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1737                         "vdiveud $VD, $VA, $VB", IIC_VecGeneral,
1738                         [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA,
1739                               v2i64:$VB))]>;
1740  def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
1741                                    "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
1742  def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RST),
1743                     "brh $RA, $RST", IIC_IntRotate, []>;
1744  def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RST),
1745                     "brw $RA, $RST", IIC_IntRotate,
1746                     [(set i32:$RA, (bswap i32:$RST))]>;
1747  let isCodeGenOnly = 1 in {
1748    def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RST),
1749                        "brh $RA, $RST", IIC_IntRotate, []>;
1750    def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RST),
1751                        "brw $RA, $RST", IIC_IntRotate, []>;
1752  }
1753  def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RST),
1754                     "brd $RA, $RST", IIC_IntRotate,
1755                     [(set i64:$RA, (bswap i64:$RST))]>;
1756
1757  // The XFormMemOp flag for the following 8 instructions is set on
1758  // the instruction format.
1759  let mayLoad = 1, mayStore = 0 in {
1760    def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
1761    def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
1762    def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
1763    def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
1764  }
1765
1766  let mayLoad = 0, mayStore = 1 in {
1767    def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
1768    def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
1769    def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
1770    def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
1771  }
1772
1773  def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1774                         "vmulesd $VD, $VA, $VB", IIC_VecGeneral,
1775                         [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA,
1776                               v2i64:$VB))]>;
1777  def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1778                         "vmuleud $VD, $VA, $VB", IIC_VecGeneral,
1779                         [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA,
1780                               v2i64:$VB))]>;
1781  def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1782                         "vmulosd $VD, $VA, $VB", IIC_VecGeneral,
1783                         [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA,
1784                               v2i64:$VB))]>;
1785  def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1786                         "vmuloud $VD, $VA, $VB", IIC_VecGeneral,
1787                         [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA,
1788                               v2i64:$VB))]>;
1789  def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
1790                           "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral,
1791                           [(set v1i128:$RT, (int_ppc_altivec_vmsumcud
1792                                 v2i64:$RA, v2i64:$RB, v1i128:$RC))]>;
1793  def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1794                        "vdivsq $VD, $VA, $VB", IIC_VecGeneral,
1795                        [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>;
1796  def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1797                        "vdivuq $VD, $VA, $VB", IIC_VecGeneral,
1798                        [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>;
1799  def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1800                         "vdivesq $VD, $VA, $VB", IIC_VecGeneral,
1801                         [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA,
1802			       v1i128:$VB))]>;
1803  def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1804                         "vdiveuq $VD, $VA, $VB", IIC_VecGeneral,
1805                         [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA,
1806			       v1i128:$VB))]>;
1807  def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>;
1808  def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>;
1809  def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>;
1810  def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>;
1811  def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>;
1812  def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>;
1813  def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1814                        "vmodsq $VD, $VA, $VB", IIC_VecGeneral,
1815                        [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>;
1816  def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
1817                        "vmoduq $VD, $VA, $VB", IIC_VecGeneral,
1818                        [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>;
1819  def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB),
1820                               "vextsd2q $VD, $VB", IIC_VecGeneral,
1821                               [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>;
1822  def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB),
1823                               "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>;
1824  def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB),
1825                               "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>;
1826  def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
1827                               [(set v1i128:$VD,
1828                                   (int_ppc_altivec_vrlqnm v1i128:$VA,
1829                                                           v1i128:$VB))]>;
1830  def VRLQMI : VXForm_1<69, (outs vrrc:$VD),
1831                        (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),
1832                        "vrlqmi $VD, $VA, $VB", IIC_VecFP,
1833                        [(set v1i128:$VD,
1834                          (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB,
1835                                                  v1i128:$VDi))]>,
1836                        RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
1837  def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
1838  def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
1839  def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
1840  def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
1841  def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
1842  def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
1843  def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
1844  def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
1845  def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),
1846                             "lxvkq $XT, $UIM", IIC_VecGeneral, []>;
1847}
1848
1849let Predicates = [IsISA3_1, HasVSX] in {
1850  def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
1851  def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
1852  def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp",
1853                               [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>;
1854  def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp",
1855                               [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>;
1856}
1857
1858// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
1859// This is analogous to the CRNotPat multiclass but specifically for Power10
1860// and newer subtargets since the extended forms use Set Boolean instructions.
1861// The first two anonymous patterns defined are actually a duplicate of those
1862// in CRNotPat, but it is preferable to define both multiclasses as complete
1863// ones rather than pulling that small common section out.
1864multiclass P10ReverseSetBool<dag pattern, dag result> {
1865  def : Pat<pattern, (crnot result)>;
1866  def : Pat<(not pattern), result>;
1867
1868  def : Pat<(i32 (zext pattern)),
1869            (SETBCR result)>;
1870  def : Pat<(i64 (zext pattern)),
1871            (SETBCR8 result)>;
1872
1873  def : Pat<(i32 (sext pattern)),
1874            (SETNBCR result)>;
1875  def : Pat<(i64 (sext pattern)),
1876            (SETNBCR8 result)>;
1877
1878  def : Pat<(i32 (anyext pattern)),
1879            (SETBCR result)>;
1880  def : Pat<(i64 (anyext pattern)),
1881            (SETBCR8 result)>;
1882}
1883
1884multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
1885                               ImmLeaf SExtTy, I Cmpi, I Cmpli,
1886                               I Cmp, I Cmpl> {
1887  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1888                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>;
1889  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1890                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>;
1891  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1892                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>;
1893  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1894                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>;
1895  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1896                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>;
1897
1898  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
1899                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>;
1900  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
1901                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>;
1902  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
1903                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>;
1904  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
1905                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>;
1906  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
1907                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>;
1908  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
1909                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>;
1910}
1911
1912multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> {
1913  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1914                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
1915  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1916                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
1917  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1918                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
1919  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1920                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
1921  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
1922                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
1923  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1924                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
1925  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
1926                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
1927}
1928
1929let Predicates = [IsISA3_1] in {
1930  def : Pat<(i32 (zext i1:$in)),
1931            (SETBC $in)>;
1932  def : Pat<(i64 (zext i1:$in)),
1933            (SETBC8 $in)>;
1934  def : Pat<(i32 (sext i1:$in)),
1935            (SETNBC $in)>;
1936  def : Pat<(i64 (sext i1:$in)),
1937            (SETNBC8 $in)>;
1938  def : Pat<(i32 (anyext i1:$in)),
1939            (SETBC $in)>;
1940  def : Pat<(i64 (anyext i1:$in)),
1941            (SETBC8 $in)>;
1942
1943  // Instantiation of the set boolean reverse patterns for 32-bit integers.
1944  defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,
1945                             CMPWI, CMPLWI, CMPW, CMPLW>;
1946  defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
1947                           (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
1948                                           (LO16 imm:$imm)), sub_eq)>;
1949
1950  // Instantiation of the set boolean reverse patterns for 64-bit integers.
1951  defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,
1952                             CMPDI, CMPLDI, CMPD, CMPLD>;
1953  defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
1954                           (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
1955                                           (LO16 imm:$imm)), sub_eq)>;
1956}
1957
1958// Instantiation of the set boolean reverse patterns for f32, f64, f128.
1959let Predicates = [IsISA3_1, HasFPU] in {
1960  defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;
1961  defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;
1962  defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;
1963}
1964
1965//---------------------------- Anonymous Patterns ----------------------------//
1966let Predicates = [IsISA3_1] in {
1967  // Exploit the vector multiply high instructions using intrinsics.
1968  def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),
1969            (v4i32 (VMULHSW $vA, $vB))>;
1970  def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)),
1971            (v4i32 (VMULHUW $vA, $vB))>;
1972  def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)),
1973            (v2i64 (VMULHSD $vA, $vB))>;
1974  def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)),
1975            (v2i64 (VMULHUD $vA, $vB))>;
1976  def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
1977            (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
1978  def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
1979            (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
1980  def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
1981            (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
1982  def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
1983            (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
1984  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
1985            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
1986  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
1987            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
1988  def : Pat<(srl (bswap i32:$RS), (i32 16)),
1989            (RLDICL_32 (BRH $RS), 0, 48)>;
1990  def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))),
1991            (RLDICL_32_64 (BRH $RS), 0, 48)>;
1992  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),
1993             (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;
1994  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),
1995             (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;
1996  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)),
1997             (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;
1998  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)),
1999             (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;
2000
2001  def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
2002            (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
2003
2004  def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
2005             (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;
2006}
2007
2008let Predicates = [IsISA3_1, HasVSX] in {
2009  def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
2010            (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;
2011  def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
2012            (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
2013}
2014
2015let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
2016  // Store element 0 of a VSX register to memory
2017  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst),
2018            (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>;
2019  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst),
2020            (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>;
2021  def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst),
2022            (STXVRWX $src, ForceXForm:$dst)>;
2023  def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst),
2024            (STXVRWX $src, ForceXForm:$dst)>;
2025  def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst),
2026            (STXVRDX $src, ForceXForm:$dst)>;
2027  def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),
2028            (STXVRDX $src, ForceXForm:$dst)>;
2029  // Load element 0 of a VSX register to memory
2030  def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))),
2031            (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>;
2032  def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))),
2033            (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>;
2034 }
2035
2036// FIXME: The swap is overkill when the shift amount is a constant.
2037// We should just fix the constant in the DAG.
2038let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
2039  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
2040            (v1i128 (VSLQ v1i128:$VRA,
2041                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2042                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2043  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
2044            (v1i128 (VSLQ v1i128:$VRA,
2045                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2046                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2047  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
2048            (v1i128 (VSRQ v1i128:$VRA,
2049                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2050                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2051  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
2052            (v1i128 (VSRQ v1i128:$VRA,
2053                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2054                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2055  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
2056            (v1i128 (VSRAQ v1i128:$VRA,
2057                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2058                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2059  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
2060            (v1i128 (VSRAQ v1i128:$VRA,
2061                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2062                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2063}
2064
2065class xxevalPattern <dag pattern, bits<8> imm> :
2066  Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
2067
2068let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
2069 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
2070                                i32immNonAllOneNonZero:$A,
2071                                i32immNonAllOneNonZero:$A,
2072                                i32immNonAllOneNonZero:$A)),
2073           (v4i32 (XXSPLTIW imm:$A))>;
2074 def : Pat<(f32 nzFPImmAsi32:$A),
2075           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2076                             VSFRC)>;
2077 def : Pat<(f64 nzFPImmAsi32:$A),
2078           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2079                             VSFRC)>;
2080
2081// To replace constant pool with XXSPLTI32DX for scalars.
2082def : Pat<(f32 nzFPImmAsi64:$A),
2083          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0,
2084                                        (getFPAs64BitIntHi $A)),
2085                                        1, (getFPAs64BitIntLo $A)),
2086                            VSSRC)>;
2087
2088def : Pat<(f64 nzFPImmAsi64:$A),
2089          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0,
2090                                        (getFPAs64BitIntHi $A)),
2091                                        1, (getFPAs64BitIntLo $A)),
2092                            VSFRC)>;
2093
2094  // Anonymous patterns for XXEVAL
2095  // AND
2096  // and(A, B, C)
2097  def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
2098  // and(A, xor(B, C))
2099  def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
2100  // and(A, or(B, C))
2101  def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
2102  // and(A, nor(B, C))
2103  def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
2104  // and(A, eqv(B, C))
2105  def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
2106  // and(A, nand(B, C))
2107  def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
2108
2109  // NAND
2110  // nand(A, B, C)
2111  def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
2112                       !sub(255, 1)>;
2113  // nand(A, xor(B, C))
2114  def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
2115                       !sub(255, 6)>;
2116  // nand(A, or(B, C))
2117  def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
2118                       !sub(255, 7)>;
2119  // nand(A, nor(B, C))
2120  def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
2121                       !sub(255, 8)>;
2122  // nand(A, eqv(B, C))
2123  def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
2124                       !sub(255, 9)>;
2125  // nand(A, nand(B, C))
2126  def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
2127                       !sub(255, 14)>;
2128
2129  // EQV
2130  // (eqv A, B, C)
2131  def : xxevalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),
2132                          (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))),
2133                       150>;
2134  // (eqv A, (and B, C))
2135  def : xxevalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>;
2136  // (eqv A, (or B, C))
2137  def : xxevalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>;
2138
2139  // NOR
2140  // (nor A, B, C)
2141  def : xxevalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>;
2142  // (nor A, (and B, C))
2143  def : xxevalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>;
2144  // (nor A, (eqv B, C))
2145  def : xxevalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>;
2146  // (nor A, (nand B, C))
2147  def : xxevalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>;
2148  // (nor A, (nor B, C))
2149  def : xxevalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>;
2150  // (nor A, (xor B, C))
2151  def : xxevalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>;
2152
2153  // OR
2154  // (or A, B, C)
2155  def : xxevalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>;
2156  // (or A, (and B, C))
2157  def : xxevalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>;
2158  // (or A, (eqv B, C))
2159  def : xxevalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>;
2160  // (or A, (nand B, C))
2161  def : xxevalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>;
2162  // (or A, (nor B, C))
2163  def : xxevalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>;
2164  // (or A, (xor B, C))
2165  def : xxevalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>;
2166
2167  // XOR
2168  // (xor A, B, C)
2169  def : xxevalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>;
2170  // (xor A, (and B, C))
2171  def : xxevalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>;
2172  // (xor A, (or B, C))
2173  def : xxevalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>;
2174
2175  // Anonymous patterns to select prefixed VSX loads and stores.
2176  // Load / Store f128
2177  def : Pat<(f128 (load PDForm:$src)),
2178            (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>;
2179  def : Pat<(store f128:$XS, PDForm:$dst),
2180            (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>;
2181
2182  // Load / Store v4i32
2183  def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>;
2184  def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2185
2186  // Load / Store v2i64
2187  def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>;
2188  def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2189
2190  // Load / Store v4f32
2191  def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>;
2192  def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2193
2194  // Load / Store v2f64
2195  def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>;
2196  def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2197
2198  // Cases For PPCstore_scal_int_from_vsr
2199  def : Pat<(PPCstore_scal_int_from_vsr f64:$src, PDForm:$dst, 8),
2200            (PSTXSD $src, PDForm:$dst)>;
2201  def : Pat<(PPCstore_scal_int_from_vsr f128:$src, PDForm:$dst, 8),
2202            (PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>;
2203}
2204
2205let Predicates = [PrefixInstrs] in {
2206  def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
2207  def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
2208  def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
2209            (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
2210                                       (COPY_TO_REGCLASS $B, VSRC),
2211                                       (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
2212  def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),
2213            (COPY_TO_REGCLASS
2214                   (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC),
2215                              (COPY_TO_REGCLASS $B, VSRC),
2216                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2217  def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)),
2218            (COPY_TO_REGCLASS
2219                   (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC),
2220                              (COPY_TO_REGCLASS $B, VSRC),
2221                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2222  def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C),
2223            (XXBLENDVW $A, $B, $C)>;
2224  def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
2225            (XXBLENDVD $A, $B, $C)>;
2226
2227  // Anonymous patterns to select prefixed loads and stores.
2228  // Load i32
2229  def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2230  def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2231  def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2232  def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2233  def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2234  def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2235  def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>;
2236  def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>;
2237
2238  // Store i32
2239  def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>;
2240  def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>;
2241  def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>;
2242
2243  // Load i64
2244  def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2245  def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2246  def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2247  def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2248  def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2249  def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2250  def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>;
2251  def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2252  def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2253  def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>;
2254  def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>;
2255
2256  // Store i64
2257  def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>;
2258  def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;
2259  def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;
2260  def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;
2261
2262  // Load / Store f32
2263  def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;
2264  def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;
2265
2266  // Load / Store f64
2267  def : Pat<(f64 (extloadf32 PDForm:$src)),
2268            (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;
2269  def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;
2270  def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;
2271
2272  // Atomic Load
2273  def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>;
2274  def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>;
2275  def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>;
2276  def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>;
2277
2278  // Atomic Store
2279  def : Pat<(atomic_store_8 PDForm:$dst, i32:$RS), (PSTB $RS, memri34:$dst)>;
2280  def : Pat<(atomic_store_16 PDForm:$dst, i32:$RS), (PSTH $RS, memri34:$dst)>;
2281  def : Pat<(atomic_store_32 PDForm:$dst, i32:$RS), (PSTW $RS, memri34:$dst)>;
2282  def : Pat<(atomic_store_64 PDForm:$dst, i64:$RS), (PSTD $RS, memri34:$dst)>;
2283
2284  // Prefixed fpext to v2f64
2285  def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
2286            (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
2287}
2288
2289def InsertEltShift {
2290  dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32));
2291  dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30);
2292  dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29);
2293  dag Left1 = (RLWINM $rB, 1, 0, 30);
2294  dag Left2 = (RLWINM $rB, 2, 0, 29);
2295  dag Left3 = (RLWINM8 $rB, 3, 0, 28);
2296}
2297
2298let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
2299  // Indexed vector insert element
2300  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
2301            (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>;
2302  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
2303            (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2304  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2305            (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2306  def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2307            (VINSDRX $vDi, InsertEltShift.Left3, $rA)>;
2308
2309  def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)),
2310            (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
2311
2312  def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2313            (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2314  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
2315            (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2316  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
2317            (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2318  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
2319            (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2320  let AddedComplexity = 400 in {
2321    // Immediate vector insert element
2322    foreach Idx = [0, 1, 2, 3] in {
2323      def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)),
2324                (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>;
2325    }
2326    foreach i = [0, 1] in
2327     def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))),
2328               (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>;
2329  }
2330}
2331
2332let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
2333  // Indexed vector insert element
2334  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)),
2335            (VINSBLX $vDi, $rB, $rA)>;
2336  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)),
2337            (VINSHLX $vDi, InsertEltShift.Left1, $rA)>;
2338  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)),
2339            (VINSWLX $vDi, InsertEltShift.Left2, $rA)>;
2340
2341  def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i32:$rB)),
2342            (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>;
2343}
2344
2345let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
2346  // Indexed vector insert element
2347  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
2348            (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>;
2349  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
2350            (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2351  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2352            (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2353  def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2354            (VINSDLX $vDi, InsertEltShift.Left3, $rA)>;
2355
2356  def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i64:$rB)),
2357            (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
2358
2359  def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2360            (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2361  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
2362            (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2363  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
2364            (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2365  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
2366            (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2367}
2368
2369let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
2370  // Immediate vector insert element
2371  foreach Ty = [i32, i64] in {
2372    foreach Idx = [0, 1, 2, 3] in {
2373      def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))),
2374               (VINSW $vDi, !mul(Idx, 4), $rA)>;
2375    }
2376  }
2377
2378  foreach Idx = [0, 1] in
2379    def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)),
2380              (VINSD $vDi, !mul(Idx, 8), $rA)>;
2381}
2382