1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8// 9//===----------------------------------------------------------------------===// 10// 11// This file describes the instructions introduced for the Power10 CPU. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Naming convention for future instruction formats 17// 18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+ 19// 20// Where: 21// <INSTR_FORM> - name of instruction format as per the ISA 22// (X-Form, VX-Form, etc.) 23// <OP_TYPE> - operand type 24// * FRT/RT/VT/XT/BT - target register 25// (FPR, GPR, VR, VSR, CR-bit respectively) 26// In some situations, the 'T' is replaced by 27// 'D' when describing the target register. 28// * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.) 29// * IMM - immediate (where signedness matters, 30// this is SI/UI for signed/unsigned) 31// * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp) 32// * R - PC-Relative bit 33// (denotes that the address is computed pc-relative) 34// * VRM - Masked Registers 35// * AT - target accumulator 36// * N - the Nth bit in a VSR 37// * Additional 1-bit operands may be required for certain 38// instruction formats such as: MC, P, MP 39// * X / Y / P - mask values. In the instruction encoding, this is 40// represented as XMSK, YMSK and PMSK. 41// * MEM - indicates if the instruction format requires any memory 42// accesses. This does not have <OP_LENGTH> attached to it. 43// <OP_LENGTH> - the length of each operand in bits. 44// For operands that are 1 bit, the '1' is omitted from the name. 45// 46// Example: 8RR_XX4Form_IMM8_XTAB6 47// 8RR_XX4Form is the instruction format. 48// The operand is an 8-bit immediate (IMM), the destination (XT) 49// and sources (XA, XB) that are all 6-bits. The destination and 50// source registers are combined if they are of the same length. 51// Moreover, the order of operands reflects the order of operands 52// in the encoding. 53 54//-------------------------- Predicate definitions ---------------------------// 55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; 56 57 58//===----------------------------------------------------------------------===// 59// PowerPC ISA 3.1 specific type constraints. 60// 61 62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>, 63 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3> 64]>; 65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [ 66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>, 67 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32> 68]>; 69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ 70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> 71]>; 72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ 73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2> 74]>; 75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ 76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2> 77]>; 78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ 79 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> 80]>; 81 82//===----------------------------------------------------------------------===// 83// ISA 3.1 specific PPCISD nodes. 84// 85 86def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>; 87def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>; 88def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>; 89def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx, 90 []>; 91def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx, 92 []>; 93def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>; 94 95//===----------------------------------------------------------------------===// 96 97// PC Relative flag (for instructions that use the address of the prefix for 98// address computations). 99class isPCRel { bit PCRel = 1; } 100 101// PowerPC specific type constraints. 102def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [ 103 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 104]>; 105 106// PPC Specific DAG Nodes. 107def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, 108 [SDNPHasChain, SDNPMayLoad]>; 109 110// Top-level class for prefixed instructions. 111class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr, 112 InstrItinClass itin> : Instruction { 113 field bits<64> Inst; 114 field bits<64> SoftFail = 0; 115 bit PCRel = 0; // Default value, set by isPCRel. 116 let Size = 8; 117 118 let Namespace = "PPC"; 119 let OutOperandList = OOL; 120 let InOperandList = IOL; 121 let AsmString = asmstr; 122 let Itinerary = itin; 123 let Inst{0-5} = pref; 124 let Inst{32-37} = opcode; 125 126 bits<1> PPC970_First = 0; 127 bits<1> PPC970_Single = 0; 128 bits<1> PPC970_Cracked = 0; 129 bits<3> PPC970_Unit = 0; 130 131 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 132 /// these must be reflected there! See comments there for what these are. 133 let TSFlags{0} = PPC970_First; 134 let TSFlags{1} = PPC970_Single; 135 let TSFlags{2} = PPC970_Cracked; 136 let TSFlags{5-3} = PPC970_Unit; 137 138 bits<1> Prefixed = 1; // This is a prefixed instruction. 139 let TSFlags{7} = Prefixed; 140 141 // For cases where multiple instruction definitions really represent the 142 // same underlying instruction but with one definition for 64-bit arguments 143 // and one for 32-bit arguments, this bit breaks the degeneracy between 144 // the two forms and allows TableGen to generate mapping tables. 145 bit Interpretation64Bit = 0; 146 147 // Fields used for relation models. 148 string BaseName = ""; 149} 150 151// VX-Form: [ PO VT R VB RC XO ] 152class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr, 153 InstrItinClass itin, list<dag> pattern> 154 : I<4, OOL, IOL, asmstr, itin> { 155 bits<5> VT; 156 bits<5> VB; 157 bit RC = 0; 158 159 let Pattern = pattern; 160 161 let Inst{6-10} = VT; 162 let Inst{11-15} = R; 163 let Inst{16-20} = VB; 164 let Inst{21} = RC; 165 let Inst{22-31} = xo; 166} 167 168// Multiclass definition to account for record and non-record form 169// instructions of VXRForm. 170multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL, 171 string asmbase, string asmstr, 172 InstrItinClass itin, list<dag> pattern> { 173 let BaseName = asmbase in { 174 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL, 175 !strconcat(asmbase, !strconcat(" ", asmstr)), 176 itin, pattern>, RecFormRel; 177 let Defs = [CR6] in 178 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL, 179 !strconcat(asmbase, !strconcat(". ", asmstr)), 180 itin, []>, isRecordForm, RecFormRel; 181 } 182} 183 184class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 185 InstrItinClass itin, list<dag> pattern> 186 : PI<1, opcode, OOL, IOL, asmstr, itin> { 187 bits<5> RST; 188 bits<5> RA; 189 bits<34> D; 190 191 let Pattern = pattern; 192 193 // The prefix. 194 let Inst{6-7} = 2; 195 let Inst{8-10} = 0; 196 let Inst{11} = PCRel; 197 let Inst{12-13} = 0; 198 let Inst{14-31} = D{33-16}; // d0 199 200 // The instruction. 201 let Inst{38-42} = RST{4-0}; 202 let Inst{43-47} = RA; 203 let Inst{48-63} = D{15-0}; // d1 204} 205 206class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 207 InstrItinClass itin, list<dag> pattern> 208 : PI<1, opcode, OOL, IOL, asmstr, itin> { 209 bits<5> RT; 210 bits<5> RA; 211 bits<34> SI; 212 213 let Pattern = pattern; 214 215 // The prefix. 216 let Inst{6-7} = 2; 217 let Inst{8-10} = 0; 218 let Inst{11} = PCRel; 219 let Inst{12-13} = 0; 220 let Inst{14-31} = SI{33-16}; 221 222 // The instruction. 223 let Inst{38-42} = RT; 224 let Inst{43-47} = RA; 225 let Inst{48-63} = SI{15-0}; 226} 227 228class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 229 InstrItinClass itin, list<dag> pattern> 230 : PI<1, opcode, OOL, IOL, asmstr, itin> { 231 bits<5> RT; 232 bits<34> SI; 233 234 let Pattern = pattern; 235 236 // The prefix. 237 let Inst{6-7} = 2; 238 let Inst{8-10} = 0; 239 let Inst{11} = 0; 240 let Inst{12-13} = 0; 241 let Inst{14-31} = SI{33-16}; 242 243 // The instruction. 244 let Inst{38-42} = RT; 245 let Inst{43-47} = 0; 246 let Inst{48-63} = SI{15-0}; 247} 248 249multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 250 dag PCRel_IOL, string asmstr, 251 InstrItinClass itin> { 252 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 253 !strconcat(asmstr, ", 0"), itin, []>; 254 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 255 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 256} 257 258class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 259 InstrItinClass itin, list<dag> pattern> 260 : PI<1, opcode, OOL, IOL, asmstr, itin> { 261 bits<5> RST; 262 bits<5> RA; 263 bits<34> D; 264 265 let Pattern = pattern; 266 267 // The prefix. 268 let Inst{6-10} = 0; 269 let Inst{11} = PCRel; 270 let Inst{12-13} = 0; 271 let Inst{14-31} = D{33-16}; // d0 272 273 // The instruction. 274 let Inst{38-42} = RST{4-0}; 275 let Inst{43-47} = RA; 276 let Inst{48-63} = D{15-0}; // d1 277} 278 279// 8LS:D-Form: [ 1 0 0 // R // d0 280// PO TX T RA d1 ] 281class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL, 282 string asmstr, InstrItinClass itin, 283 list<dag> pattern> 284 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { 285 bits<6> XST; 286 bits<5> RA; 287 bits<34> D; 288 289 let Pattern = pattern; 290 291 // The prefix. 292 let Inst{6-7} = 0; 293 let Inst{8} = 0; 294 let Inst{9-10} = 0; // reserved 295 let Inst{11} = PCRel; 296 let Inst{12-13} = 0; // reserved 297 let Inst{14-31} = D{33-16}; // d0 298 299 // The instruction. 300 let Inst{37} = XST{5}; 301 let Inst{38-42} = XST{4-0}; 302 let Inst{43-47} = RA; 303 let Inst{48-63} = D{15-0}; // d1 304} 305 306// X-Form: [PO T IMM VRB XO TX] 307class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 308 string asmstr, InstrItinClass itin, list<dag> pattern> 309 : I<opcode, OOL, IOL, asmstr, itin> { 310 bits<6> XT; 311 bits<5> VRB; 312 bits<5> IMM; 313 314 let Pattern = pattern; 315 let Inst{6-10} = XT{4-0}; 316 let Inst{11-15} = IMM; 317 let Inst{16-20} = VRB; 318 let Inst{21-30} = xo; 319 let Inst{31} = XT{5}; 320} 321 322class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo, 323 dag OOL, dag IOL, string asmstr, 324 InstrItinClass itin, list<dag> pattern> 325 : PI<1, opcode, OOL, IOL, asmstr, itin> { 326 bits<6> XT; 327 bits<6> XA; 328 bits<6> XB; 329 bits<6> XC; 330 bits<8> IMM; 331 332 let Pattern = pattern; 333 334 // The prefix. 335 let Inst{6-7} = 1; 336 let Inst{8} = 0; 337 let Inst{9-11} = 0; 338 let Inst{12-13} = 0; 339 let Inst{14-23} = 0; 340 let Inst{24-31} = IMM; 341 342 // The instruction. 343 let Inst{38-42} = XT{4-0}; 344 let Inst{43-47} = XA{4-0}; 345 let Inst{48-52} = XB{4-0}; 346 let Inst{53-57} = XC{4-0}; 347 let Inst{58-59} = xo; 348 let Inst{60} = XC{5}; 349 let Inst{61} = XA{5}; 350 let Inst{62} = XB{5}; 351 let Inst{63} = XT{5}; 352} 353 354class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 355 InstrItinClass itin, list<dag> pattern> 356 : I<4, OOL, IOL, asmstr, itin> { 357 bits<5> RD; 358 bits<5> VB; 359 bits<3> N; 360 361 let Pattern = pattern; 362 363 let Inst{6-10} = RD; 364 let Inst{11-12} = 0; 365 let Inst{13-15} = N; 366 let Inst{16-20} = VB; 367 let Inst{21-31} = xo; 368} 369 370 371// VX-Form: [PO VRT RA VRB XO]. 372// Destructive (insert) forms are suffixed with _ins. 373class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> 374 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB), 375 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>, 376 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 377 378// VX-Form: [PO VRT RA RB XO]. 379// Destructive (insert) forms are suffixed with _ins. 380class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> 381 : VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB), 382 !strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>, 383 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 384 385// VX-Form: [ PO BF // VRA VRB XO ] 386class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 387 InstrItinClass itin, list<dag> pattern> 388 : I<4, OOL, IOL, asmstr, itin> { 389 bits<3> BF; 390 bits<5> VA; 391 bits<5> VB; 392 393 let Pattern = pattern; 394 395 let Inst{6-8} = BF; 396 let Inst{9-10} = 0; 397 let Inst{11-15} = VA; 398 let Inst{16-20} = VB; 399 let Inst{21-31} = xo; 400} 401 402// VN-Form: [PO VRT VRA VRB PS SD XO] 403// SD is "Shift Direction" 404class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, 405 InstrItinClass itin, list<dag> pattern> 406 : I<4, OOL, IOL, asmstr, itin> { 407 bits<5> VRT; 408 bits<5> VRA; 409 bits<5> VRB; 410 bits<3> SD; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = VRT; 415 let Inst{11-15} = VRA; 416 let Inst{16-20} = VRB; 417 let Inst{21-22} = ps; 418 let Inst{23-25} = SD; 419 let Inst{26-31} = xo; 420} 421 422class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 423 string asmstr, InstrItinClass itin, list<dag> pattern> 424 : I<4, OOL, IOL, asmstr, itin> { 425 bits<5> RD; 426 bits<5> VB; 427 bit MP; 428 429 let Pattern = pattern; 430 431 let Inst{6-10} = RD; 432 let Inst{11-14} = eo; 433 let Inst{15} = MP; 434 let Inst{16-20} = VB; 435 let Inst{21-31} = xo; 436} 437 438// 8RR:D-Form: [ 1 1 0 // // imm0 439// PO T XO TX imm1 ]. 440class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 441 string asmstr, InstrItinClass itin, 442 list<dag> pattern> 443 : PI<1, opcode, OOL, IOL, asmstr, itin> { 444 bits<6> XT; 445 bits<32> IMM32; 446 447 let Pattern = pattern; 448 449 // The prefix. 450 let Inst{6-7} = 1; 451 let Inst{8-11} = 0; 452 let Inst{12-13} = 0; // reserved 453 let Inst{14-15} = 0; // reserved 454 let Inst{16-31} = IMM32{31-16}; 455 456 // The instruction. 457 let Inst{38-42} = XT{4-0}; 458 let Inst{43-46} = xo; 459 let Inst{47} = XT{5}; 460 let Inst{48-63} = IMM32{15-0}; 461} 462 463// 8RR:D-Form: [ 1 1 0 // // imm0 464// PO T XO IX TX imm1 ]. 465class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 466 string asmstr, InstrItinClass itin, 467 list<dag> pattern> 468 : PI<1, opcode, OOL, IOL, asmstr, itin> { 469 bits<6> XT; 470 bit IX; 471 bits<32> IMM32; 472 473 let Pattern = pattern; 474 475 // The prefix. 476 let Inst{6-7} = 1; 477 let Inst{8-11} = 0; 478 let Inst{12-13} = 0; // reserved 479 let Inst{14-15} = 0; // reserved 480 let Inst{16-31} = IMM32{31-16}; 481 482 // The instruction. 483 let Inst{38-42} = XT{4-0}; 484 let Inst{43-45} = xo; 485 let Inst{46} = IX; 486 let Inst{47} = XT{5}; 487 let Inst{48-63} = IMM32{15-0}; 488} 489 490class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 491 string asmstr, InstrItinClass itin, list<dag> pattern> 492 : PI<1, opcode, OOL, IOL, asmstr, itin> { 493 bits<6> XT; 494 bits<6> XA; 495 bits<6> XB; 496 bits<6> XC; 497 498 let Pattern = pattern; 499 500 // The prefix. 501 let Inst{6-7} = 1; 502 let Inst{8-11} = 0; 503 let Inst{12-13} = 0; 504 let Inst{14-31} = 0; 505 506 // The instruction. 507 let Inst{38-42} = XT{4-0}; 508 let Inst{43-47} = XA{4-0}; 509 let Inst{48-52} = XB{4-0}; 510 let Inst{53-57} = XC{4-0}; 511 let Inst{58-59} = xo; 512 let Inst{60} = XC{5}; 513 let Inst{61} = XA{5}; 514 let Inst{62} = XB{5}; 515 let Inst{63} = XT{5}; 516} 517 518class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 519 string asmstr, InstrItinClass itin, 520 list<dag> pattern> 521 : PI<1, opcode, OOL, IOL, asmstr, itin> { 522 bits<6> XT; 523 bits<6> XA; 524 bits<6> XB; 525 bits<6> XC; 526 bits<3> IMM; 527 528 let Pattern = pattern; 529 530 // The prefix. 531 let Inst{6-7} = 1; 532 let Inst{8-11} = 0; 533 let Inst{12-13} = 0; 534 let Inst{14-28} = 0; 535 let Inst{29-31} = IMM; 536 537 // The instruction. 538 let Inst{38-42} = XT{4-0}; 539 let Inst{43-47} = XA{4-0}; 540 let Inst{48-52} = XB{4-0}; 541 let Inst{53-57} = XC{4-0}; 542 let Inst{58-59} = xo; 543 let Inst{60} = XC{5}; 544 let Inst{61} = XA{5}; 545 let Inst{62} = XB{5}; 546 let Inst{63} = XT{5}; 547} 548 549// [PO BF / XO2 B XO BX /] 550class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, 551 dag IOL, string asmstr, InstrItinClass itin, 552 list<dag> pattern> 553 : I<opcode, OOL, IOL, asmstr, itin> { 554 bits<3> BF; 555 bits<6> XB; 556 557 let Pattern = pattern; 558 559 let Inst{6-8} = BF; 560 let Inst{9-10} = 0; 561 let Inst{11-15} = xo2; 562 let Inst{16-20} = XB{4-0}; 563 let Inst{21-29} = xo; 564 let Inst{30} = XB{5}; 565 let Inst{31} = 0; 566} 567 568// X-Form: [ PO RT BI /// XO / ] 569class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 570 string asmstr, InstrItinClass itin, list<dag> pattern> 571 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 572 bits<5> BI; 573 let RA = BI; 574 let RB = 0; 575} 576 577multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 578 dag PCRel_IOL, dag PCRelOnly_IOL, 579 string asmstr, string asmstr_pcext, 580 InstrItinClass itin> { 581 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 582 !strconcat(asmstr, ", 0"), itin, []>; 583 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 584 !strconcat(asmstr, ", 1"), itin, []>, 585 isPCRel; 586 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 587 def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 588 let RA = 0 in 589 def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL, 590 asmstr_pcext, itin, []>, isPCRel; 591 } 592} 593 594multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 595 dag PCRel_IOL, dag PCRelOnly_IOL, 596 string asmstr, string asmstr_pcext, 597 InstrItinClass itin> { 598 def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 599 !strconcat(asmstr, ", 0"), itin, []>; 600 def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 601 !strconcat(asmstr, ", 1"), itin, []>, 602 isPCRel; 603 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 604 def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 605 let RA = 0 in 606 def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL, 607 asmstr_pcext, itin, []>, isPCRel; 608 } 609} 610 611multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL, 612 dag PCRel_IOL, dag PCRelOnly_IOL, 613 string asmstr, string asmstr_pcext, 614 InstrItinClass itin> { 615 def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, 616 !strconcat(asmstr, ", 0"), itin, []>; 617 def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL, 618 !strconcat(asmstr, ", 1"), itin, []>, 619 isPCRel; 620 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 621 def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>; 622 let RA = 0 in 623 def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL, 624 asmstr_pcext, itin, []>, isPCRel; 625 } 626} 627 628def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; 629def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; 630def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; 631def RCCp { 632 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); 633 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); 634} 635 636let Predicates = [PrefixInstrs] in { 637 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 638 defm PADDI8 : 639 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI), 640 (ins immZero:$RA, s34imm_pcrel:$SI), 641 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 642 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 643 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 644 (ins s34imm:$SI), 645 "pli $RT, $SI", IIC_IntSimple, []>; 646 } 647 } 648 defm PADDI : 649 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI), 650 (ins immZero:$RA, s34imm_pcrel:$SI), 651 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 652 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 653 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 654 (ins s34imm:$SI), 655 "pli $RT, $SI", IIC_IntSimple, []>; 656 } 657 658 let mayLoad = 1, mayStore = 0 in { 659 defm PLXV : 660 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr), 661 (ins (memri34_pcrel $D, $RA):$addr), 662 (ins s34imm_pcrel:$D), 663 "plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>; 664 defm PLFS : 665 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr), 666 (ins (memri34_pcrel $D, $RA):$addr), 667 (ins s34imm_pcrel:$D), "plfs $RST, $addr", 668 "plfs $RST, $D", IIC_LdStLFD>; 669 defm PLFD : 670 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr), 671 (ins (memri34_pcrel $D, $RA):$addr), 672 (ins s34imm_pcrel:$D), "plfd $RST, $addr", 673 "plfd $RST, $D", IIC_LdStLFD>; 674 defm PLXSSP : 675 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr), 676 (ins (memri34_pcrel $D, $RA):$addr), 677 (ins s34imm_pcrel:$D), 678 "plxssp $RST, $addr", "plxssp $RST, $D", 679 IIC_LdStLFD>; 680 defm PLXSD : 681 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr), 682 (ins (memri34_pcrel $D, $RA):$addr), 683 (ins s34imm_pcrel:$D), 684 "plxsd $RST, $addr", "plxsd $RST, $D", 685 IIC_LdStLFD>; 686 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 687 defm PLBZ8 : 688 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 689 (ins (memri34_pcrel $D, $RA):$addr), 690 (ins s34imm_pcrel:$D), "plbz $RST, $addr", 691 "plbz $RST, $D", IIC_LdStLFD>; 692 defm PLHZ8 : 693 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 694 (ins (memri34_pcrel $D, $RA):$addr), 695 (ins s34imm_pcrel:$D), "plhz $RST, $addr", 696 "plhz $RST, $D", IIC_LdStLFD>; 697 defm PLHA8 : 698 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 699 (ins (memri34_pcrel $D, $RA):$addr), 700 (ins s34imm_pcrel:$D), "plha $RST, $addr", 701 "plha $RST, $D", IIC_LdStLFD>; 702 defm PLWA8 : 703 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 704 (ins (memri34_pcrel $D, $RA):$addr), 705 (ins s34imm_pcrel:$D), 706 "plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>; 707 defm PLWZ8 : 708 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 709 (ins (memri34_pcrel $D, $RA):$addr), 710 (ins s34imm_pcrel:$D), "plwz $RST, $addr", 711 "plwz $RST, $D", IIC_LdStLFD>; 712 } 713 defm PLBZ : 714 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 715 (ins (memri34_pcrel $D, $RA):$addr), 716 (ins s34imm_pcrel:$D), "plbz $RST, $addr", 717 "plbz $RST, $D", IIC_LdStLFD>; 718 defm PLHZ : 719 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 720 (ins (memri34_pcrel $D, $RA):$addr), 721 (ins s34imm_pcrel:$D), "plhz $RST, $addr", 722 "plhz $RST, $D", IIC_LdStLFD>; 723 defm PLHA : 724 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 725 (ins (memri34_pcrel $D, $RA):$addr), 726 (ins s34imm_pcrel:$D), "plha $RST, $addr", 727 "plha $RST, $D", IIC_LdStLFD>; 728 defm PLWZ : 729 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 730 (ins (memri34_pcrel $D, $RA):$addr), 731 (ins s34imm_pcrel:$D), "plwz $RST, $addr", 732 "plwz $RST, $D", IIC_LdStLFD>; 733 defm PLWA : 734 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr), 735 (ins (memri34_pcrel $D, $RA):$addr), 736 (ins s34imm_pcrel:$D), 737 "plwa $RST, $addr", "plwa $RST, $D", 738 IIC_LdStLFD>; 739 defm PLD : 740 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr), 741 (ins (memri34_pcrel $D, $RA):$addr), 742 (ins s34imm_pcrel:$D), 743 "pld $RST, $addr", "pld $RST, $D", 744 IIC_LdStLFD>; 745 } 746 747 let mayStore = 1, mayLoad = 0 in { 748 defm PSTXV : 749 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr), 750 (ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr), 751 (ins vsrc:$XST, s34imm_pcrel:$D), 752 "pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>; 753 defm PSTFS : 754 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr), 755 (ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr), 756 (ins f4rc:$RST, s34imm_pcrel:$D), 757 "pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>; 758 defm PSTFD : 759 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr), 760 (ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr), 761 (ins f8rc:$RST, s34imm_pcrel:$D), 762 "pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>; 763 defm PSTXSSP : 764 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr), 765 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr), 766 (ins vfrc:$RST, s34imm_pcrel:$D), 767 "pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>; 768 defm PSTXSD : 769 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr), 770 (ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr), 771 (ins vfrc:$RST, s34imm_pcrel:$D), 772 "pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>; 773 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 774 defm PSTB8 : 775 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 776 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 777 (ins g8rc:$RST, s34imm_pcrel:$D), 778 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>; 779 defm PSTH8 : 780 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 781 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 782 (ins g8rc:$RST, s34imm_pcrel:$D), 783 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>; 784 defm PSTW8 : 785 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 786 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 787 (ins g8rc:$RST, s34imm_pcrel:$D), 788 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>; 789 } 790 defm PSTB : 791 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 792 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 793 (ins gprc:$RST, s34imm_pcrel:$D), 794 "pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>; 795 defm PSTH : 796 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 797 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 798 (ins gprc:$RST, s34imm_pcrel:$D), 799 "psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>; 800 defm PSTW : 801 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr), 802 (ins gprc:$RST, (memri34_pcrel $D, $RA):$addr), 803 (ins gprc:$RST, s34imm_pcrel:$D), 804 "pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>; 805 defm PSTD : 806 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr), 807 (ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr), 808 (ins g8rc:$RST, s34imm_pcrel:$D), 809 "pstd $RST, $addr", "pstd $RST, $D", IIC_LdStLFD>; 810 } 811} 812 813class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 814 string asmstr, InstrItinClass itin, list<dag> pattern> 815 : I<opcode, OOL, IOL, asmstr, itin> { 816 bits<5> XTp; 817 bits<5> RA; 818 bits<12> DQ; 819 820 let Pattern = pattern; 821 822 let Inst{6-9} = XTp{3-0}; 823 let Inst{10} = XTp{4}; 824 let Inst{11-15} = RA; 825 let Inst{16-27} = DQ; 826 let Inst{28-31} = xo; 827} 828 829class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 830 string asmstr, InstrItinClass itin, list<dag> pattern> 831 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { 832 bits<5> XTp; 833 bits<5> RA; 834 bits<5> RB; 835 836 let Pattern = pattern; 837 let Inst{6-9} = XTp{3-0}; 838 let Inst{10} = XTp{4}; 839 let Inst{11-15} = RA; 840 let Inst{16-20} = RB; 841 let Inst{21-30} = xo; 842 let Inst{31} = 0; 843} 844 845class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 846 InstrItinClass itin, list<dag> pattern> 847 : PI<1, opcode, OOL, IOL, asmstr, itin> { 848 bits<5> XTp; 849 bits<5> RA; 850 bits<34> D; 851 852 let Pattern = pattern; 853 854 // The prefix. 855 let Inst{6-10} = 0; 856 let Inst{11} = PCRel; 857 let Inst{12-13} = 0; 858 let Inst{14-31} = D{33-16}; // Imm18 859 860 // The instruction. 861 let Inst{38-41} = XTp{3-0}; 862 let Inst{42} = XTp{4}; 863 let Inst{43-47} = RA; 864 let Inst{48-63} = D{15-0}; 865} 866 867multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL, 868 dag IOL, dag PCRel_IOL, dag PCRelOnly_IOL, 869 string asmstr, string asmstr_pcext, 870 InstrItinClass itin> { 871 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, 872 !strconcat(asmstr, ", 0"), itin, []>; 873 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL, 874 !strconcat(asmstr, ", 1"), itin, []>, 875 isPCRel; 876 let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 877 def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>; 878 let RA = 0 in 879 def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL, 880 asmstr_pcext, itin, []>, isPCRel; 881 } 882} 883 884 885 886// [PO AS XO2 XO] 887class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 888 string asmstr, InstrItinClass itin, list<dag> pattern> 889 : I<opcode, OOL, IOL, asmstr, itin> { 890 bits<3> AT; 891 892 let Pattern = pattern; 893 894 let Inst{6-8} = AT; 895 let Inst{9-10} = 0; 896 let Inst{11-15} = xo2; 897 let Inst{16-20} = 0; 898 let Inst{21-30} = xo; 899 let Inst{31} = 0; 900} 901 902// X-Form: [ PO T EO UIM XO TX ] 903class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL, 904 string asmstr, InstrItinClass itin, list<dag> pattern> 905 : I<opcode, OOL, IOL, asmstr, itin> { 906 bits<6> XT; 907 bits<5> UIM; 908 909 let Pattern = pattern; 910 911 let Inst{6-10} = XT{4-0}; 912 let Inst{11-15} = eo; 913 let Inst{16-20} = UIM; 914 let Inst{21-30} = xo; 915 let Inst{31} = XT{5}; 916} 917 918class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 919 string asmstr, InstrItinClass itin, 920 list<dag> pattern> 921 : I<opcode, OOL, IOL, asmstr, itin> { 922 bits<3> AT; 923 bits<6> XA; 924 bits<6> XB; 925 926 let Pattern = pattern; 927 928 let Inst{6-8} = AT; 929 let Inst{9-10} = 0; 930 let Inst{11-15} = XA{4-0}; 931 let Inst{16-20} = XB{4-0}; 932 let Inst{21-28} = xo; 933 let Inst{29} = XA{5}; 934 let Inst{30} = XB{5}; 935 let Inst{31} = 0; 936} 937 938class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 939 string asmstr, InstrItinClass itin, 940 list<dag> pattern> 941 : PI<1, opcode, OOL, IOL, asmstr, itin> { 942 bits<3> AT; 943 bits<6> XA; 944 bits<6> XB; 945 bits<4> XMSK; 946 bits<4> YMSK; 947 bits<2> PMSK; 948 949 let Pattern = pattern; 950 951 // The prefix. 952 let Inst{6-7} = 3; 953 let Inst{8-11} = 9; 954 let Inst{12-15} = 0; 955 let Inst{16-17} = PMSK; 956 let Inst{18-23} = 0; 957 let Inst{24-27} = XMSK; 958 let Inst{28-31} = YMSK; 959 960 // The instruction. 961 let Inst{38-40} = AT; 962 let Inst{41-42} = 0; 963 let Inst{43-47} = XA{4-0}; 964 let Inst{48-52} = XB{4-0}; 965 let Inst{53-60} = xo; 966 let Inst{61} = XA{5}; 967 let Inst{62} = XB{5}; 968 let Inst{63} = 0; 969} 970 971class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 972 string asmstr, InstrItinClass itin, 973 list<dag> pattern> 974 : PI<1, opcode, OOL, IOL, asmstr, itin> { 975 bits<3> AT; 976 bits<6> XA; 977 bits<6> XB; 978 bits<4> XMSK; 979 bits<4> YMSK; 980 981 let Pattern = pattern; 982 983 // The prefix. 984 let Inst{6-7} = 3; 985 let Inst{8-11} = 9; 986 let Inst{12-23} = 0; 987 let Inst{24-27} = XMSK; 988 let Inst{28-31} = YMSK; 989 990 // The instruction. 991 let Inst{38-40} = AT; 992 let Inst{41-42} = 0; 993 let Inst{43-47} = XA{4-0}; 994 let Inst{48-52} = XB{4-0}; 995 let Inst{53-60} = xo; 996 let Inst{61} = XA{5}; 997 let Inst{62} = XB{5}; 998 let Inst{63} = 0; 999} 1000 1001class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1002 string asmstr, InstrItinClass itin, 1003 list<dag> pattern> 1004 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1005 bits<3> AT; 1006 bits<6> XA; 1007 bits<6> XB; 1008 bits<4> XMSK; 1009 bits<2> YMSK; 1010 1011 let Pattern = pattern; 1012 1013 // The prefix. 1014 let Inst{6-7} = 3; 1015 let Inst{8-11} = 9; 1016 let Inst{12-23} = 0; 1017 let Inst{24-27} = XMSK; 1018 let Inst{28-29} = YMSK; 1019 let Inst{30-31} = 0; 1020 1021 // The instruction. 1022 let Inst{38-40} = AT; 1023 let Inst{41-42} = 0; 1024 let Inst{43-47} = XA{4-0}; 1025 let Inst{48-52} = XB{4-0}; 1026 let Inst{53-60} = xo; 1027 let Inst{61} = XA{5}; 1028 let Inst{62} = XB{5}; 1029 let Inst{63} = 0; 1030} 1031 1032class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1033 string asmstr, InstrItinClass itin, 1034 list<dag> pattern> 1035 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1036 bits<3> AT; 1037 bits<6> XA; 1038 bits<6> XB; 1039 bits<4> XMSK; 1040 bits<4> YMSK; 1041 bits<8> PMSK; 1042 1043 let Pattern = pattern; 1044 1045 // The prefix. 1046 let Inst{6-7} = 3; 1047 let Inst{8-11} = 9; 1048 let Inst{12-15} = 0; 1049 let Inst{16-23} = PMSK; 1050 let Inst{24-27} = XMSK; 1051 let Inst{28-31} = YMSK; 1052 1053 // The instruction. 1054 let Inst{38-40} = AT; 1055 let Inst{41-42} = 0; 1056 let Inst{43-47} = XA{4-0}; 1057 let Inst{48-52} = XB{4-0}; 1058 let Inst{53-60} = xo; 1059 let Inst{61} = XA{5}; 1060 let Inst{62} = XB{5}; 1061 let Inst{63} = 0; 1062} 1063 1064class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1065 string asmstr, InstrItinClass itin, 1066 list<dag> pattern> 1067 : PI<1, opcode, OOL, IOL, asmstr, itin> { 1068 bits<3> AT; 1069 bits<6> XA; 1070 bits<6> XB; 1071 bits<4> XMSK; 1072 bits<4> YMSK; 1073 bits<4> PMSK; 1074 1075 let Pattern = pattern; 1076 1077 // The prefix. 1078 let Inst{6-7} = 3; 1079 let Inst{8-11} = 9; 1080 let Inst{12-15} = 0; 1081 let Inst{16-19} = PMSK; 1082 let Inst{20-23} = 0; 1083 let Inst{24-27} = XMSK; 1084 let Inst{28-31} = YMSK; 1085 1086 // The instruction. 1087 let Inst{38-40} = AT; 1088 let Inst{41-42} = 0; 1089 let Inst{43-47} = XA{4-0}; 1090 let Inst{48-52} = XB{4-0}; 1091 let Inst{53-60} = xo; 1092 let Inst{61} = XA{5}; 1093 let Inst{62} = XB{5}; 1094 let Inst{63} = 0; 1095} 1096 1097 1098 1099def Concats { 1100 dag VecsToVecPair0 = 1101 (v256i1 (INSERT_SUBREG 1102 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1103 $vs1, sub_vsx0)); 1104 dag VecsToVecPair1 = 1105 (v256i1 (INSERT_SUBREG 1106 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1107 $vs3, sub_vsx0)); 1108} 1109 1110let Predicates = [PairedVectorMemops] in { 1111 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)), 1112 Concats.VecsToVecPair0>; 1113 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), 1114 Concats.VecsToVecPair0>; 1115 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)), 1116 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; 1117 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), 1118 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; 1119} 1120 1121let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in { 1122 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), 1123 (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr", 1124 IIC_LdStLFD, []>; 1125 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr), 1126 "lxvpx $XTp, $addr", IIC_LdStLFD, 1127 []>; 1128} 1129 1130let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in { 1131 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, 1132 (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr", 1133 IIC_LdStLFD, []>; 1134 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr), 1135 "stxvpx $XTp, $addr", IIC_LdStLFD, 1136 []>; 1137} 1138 1139let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1140 defm PLXVP : 1141 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr), 1142 (ins (memri34_pcrel $D, $RA):$addr), 1143 (ins s34imm_pcrel:$D), 1144 "plxvp $XTp, $addr", "plxvp $XTp, $D", 1145 IIC_LdStLFD>; 1146} 1147 1148let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1149 defm PSTXVP : 1150 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr), 1151 (ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr), 1152 (ins vsrprc:$XTp, s34imm_pcrel:$D), 1153 "pstxvp $XTp, $addr", "pstxvp $XTp, $D", IIC_LdStLFD>; 1154} 1155 1156let Predicates = [PairedVectorMemops] in { 1157 // Intrinsics for Paired Vector Loads. 1158 def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>; 1159 def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>; 1160 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1161 def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>; 1162 } 1163 // Intrinsics for Paired Vector Stores. 1164 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst), 1165 (STXVP $XSp, memrix16:$dst)>; 1166 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst), 1167 (STXVPX $XSp, XForm:$dst)>; 1168 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1169 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst), 1170 (PSTXVP $XSp, memri34:$dst)>; 1171 } 1172} 1173 1174let Predicates = [IsISA3_1] in { 1175 def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>; 1176 def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>; 1177 def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>; 1178} 1179 1180let Predicates = [PCRelativeMemops] in { 1181 // Load i32 1182 def : Pat<(i32 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1183 (PLBZpc $ga, 0)>; 1184 def : Pat<(i32 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1185 (PLBZpc $ga, 0)>; 1186 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1187 (PLBZpc $ga, 0)>; 1188 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1189 (PLBZpc $ga, 0)>; 1190 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1191 (PLHApc $ga, 0)>; 1192 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1193 (PLHZpc $ga, 0)>; 1194 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1195 (PLHZpc $ga, 0)>; 1196 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>; 1197 1198 // Store i32 1199 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1200 (PSTBpc $RS, $ga, 0)>; 1201 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1202 (PSTHpc $RS, $ga, 0)>; 1203 def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1204 (PSTWpc $RS, $ga, 0)>; 1205 1206 // Load i64 1207 def : Pat<(i64 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1208 (PLBZ8pc $ga, 0)>; 1209 def : Pat<(i64 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1210 (PLBZ8pc $ga, 0)>; 1211 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1212 (PLBZ8pc $ga, 0)>; 1213 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1214 (PLBZ8pc $ga, 0)>; 1215 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1216 (PLHA8pc $ga, 0)>; 1217 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1218 (PLHZ8pc $ga, 0)>; 1219 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1220 (PLHZ8pc $ga, 0)>; 1221 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1222 (PLWZ8pc $ga, 0)>; 1223 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1224 (PLWA8pc $ga, 0)>; 1225 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1226 (PLWZ8pc $ga, 0)>; 1227 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>; 1228 1229 // Store i64 1230 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1231 (PSTB8pc $RS, $ga, 0)>; 1232 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1233 (PSTH8pc $RS, $ga, 0)>; 1234 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1235 (PSTW8pc $RS, $ga, 0)>; 1236 def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1237 (PSTDpc $RS, $ga, 0)>; 1238 1239 // Load f32 1240 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>; 1241 1242 // Store f32 1243 def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1244 (PSTFSpc $FRS, $ga, 0)>; 1245 1246 // Load f64 1247 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))), 1248 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>; 1249 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>; 1250 1251 // Store f64 1252 def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1253 (PSTFDpc $FRS, $ga, 0)>; 1254 1255 // Load f128 1256 def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))), 1257 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>; 1258 1259 // Store f128 1260 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1261 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>; 1262 1263 // Load v4i32 1264 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1265 1266 // Store v4i32 1267 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1268 (PSTXVpc $XS, $ga, 0)>; 1269 1270 // Load v2i64 1271 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1272 1273 // Store v2i64 1274 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1275 (PSTXVpc $XS, $ga, 0)>; 1276 1277 // Load v4f32 1278 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1279 1280 // Store v4f32 1281 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1282 (PSTXVpc $XS, $ga, 0)>; 1283 1284 // Load v2f64 1285 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1286 1287 // Store v2f64 1288 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1289 (PSTXVpc $XS, $ga, 0)>; 1290 1291 // Atomic Load 1292 def : Pat<(atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga)), 1293 (PLBZpc $ga, 0)>; 1294 def : Pat<(atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga)), 1295 (PLHZpc $ga, 0)>; 1296 def : Pat<(atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga)), 1297 (PLWZpc $ga, 0)>; 1298 def : Pat<(atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga)), 1299 (PLDpc $ga, 0)>; 1300 1301 // Atomic Store 1302 def : Pat<(atomic_store_8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1303 (PSTBpc $RS, $ga, 0)>; 1304 def : Pat<(atomic_store_16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1305 (PSTHpc $RS, $ga, 0)>; 1306 def : Pat<(atomic_store_32 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1307 (PSTWpc $RS, $ga, 0)>; 1308 def : Pat<(atomic_store_8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1309 (PSTB8pc $RS, $ga, 0)>; 1310 def : Pat<(atomic_store_16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1311 (PSTH8pc $RS, $ga, 0)>; 1312 def : Pat<(atomic_store_32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1313 (PSTW8pc $RS, $ga, 0)>; 1314 def : Pat<(atomic_store_64 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1315 (PSTDpc $RS, $ga, 0)>; 1316 1317 // Special Cases For PPCstore_scal_int_from_vsr 1318 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8), 1319 (PSTXSDpc $src, $dst, 0)>; 1320 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8), 1321 (PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>; 1322 1323 def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), 1324 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; 1325 1326 // If the PPCmatpcreladdr node is not caught by any other pattern it should be 1327 // caught here and turned into a paddi instruction to materialize the address. 1328 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1329 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize 1330 // tls global address with paddi instruction. 1331 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1332 // PPCtlslocalexecmataddr node is used for TLS local exec models to 1333 // materialize tls global address with paddi instruction. 1334 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), 1335 (PADDI8 $in, $addr)>; 1336} 1337 1338let Predicates = [PrefixInstrs] in { 1339 def XXPERMX : 1340 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1341 vsrc:$XC, u3imm:$IMM), 1342 "xxpermx $XT, $XA, $XB, $XC, $IMM", 1343 IIC_VecPerm, []>; 1344 def XXBLENDVB : 1345 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1346 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", 1347 IIC_VecGeneral, []>; 1348 def XXBLENDVH : 1349 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1350 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", 1351 IIC_VecGeneral, []>; 1352 def XXBLENDVW : 1353 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1354 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC", 1355 IIC_VecGeneral, []>; 1356 def XXBLENDVD : 1357 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1358 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC", 1359 IIC_VecGeneral, []>; 1360} 1361 1362// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt 1363// to spill part of the instruction when the values are similar. 1364let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in { 1365 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT), 1366 (ins i32imm:$IMM32), 1367 "xxspltiw $XT, $IMM32", IIC_VecGeneral, 1368 []>; 1369 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT), 1370 (ins i32imm:$IMM32), 1371 "xxspltidp $XT, $IMM32", IIC_VecGeneral, 1372 [(set v2f64:$XT, 1373 (PPCxxspltidp i32:$IMM32))]>; 1374 def XXSPLTI32DX : 1375 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT), 1376 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32), 1377 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, 1378 [(set v2i64:$XT, 1379 (PPCxxsplti32dx v2i64:$XTi, i32:$IX, 1380 i32:$IMM32))]>, 1381 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1382} 1383 1384let Predicates = [IsISA3_1] in { 1385 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI), 1386 "setbc $RST, $BI", IIC_IntCompare, []>, 1387 SExt32To64, ZExt32To64; 1388 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI), 1389 "setbcr $RST, $BI", IIC_IntCompare, []>, 1390 SExt32To64, ZExt32To64; 1391 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI), 1392 "setnbc $RST, $BI", IIC_IntCompare, []>, 1393 SExt32To64; 1394 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI), 1395 "setnbcr $RST, $BI", IIC_IntCompare, []>, 1396 SExt32To64; 1397 1398 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1399 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI), 1400 "setbc $RST, $BI", IIC_IntCompare, []>, 1401 SExt32To64, ZExt32To64; 1402 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI), 1403 "setbcr $RST, $BI", IIC_IntCompare, []>, 1404 SExt32To64, ZExt32To64; 1405 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI), 1406 "setnbc $RST, $BI", IIC_IntCompare, []>, 1407 SExt32To64; 1408 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI), 1409 "setnbcr $RST, $BI", IIC_IntCompare, []>, 1410 SExt32To64; 1411 } 1412 1413 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), 1414 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), 1415 "vsldbi $VRT, $VRA, $VRB, $SD", 1416 IIC_VecGeneral, 1417 [(set v16i8:$VRT, 1418 (int_ppc_altivec_vsldbi v16i8:$VRA, 1419 v16i8:$VRB, 1420 timm:$SD))]>; 1421 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), 1422 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), 1423 "vsrdbi $VRT, $VRA, $VRB, $SD", 1424 IIC_VecGeneral, 1425 [(set v16i8:$VRT, 1426 (int_ppc_altivec_vsrdbi v16i8:$VRA, 1427 v16i8:$VRB, 1428 timm:$SD))]>; 1429 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB), 1430 "vstribr", "$VT, $VB", IIC_VecGeneral, 1431 [(set v16i8:$VT, 1432 (int_ppc_altivec_vstribr v16i8:$VB))]>; 1433 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB), 1434 "vstribl", "$VT, $VB", IIC_VecGeneral, 1435 [(set v16i8:$VT, 1436 (int_ppc_altivec_vstribl v16i8:$VB))]>; 1437 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB), 1438 "vstrihr", "$VT, $VB", IIC_VecGeneral, 1439 [(set v8i16:$VT, 1440 (int_ppc_altivec_vstrihr v8i16:$VB))]>; 1441 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB), 1442 "vstrihl", "$VT, $VB", IIC_VecGeneral, 1443 [(set v8i16:$VT, 1444 (int_ppc_altivec_vstrihl v8i16:$VB))]>; 1445 def VINSW : 1446 VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB), 1447 "vinsw $VD, $VB, $VA", IIC_VecGeneral, 1448 [(set v4i32:$VD, 1449 (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>, 1450 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1451 def VINSD : 1452 VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB), 1453 "vinsd $VD, $VB, $VA", IIC_VecGeneral, 1454 [(set v2i64:$VD, 1455 (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>, 1456 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1457 def VINSBVLX : 1458 VXForm_VTB5_RA5_ins<15, "vinsbvlx", 1459 [(set v16i8:$VD, 1460 (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA, 1461 v16i8:$VB))]>; 1462 def VINSBVRX : 1463 VXForm_VTB5_RA5_ins<271, "vinsbvrx", 1464 [(set v16i8:$VD, 1465 (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA, 1466 v16i8:$VB))]>; 1467 def VINSHVLX : 1468 VXForm_VTB5_RA5_ins<79, "vinshvlx", 1469 [(set v8i16:$VD, 1470 (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA, 1471 v8i16:$VB))]>; 1472 def VINSHVRX : 1473 VXForm_VTB5_RA5_ins<335, "vinshvrx", 1474 [(set v8i16:$VD, 1475 (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA, 1476 v8i16:$VB))]>; 1477 def VINSWVLX : 1478 VXForm_VTB5_RA5_ins<143, "vinswvlx", 1479 [(set v4i32:$VD, 1480 (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA, 1481 v4i32:$VB))]>; 1482 def VINSWVRX : 1483 VXForm_VTB5_RA5_ins<399, "vinswvrx", 1484 [(set v4i32:$VD, 1485 (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA, 1486 v4i32:$VB))]>; 1487 def VINSBLX : 1488 VXForm_VRT5_RAB5_ins<527, "vinsblx", 1489 [(set v16i8:$VD, 1490 (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA, 1491 i32:$VB))]>; 1492 def VINSBRX : 1493 VXForm_VRT5_RAB5_ins<783, "vinsbrx", 1494 [(set v16i8:$VD, 1495 (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA, 1496 i32:$VB))]>; 1497 def VINSHLX : 1498 VXForm_VRT5_RAB5_ins<591, "vinshlx", 1499 [(set v8i16:$VD, 1500 (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA, 1501 i32:$VB))]>; 1502 def VINSHRX : 1503 VXForm_VRT5_RAB5_ins<847, "vinshrx", 1504 [(set v8i16:$VD, 1505 (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA, 1506 i32:$VB))]>; 1507 def VINSWLX : 1508 VXForm_VRT5_RAB5_ins<655, "vinswlx", 1509 [(set v4i32:$VD, 1510 (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA, 1511 i32:$VB))]>; 1512 def VINSWRX : 1513 VXForm_VRT5_RAB5_ins<911, "vinswrx", 1514 [(set v4i32:$VD, 1515 (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA, 1516 i32:$VB))]>; 1517 def VINSDLX : 1518 VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), 1519 "vinsdlx $VD, $VA, $VB", IIC_VecGeneral, 1520 [(set v2i64:$VD, 1521 (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>, 1522 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1523 def VINSDRX : 1524 VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), 1525 "vinsdrx $VD, $VA, $VB", IIC_VecGeneral, 1526 [(set v2i64:$VD, 1527 (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>, 1528 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1529 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB), 1530 "vextractbm $VD, $VB", IIC_VecGeneral, 1531 [(set i32:$VD, 1532 (int_ppc_altivec_vextractbm v16i8:$VB))]>, 1533 ZExt32To64; 1534 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB), 1535 "vextracthm $VD, $VB", IIC_VecGeneral, 1536 [(set i32:$VD, 1537 (int_ppc_altivec_vextracthm v8i16:$VB))]>, 1538 ZExt32To64; 1539 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB), 1540 "vextractwm $VD, $VB", IIC_VecGeneral, 1541 [(set i32:$VD, 1542 (int_ppc_altivec_vextractwm v4i32:$VB))]>, 1543 ZExt32To64; 1544 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB), 1545 "vextractdm $VD, $VB", IIC_VecGeneral, 1546 [(set i32:$VD, 1547 (int_ppc_altivec_vextractdm v2i64:$VB))]>, 1548 ZExt32To64; 1549 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB), 1550 "vextractqm $VD, $VB", IIC_VecGeneral, 1551 [(set i32:$VD, 1552 (int_ppc_altivec_vextractqm v1i128:$VB))]>; 1553 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB), 1554 "vexpandbm $VD, $VB", IIC_VecGeneral, 1555 [(set v16i8:$VD, (int_ppc_altivec_vexpandbm 1556 v16i8:$VB))]>; 1557 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB), 1558 "vexpandhm $VD, $VB", IIC_VecGeneral, 1559 [(set v8i16:$VD, (int_ppc_altivec_vexpandhm 1560 v8i16:$VB))]>; 1561 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB), 1562 "vexpandwm $VD, $VB", IIC_VecGeneral, 1563 [(set v4i32:$VD, (int_ppc_altivec_vexpandwm 1564 v4i32:$VB))]>; 1565 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB), 1566 "vexpanddm $VD, $VB", IIC_VecGeneral, 1567 [(set v2i64:$VD, (int_ppc_altivec_vexpanddm 1568 v2i64:$VB))]>; 1569 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB), 1570 "vexpandqm $VD, $VB", IIC_VecGeneral, 1571 [(set v1i128:$VD, (int_ppc_altivec_vexpandqm 1572 v1i128:$VB))]>; 1573 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB), 1574 "mtvsrbm $VD, $VB", IIC_VecGeneral, 1575 [(set v16i8:$VD, 1576 (int_ppc_altivec_mtvsrbm i64:$VB))]>; 1577 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB), 1578 "mtvsrhm $VD, $VB", IIC_VecGeneral, 1579 [(set v8i16:$VD, 1580 (int_ppc_altivec_mtvsrhm i64:$VB))]>; 1581 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB), 1582 "mtvsrwm $VD, $VB", IIC_VecGeneral, 1583 [(set v4i32:$VD, 1584 (int_ppc_altivec_mtvsrwm i64:$VB))]>; 1585 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB), 1586 "mtvsrdm $VD, $VB", IIC_VecGeneral, 1587 [(set v2i64:$VD, 1588 (int_ppc_altivec_mtvsrdm i64:$VB))]>; 1589 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB), 1590 "mtvsrqm $VD, $VB", IIC_VecGeneral, 1591 [(set v1i128:$VD, 1592 (int_ppc_altivec_mtvsrqm i64:$VB))]>; 1593 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D), 1594 "mtvsrbmi $RT, $D", IIC_VecGeneral, 1595 [(set v16i8:$RT, 1596 (int_ppc_altivec_mtvsrbm imm:$D))]>; 1597 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD), 1598 (ins vrrc:$VB, u1imm:$MP), 1599 "vcntmbb $RD, $VB, $MP", IIC_VecGeneral, 1600 [(set i64:$RD, (int_ppc_altivec_vcntmbb 1601 v16i8:$VB, timm:$MP))]>; 1602 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD), 1603 (ins vrrc:$VB, u1imm:$MP), 1604 "vcntmbh $RD, $VB, $MP", IIC_VecGeneral, 1605 [(set i64:$RD, (int_ppc_altivec_vcntmbh 1606 v8i16:$VB, timm:$MP))]>; 1607 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD), 1608 (ins vrrc:$VB, u1imm:$MP), 1609 "vcntmbw $RD, $VB, $MP", IIC_VecGeneral, 1610 [(set i64:$RD, (int_ppc_altivec_vcntmbw 1611 v4i32:$VB, timm:$MP))]>; 1612 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD), 1613 (ins vrrc:$VB, u1imm:$MP), 1614 "vcntmbd $RD, $VB, $MP", IIC_VecGeneral, 1615 [(set i64:$RD, (int_ppc_altivec_vcntmbd 1616 v2i64:$VB, timm:$MP))]>; 1617 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT), 1618 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1619 "vextdubvlx $RT, $RA, $RB, $RC", 1620 IIC_VecGeneral, 1621 [(set v2i64:$RT, 1622 (int_ppc_altivec_vextdubvlx v16i8:$RA, 1623 v16i8:$RB, 1624 i32:$RC))]>; 1625 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT), 1626 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1627 "vextdubvrx $RT, $RA, $RB, $RC", 1628 IIC_VecGeneral, 1629 [(set v2i64:$RT, 1630 (int_ppc_altivec_vextdubvrx v16i8:$RA, 1631 v16i8:$RB, 1632 i32:$RC))]>; 1633 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT), 1634 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1635 "vextduhvlx $RT, $RA, $RB, $RC", 1636 IIC_VecGeneral, 1637 [(set v2i64:$RT, 1638 (int_ppc_altivec_vextduhvlx v8i16:$RA, 1639 v8i16:$RB, 1640 i32:$RC))]>; 1641 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT), 1642 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1643 "vextduhvrx $RT, $RA, $RB, $RC", 1644 IIC_VecGeneral, 1645 [(set v2i64:$RT, 1646 (int_ppc_altivec_vextduhvrx v8i16:$RA, 1647 v8i16:$RB, 1648 i32:$RC))]>; 1649 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT), 1650 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1651 "vextduwvlx $RT, $RA, $RB, $RC", 1652 IIC_VecGeneral, 1653 [(set v2i64:$RT, 1654 (int_ppc_altivec_vextduwvlx v4i32:$RA, 1655 v4i32:$RB, 1656 i32:$RC))]>; 1657 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT), 1658 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1659 "vextduwvrx $RT, $RA, $RB, $RC", 1660 IIC_VecGeneral, 1661 [(set v2i64:$RT, 1662 (int_ppc_altivec_vextduwvrx v4i32:$RA, 1663 v4i32:$RB, 1664 i32:$RC))]>; 1665 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT), 1666 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1667 "vextddvlx $RT, $RA, $RB, $RC", 1668 IIC_VecGeneral, 1669 [(set v2i64:$RT, 1670 (int_ppc_altivec_vextddvlx v2i64:$RA, 1671 v2i64:$RB, 1672 i32:$RC))]>; 1673 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT), 1674 (ins vrrc:$RA, vrrc:$RB, gprc:$RC), 1675 "vextddvrx $RT, $RA, $RB, $RC", 1676 IIC_VecGeneral, 1677 [(set v2i64:$RT, 1678 (int_ppc_altivec_vextddvrx v2i64:$RA, 1679 v2i64:$RB, 1680 i32:$RC))]>; 1681 def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1682 "vpdepd $VD, $VA, $VB", IIC_VecGeneral, 1683 [(set v2i64:$VD, 1684 (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>; 1685 def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1686 "vpextd $VD, $VA, $VB", IIC_VecGeneral, 1687 [(set v2i64:$VD, 1688 (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>; 1689 def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1690 "pdepd $RA, $RST, $RB", IIC_IntGeneral, 1691 [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>; 1692 def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1693 "pextd $RA, $RST, $RB", IIC_IntGeneral, 1694 [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>; 1695 def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1696 "vcfuged $VD, $VA, $VB", IIC_VecGeneral, 1697 [(set v2i64:$VD, 1698 (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>; 1699 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N), 1700 "vgnb $RD, $VB, $N", IIC_VecGeneral, 1701 [(set i64:$RD, 1702 (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>; 1703 def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1704 "cfuged $RA, $RST, $RB", IIC_IntGeneral, 1705 [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>; 1706 def XXEVAL : 1707 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1708 vsrc:$XC, u8imm:$IMM), 1709 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, 1710 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, 1711 v2i64:$XB, v2i64:$XC, timm:$IMM))]>; 1712 def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1713 "vclzdm $VD, $VA, $VB", IIC_VecGeneral, 1714 [(set v2i64:$VD, 1715 (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>; 1716 def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1717 "vctzdm $VD, $VA, $VB", IIC_VecGeneral, 1718 [(set v2i64:$VD, 1719 (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>; 1720 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1721 "cntlzdm $RA, $RST, $RB", IIC_IntGeneral, 1722 [(set i64:$RA, 1723 (int_ppc_cntlzdm i64:$RST, i64:$RB))]>; 1724 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1725 "cnttzdm $RA, $RST, $RB", IIC_IntGeneral, 1726 [(set i64:$RA, 1727 (int_ppc_cnttzdm i64:$RST, i64:$RB))]>; 1728 def XXGENPCVBM : 1729 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1730 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1731 def XXGENPCVHM : 1732 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1733 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1734 def XXGENPCVWM : 1735 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1736 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1737 def XXGENPCVDM : 1738 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1739 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1740 def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), 1741 "vclrlb $VD, $VA, $VB", IIC_VecGeneral, 1742 [(set v16i8:$VD, 1743 (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>; 1744 def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), 1745 "vclrrb $VD, $VA, $VB", IIC_VecGeneral, 1746 [(set v16i8:$VD, 1747 (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>; 1748 def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1749 "vmulld $VD, $VA, $VB", IIC_VecGeneral, 1750 [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>; 1751 def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1752 "vmulhsw $VD, $VA, $VB", IIC_VecGeneral, 1753 [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>; 1754 def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1755 "vmulhuw $VD, $VA, $VB", IIC_VecGeneral, 1756 [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>; 1757 def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1758 "vmulhsd $VD, $VA, $VB", IIC_VecGeneral, 1759 [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>; 1760 def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1761 "vmulhud $VD, $VA, $VB", IIC_VecGeneral, 1762 [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>; 1763 def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1764 "vmodsw $VD, $VA, $VB", IIC_VecGeneral, 1765 [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>; 1766 def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1767 "vmoduw $VD, $VA, $VB", IIC_VecGeneral, 1768 [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>; 1769 def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1770 "vmodsd $VD, $VA, $VB", IIC_VecGeneral, 1771 [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>; 1772 def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1773 "vmodud $VD, $VA, $VB", IIC_VecGeneral, 1774 [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>; 1775 def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1776 "vdivsw $VD, $VA, $VB", IIC_VecGeneral, 1777 [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>; 1778 def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1779 "vdivuw $VD, $VA, $VB", IIC_VecGeneral, 1780 [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>; 1781 def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1782 "vdivsd $VD, $VA, $VB", IIC_VecGeneral, 1783 [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>; 1784 def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1785 "vdivud $VD, $VA, $VB", IIC_VecGeneral, 1786 [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>; 1787 def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1788 "vdivesw $VD, $VA, $VB", IIC_VecGeneral, 1789 [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA, 1790 v4i32:$VB))]>; 1791 def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1792 "vdiveuw $VD, $VA, $VB", IIC_VecGeneral, 1793 [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA, 1794 v4i32:$VB))]>; 1795 def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1796 "vdivesd $VD, $VA, $VB", IIC_VecGeneral, 1797 [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA, 1798 v2i64:$VB))]>; 1799 def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1800 "vdiveud $VD, $VA, $VB", IIC_VecGeneral, 1801 [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA, 1802 v2i64:$VB))]>; 1803 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), 1804 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; 1805 def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RST), 1806 "brh $RA, $RST", IIC_IntRotate, []>; 1807 def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RST), 1808 "brw $RA, $RST", IIC_IntRotate, 1809 [(set i32:$RA, (bswap i32:$RST))]>; 1810 let isCodeGenOnly = 1 in { 1811 def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RST), 1812 "brh $RA, $RST", IIC_IntRotate, []>; 1813 def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RST), 1814 "brw $RA, $RST", IIC_IntRotate, []>; 1815 } 1816 def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RST), 1817 "brd $RA, $RST", IIC_IntRotate, 1818 [(set i64:$RA, (bswap i64:$RST))]>; 1819 1820 // The XFormMemOp flag for the following 8 instructions is set on 1821 // the instruction format. 1822 let mayLoad = 1, mayStore = 0 in { 1823 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; 1824 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; 1825 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; 1826 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; 1827 } 1828 1829 let mayLoad = 0, mayStore = 1 in { 1830 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; 1831 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; 1832 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; 1833 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; 1834 } 1835 1836 def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1837 "vmulesd $VD, $VA, $VB", IIC_VecGeneral, 1838 [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA, 1839 v2i64:$VB))]>; 1840 def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1841 "vmuleud $VD, $VA, $VB", IIC_VecGeneral, 1842 [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA, 1843 v2i64:$VB))]>; 1844 def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1845 "vmulosd $VD, $VA, $VB", IIC_VecGeneral, 1846 [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA, 1847 v2i64:$VB))]>; 1848 def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1849 "vmuloud $VD, $VA, $VB", IIC_VecGeneral, 1850 [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA, 1851 v2i64:$VB))]>; 1852 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC), 1853 "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral, 1854 [(set v1i128:$RT, (int_ppc_altivec_vmsumcud 1855 v2i64:$RA, v2i64:$RB, v1i128:$RC))]>; 1856 def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1857 "vdivsq $VD, $VA, $VB", IIC_VecGeneral, 1858 [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>; 1859 def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1860 "vdivuq $VD, $VA, $VB", IIC_VecGeneral, 1861 [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>; 1862 def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1863 "vdivesq $VD, $VA, $VB", IIC_VecGeneral, 1864 [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA, 1865 v1i128:$VB))]>; 1866 def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1867 "vdiveuq $VD, $VA, $VB", IIC_VecGeneral, 1868 [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA, 1869 v1i128:$VB))]>; 1870 def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>; 1871 def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>; 1872 def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>; 1873 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>; 1874 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>; 1875 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>; 1876 def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1877 "vmodsq $VD, $VA, $VB", IIC_VecGeneral, 1878 [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>; 1879 def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), 1880 "vmoduq $VD, $VA, $VB", IIC_VecGeneral, 1881 [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>; 1882 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB), 1883 "vextsd2q $VD, $VB", IIC_VecGeneral, 1884 [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>; 1885 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), 1886 "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>; 1887 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), 1888 "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>; 1889 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", 1890 [(set v1i128:$VD, 1891 (int_ppc_altivec_vrlqnm v1i128:$VA, 1892 v1i128:$VB))]>; 1893 def VRLQMI : VXForm_1<69, (outs vrrc:$VD), 1894 (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi), 1895 "vrlqmi $VD, $VA, $VB", IIC_VecFP, 1896 [(set v1i128:$VD, 1897 (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB, 1898 v1i128:$VDi))]>, 1899 RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; 1900 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; 1901 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; 1902 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; 1903 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; 1904 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; 1905 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; 1906 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; 1907 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; 1908 def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM), 1909 "lxvkq $XT, $UIM", IIC_VecGeneral, []>; 1910} 1911 1912let Predicates = [IsISA3_1, HasVSX] in { 1913 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; 1914 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; 1915 def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", 1916 [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>; 1917 def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", 1918 [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>; 1919} 1920 1921let Predicates = [IsISA3_1] in { 1922 def WAITP10 : XForm_IMM2_IMM2<31, 30, (outs), (ins u2imm:$L, u2imm:$PL), 1923 "wait $L $PL", IIC_LdStLoad, []>; 1924 def SYNCP10 : XForm_IMM3_IMM2<31, 598, (outs), (ins u3imm:$L, u2imm:$SC), 1925 "sync $L, $SC", IIC_LdStSync, []>; 1926} 1927 1928// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. 1929// This is analogous to the CRNotPat multiclass but specifically for Power10 1930// and newer subtargets since the extended forms use Set Boolean instructions. 1931// The first two anonymous patterns defined are actually a duplicate of those 1932// in CRNotPat, but it is preferable to define both multiclasses as complete 1933// ones rather than pulling that small common section out. 1934multiclass P10ReverseSetBool<dag pattern, dag result> { 1935 def : Pat<pattern, (crnot result)>; 1936 def : Pat<(not pattern), result>; 1937 1938 def : Pat<(i32 (zext pattern)), 1939 (SETBCR result)>; 1940 def : Pat<(i64 (zext pattern)), 1941 (SETBCR8 result)>; 1942 1943 def : Pat<(i32 (sext pattern)), 1944 (SETNBCR result)>; 1945 def : Pat<(i64 (sext pattern)), 1946 (SETNBCR8 result)>; 1947 1948 def : Pat<(i32 (anyext pattern)), 1949 (SETBCR result)>; 1950 def : Pat<(i64 (anyext pattern)), 1951 (SETBCR8 result)>; 1952} 1953 1954multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy, 1955 ImmLeaf SExtTy, I Cmpi, I Cmpli, 1956 I Cmp, I Cmpl> { 1957 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1958 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>; 1959 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1960 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>; 1961 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1962 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>; 1963 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1964 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>; 1965 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1966 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>; 1967 1968 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)), 1969 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>; 1970 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)), 1971 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>; 1972 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)), 1973 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>; 1974 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)), 1975 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>; 1976 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)), 1977 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>; 1978 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)), 1979 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>; 1980} 1981 1982multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> { 1983 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1984 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1985 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1986 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1987 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1988 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 1989 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1990 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 1991 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 1992 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 1993 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1994 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 1995 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 1996 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 1997} 1998 1999let Predicates = [IsISA3_1] in { 2000 def : Pat<(i32 (zext i1:$in)), 2001 (SETBC $in)>; 2002 def : Pat<(i64 (zext i1:$in)), 2003 (SETBC8 $in)>; 2004 def : Pat<(i32 (sext i1:$in)), 2005 (SETNBC $in)>; 2006 def : Pat<(i64 (sext i1:$in)), 2007 (SETNBC8 $in)>; 2008 def : Pat<(i32 (anyext i1:$in)), 2009 (SETBC $in)>; 2010 def : Pat<(i64 (anyext i1:$in)), 2011 (SETBC8 $in)>; 2012 2013 // Instantiation of the set boolean reverse patterns for 32-bit integers. 2014 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16, 2015 CMPWI, CMPLWI, CMPW, CMPLW>; 2016 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 2017 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2018 (LO16 imm:$imm)), sub_eq)>; 2019 2020 // Instantiation of the set boolean reverse patterns for 64-bit integers. 2021 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16, 2022 CMPDI, CMPLDI, CMPD, CMPLD>; 2023 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 2024 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2025 (LO16 imm:$imm)), sub_eq)>; 2026} 2027 2028// Instantiation of the set boolean reverse patterns for f32, f64, f128. 2029let Predicates = [IsISA3_1, HasFPU] in { 2030 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>; 2031 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>; 2032 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>; 2033} 2034 2035//---------------------------- Anonymous Patterns ----------------------------// 2036let Predicates = [IsISA3_1] in { 2037 // Exploit the vector multiply high instructions using intrinsics. 2038 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), 2039 (v4i32 (VMULHSW $vA, $vB))>; 2040 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), 2041 (v4i32 (VMULHUW $vA, $vB))>; 2042 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), 2043 (v2i64 (VMULHSD $vA, $vB))>; 2044 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)), 2045 (v2i64 (VMULHUD $vA, $vB))>; 2046 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), 2047 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; 2048 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), 2049 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; 2050 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), 2051 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; 2052 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), 2053 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; 2054 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), 2055 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; 2056 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), 2057 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; 2058 def : Pat<(srl (bswap i32:$RS), (i32 16)), 2059 (RLDICL_32 (BRH $RS), 0, 48)>; 2060 def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))), 2061 (RLDICL_32_64 (BRH $RS), 0, 48)>; 2062 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)), 2063 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>; 2064 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)), 2065 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>; 2066 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)), 2067 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>; 2068 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)), 2069 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>; 2070 2071 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)), 2072 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>; 2073 2074 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)), 2075 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>; 2076} 2077 2078let Predicates = [IsISA3_1, HasVSX] in { 2079 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)), 2080 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>; 2081 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)), 2082 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>; 2083} 2084 2085let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in { 2086 // Store element 0 of a VSX register to memory 2087 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst), 2088 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>; 2089 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst), 2090 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>; 2091 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst), 2092 (STXVRWX $src, ForceXForm:$dst)>; 2093 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst), 2094 (STXVRWX $src, ForceXForm:$dst)>; 2095 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst), 2096 (STXVRDX $src, ForceXForm:$dst)>; 2097 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst), 2098 (STXVRDX $src, ForceXForm:$dst)>; 2099 // Load element 0 of a VSX register to memory 2100 def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))), 2101 (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>; 2102 def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))), 2103 (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>; 2104 def : Pat<(store (i64 (extractelt v2i64:$A, 1)), ForceXForm:$src), 2105 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 2106 } 2107 2108let Predicates = [IsISA3_1, IsBigEndian] in { 2109 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), ForceXForm:$src), 2110 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), ForceXForm:$src)>; 2111} 2112 2113// FIXME: The swap is overkill when the shift amount is a constant. 2114// We should just fix the constant in the DAG. 2115let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { 2116 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)), 2117 (v1i128 (VSLQ v1i128:$VRA, 2118 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2119 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2120 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), 2121 (v1i128 (VSLQ v1i128:$VRA, 2122 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2123 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2124 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)), 2125 (v1i128 (VSRQ v1i128:$VRA, 2126 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2127 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2128 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)), 2129 (v1i128 (VSRQ v1i128:$VRA, 2130 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2131 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2132 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)), 2133 (v1i128 (VSRAQ v1i128:$VRA, 2134 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2135 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2136 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)), 2137 (v1i128 (VSRAQ v1i128:$VRA, 2138 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2139 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2140} 2141 2142class xxevalPattern <dag pattern, bits<8> imm> : 2143 Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} 2144 2145let AddedComplexity = 400, Predicates = [PrefixInstrs] in { 2146 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A, 2147 i32immNonAllOneNonZero:$A, 2148 i32immNonAllOneNonZero:$A, 2149 i32immNonAllOneNonZero:$A)), 2150 (v4i32 (XXSPLTIW imm:$A))>; 2151 def : Pat<(f32 nzFPImmAsi32:$A), 2152 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2153 VSFRC)>; 2154 def : Pat<(f64 nzFPImmAsi32:$A), 2155 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2156 VSFRC)>; 2157 2158// To replace constant pool with XXSPLTI32DX for scalars. 2159def : Pat<(f32 nzFPImmAsi64:$A), 2160 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0, 2161 (getFPAs64BitIntHi $A)), 2162 1, (getFPAs64BitIntLo $A)), 2163 VSSRC)>; 2164 2165def : Pat<(f64 nzFPImmAsi64:$A), 2166 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0, 2167 (getFPAs64BitIntHi $A)), 2168 1, (getFPAs64BitIntLo $A)), 2169 VSFRC)>; 2170 2171 // Anonymous patterns for XXEVAL 2172 // AND 2173 // and(A, B, C) 2174 def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; 2175 // and(A, xor(B, C)) 2176 def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; 2177 // and(A, or(B, C)) 2178 def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; 2179 // and(A, nor(B, C)) 2180 def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; 2181 // and(A, eqv(B, C)) 2182 def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; 2183 // and(A, nand(B, C)) 2184 def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; 2185 2186 // NAND 2187 // nand(A, B, C) 2188 def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 2189 !sub(255, 1)>; 2190 // nand(A, xor(B, C)) 2191 def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 2192 !sub(255, 6)>; 2193 // nand(A, or(B, C)) 2194 def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 2195 !sub(255, 7)>; 2196 // nand(A, nor(B, C)) 2197 def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 2198 !sub(255, 8)>; 2199 // nand(A, eqv(B, C)) 2200 def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 2201 !sub(255, 9)>; 2202 // nand(A, nand(B, C)) 2203 def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 2204 !sub(255, 14)>; 2205 2206 // EQV 2207 // (eqv A, B, C) 2208 def : xxevalPattern<(or (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 2209 (vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)))), 2210 150>; 2211 // (eqv A, (and B, C)) 2212 def : xxevalPattern<(vnot (xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 225>; 2213 // (eqv A, (or B, C)) 2214 def : xxevalPattern<(vnot (xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 135>; 2215 2216 // NOR 2217 // (nor A, B, C) 2218 def : xxevalPattern<(vnot (or v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 128>; 2219 // (nor A, (and B, C)) 2220 def : xxevalPattern<(vnot (or v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 224>; 2221 // (nor A, (eqv B, C)) 2222 def : xxevalPattern<(and (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 96>; 2223 // (nor A, (nand B, C)) 2224 def : xxevalPattern<(and (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 16>; 2225 // (nor A, (nor B, C)) 2226 def : xxevalPattern<(and (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 112>; 2227 // (nor A, (xor B, C)) 2228 def : xxevalPattern<(vnot (or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 144>; 2229 2230 // OR 2231 // (or A, B, C) 2232 def : xxevalPattern<(or v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 127>; 2233 // (or A, (and B, C)) 2234 def : xxevalPattern<(or v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 31>; 2235 // (or A, (eqv B, C)) 2236 def : xxevalPattern<(or v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 159>; 2237 // (or A, (nand B, C)) 2238 def : xxevalPattern<(or v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 239>; 2239 // (or A, (nor B, C)) 2240 def : xxevalPattern<(or v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 143>; 2241 // (or A, (xor B, C)) 2242 def : xxevalPattern<(or v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 111>; 2243 2244 // XOR 2245 // (xor A, B, C) 2246 def : xxevalPattern<(xor v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 105>; 2247 // (xor A, (and B, C)) 2248 def : xxevalPattern<(xor v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 30>; 2249 // (xor A, (or B, C)) 2250 def : xxevalPattern<(xor v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 120>; 2251 2252 // Anonymous patterns to select prefixed VSX loads and stores. 2253 // Load / Store f128 2254 def : Pat<(f128 (load PDForm:$src)), 2255 (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>; 2256 def : Pat<(store f128:$XS, PDForm:$dst), 2257 (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>; 2258 2259 // Load / Store v4i32 2260 def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>; 2261 def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2262 2263 // Load / Store v2i64 2264 def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>; 2265 def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2266 2267 // Load / Store v4f32 2268 def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>; 2269 def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2270 2271 // Load / Store v2f64 2272 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>; 2273 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2274 2275 // Cases For PPCstore_scal_int_from_vsr 2276 def : Pat<(PPCstore_scal_int_from_vsr f64:$src, PDForm:$dst, 8), 2277 (PSTXSD $src, PDForm:$dst)>; 2278 def : Pat<(PPCstore_scal_int_from_vsr f128:$src, PDForm:$dst, 8), 2279 (PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>; 2280} 2281 2282let Predicates = [PrefixInstrs] in { 2283 def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>; 2284 def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>; 2285 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)), 2286 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC), 2287 (COPY_TO_REGCLASS $B, VSRC), 2288 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>; 2289 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)), 2290 (COPY_TO_REGCLASS 2291 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC), 2292 (COPY_TO_REGCLASS $B, VSRC), 2293 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2294 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)), 2295 (COPY_TO_REGCLASS 2296 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC), 2297 (COPY_TO_REGCLASS $B, VSRC), 2298 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2299 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C), 2300 (XXBLENDVW $A, $B, $C)>; 2301 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C), 2302 (XXBLENDVD $A, $B, $C)>; 2303 2304 // Anonymous patterns to select prefixed loads and stores. 2305 // Load i32 2306 def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2307 def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2308 def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2309 def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2310 def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2311 def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2312 def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>; 2313 def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>; 2314 2315 // Store i32 2316 def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>; 2317 def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>; 2318 def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>; 2319 2320 // Load i64 2321 def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2322 def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2323 def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2324 def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2325 def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2326 def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2327 def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>; 2328 def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2329 def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2330 def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>; 2331 def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>; 2332 2333 // Store i64 2334 def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>; 2335 def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>; 2336 def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>; 2337 def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>; 2338 2339 // Load / Store f32 2340 def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>; 2341 def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>; 2342 2343 // Load / Store f64 2344 def : Pat<(f64 (extloadf32 PDForm:$src)), 2345 (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>; 2346 def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>; 2347 def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; 2348 2349 // Atomic Load 2350 def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>; 2351 def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>; 2352 def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>; 2353 def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>; 2354 2355 // Atomic Store 2356 def : Pat<(atomic_store_8 i32:$RS, PDForm:$dst), (PSTB $RS, memri34:$dst)>; 2357 def : Pat<(atomic_store_16 i32:$RS, PDForm:$dst), (PSTH $RS, memri34:$dst)>; 2358 def : Pat<(atomic_store_32 i32:$RS, PDForm:$dst), (PSTW $RS, memri34:$dst)>; 2359 def : Pat<(atomic_store_64 i64:$RS, PDForm:$dst), (PSTD $RS, memri34:$dst)>; 2360 2361 // Prefixed fpext to v2f64 2362 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), 2363 (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; 2364} 2365 2366def InsertEltShift { 2367 dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32)); 2368 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30); 2369 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29); 2370 dag Left1 = (RLWINM $rB, 1, 0, 30); 2371 dag Left2 = (RLWINM $rB, 2, 0, 29); 2372 dag Left3 = (RLWINM8 $rB, 3, 0, 28); 2373} 2374 2375let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in { 2376 // Indexed vector insert element 2377 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2378 (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>; 2379 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2380 (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2381 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2382 (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2383 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2384 (VINSDRX $vDi, InsertEltShift.Left3, $rA)>; 2385 2386 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2387 (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2388 2389 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2390 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2391 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2392 (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2393 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2394 (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2395 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2396 (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2397 let AddedComplexity = 400 in { 2398 // Immediate vector insert element 2399 foreach Idx = [0, 1, 2, 3] in { 2400 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)), 2401 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>; 2402 } 2403 foreach i = [0, 1] in 2404 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))), 2405 (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>; 2406 } 2407} 2408 2409let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in { 2410 // Indexed vector insert element 2411 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)), 2412 (VINSBLX $vDi, $rB, $rA)>; 2413 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)), 2414 (VINSHLX $vDi, InsertEltShift.Left1, $rA)>; 2415 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)), 2416 (VINSWLX $vDi, InsertEltShift.Left2, $rA)>; 2417 2418 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i32:$rB)), 2419 (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>; 2420} 2421 2422let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in { 2423 // Indexed vector insert element 2424 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2425 (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>; 2426 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2427 (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2428 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2429 (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2430 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2431 (VINSDLX $vDi, InsertEltShift.Left3, $rA)>; 2432 2433 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2434 (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2435 2436 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2437 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2438 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2439 (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2440 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2441 (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2442 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2443 (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2444} 2445 2446let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in { 2447 // Immediate vector insert element 2448 foreach Ty = [i32, i64] in { 2449 foreach Idx = [0, 1, 2, 3] in { 2450 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))), 2451 (VINSW $vDi, !mul(Idx, 4), $rA)>; 2452 } 2453 } 2454 2455 foreach Idx = [0, 1] in 2456 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)), 2457 (VINSD $vDi, !mul(Idx, 8), $rA)>; 2458} 2459 2460 2461//===----------------------------------------------------------------------===// 2462// PowerPC ISA 3.1 Extended Mnemonics. 2463// 2464 2465let Predicates = [IsISA3_1] in { 2466 def : InstAlias<"wait", (WAITP10 0, 0)>; 2467 def : InstAlias<"wait 0", (WAITP10 0, 0), 0>; 2468 def : InstAlias<"wait 1", (WAITP10 1, 0), 0>; 2469 def : InstAlias<"waitrsv", (WAITP10 1, 0)>; 2470 def : InstAlias<"pause_short", (WAITP10 2, 0), 0>; 2471 2472 def : InstAlias<"sync", (SYNCP10 0, 0)>; 2473 def : InstAlias<"hwsync", (SYNCP10 0, 0), 0>; 2474 def : InstAlias<"wsync", (SYNCP10 1, 0), 0>; 2475 def : InstAlias<"ptesync", (SYNCP10 2, 0)>; 2476 def : InstAlias<"phwsync", (SYNCP10 4, 0)>; 2477 def : InstAlias<"plwsync", (SYNCP10 5, 0)>; 2478 def : InstAlias<"sync $L", (SYNCP10 u3imm:$L, 0)>; 2479 def : InstAlias<"stncisync", (SYNCP10 1, 1)>; 2480 def : InstAlias<"stcisync", (SYNCP10 0, 2)>; 2481 def : InstAlias<"stsync", (SYNCP10 0, 3)>; 2482 2483 def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>; 2484} 2485 2486let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in { 2487 let Interpretation64Bit = 1 in { 2488 def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 2489 (ins g8rc_nox0:$RA, s34imm:$SI), 2490 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>; 2491 def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 2492 (ins s34imm_pcrel:$SI), 2493 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel; 2494 } 2495 2496 def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI", 2497 (ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>; 2498 2499 def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 2500 (ins gprc_nor0:$RA, s34imm:$SI), 2501 "pla $RT, ${SI} ${RA}", IIC_IntSimple, []>; 2502 def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 2503 (ins s34imm_pcrel:$SI), 2504 "pla $RT, $SI", IIC_IntSimple, []>, isPCRel; 2505} 2506