1 2// Mask immediates for MMA instructions (2, 4 and 8 bits). 3def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>; 4def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>; 5def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>; 6 7def MMA : Predicate<"Subtarget->hasMMA()">; 8 9 10// Multiclass definitions for MMA accumulator instructions. 11// ---------------------------------------------------------------------------- 12 13// Defines 2 unmasked instructions where the xo field for acc/non-acc version 14// is even/odd. 15multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 16 string asmstr> { 17 let Predicates = [MMA, IsNotISAFuture] in { 18 def NAME : 19 XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL, 20 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 21 RegConstraint<"@earlyclobber $AT">; 22 def PP : 23 XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL), 24 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 25 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 26 } 27 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in { 28 def NAME#W : 29 XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs wacc:$AT), IOL, 30 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 31 RegConstraint<"@earlyclobber $AT">; 32 def WPP : 33 XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), !con((ins wacc:$ATi), IOL), 34 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 35 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 36 } 37} 38 39// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits. 40// The XO field for acc/non-acc version is even/odd. 41multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 42 string asmstr> { 43 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 44 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 45 def PM#NAME : 46 MMIRR_XX3Form_XY4P8_XAB6< 47 opcode, !or(xo, 0x01), (outs acc:$AT), 48 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)), 49 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 50 IIC_VecFP, []>, 51 RegConstraint<"@earlyclobber $AT">; 52 def PM#NAME#PP : 53 MMIRR_XX3Form_XY4P8_XAB6< 54 opcode, xo, (outs acc:$AT), 55 !con((ins acc:$ATi), 56 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))), 57 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 58 IIC_VecFP, []>, 59 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 60 } 61 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 62 def PM#NAME#W : 63 MMIRR_XX3Form_XY4P8_XAB6< 64 opcode, !or(xo, 0x01), (outs wacc:$AT), 65 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)), 66 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 67 IIC_VecFP, []>, 68 RegConstraint<"@earlyclobber $AT">; 69 def PM#NAME#WPP : 70 MMIRR_XX3Form_XY4P8_XAB6< 71 opcode, xo, (outs wacc:$AT), 72 !con((ins wacc:$ATi), 73 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))), 74 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 75 IIC_VecFP, []>, 76 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 77 } 78} 79 80// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits. 81// The XO field for acc/non-acc version is even/odd. 82multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 83 string asmstr> { 84 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 85 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 86 def PM#NAME : 87 MMIRR_XX3Form_XYP4_XAB6< 88 opcode, !or(xo, 0x01), (outs acc:$AT), 89 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)), 90 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 91 IIC_VecFP, []>, 92 RegConstraint<"@earlyclobber $AT">; 93 def PM#NAME#PP : 94 MMIRR_XX3Form_XYP4_XAB6< 95 opcode, xo, (outs acc:$AT), 96 !con((ins acc:$ATi), 97 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))), 98 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 99 IIC_VecFP, []>, 100 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 101 } 102 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 103 def PM#NAME#W : 104 MMIRR_XX3Form_XYP4_XAB6< 105 opcode, !or(xo, 0x01), (outs wacc:$AT), 106 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)), 107 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 108 IIC_VecFP, []>, 109 RegConstraint<"@earlyclobber $AT">; 110 def PM#NAME#WPP : 111 MMIRR_XX3Form_XYP4_XAB6< 112 opcode, xo, (outs wacc:$AT), 113 !con((ins wacc:$ATi), 114 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))), 115 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 116 IIC_VecFP, []>, 117 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 118 } 119} 120 121// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits. 122// The XO field for acc/non-acc version is even/odd. 123multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 124 string asmstr> { 125 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 126 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 127 def PM#NAME : 128 MMIRR_XX3Form_XY4P2_XAB6< 129 opcode, !or(xo, 0x01), (outs acc:$AT), 130 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 131 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 132 IIC_VecFP, []>, 133 RegConstraint<"@earlyclobber $AT">; 134 def PM#NAME#PP : 135 MMIRR_XX3Form_XY4P2_XAB6< 136 opcode, xo, (outs acc:$AT), 137 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 138 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 139 IIC_VecFP, []>, 140 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 141 } 142 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 143 def PM#NAME#W : 144 MMIRR_XX3Form_XY4P2_XAB6< 145 opcode, !or(xo, 0x01), (outs wacc:$AT), 146 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 147 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 148 IIC_VecFP, []>, 149 RegConstraint<"@earlyclobber $AT">; 150 def PM#NAME#WPP : 151 MMIRR_XX3Form_XY4P2_XAB6< 152 opcode, xo, (outs wacc:$AT), 153 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 154 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 155 IIC_VecFP, []>, 156 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 157 } 158} 159 160// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits. 161// Upper nibble of XO field for acc/non-acc version is 0x4/0x6. 162multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 163 string asmstr> { 164 let Predicates = [MMA, IsNotISAFuture] in { 165 def NAME : 166 XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL, 167 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 168 RegConstraint<"@earlyclobber $AT">; 169 def PP : 170 XX3Form_AT3_XAB6< 171 opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL), 172 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 173 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 174 } 175 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 176 def PM#NAME : 177 MMIRR_XX3Form_XY4P2_XAB6< 178 opcode, xo, (outs acc:$AT), 179 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 180 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 181 IIC_VecFP, []>, 182 RegConstraint<"@earlyclobber $AT">; 183 def PM#NAME#PP : 184 MMIRR_XX3Form_XY4P2_XAB6< 185 opcode, !or(xo, 0x20), (outs acc:$AT), 186 !con((ins acc:$ATi), 187 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 188 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 189 IIC_VecFP, []>, 190 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 191 } 192 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in { 193 def NAME#W : 194 XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), IOL, 195 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 196 RegConstraint<"@earlyclobber $AT">; 197 def WPP : 198 XX3Form_AT3_XAB6< 199 opcode, !or(xo, 0x20), (outs wacc:$AT), !con((ins wacc:$ATi), IOL), 200 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 201 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 202 } 203 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 204 def PM#NAME#W : 205 MMIRR_XX3Form_XY4P2_XAB6< 206 opcode, xo, (outs wacc:$AT), 207 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 208 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 209 IIC_VecFP, []>, 210 RegConstraint<"@earlyclobber $AT">; 211 def PM#NAME#WPP : 212 MMIRR_XX3Form_XY4P2_XAB6< 213 opcode, !or(xo, 0x20), (outs acc:$AT), 214 !con((ins wacc:$ATi), 215 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 216 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 217 IIC_VecFP, []>, 218 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 219 } 220} 221 222// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4 223// bits. Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 224multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 225 string asmbase, string asmstr> { 226 defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>; 227 let Predicates = [MMA, IsNotISAFuture] in { 228 def PN : XX3Form_AT3_XAB6< 229 opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL), 230 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 231 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 232 def NP : XX3Form_AT3_XAB6< 233 opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL), 234 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 235 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 236 def NN : XX3Form_AT3_XAB6< 237 opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL), 238 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 239 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 240 } 241 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in { 242 def WPN : XX3Form_AT3_XAB6< 243 opcode, !or(xo, 0x80), (outs wacc:$AT), !con((ins wacc:$ATi), IOL), 244 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 245 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 246 def WNP : XX3Form_AT3_XAB6< 247 opcode, !or(xo, 0x40), (outs wacc:$AT), !con((ins wacc:$ATi), IOL), 248 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 249 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 250 def WNN : XX3Form_AT3_XAB6< 251 opcode, !or(xo, 0xC0), (outs wacc:$AT), !con((ins wacc:$ATi), IOL), 252 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 253 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 254 } 255 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 256 def PM#NAME#PN : 257 MMIRR_XX3Form_XY4P2_XAB6< 258 opcode, !or(xo, 0x80), (outs acc:$AT), 259 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 260 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"), 261 IIC_VecFP, []>, 262 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 263 def PM#NAME#NP : 264 MMIRR_XX3Form_XY4P2_XAB6< 265 opcode, !or(xo, 0x40), (outs acc:$AT), 266 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 267 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"), 268 IIC_VecFP, []>, 269 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 270 def PM#NAME#NN : 271 MMIRR_XX3Form_XY4P2_XAB6< 272 opcode, !or(xo, 0xC0), (outs acc:$AT), 273 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 274 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"), 275 IIC_VecFP, []>, 276 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 277 } 278 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 279 def PM#NAME#WPN : 280 MMIRR_XX3Form_XY4P2_XAB6< 281 opcode, !or(xo, 0x80), (outs wacc:$AT), 282 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 283 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"), 284 IIC_VecFP, []>, 285 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 286 def PM#NAME#WNP : 287 MMIRR_XX3Form_XY4P2_XAB6< 288 opcode, !or(xo, 0x40), (outs wacc:$AT), 289 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 290 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"), 291 IIC_VecFP, []>, 292 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 293 def PM#NAME#WNN : 294 MMIRR_XX3Form_XY4P2_XAB6< 295 opcode, !or(xo, 0xC0), (outs wacc:$AT), 296 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 297 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"), 298 IIC_VecFP, []>, 299 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 300 } 301} 302 303// Defines 5 instructions, unmasked, operand negating. 304// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 305multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 306 string asmbase, string asmstr> { 307 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 308 let Predicates = [MMA, IsNotISAFuture] in { 309 def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT), 310 !con((ins acc:$ATi), IOL), 311 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 312 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 313 def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT), 314 !con((ins acc:$ATi), IOL), 315 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 316 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 317 def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT), 318 !con((ins acc:$ATi), IOL), 319 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 320 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 321 } 322 let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in { 323 def WPN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs wacc:$AT), 324 !con((ins wacc:$ATi), IOL), 325 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 326 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 327 def WNP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs wacc:$AT), 328 !con((ins wacc:$ATi), IOL), 329 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 330 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 331 def WNN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs wacc:$AT), 332 !con((ins wacc:$ATi), IOL), 333 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 334 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 335 } 336} 337 338// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits. 339// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 340multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 341 string asmbase, string asmstr> { 342 defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>; 343 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 344 def PM#NAME : 345 MMIRR_XX3Form_XY4_XAB6< 346 opcode, !or(xo, 0x01), (outs acc:$AT), 347 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)), 348 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"), 349 IIC_VecFP, []>, 350 RegConstraint<"@earlyclobber $AT">; 351 def PM#NAME#PP : 352 MMIRR_XX3Form_XY4_XAB6< 353 opcode, xo, (outs acc:$AT), 354 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 355 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"), 356 IIC_VecFP, []>, 357 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 358 def PM#NAME#PN : 359 MMIRR_XX3Form_XY4_XAB6< 360 opcode, !or(xo, 0x80), (outs acc:$AT), 361 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 362 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"), 363 IIC_VecFP, []>, 364 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 365 def PM#NAME#NP : 366 MMIRR_XX3Form_XY4_XAB6< 367 opcode, !or(xo, 0x40), (outs acc:$AT), 368 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 369 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"), 370 IIC_VecFP, []>, 371 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 372 def PM#NAME#NN : 373 MMIRR_XX3Form_XY4_XAB6< 374 opcode, !or(xo, 0xC0), (outs acc:$AT), 375 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 376 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"), 377 IIC_VecFP, []>, 378 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 379 } 380 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 381 def PM#NAME#W : 382 MMIRR_XX3Form_XY4_XAB6< 383 opcode, !or(xo, 0x01), (outs wacc:$AT), 384 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)), 385 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"), 386 IIC_VecFP, []>, 387 RegConstraint<"@earlyclobber $AT">; 388 def PM#NAME#WPP : 389 MMIRR_XX3Form_XY4_XAB6< 390 opcode, xo, (outs wacc:$AT), 391 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 392 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"), 393 IIC_VecFP, []>, 394 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 395 def PM#NAME#WPN : 396 MMIRR_XX3Form_XY4_XAB6< 397 opcode, !or(xo, 0x80), (outs wacc:$AT), 398 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 399 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"), 400 IIC_VecFP, []>, 401 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 402 def PM#NAME#WNP : 403 MMIRR_XX3Form_XY4_XAB6< 404 opcode, !or(xo, 0x40), (outs wacc:$AT), 405 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 406 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"), 407 IIC_VecFP, []>, 408 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 409 def PM#NAME#WNN : 410 MMIRR_XX3Form_XY4_XAB6< 411 opcode, !or(xo, 0xC0), (outs wacc:$AT), 412 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 413 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"), 414 IIC_VecFP, []>, 415 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 416 } 417} 418 419// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits. 420// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 421multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 422 string asmbase, string asmstr> { 423 defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>; 424 let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 425 def PM#NAME : 426 MMIRR_XX3Form_X4Y2_XAB6< 427 opcode, !or(xo, 0x01), (outs acc:$AT), 428 !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)), 429 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"), 430 IIC_VecFP, []>, 431 RegConstraint<"@earlyclobber $AT">; 432 def PM#NAME#PP : 433 MMIRR_XX3Form_X4Y2_XAB6< 434 opcode, xo, (outs acc:$AT), 435 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 436 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"), 437 IIC_VecFP, []>, 438 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 439 def PM#NAME#PN : 440 MMIRR_XX3Form_X4Y2_XAB6< 441 opcode, !or(xo, 0x80), (outs acc:$AT), 442 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 443 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"), 444 IIC_VecFP, []>, 445 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 446 def PM#NAME#NP : 447 MMIRR_XX3Form_X4Y2_XAB6< 448 opcode, !or(xo, 0x40), (outs acc:$AT), 449 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 450 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"), 451 IIC_VecFP, []>, 452 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 453 def PM#NAME#NN : 454 MMIRR_XX3Form_X4Y2_XAB6< 455 opcode, !or(xo, 0xC0), (outs acc:$AT), 456 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 457 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"), 458 IIC_VecFP, []>, 459 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 460 } 461 let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 462 def PM#NAME#W : 463 MMIRR_XX3Form_X4Y2_XAB6< 464 opcode, !or(xo, 0x01), (outs wacc:$AT), 465 !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)), 466 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"), 467 IIC_VecFP, []>, 468 RegConstraint<"@earlyclobber $AT">; 469 def PM#NAME#WPP : 470 MMIRR_XX3Form_X4Y2_XAB6< 471 opcode, xo, (outs wacc:$AT), 472 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 473 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"), 474 IIC_VecFP, []>, 475 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 476 def PM#NAME#WPN : 477 MMIRR_XX3Form_X4Y2_XAB6< 478 opcode, !or(xo, 0x80), (outs wacc:$AT), 479 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 480 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"), 481 IIC_VecFP, []>, 482 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 483 def PM#NAME#WNP : 484 MMIRR_XX3Form_X4Y2_XAB6< 485 opcode, !or(xo, 0x40), (outs wacc:$AT), 486 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 487 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"), 488 IIC_VecFP, []>, 489 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 490 def PM#NAME#WNN : 491 MMIRR_XX3Form_X4Y2_XAB6< 492 opcode, !or(xo, 0xC0), (outs wacc:$AT), 493 !con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 494 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"), 495 IIC_VecFP, []>, 496 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 497 } 498} 499 500// End of class definitions. 501//----------------------------------------------------------------------------- 502 503let Predicates = [MMA, IsNotISAFuture] in { 504 def XXMFACC : 505 XForm_AT3<31, 0, 177, (outs acc:$ATo), (ins acc:$AT), "xxmfacc $AT", 506 IIC_VecGeneral, 507 [(set v512i1:$ATo, (int_ppc_mma_xxmfacc v512i1:$AT))]>, 508 RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">; 509 def XXMTACC : 510 XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT", 511 IIC_VecGeneral, 512 [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>, 513 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 514 def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp), 515 "#KILL_PAIR", []>, 516 RegConstraint<"$XTp = $XSp">; 517 def BUILD_UACC : PPCPostRAExpPseudo<(outs acc:$AT), (ins uacc:$AS), 518 "#BUILD_UACC $AT, $AS", []>; 519 // We define XXSETACCZ as rematerializable to undo CSE of that intrinsic in 520 // the backend. We avoid CSE here because it generates a copy of the acc 521 // register and this copy is more expensive than calling the intrinsic again. 522 let isAsCheapAsAMove = 1, isReMaterializable = 1 in { 523 def XXSETACCZ : 524 XForm_AT3<31, 3, 177, (outs acc:$AT), (ins), "xxsetaccz $AT", IIC_VecGeneral, 525 [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>; 526 } 527 def XVI8GER4SPP : 528 XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB), 529 "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>, 530 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 531 let mayStore = 1 in { 532 def SPILL_ACC: PPCEmitTimePseudo<(outs), (ins acc:$AT, memrix16:$dst), 533 "#SPILL_ACC", []>; 534 def SPILL_UACC: PPCEmitTimePseudo<(outs), (ins uacc:$AT, memrix16:$dst), 535 "#SPILL_UACC", []>; 536 } 537 let mayLoad = 1, hasSideEffects = 0 in { 538 def RESTORE_ACC: PPCEmitTimePseudo<(outs acc:$AT), (ins memrix16:$src), 539 "#RESTORE_ACC", []>; 540 def RESTORE_UACC: PPCEmitTimePseudo<(outs uacc:$AT), (ins memrix16:$src), 541 "#RESTORE_UACC", []>; 542 } 543} 544 545let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in { 546 // For Future and up XXMFACCW and XXMTACCW will not have patterns. 547 // On Future CPU the wacc registers no longer overlap with the vsr registers 548 // and so register allocation would have to know to match 4 vsr registers 549 // with one wacc register. 550 // On top of that Future CPU has a more convenient way to move between vsrs 551 // and wacc registers using xxextfdmr512 and xxinstdmr512. 552 def XXMFACCW : 553 XForm_AT3<31, 0, 177, (outs wacc:$ATo), (ins wacc:$AT), "xxmfacc $AT", 554 IIC_VecGeneral, []>, 555 RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">; 556 def XXMTACCW : 557 XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "xxmtacc $AT", 558 IIC_VecGeneral, []>, 559 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 560 561 let isAsCheapAsAMove = 1, isReMaterializable = 1 in { 562 def XXSETACCZW : 563 XForm_AT3<31, 3, 177, (outs wacc:$AT), (ins), "xxsetaccz $AT", 564 IIC_VecGeneral, [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>; 565 } 566 567 def XVI8GER4WSPP : 568 XX3Form_AT3_XAB6<59, 99, (outs wacc:$AT), 569 (ins wacc:$ATi, vsrc:$XA, vsrc:$XB), 570 "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>, 571 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 572 573 let mayStore = 1 in { 574 def SPILL_WACC: PPCEmitTimePseudo<(outs), (ins wacc:$AT, memrix16:$dst), 575 "#SPILL_WACC", []>; 576 } 577 let mayLoad = 1, hasSideEffects = 0 in { 578 def RESTORE_WACC: PPCEmitTimePseudo<(outs wacc:$AT), (ins memrix16:$src), 579 "#RESTORE_WACC", []>; 580 } 581} 582 583let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 584 def PMXVI8GER4SPP : 585 MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT), 586 (ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK, 587 u4imm:$YMSK, u4imm:$PMSK), 588 "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK", 589 IIC_VecGeneral, []>, 590 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 591} 592 593let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in { 594 def PMXVI8GER4WSPP : 595 MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs wacc:$AT), 596 (ins wacc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK, 597 u4imm:$YMSK, u4imm:$PMSK), 598 "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK", 599 IIC_VecGeneral, []>, 600 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 601} 602 603// MMA accumulating/non-accumulating instructions. 604//------------------------------------------------------------------------------ 605 606// XVBF16GER2, XVBF16GER2PP, XVBF16GER2PN, XVBF16GER2NP, XVBF16GER2NN 607// PMXVBF16GER2, PMXVBF16GER2PP, PMXVBF16GER2PN, PMXVBF16GER2NP, PMXVBF16GER2NN 608defm XVBF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 50, (ins vsrc:$XA, vsrc:$XB), 609 "xvbf16ger2", "$AT, $XA, $XB">; 610 611// XVI4GER8, XVI4GER8PP, PMXVI4GER8, PMXVI4GER8PP 612defm XVI4GER8 : ACC_UM_M844_XOEO<59, 34, (ins vsrc:$XA, vsrc:$XB), 613 "xvi4ger8", "$AT, $XA, $XB">; 614 615// XVI8GER4, XVI8GER4PP, PMXVI8GER4, PMXVI8GER4PP 616defm XVI8GER4 : ACC_UM_M444_XOEO<59, 2, (ins vsrc:$XA, vsrc:$XB), 617 "xvi8ger4", "$AT, $XA, $XB">; 618 619// XVI16GER2, XVI16GER2PP, PMXVI16GER2, PMXVI16GER2PP 620defm XVI16GER2 : ACC_UM_M244_XO46<59, 75, (ins vsrc:$XA, vsrc:$XB), 621 "xvi16ger2", "$AT, $XA, $XB">; 622 623// XVI16GER2S, XVI16GER2SPP, PMXVI16GER2S, PMXVI16GER2SPP 624defm XVI16GER2S : ACC_UM_M244_XOEO<59, 42, (ins vsrc:$XA, vsrc:$XB), 625 "xvi16ger2s", "$AT, $XA, $XB">; 626 627// XVF16GER2, XVF16GER2PP, XVF16GER2PN, XVF16GER2NP, XVF16GER2NN 628// PMXVF16GER2, PMXVF16GER2PP, PMXVF16GER2PN, PMXVF16GER2NP, PMXVF16GER2NN 629defm XVF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 18, (ins vsrc:$XA, vsrc:$XB), 630 "xvf16ger2", "$AT, $XA, $XB">; 631 632// XVF32GER, XVF32GERPP, XVF32GERPN, XVF32GERNP, XVF32GERPP 633// PMXVF32GER, PMXVF32GERPP, PMXVF32GERPN, PMXVF32GERNP, PMXVF32GERPP 634defm XVF32GER : ACC_NEG_UM_M44_XOM84C<59, 26, (ins vsrc:$XA, vsrc:$XB), 635 "xvf32ger", "$AT, $XA, $XB">; 636 637// XVF64GER, XVF64GERPP, XVF64GERPN, XVF64GERNP, XVF64GERNN 638// PMXVF64GER, PMXVF64GERPP, PMXVF64GERPN, PMXVF64GERNP, PMXVF64GERNN 639defm XVF64GER : ACC_NEG_UM_M42_XOM84C<59, 58, (ins vsrpevenrc:$XA, vsrc:$XB), 640 "xvf64ger", "$AT, $XA, $XB">; 641//------------------------------------------------------------------------------ 642 643// MMA Intrinsics 644let Predicates = [MMA, IsNotISAFuture] in { 645 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)), 646 (XVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC)>; 647 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 648 (XVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 649 650 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)), 651 (XVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC)>; 652 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 653 (XVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 654 655 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)), 656 (XVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC)>; 657 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 658 (XVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 659} 660 661let Predicates = [MMA, IsISAFuture] in { 662 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)), 663 (XVI4GER8W RCCp.AToVSRC, RCCp.BToVSRC)>; 664 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 665 (XVI4GER8WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 666 667 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)), 668 (XVI8GER4W RCCp.AToVSRC, RCCp.BToVSRC)>; 669 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 670 (XVI8GER4WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 671 672 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)), 673 (XVI16GER2SW RCCp.AToVSRC, RCCp.BToVSRC)>; 674 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 675 (XVI16GER2SWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 676} 677 678let Predicates = [MMA, IsNotISAFuture] in { 679 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)), 680 (XVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>; 681 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 682 (XVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 683 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 684 (XVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 685 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 686 (XVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 687 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 688 (XVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 689} 690 691let Predicates = [MMA, IsISAFuture] in { 692 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)), 693 (XVF16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>; 694 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 695 (XVF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 696 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 697 (XVF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 698 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 699 (XVF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 700 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 701 (XVF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 702} 703 704let Predicates = [MMA, IsNotISAFuture] in { 705 def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)), 706 (XVF32GER RCCp.AToVSRC, RCCp.BToVSRC)>; 707 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 708 (XVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 709 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 710 (XVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 711 def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 712 (XVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 713 def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 714 (XVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 715 def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)), 716 (XVF64GER $XA, RCCp.BToVSRC)>; 717 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 718 (XVF64GERPP $ATi, $XA, RCCp.BToVSRC)>; 719 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 720 (XVF64GERPN $ATi, $XA, RCCp.BToVSRC)>; 721 def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 722 (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>; 723 def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 724 (XVF64GERNN $ATi, $XA, RCCp.BToVSRC)>; 725 726 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)), 727 (XVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>; 728 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 729 (XVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 730 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 731 (XVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 732 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 733 (XVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 734 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 735 (XVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 736 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)), 737 (XVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>; 738 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 739 (XVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 740 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 741 (XVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 742} 743 744let Predicates = [MMA, IsISAFuture] in { 745 def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)), 746 (XVF32GERW RCCp.AToVSRC, RCCp.BToVSRC)>; 747 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 748 (XVF32GERWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 749 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 750 (XVF32GERWPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 751 def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 752 (XVF32GERWNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 753 def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 754 (XVF32GERWNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 755 def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)), 756 (XVF64GERW $XA, RCCp.BToVSRC)>; 757 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 758 (XVF64GERWPP $ATi, $XA, RCCp.BToVSRC)>; 759 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 760 (XVF64GERWPN $ATi, $XA, RCCp.BToVSRC)>; 761 def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 762 (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>; 763 def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 764 (XVF64GERWNN $ATi, $XA, RCCp.BToVSRC)>; 765 766 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)), 767 (XVBF16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>; 768 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 769 (XVBF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 770 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 771 (XVBF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 772 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 773 (XVBF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 774 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 775 (XVBF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 776 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)), 777 (XVI16GER2W RCCp.AToVSRC, RCCp.BToVSRC)>; 778 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 779 (XVI16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 780 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 781 (XVI8GER4WSPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 782} 783// MMA Intrinsics 784 785let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in { 786 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 787 Msk4Imm:$YMSK, Msk8Imm:$PMSK)), 788 (PMXVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 789 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>; 790 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 791 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 792 Msk8Imm:$PMSK)), 793 (PMXVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 794 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>; 795 796 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 797 Msk4Imm:$YMSK, Msk4Imm:$PMSK)), 798 (PMXVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 799 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 800 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 801 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 802 Msk4Imm:$PMSK)), 803 (PMXVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 804 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 805 806 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 807 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 808 (PMXVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 809 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 810 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 811 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 812 Msk2Imm:$PMSK)), 813 (PMXVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 814 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 815 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 816 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 817 (PMXVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 818 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 819 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 820 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 821 Msk2Imm:$PMSK)), 822 (PMXVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 823 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 824 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 825 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 826 Msk2Imm:$PMSK)), 827 (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 828 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 829 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 830 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 831 Msk2Imm:$PMSK)), 832 (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 833 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 834 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 835 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 836 Msk2Imm:$PMSK)), 837 (PMXVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 838 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 839 840 def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 841 Msk4Imm:$YMSK)), 842 (PMXVF32GER RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 843 Msk4Imm:$YMSK)>; 844 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 845 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 846 (PMXVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 847 Msk4Imm:$YMSK)>; 848 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 849 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 850 (PMXVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 851 Msk4Imm:$YMSK)>; 852 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 853 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 854 (PMXVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 855 Msk4Imm:$YMSK)>; 856 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 857 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 858 (PMXVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 859 Msk4Imm:$YMSK)>; 860 861 def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK, 862 Msk2Imm:$YMSK)), 863 (PMXVF64GER $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>; 864 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB, 865 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 866 (PMXVF64GERPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 867 Msk2Imm:$YMSK)>; 868 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB, 869 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 870 (PMXVF64GERPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 871 Msk2Imm:$YMSK)>; 872 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB, 873 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 874 (PMXVF64GERNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 875 Msk2Imm:$YMSK)>; 876 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB, 877 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 878 (PMXVF64GERNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 879 Msk2Imm:$YMSK)>; 880 881 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 882 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 883 (PMXVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 884 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 885 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 886 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 887 Msk2Imm:$PMSK)), 888 (PMXVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 889 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 890 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 891 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 892 Msk2Imm:$PMSK)), 893 (PMXVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 894 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 895 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 896 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 897 Msk2Imm:$PMSK)), 898 (PMXVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 899 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 900 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 901 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 902 Msk2Imm:$PMSK)), 903 (PMXVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 904 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 905 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 906 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 907 (PMXVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 908 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 909 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 910 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 911 Msk2Imm:$PMSK)), 912 (PMXVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 913 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 914 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 915 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 916 Msk2Imm:$PMSK)), 917 (PMXVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 918 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 919} 920 921let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 922 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 923 Msk4Imm:$YMSK, Msk8Imm:$PMSK)), 924 (PMXVI4GER8W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 925 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>; 926 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 927 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 928 Msk8Imm:$PMSK)), 929 (PMXVI4GER8WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 930 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>; 931 932 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 933 Msk4Imm:$YMSK, Msk4Imm:$PMSK)), 934 (PMXVI8GER4W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 935 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 936 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 937 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 938 Msk4Imm:$PMSK)), 939 (PMXVI8GER4WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 940 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 941 942 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 943 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 944 (PMXVI16GER2SW RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 945 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 946 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 947 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 948 Msk2Imm:$PMSK)), 949 (PMXVI16GER2SWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 950 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 951 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 952 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 953 (PMXVF16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 954 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 955 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 956 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 957 Msk2Imm:$PMSK)), 958 (PMXVF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 959 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 960 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 961 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 962 Msk2Imm:$PMSK)), 963 (PMXVF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 964 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 965 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 966 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 967 Msk2Imm:$PMSK)), 968 (PMXVF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 969 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 970 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 971 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 972 Msk2Imm:$PMSK)), 973 (PMXVF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 974 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 975 976 def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 977 Msk4Imm:$YMSK)), 978 (PMXVF32GERW RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 979 Msk4Imm:$YMSK)>; 980 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 981 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 982 (PMXVF32GERWPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 983 Msk4Imm:$YMSK)>; 984 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 985 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 986 (PMXVF32GERWPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 987 Msk4Imm:$YMSK)>; 988 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 989 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 990 (PMXVF32GERWNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 991 Msk4Imm:$YMSK)>; 992 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 993 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 994 (PMXVF32GERWNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 995 Msk4Imm:$YMSK)>; 996 997 def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK, 998 Msk2Imm:$YMSK)), 999 (PMXVF64GERW $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>; 1000 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1001 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1002 (PMXVF64GERWPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1003 Msk2Imm:$YMSK)>; 1004 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1005 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1006 (PMXVF64GERWPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1007 Msk2Imm:$YMSK)>; 1008 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1009 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1010 (PMXVF64GERWNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1011 Msk2Imm:$YMSK)>; 1012 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1013 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1014 (PMXVF64GERWNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1015 Msk2Imm:$YMSK)>; 1016 1017 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1018 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 1019 (PMXVBF16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1020 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1021 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1022 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1023 Msk2Imm:$PMSK)), 1024 (PMXVBF16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1025 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1026 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1027 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1028 Msk2Imm:$PMSK)), 1029 (PMXVBF16GER2WPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1030 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1031 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1032 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1033 Msk2Imm:$PMSK)), 1034 (PMXVBF16GER2WNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1035 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1036 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1037 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1038 Msk2Imm:$PMSK)), 1039 (PMXVBF16GER2WNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1040 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1041 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1042 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 1043 (PMXVI16GER2W RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1044 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1045 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1046 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1047 Msk2Imm:$PMSK)), 1048 (PMXVI8GER4WSPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1049 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1050 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1051 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1052 Msk2Imm:$PMSK)), 1053 (PMXVI16GER2WPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1054 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1055} 1056 1057def ConcatsMMA { 1058 dag VecsToVecPair0 = 1059 (v256i1 (INSERT_SUBREG 1060 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1061 $vs1, sub_vsx0)); 1062 dag VecsToVecPair1 = 1063 (v256i1 (INSERT_SUBREG 1064 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1065 $vs3, sub_vsx0)); 1066 dag VecsToVecQuad = 1067 (BUILD_UACC (INSERT_SUBREG 1068 (INSERT_SUBREG (v512i1 (IMPLICIT_DEF)), 1069 (KILL_PAIR VecsToVecPair0), sub_pair0), 1070 (KILL_PAIR VecsToVecPair1), sub_pair1)); 1071} 1072 1073def Extracts { 1074 dag Pair0 = (v256i1 (EXTRACT_SUBREG $v, sub_pair0)); 1075 dag Pair1 = (v256i1 (EXTRACT_SUBREG $v, sub_pair1)); 1076 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0)); 1077 dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1)); 1078 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0)); 1079 dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1)); 1080} 1081 1082let Predicates = [MMA, IsNotISAFuture] in { 1083 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)), 1084 (XXMTACC ConcatsMMA.VecsToVecQuad)>; 1085 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0, 1086 v16i8:$vs3, v16i8:$vs2)), 1087 (XXMTACC ConcatsMMA.VecsToVecQuad)>; 1088 def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>; 1089 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 0)), 1090 Extracts.Vec0>; 1091 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 1)), 1092 Extracts.Vec1>; 1093 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 2)), 1094 Extracts.Vec2>; 1095 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 3)), 1096 Extracts.Vec3>; 1097} 1098 1099let Predicates = [MMA, IsISAFuture] in { 1100 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)), 1101 (DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>; 1102 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0, 1103 v16i8:$vs3, v16i8:$vs2)), 1104 (DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>; 1105 def : Pat<(v512i1 immAllZerosV), (XXSETACCZW)>; 1106} 1107