1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86 87def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 88 SDTCisPtrTy<0>, SDTCisVT<1, i32> 89]>; 90 91def tocentry32 : Operand<iPTR> { 92 let MIOperandInfo = (ops i32imm:$imm); 93} 94 95def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 96 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 97]>; 98def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 99 SDTCisVec<0>, SDTCisInt<1> 100]>; 101def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 102 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 103]>; 104def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 106]>; 107 108def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 109 SDTCisVec<0>, SDTCisVec<1> 110]>; 111 112def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 113 SDTCisVec<0>, SDTCisPtrTy<1> 114]>; 115 116def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 118]>; 119 120def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 121 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 122]>; 123 124//===----------------------------------------------------------------------===// 125// PowerPC specific DAG Nodes. 126// 127 128def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 129def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 130def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 131def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 132 133def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 134def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 135def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 136def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 137def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 138def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 139def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 140def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 141 142def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 143 SDTFPUnaryOp, [SDNPHasChain]>; 144def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 145 SDTFPUnaryOp, [SDNPHasChain]>; 146def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 147 SDTFPRoundOp, [SDNPHasChain]>; 148def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 149 SDTFPRoundOp, [SDNPHasChain]>; 150 151def PPCany_fcfid : PatFrags<(ops node:$op), 152 [(PPCfcfid node:$op), 153 (PPCstrict_fcfid node:$op)]>; 154def PPCany_fcfidu : PatFrags<(ops node:$op), 155 [(PPCfcfidu node:$op), 156 (PPCstrict_fcfidu node:$op)]>; 157def PPCany_fcfids : PatFrags<(ops node:$op), 158 [(PPCfcfids node:$op), 159 (PPCstrict_fcfids node:$op)]>; 160def PPCany_fcfidus : PatFrags<(ops node:$op), 161 [(PPCfcfidus node:$op), 162 (PPCstrict_fcfidus node:$op)]>; 163 164def PPCcv_fp_to_uint_in_vsr: 165 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 166def PPCcv_fp_to_sint_in_vsr: 167 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 168def PPCstore_scal_int_from_vsr: 169 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 170 [SDNPHasChain, SDNPMayStore]>; 171def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 172 [SDNPHasChain, SDNPMayStore]>; 173def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 174 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 175def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 176 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 177def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 178 [SDNPHasChain, SDNPMayLoad]>; 179def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 180 [SDNPHasChain, SDNPMayStore]>; 181def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 182 183// Extract FPSCR (not modeled at the DAG level). 184def PPCmffs : SDNode<"PPCISD::MFFS", 185 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 186 [SDNPHasChain]>; 187 188// Perform FADD in round-to-zero mode. 189def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 190def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 191 [SDNPHasChain]>; 192 193def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 194 [(PPCfaddrtz node:$lhs, node:$rhs), 195 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 196 197def PPCfsel : SDNode<"PPCISD::FSEL", 198 // Type constraint for fsel. 199 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 200 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 201def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 202def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 203def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 204def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 205def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 206 [SDNPMayLoad, SDNPMemOperand]>; 207 208def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 209 210def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 211def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 212 [SDNPMayLoad]>; 213def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 214def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 215def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 216def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 217def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 218 SDTypeProfile<1, 3, [ 219 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 220 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 221def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 222def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 223def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 224def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 225def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 226 SDTypeProfile<1, 3, [ 227 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 228 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 229def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 230def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 231def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 232 233def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 234def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 235def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 236def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 237def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 238def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 239 240def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 241 242// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 243// amounts. These nodes are generated by the multi-precision shift code. 244def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 245def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 246def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 247 248def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 249 250def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 251 252def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 253 SDTFPUnaryOp, [SDNPHasChain]>; 254def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260 261def PPCany_fctidz : PatFrags<(ops node:$op), 262 [(PPCstrict_fctidz node:$op), 263 (PPCfctidz node:$op)]>; 264def PPCany_fctiwz : PatFrags<(ops node:$op), 265 [(PPCstrict_fctiwz node:$op), 266 (PPCfctiwz node:$op)]>; 267def PPCany_fctiduz : PatFrags<(ops node:$op), 268 [(PPCstrict_fctiduz node:$op), 269 (PPCfctiduz node:$op)]>; 270def PPCany_fctiwuz : PatFrags<(ops node:$op), 271 [(PPCstrict_fctiwuz node:$op), 272 (PPCfctiwuz node:$op)]>; 273 274// Move 2 i64 values into a VSX register 275def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 276 SDTypeProfile<1, 2, 277 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 278 SDTCisSameAs<1,2>]>, 279 []>; 280 281def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 282 SDTypeProfile<1, 2, 283 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 284 SDTCisVT<1,i32>]>, 285 []>; 286 287def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 288 SDTypeProfile<1, 2, 289 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 290 SDTCisPtrTy<2>]>, 291 []>; 292 293// These are target-independent nodes, but have target-specific formats. 294def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 295 [SDNPHasChain, SDNPOutGlue]>; 296def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 297 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 298 299def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 300def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 301 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 302 SDNPVariadic]>; 303def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 304 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 305 SDNPVariadic]>; 306def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 307 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 308 SDNPVariadic]>; 309def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 310 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 311def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 313 SDNPVariadic]>; 314def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 315 SDTypeProfile<0, 1, []>, 316 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 317 SDNPVariadic]>; 318 319// Call nodes for strictfp calls (that define RM). 320def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 321 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 322 SDNPVariadic]>; 323def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 324 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 325 SDNPVariadic]>; 326def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 327 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 328 SDNPVariadic]>; 329def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 330 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 331 SDNPVariadic]>; 332def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 333 SDTypeProfile<0, 1, []>, 334 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 335 SDNPVariadic]>; 336 337def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 338 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 339 340def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 341 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 342 343def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 344 SDTypeProfile<1, 1, [SDTCisInt<0>, 345 SDTCisPtrTy<1>]>, 346 [SDNPHasChain, SDNPSideEffect]>; 347def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 348 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 349 [SDNPHasChain, SDNPSideEffect]>; 350 351def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 352def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 353 [SDNPHasChain, SDNPSideEffect]>; 354 355def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 356 [SDNPHasChain, SDNPSideEffect]>; 357def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 358def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 359 [SDNPHasChain, SDNPSideEffect]>; 360 361def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 362def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 363 364def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 365 [SDNPHasChain, SDNPOptInGlue]>; 366 367// PPC-specific atomic operations. 368def PPCatomicCmpSwap_8 : 369 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def PPCatomicCmpSwap_16 : 372 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 375 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 376def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 377 [SDNPHasChain, SDNPMayStore]>; 378 379// Instructions to set/unset CR bit 6 for SVR4 vararg calls 380def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 381 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 382def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 383 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 384 385// Instructions to support dynamic alloca. 386def SDTDynOp : SDTypeProfile<1, 2, []>; 387def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 388def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 389def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 390def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 391 392// PC Relative Specific Nodes 393def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 394def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 395 SDTIntUnaryOp, []>; 396def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 397 SDTIntUnaryOp, []>; 398 399//===----------------------------------------------------------------------===// 400// PowerPC specific transformation functions and pattern fragments. 401// 402 403// A floating point immediate that is not a positive zero and can be converted 404// to a single precision floating point non-denormal immediate without loss of 405// information. 406def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 407 APFloat APFloatOfN = N->getValueAPF(); 408 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 409}]>; 410 411// Convert the floating point immediate into a 32 bit floating point immediate 412// and get a i32 with the resulting bits. 413def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 414 APFloat APFloatOfN = N->getValueAPF(); 415 convertToNonDenormSingle(APFloatOfN); 416 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 417 SDLoc(N), MVT::i32); 418}]>; 419 420// Check if the value can be converted to be single precision immediate, which 421// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 422// precision before exploiting with XXSPLTI32DX. 423def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 424 APFloat APFloatOfN = N->getValueAPF(); 425 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 426}]>; 427 428// Get the Hi bits of a 64 bit immediate. 429def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 430 APFloat APFloatOfN = N->getValueAPF(); 431 bool Unused; 432 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 433 &Unused); 434 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 435 0xFFFFFFFF00000000LL) >> 32); 436 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 437}]>; 438 439// Get the Lo bits of a 64 bit immediate. 440def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 441 APFloat APFloatOfN = N->getValueAPF(); 442 bool Unused; 443 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 444 &Unused); 445 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 446 0xFFFFFFFF); 447 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 448}]>; 449 450def imm34 : PatLeaf<(imm), [{ 451 return isInt<34>(N->getSExtValue()); 452}]>; 453 454def getImmAs64BitInt : SDNodeXForm<imm, [{ 455 return getI64Imm(N->getSExtValue(), SDLoc(N)); 456}]>; 457 458def SHL32 : SDNodeXForm<imm, [{ 459 // Transformation function: 31 - imm 460 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 461}]>; 462 463def SRL32 : SDNodeXForm<imm, [{ 464 // Transformation function: 32 - imm 465 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 466 : getI32Imm(0, SDLoc(N)); 467}]>; 468 469def LO16 : SDNodeXForm<imm, [{ 470 // Transformation function: get the low 16 bits. 471 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 472}]>; 473 474def HI16 : SDNodeXForm<imm, [{ 475 // Transformation function: shift the immediate value down into the low bits. 476 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 477}]>; 478 479def HA16 : SDNodeXForm<imm, [{ 480 // Transformation function: shift the immediate value down into the low bits. 481 long Val = N->getZExtValue(); 482 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 483}]>; 484def MB : SDNodeXForm<imm, [{ 485 // Transformation function: get the start bit of a mask 486 unsigned mb = 0, me; 487 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 488 return getI32Imm(mb, SDLoc(N)); 489}]>; 490 491def ME : SDNodeXForm<imm, [{ 492 // Transformation function: get the end bit of a mask 493 unsigned mb, me = 0; 494 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 495 return getI32Imm(me, SDLoc(N)); 496}]>; 497def maskimm32 : PatLeaf<(imm), [{ 498 // maskImm predicate - True if immediate is a run of ones. 499 unsigned mb, me; 500 if (N->getValueType(0) == MVT::i32) 501 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 502 else 503 return false; 504}]>; 505 506def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 507 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 508 // sign extended field. Used by instructions like 'addi'. 509 return (int32_t)Imm == (short)Imm; 510}]>; 511def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 512 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 513 // sign extended field. Used by instructions like 'addi'. 514 return (int64_t)Imm == (short)Imm; 515}]>; 516def immZExt16 : PatLeaf<(imm), [{ 517 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 518 // field. Used by instructions like 'ori'. 519 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 520}], LO16>; 521def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 522 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 523}]>; 524def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 525def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 526 527// imm16Shifted* - These match immediates where the low 16-bits are zero. There 528// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 529// identical in 32-bit mode, but in 64-bit mode, they return true if the 530// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 531// clear). 532def imm16ShiftedZExt : PatLeaf<(imm), [{ 533 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 534 // immediate are set. Used by instructions like 'xoris'. 535 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 536}], HI16>; 537 538def imm16ShiftedSExt : PatLeaf<(imm), [{ 539 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 540 // immediate are set. Used by instructions like 'addis'. Identical to 541 // imm16ShiftedZExt in 32-bit mode. 542 if (N->getZExtValue() & 0xFFFF) return false; 543 if (N->getValueType(0) == MVT::i32) 544 return true; 545 // For 64-bit, make sure it is sext right. 546 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 547}], HI16>; 548 549def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 550 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 551 // zero extended field. 552 return isUInt<32>(Imm); 553}]>; 554 555// This is a somewhat weaker condition than actually checking for 4-byte 556// alignment. It is simply checking that the displacement can be represented 557// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 558// instructions). 559// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 560// restricted memrix (4-aligned) constants are alignment sensitive. If these 561// offsets are hidden behind TOC entries than the values of the lower-order 562// bits cannot be checked directly. As a result, we need to also incorporate 563// an alignment check into the relevant patterns. 564 565def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 566 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 567}]>; 568def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 569 (store node:$val, node:$ptr), [{ 570 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 571}]>; 572def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 573 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 574}]>; 575def DSFormPreStore : PatFrag< 576 (ops node:$val, node:$base, node:$offset), 577 (pre_store node:$val, node:$base, node:$offset), [{ 578 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 579}]>; 580 581def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 582 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 583}]>; 584def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 585 (store node:$val, node:$ptr), [{ 586 return cast<StoreSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 587}]>; 588def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 589 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 590}]>; 591 592// This is a somewhat weaker condition than actually checking for 16-byte 593// alignment. It is simply checking that the displacement can be represented 594// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 595// instructions). 596def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 597 return isOffsetMultipleOf(N, 16); 598}]>; 599def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 600 (store node:$val, node:$ptr), [{ 601 return isOffsetMultipleOf(N, 16); 602}]>; 603def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 604 return !isOffsetMultipleOf(N, 16); 605}]>; 606def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 607 (store node:$val, node:$ptr), [{ 608 return !isOffsetMultipleOf(N, 16); 609}]>; 610 611// PatFrag for binary operation whose operands are both non-constant 612class BinOpWithoutSImm16Operand<SDNode opcode> : 613 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 614 int16_t Imm; 615 return !isIntS16Immediate(N->getOperand(0), Imm) 616 && !isIntS16Immediate(N->getOperand(1), Imm); 617}]>; 618 619def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 620def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 621 622//===----------------------------------------------------------------------===// 623// PowerPC Flag Definitions. 624 625class isPPC64 { bit PPC64 = 1; } 626class isRecordForm { bit RC = 1; } 627 628class RegConstraint<string C> { 629 string Constraints = C; 630} 631class NoEncode<string E> { 632 string DisableEncoding = E; 633} 634 635 636// Define PowerPC specific addressing mode. 637 638// d-form 639def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 640// ds-form 641def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 642// dq-form 643def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 644// 8LS:d-form 645def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 646 647// Below forms are all x-form addressing mode, use three different ones so we 648// can make a accurate check for x-form instructions in ISEL. 649// x-form addressing mode whose associated displacement form is D. 650def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 651// x-form addressing mode whose associated displacement form is DS. 652def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 653// x-form addressing mode whose associated displacement form is DQ. 654def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 655 656def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 657 658// The address in a single register. This is used with the SjLj 659// pseudo-instructions. 660def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 661 662/// This is just the offset part of iaddr, used for preinc. 663def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 664 665// Load and Store Instruction Selection addressing modes. 666def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 667def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 668def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 669def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 670def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 671def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; 672def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; 673 674//===----------------------------------------------------------------------===// 675// PowerPC Instruction Predicate Definitions. 676def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 677def In64BitMode : Predicate<"Subtarget->isPPC64()">; 678def IsBookE : Predicate<"Subtarget->isBookE()">; 679def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 680def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 681def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 682def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 683def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 684def IsE500 : Predicate<"Subtarget->isE500()">; 685def HasSPE : Predicate<"Subtarget->hasSPE()">; 686def HasICBT : Predicate<"Subtarget->hasICBT()">; 687def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 688def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 689def NoNaNsFPMath 690 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 691def NaNsFPMath 692 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 693def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 694def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 695def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 696def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 697def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 698def HasFPU : Predicate<"Subtarget->hasFPU()">; 699def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 700def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 701 702// AIX assembler may not be modern enough to support some extended mne. 703def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 704 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 705def IsAIX : Predicate<"Subtarget->isAIXABI()">; 706def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 707def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; 708 709//===----------------------------------------------------------------------===// 710// PowerPC Multiclass Definitions. 711 712multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 713 string asmbase, string asmstr, InstrItinClass itin, 714 list<dag> pattern> { 715 let BaseName = asmbase in { 716 def NAME : XForm_6<opcode, xo, OOL, IOL, 717 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 718 pattern>, RecFormRel; 719 let Defs = [CR0] in 720 def _rec : XForm_6<opcode, xo, OOL, IOL, 721 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 722 []>, isRecordForm, RecFormRel; 723 } 724} 725 726multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 727 string asmbase, string asmstr, InstrItinClass itin, 728 list<dag> pattern> { 729 let BaseName = asmbase in { 730 let Defs = [CARRY] in 731 def NAME : XForm_6<opcode, xo, OOL, IOL, 732 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 733 pattern>, RecFormRel; 734 let Defs = [CARRY, CR0] in 735 def _rec : XForm_6<opcode, xo, OOL, IOL, 736 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 737 []>, isRecordForm, RecFormRel; 738 } 739} 740 741multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 742 string asmbase, string asmstr, InstrItinClass itin, 743 list<dag> pattern> { 744 let BaseName = asmbase in { 745 let Defs = [CARRY] in 746 def NAME : XForm_10<opcode, xo, OOL, IOL, 747 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 748 pattern>, RecFormRel; 749 let Defs = [CARRY, CR0] in 750 def _rec : XForm_10<opcode, xo, OOL, IOL, 751 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 752 []>, isRecordForm, RecFormRel; 753 } 754} 755 756multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 757 string asmbase, string asmstr, InstrItinClass itin, 758 list<dag> pattern> { 759 let BaseName = asmbase in { 760 def NAME : XForm_11<opcode, xo, OOL, IOL, 761 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 762 pattern>, RecFormRel; 763 let Defs = [CR0] in 764 def _rec : XForm_11<opcode, xo, OOL, IOL, 765 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 766 []>, isRecordForm, RecFormRel; 767 } 768} 769 770multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 771 string asmbase, string asmstr, InstrItinClass itin, 772 list<dag> pattern> { 773 let BaseName = asmbase in { 774 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 775 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 776 pattern>, RecFormRel; 777 let Defs = [CR0] in 778 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 779 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 780 []>, isRecordForm, RecFormRel; 781 } 782} 783 784// Multiclass for instructions which have a record overflow form as well 785// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 786multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 787 string asmbase, string asmstr, InstrItinClass itin, 788 list<dag> pattern> { 789 let BaseName = asmbase in { 790 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 791 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 792 pattern>, RecFormRel; 793 let Defs = [CR0] in 794 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 795 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 796 []>, isRecordForm, RecFormRel; 797 } 798 let BaseName = !strconcat(asmbase, "O") in { 799 let Defs = [XER] in 800 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 801 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 802 []>, RecFormRel; 803 let Defs = [XER, CR0] in 804 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 805 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 806 []>, isRecordForm, RecFormRel; 807 } 808} 809 810// Multiclass for instructions for which the non record form is not cracked 811// and the record form is cracked (i.e. divw, mullw, etc.) 812multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 813 string asmbase, string asmstr, InstrItinClass itin, 814 list<dag> pattern> { 815 let BaseName = asmbase in { 816 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 817 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 818 pattern>, RecFormRel; 819 let Defs = [CR0] in 820 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 821 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 822 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 823 PPC970_DGroup_Cracked; 824 } 825 let BaseName = !strconcat(asmbase, "O") in { 826 let Defs = [XER] in 827 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 828 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 829 []>, RecFormRel; 830 let Defs = [XER, CR0] in 831 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 832 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 833 []>, isRecordForm, RecFormRel; 834 } 835} 836 837multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 838 string asmbase, string asmstr, InstrItinClass itin, 839 list<dag> pattern> { 840 let BaseName = asmbase in { 841 let Defs = [CARRY] in 842 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 843 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 844 pattern>, RecFormRel; 845 let Defs = [CARRY, CR0] in 846 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 847 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 848 []>, isRecordForm, RecFormRel; 849 } 850 let BaseName = !strconcat(asmbase, "O") in { 851 let Defs = [CARRY, XER] in 852 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 853 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 854 []>, RecFormRel; 855 let Defs = [CARRY, XER, CR0] in 856 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 857 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 858 []>, isRecordForm, RecFormRel; 859 } 860} 861 862multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 863 string asmbase, string asmstr, InstrItinClass itin, 864 list<dag> pattern> { 865 let BaseName = asmbase in { 866 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 867 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 868 pattern>, RecFormRel; 869 let Defs = [CR0] in 870 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 871 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 872 []>, isRecordForm, RecFormRel; 873 } 874 let BaseName = !strconcat(asmbase, "O") in { 875 let Defs = [XER] in 876 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 877 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 878 []>, RecFormRel; 879 let Defs = [XER, CR0] in 880 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 881 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 882 []>, isRecordForm, RecFormRel; 883 } 884} 885 886multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 887 string asmbase, string asmstr, InstrItinClass itin, 888 list<dag> pattern> { 889 let BaseName = asmbase in { 890 let Defs = [CARRY] in 891 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 892 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 893 pattern>, RecFormRel; 894 let Defs = [CARRY, CR0] in 895 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 896 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 897 []>, isRecordForm, RecFormRel; 898 } 899 let BaseName = !strconcat(asmbase, "O") in { 900 let Defs = [CARRY, XER] in 901 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 902 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 903 []>, RecFormRel; 904 let Defs = [CARRY, XER, CR0] in 905 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 906 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 907 []>, isRecordForm, RecFormRel; 908 } 909} 910 911multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 912 string asmbase, string asmstr, InstrItinClass itin, 913 list<dag> pattern> { 914 let BaseName = asmbase in { 915 def NAME : MForm_2<opcode, OOL, IOL, 916 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 917 pattern>, RecFormRel; 918 let Defs = [CR0] in 919 def _rec : MForm_2<opcode, OOL, IOL, 920 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 921 []>, isRecordForm, RecFormRel; 922 } 923} 924 925multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 926 string asmbase, string asmstr, InstrItinClass itin, 927 list<dag> pattern> { 928 let BaseName = asmbase in { 929 def NAME : MDForm_1<opcode, xo, OOL, IOL, 930 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 931 pattern>, RecFormRel; 932 let Defs = [CR0] in 933 def _rec : MDForm_1<opcode, xo, OOL, IOL, 934 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 935 []>, isRecordForm, RecFormRel; 936 } 937} 938 939multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 940 string asmbase, string asmstr, InstrItinClass itin, 941 list<dag> pattern> { 942 let BaseName = asmbase in { 943 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 944 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 945 pattern>, RecFormRel; 946 let Defs = [CR0] in 947 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 948 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 949 []>, isRecordForm, RecFormRel; 950 } 951} 952 953multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 954 string asmbase, string asmstr, InstrItinClass itin, 955 list<dag> pattern> { 956 let BaseName = asmbase in { 957 let Defs = [CARRY] in 958 def NAME : XSForm_1<opcode, xo, OOL, IOL, 959 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 960 pattern>, RecFormRel; 961 let Defs = [CARRY, CR0] in 962 def _rec : XSForm_1<opcode, xo, OOL, IOL, 963 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 964 []>, isRecordForm, RecFormRel; 965 } 966} 967 968multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 969 string asmbase, string asmstr, InstrItinClass itin, 970 list<dag> pattern> { 971 let BaseName = asmbase in { 972 def NAME : XSForm_1<opcode, xo, OOL, IOL, 973 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 974 pattern>, RecFormRel; 975 let Defs = [CR0] in 976 def _rec : XSForm_1<opcode, xo, OOL, IOL, 977 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 978 []>, isRecordForm, RecFormRel; 979 } 980} 981 982multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 983 string asmbase, string asmstr, InstrItinClass itin, 984 list<dag> pattern> { 985 let BaseName = asmbase in { 986 def NAME : XForm_26<opcode, xo, OOL, IOL, 987 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 988 pattern>, RecFormRel; 989 let Defs = [CR1] in 990 def _rec : XForm_26<opcode, xo, OOL, IOL, 991 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 992 []>, isRecordForm, RecFormRel; 993 } 994} 995 996multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 997 string asmbase, string asmstr, InstrItinClass itin, 998 list<dag> pattern> { 999 let BaseName = asmbase in { 1000 def NAME : XForm_28<opcode, xo, OOL, IOL, 1001 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1002 pattern>, RecFormRel; 1003 let Defs = [CR1] in 1004 def _rec : XForm_28<opcode, xo, OOL, IOL, 1005 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1006 []>, isRecordForm, RecFormRel; 1007 } 1008} 1009 1010multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1011 string asmbase, string asmstr, InstrItinClass itin, 1012 list<dag> pattern> { 1013 let BaseName = asmbase in { 1014 def NAME : AForm_1<opcode, xo, OOL, IOL, 1015 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1016 pattern>, RecFormRel; 1017 let Defs = [CR1] in 1018 def _rec : AForm_1<opcode, xo, OOL, IOL, 1019 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1020 []>, isRecordForm, RecFormRel; 1021 } 1022} 1023 1024multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1025 string asmbase, string asmstr, InstrItinClass itin, 1026 list<dag> pattern> { 1027 let BaseName = asmbase in { 1028 def NAME : AForm_2<opcode, xo, OOL, IOL, 1029 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1030 pattern>, RecFormRel; 1031 let Defs = [CR1] in 1032 def _rec : AForm_2<opcode, xo, OOL, IOL, 1033 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1034 []>, isRecordForm, RecFormRel; 1035 } 1036} 1037 1038multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1039 string asmbase, string asmstr, InstrItinClass itin, 1040 list<dag> pattern> { 1041 let BaseName = asmbase in { 1042 def NAME : AForm_3<opcode, xo, OOL, IOL, 1043 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1044 pattern>, RecFormRel; 1045 let Defs = [CR1] in 1046 def _rec : AForm_3<opcode, xo, OOL, IOL, 1047 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1048 []>, isRecordForm, RecFormRel; 1049 } 1050} 1051 1052//===----------------------------------------------------------------------===// 1053// PowerPC Instruction Definitions. 1054 1055// Pseudo instructions: 1056 1057let hasCtrlDep = 1 in { 1058let Defs = [R1], Uses = [R1] in { 1059def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1060 "#ADJCALLSTACKDOWN $amt1 $amt2", 1061 [(callseq_start timm:$amt1, timm:$amt2)]>; 1062def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1063 "#ADJCALLSTACKUP $amt1 $amt2", 1064 [(callseq_end timm:$amt1, timm:$amt2)]>; 1065} 1066} // hasCtrlDep 1067 1068let Defs = [R1], Uses = [R1] in 1069def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1070 [(set i32:$result, 1071 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1072def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1073 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1074// Probed alloca to support stack clash protection. 1075let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1076def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1077 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1078 [(set i32:$result, 1079 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1080def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1081 gprc:$fp, gprc:$actual_negsize), 1082 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1083def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1084 gprc:$fp, gprc:$actual_negsize), 1085 (ins gprc:$negsize, memri:$fpsi), 1086 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1087 RegConstraint<"$actual_negsize = $negsize">; 1088def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1089 (ins i64imm:$stacksize), 1090 "#PROBED_STACKALLOC_32", []>; 1091} 1092 1093// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1094// instruction selection into a branch sequence. 1095let PPC970_Single = 1 in { 1096 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1097 // because either operand might become the first operand in an isel, and 1098 // that operand cannot be r0. 1099 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1100 gprc_nor0:$T, gprc_nor0:$F, 1101 i32imm:$BROPC), "#SELECT_CC_I4", 1102 []>; 1103 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1104 g8rc_nox0:$T, g8rc_nox0:$F, 1105 i32imm:$BROPC), "#SELECT_CC_I8", 1106 []>; 1107 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1108 i32imm:$BROPC), "#SELECT_CC_F4", 1109 []>; 1110 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1111 i32imm:$BROPC), "#SELECT_CC_F8", 1112 []>; 1113 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1114 i32imm:$BROPC), "#SELECT_CC_F16", 1115 []>; 1116 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1117 i32imm:$BROPC), "#SELECT_CC_VRRC", 1118 []>; 1119 1120 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1121 // register bit directly. 1122 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1123 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1124 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1125 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1126 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1127 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1128let Predicates = [HasFPU] in { 1129 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1130 f4rc:$T, f4rc:$F), "#SELECT_F4", 1131 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1132 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1133 f8rc:$T, f8rc:$F), "#SELECT_F8", 1134 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1135 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1136 vrrc:$T, vrrc:$F), "#SELECT_F16", 1137 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1138} 1139 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1140 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1141 [(set v4i32:$dst, 1142 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1143} 1144 1145// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1146// scavenge a register for it. 1147let mayStore = 1 in { 1148def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1149 "#SPILL_CR", []>; 1150def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1151 "#SPILL_CRBIT", []>; 1152} 1153 1154// RESTORE_CR - Indicate that we're restoring the CR register (previously 1155// spilled), so we'll need to scavenge a register for it. 1156let mayLoad = 1 in { 1157def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1158 "#RESTORE_CR", []>; 1159def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1160 "#RESTORE_CRBIT", []>; 1161} 1162 1163let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1164 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1165 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1166 [(retflag)]>, Requires<[In32BitMode]>; 1167 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1168 let isPredicable = 1 in 1169 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1170 []>; 1171 1172 let isCodeGenOnly = 1 in { 1173 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1174 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1175 []>; 1176 1177 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1178 "bcctr 12, $bi, 0", IIC_BrB, []>; 1179 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1180 "bcctr 4, $bi, 0", IIC_BrB, []>; 1181 } 1182 } 1183} 1184 1185// Set the float rounding mode. 1186let Uses = [RM], Defs = [RM] in { 1187def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1188 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1189 1190def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1191 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1192 1193def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1194 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1195} 1196 1197let Defs = [LR] in 1198 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1199 PPC970_Unit_BRU; 1200let Defs = [LR] in 1201 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1202 PPC970_Unit_BRU; 1203 1204let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1205 hasSideEffects = 0 in { 1206 let isBarrier = 1 in { 1207 let isPredicable = 1 in 1208 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1209 "b $dst", IIC_BrB, 1210 [(br bb:$dst)]>; 1211 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1212 "ba $dst", IIC_BrB, []>; 1213 } 1214 1215 // BCC represents an arbitrary conditional branch on a predicate. 1216 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1217 // a two-value operand where a dag node expects two operands. :( 1218 let isCodeGenOnly = 1 in { 1219 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1220 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1221 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1222 def BCC : BCC_class; 1223 1224 // The same as BCC, except that it's not a terminator. Used for introducing 1225 // control flow dependency without creating new blocks. 1226 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1227 1228 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1229 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1230 1231 let isReturn = 1, Uses = [LR, RM] in 1232 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1233 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1234 } 1235 1236 let isCodeGenOnly = 1 in { 1237 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1238 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1239 "bc 12, $bi, $dst">; 1240 1241 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1242 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1243 "bc 4, $bi, $dst">; 1244 1245 let isReturn = 1, Uses = [LR, RM] in { 1246 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1247 "bclr 12, $bi, 0", IIC_BrB, []>; 1248 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1249 "bclr 4, $bi, 0", IIC_BrB, []>; 1250 } 1251 } 1252 1253 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1254 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1255 "bdzlr", IIC_BrB, []>; 1256 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1257 "bdnzlr", IIC_BrB, []>; 1258 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1259 "bdzlr+", IIC_BrB, []>; 1260 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1261 "bdnzlr+", IIC_BrB, []>; 1262 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1263 "bdzlr-", IIC_BrB, []>; 1264 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1265 "bdnzlr-", IIC_BrB, []>; 1266 } 1267 1268 let Defs = [CTR], Uses = [CTR] in { 1269 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1270 "bdz $dst">; 1271 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1272 "bdnz $dst">; 1273 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1274 "bdza $dst">; 1275 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1276 "bdnza $dst">; 1277 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1278 "bdz+ $dst">; 1279 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1280 "bdnz+ $dst">; 1281 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1282 "bdza+ $dst">; 1283 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1284 "bdnza+ $dst">; 1285 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1286 "bdz- $dst">; 1287 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1288 "bdnz- $dst">; 1289 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1290 "bdza- $dst">; 1291 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1292 "bdnza- $dst">; 1293 } 1294} 1295 1296// The unconditional BCL used by the SjLj setjmp code. 1297let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1298 hasSideEffects = 0 in { 1299 let Defs = [LR], Uses = [RM] in { 1300 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1301 "bcl 20, 31, $dst">; 1302 } 1303} 1304 1305let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1306 // Convenient aliases for call instructions 1307 let Uses = [RM] in { 1308 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1309 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1310 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1311 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1312 1313 let isCodeGenOnly = 1 in { 1314 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1315 "bl $func", IIC_BrB, []>; 1316 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1317 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1318 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1319 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1320 1321 def BCL : BForm_4<16, 12, 0, 1, (outs), 1322 (ins crbitrc:$bi, condbrtarget:$dst), 1323 "bcl 12, $bi, $dst">; 1324 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1325 (ins crbitrc:$bi, condbrtarget:$dst), 1326 "bcl 4, $bi, $dst">; 1327 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1328 (outs), (ins calltarget:$func), 1329 "bl $func\n\tnop", IIC_BrB, []>; 1330 } 1331 } 1332 let Uses = [CTR, RM] in { 1333 let isPredicable = 1 in 1334 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1335 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1336 Requires<[In32BitMode]>; 1337 1338 let isCodeGenOnly = 1 in { 1339 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1340 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1341 []>; 1342 1343 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1344 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1345 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1346 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1347 } 1348 } 1349 let Uses = [LR, RM] in { 1350 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1351 "blrl", IIC_BrB, []>; 1352 1353 let isCodeGenOnly = 1 in { 1354 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1355 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1356 []>; 1357 1358 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1359 "bclrl 12, $bi, 0", IIC_BrB, []>; 1360 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1361 "bclrl 4, $bi, 0", IIC_BrB, []>; 1362 } 1363 } 1364 let Defs = [CTR], Uses = [CTR, RM] in { 1365 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1366 "bdzl $dst">; 1367 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1368 "bdnzl $dst">; 1369 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1370 "bdzla $dst">; 1371 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1372 "bdnzla $dst">; 1373 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1374 "bdzl+ $dst">; 1375 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1376 "bdnzl+ $dst">; 1377 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1378 "bdzla+ $dst">; 1379 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1380 "bdnzla+ $dst">; 1381 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1382 "bdzl- $dst">; 1383 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1384 "bdnzl- $dst">; 1385 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1386 "bdzla- $dst">; 1387 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1388 "bdnzla- $dst">; 1389 } 1390 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1391 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1392 "bdzlrl", IIC_BrB, []>; 1393 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1394 "bdnzlrl", IIC_BrB, []>; 1395 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1396 "bdzlrl+", IIC_BrB, []>; 1397 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1398 "bdnzlrl+", IIC_BrB, []>; 1399 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1400 "bdzlrl-", IIC_BrB, []>; 1401 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1402 "bdnzlrl-", IIC_BrB, []>; 1403 } 1404} 1405 1406let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1407 // Convenient aliases for call instructions 1408 let Uses = [RM] in { 1409 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1410 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1411 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1412 "bla $func", IIC_BrB, [(PPCcall_rm (i32 imm:$func))]>; 1413 1414 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1415 (outs), (ins calltarget:$func), 1416 "bl $func\n\tnop", IIC_BrB, []>; 1417 } 1418 let Uses = [CTR, RM] in { 1419 let isPredicable = 1 in 1420 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1421 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1422 Requires<[In32BitMode]>; 1423 } 1424} 1425 1426let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1427def TCRETURNdi :PPCEmitTimePseudo< (outs), 1428 (ins calltarget:$dst, i32imm:$offset), 1429 "#TC_RETURNd $dst $offset", 1430 []>; 1431 1432 1433let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1434def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1435 "#TC_RETURNa $func $offset", 1436 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1437 1438let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1439def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1440 "#TC_RETURNr $dst $offset", 1441 []>; 1442 1443let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1444 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1445 def BCTRL_LWZinto_toc: 1446 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1447 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1448 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1449 1450} 1451 1452let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1453 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1454 def BCTRL_LWZinto_toc_RM: 1455 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1456 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1457 [(PPCbctrl_load_toc_rm iaddr:$src)]>, Requires<[In32BitMode]>; 1458 1459} 1460 1461let isCodeGenOnly = 1, hasSideEffects = 0 in { 1462 1463let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1464 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1465def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1466 []>, Requires<[In32BitMode]>; 1467 1468let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1469 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1470def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1471 "b $dst", IIC_BrB, 1472 []>; 1473 1474let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1475 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1476def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1477 "ba $dst", IIC_BrB, 1478 []>; 1479 1480} 1481 1482// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1483// is not. 1484let hasSideEffects = 1 in { 1485 let Defs = [CTR] in 1486 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1487 "#EH_SJLJ_SETJMP32", 1488 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1489 Requires<[In32BitMode]>; 1490} 1491 1492let hasSideEffects = 1, isBarrier = 1 in { 1493 let isTerminator = 1 in 1494 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1495 "#EH_SJLJ_LONGJMP32", 1496 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1497 Requires<[In32BitMode]>; 1498} 1499 1500// This pseudo is never removed from the function, as it serves as 1501// a terminator. Size is set to 0 to prevent the builtin assembler 1502// from emitting it. 1503let isBranch = 1, isTerminator = 1, Size = 0 in { 1504 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1505 "#EH_SjLj_Setup\t$dst", []>; 1506} 1507 1508// System call. 1509let PPC970_Unit = 7 in { 1510 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1511 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1512} 1513 1514// Branch history rolling buffer. 1515def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1516 [(PPCclrbhrb)]>, 1517 PPC970_DGroup_Single; 1518// The $dmy argument used for MFBHRBE is not needed; however, including 1519// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1520// interferes with necessary special handling (see PPCFastISel.cpp). 1521def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1522 (ins u10imm:$imm, u10imm:$dmy), 1523 "mfbhrbe $rD, $imm", IIC_BrB, 1524 [(set i32:$rD, 1525 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1526 PPC970_DGroup_First; 1527 1528def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1529 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1530 PPC970_DGroup_Single; 1531 1532def : InstAlias<"rfebb", (RFEBB 1)>; 1533 1534// DCB* instructions. 1535def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1536 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1537 PPC970_DGroup_Single; 1538def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1539 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1540 PPC970_DGroup_Single; 1541def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1542 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1543 PPC970_DGroup_Single; 1544def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1545 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1546 PPC970_DGroup_Single; 1547def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1548 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1549 PPC970_DGroup_Single; 1550 1551def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), 1552 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 1553 PPC970_DGroup_Single; 1554 1555let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1556def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1557 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1558 PPC970_DGroup_Single; 1559def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1560 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1561 PPC970_DGroup_Single; 1562} // hasSideEffects = 0 1563 1564def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 1565 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 1566def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 1567 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1568def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1569 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1570def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 1571 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1572 1573def : Pat<(int_ppc_dcbt xoaddr:$dst), 1574 (DCBT 0, xoaddr:$dst)>; 1575def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1576 (DCBTST 0, xoaddr:$dst)>; 1577def : Pat<(int_ppc_dcbf xoaddr:$dst), 1578 (DCBF 0, xoaddr:$dst)>; 1579def : Pat<(int_ppc_icbt xoaddr:$dst), 1580 (ICBT 0, xoaddr:$dst)>; 1581 1582def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1583 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1584def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1585 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1586def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1587 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1588 1589def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1590 (DCBT i32:$TH, xoaddr:$dst)>; 1591def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1592 (DCBTST i32:$TH, xoaddr:$dst)>; 1593 1594// Atomic operations 1595// FIXME: some of these might be used with constant operands. This will result 1596// in constant materialization instructions that may be redundant. We currently 1597// clean this up in PPCMIPeephole with calls to 1598// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1599// in the first place. 1600let Defs = [CR0] in { 1601 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1602 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1603 [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; 1604 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1605 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1606 [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; 1607 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1608 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1609 [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; 1610 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1611 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1612 [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; 1613 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1614 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1615 [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; 1616 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1617 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1618 [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; 1619 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1620 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1621 [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; 1622 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1623 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1624 [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; 1625 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1626 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1627 [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; 1628 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1629 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1630 [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; 1631 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1632 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1633 [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; 1634 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1635 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1636 [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; 1637 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1638 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1639 [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; 1640 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1641 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1642 [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; 1643 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1644 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1645 [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; 1646 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1647 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1648 [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; 1649 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1650 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1651 [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; 1652 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1653 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1654 [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; 1655 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1656 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1657 [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; 1658 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1659 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1660 [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; 1661 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1662 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1663 [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; 1664 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1665 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1666 [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; 1667 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1668 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1669 [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; 1670 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1671 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1672 [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; 1673 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1674 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1675 [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; 1676 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1677 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1678 [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; 1679 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1680 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1681 [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; 1682 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1683 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1684 [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; 1685 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1686 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1687 [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; 1688 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1689 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1690 [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; 1691 1692 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1693 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1694 [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1695 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1696 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1697 [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1698 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1699 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1700 [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1701 1702 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1703 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1704 [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; 1705 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1706 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1707 [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; 1708 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1709 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1710 [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; 1711} 1712 1713def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1714 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1715def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1716 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1717 1718// Instructions to support atomic operations 1719let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1720def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1721 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1722 Requires<[HasPartwordAtomics]>; 1723 1724def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1725 "lharx $rD, $src", IIC_LdStLWARX, []>, 1726 Requires<[HasPartwordAtomics]>; 1727 1728def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1729 "lwarx $rD, $src", IIC_LdStLWARX, []>; 1730 1731// Instructions to support lock versions of atomics 1732// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1733def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1734 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1735 Requires<[HasPartwordAtomics]>; 1736 1737def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1738 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1739 Requires<[HasPartwordAtomics]>; 1740 1741def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1742 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 1743 1744// The atomic instructions use the destination register as well as the next one 1745// or two registers in order (modulo 31). 1746let hasExtraSrcRegAllocReq = 1 in 1747def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 1748 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 1749 Requires<[IsISA3_0]>; 1750} 1751 1752let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1753def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 1754 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 1755 isRecordForm, Requires<[HasPartwordAtomics]>; 1756 1757def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 1758 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 1759 isRecordForm, Requires<[HasPartwordAtomics]>; 1760 1761def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1762 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 1763} 1764 1765let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1766def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 1767 "stwat $rS, $rA, $FC", IIC_LdStStore>, 1768 Requires<[IsISA3_0]>; 1769 1770let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1771def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1772 1773def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1774 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1775def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1776 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1777def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1778 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1779def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1780 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1781 1782def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 1783 "popcntb $rA, $rS", IIC_IntGeneral, 1784 [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>; 1785 1786//===----------------------------------------------------------------------===// 1787// PPC32 Load Instructions. 1788// 1789 1790// Unindexed (r+i) Loads. 1791let PPC970_Unit = 2 in { 1792def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1793 "lbz $rD, $src", IIC_LdStLoad, 1794 [(set i32:$rD, (zextloadi8 DForm:$src))]>; 1795def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1796 "lha $rD, $src", IIC_LdStLHA, 1797 [(set i32:$rD, (sextloadi16 DForm:$src))]>, 1798 PPC970_DGroup_Cracked; 1799def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1800 "lhz $rD, $src", IIC_LdStLoad, 1801 [(set i32:$rD, (zextloadi16 DForm:$src))]>; 1802def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1803 "lwz $rD, $src", IIC_LdStLoad, 1804 [(set i32:$rD, (load DForm:$src))]>; 1805 1806let Predicates = [HasFPU] in { 1807def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1808 "lfs $rD, $src", IIC_LdStLFD, 1809 [(set f32:$rD, (load DForm:$src))]>; 1810def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1811 "lfd $rD, $src", IIC_LdStLFD, 1812 [(set f64:$rD, (load DForm:$src))]>; 1813} 1814 1815 1816// Unindexed (r+i) Loads with Update (preinc). 1817let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1818def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1819 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1820 []>, RegConstraint<"$addr.reg = $ea_result">, 1821 NoEncode<"$ea_result">; 1822 1823def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1824 "lhau $rD, $addr", IIC_LdStLHAU, 1825 []>, RegConstraint<"$addr.reg = $ea_result">, 1826 NoEncode<"$ea_result">; 1827 1828def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1829 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1830 []>, RegConstraint<"$addr.reg = $ea_result">, 1831 NoEncode<"$ea_result">; 1832 1833def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1834 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1835 []>, RegConstraint<"$addr.reg = $ea_result">, 1836 NoEncode<"$ea_result">; 1837 1838let Predicates = [HasFPU] in { 1839def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1840 "lfsu $rD, $addr", IIC_LdStLFDU, 1841 []>, RegConstraint<"$addr.reg = $ea_result">, 1842 NoEncode<"$ea_result">; 1843 1844def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1845 "lfdu $rD, $addr", IIC_LdStLFDU, 1846 []>, RegConstraint<"$addr.reg = $ea_result">, 1847 NoEncode<"$ea_result">; 1848} 1849 1850 1851// Indexed (r+r) Loads with Update (preinc). 1852def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1853 (ins memrr:$addr), 1854 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1855 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1856 NoEncode<"$ea_result">; 1857 1858def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1859 (ins memrr:$addr), 1860 "lhaux $rD, $addr", IIC_LdStLHAUX, 1861 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1862 NoEncode<"$ea_result">; 1863 1864def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1865 (ins memrr:$addr), 1866 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1867 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1868 NoEncode<"$ea_result">; 1869 1870def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1871 (ins memrr:$addr), 1872 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1873 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1874 NoEncode<"$ea_result">; 1875 1876let Predicates = [HasFPU] in { 1877def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1878 (ins memrr:$addr), 1879 "lfsux $rD, $addr", IIC_LdStLFDUX, 1880 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1881 NoEncode<"$ea_result">; 1882 1883def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1884 (ins memrr:$addr), 1885 "lfdux $rD, $addr", IIC_LdStLFDUX, 1886 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1887 NoEncode<"$ea_result">; 1888} 1889} 1890} 1891 1892// Indexed (r+r) Loads. 1893// 1894let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 1895def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 1896 "lbzx $rD, $src", IIC_LdStLoad, 1897 [(set i32:$rD, (zextloadi8 XForm:$src))]>; 1898def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 1899 "lhax $rD, $src", IIC_LdStLHA, 1900 [(set i32:$rD, (sextloadi16 XForm:$src))]>, 1901 PPC970_DGroup_Cracked; 1902def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 1903 "lhzx $rD, $src", IIC_LdStLoad, 1904 [(set i32:$rD, (zextloadi16 XForm:$src))]>; 1905def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 1906 "lwzx $rD, $src", IIC_LdStLoad, 1907 [(set i32:$rD, (load XForm:$src))]>; 1908def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 1909 "lhbrx $rD, $src", IIC_LdStLoad, 1910 [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>; 1911def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 1912 "lwbrx $rD, $src", IIC_LdStLoad, 1913 [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>; 1914 1915let Predicates = [HasFPU] in { 1916def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1917 "lfsx $frD, $src", IIC_LdStLFD, 1918 [(set f32:$frD, (load XForm:$src))]>; 1919def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1920 "lfdx $frD, $src", IIC_LdStLFD, 1921 [(set f64:$frD, (load XForm:$src))]>; 1922 1923def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1924 "lfiwax $frD, $src", IIC_LdStLFD, 1925 [(set f64:$frD, (PPClfiwax ForceXForm:$src))]>; 1926def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1927 "lfiwzx $frD, $src", IIC_LdStLFD, 1928 [(set f64:$frD, (PPClfiwzx ForceXForm:$src))]>; 1929} 1930} 1931 1932// Load Multiple 1933let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 1934def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1935 "lmw $rD, $src", IIC_LdStLMW, []>; 1936 1937//===----------------------------------------------------------------------===// 1938// PPC32 Store Instructions. 1939// 1940 1941// Unindexed (r+i) Stores. 1942let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1943def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 1944 "stb $rS, $dst", IIC_LdStStore, 1945 [(truncstorei8 i32:$rS, DForm:$dst)]>; 1946def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 1947 "sth $rS, $dst", IIC_LdStStore, 1948 [(truncstorei16 i32:$rS, DForm:$dst)]>; 1949def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 1950 "stw $rS, $dst", IIC_LdStStore, 1951 [(store i32:$rS, DForm:$dst)]>; 1952let Predicates = [HasFPU] in { 1953def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1954 "stfs $rS, $dst", IIC_LdStSTFD, 1955 [(store f32:$rS, DForm:$dst)]>; 1956def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1957 "stfd $rS, $dst", IIC_LdStSTFD, 1958 [(store f64:$rS, DForm:$dst)]>; 1959} 1960} 1961 1962// Unindexed (r+i) Stores with Update (preinc). 1963let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1964def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1965 "stbu $rS, $dst", IIC_LdStSTU, []>, 1966 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1967def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1968 "sthu $rS, $dst", IIC_LdStSTU, []>, 1969 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1970def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1971 "stwu $rS, $dst", IIC_LdStSTU, []>, 1972 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1973let Predicates = [HasFPU] in { 1974def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1975 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 1976 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1977def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1978 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 1979 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1980} 1981} 1982 1983// Patterns to match the pre-inc stores. We can't put the patterns on 1984// the instruction definitions directly as ISel wants the address base 1985// and offset to be separate operands, not a single complex operand. 1986def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1987 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1988def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1989 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1990def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1991 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1992def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1993 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1994def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1995 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1996 1997// Indexed (r+r) Stores. 1998let PPC970_Unit = 2 in { 1999def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 2000 "stbx $rS, $dst", IIC_LdStStore, 2001 [(truncstorei8 i32:$rS, XForm:$dst)]>, 2002 PPC970_DGroup_Cracked; 2003def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2004 "sthx $rS, $dst", IIC_LdStStore, 2005 [(truncstorei16 i32:$rS, XForm:$dst)]>, 2006 PPC970_DGroup_Cracked; 2007def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2008 "stwx $rS, $dst", IIC_LdStStore, 2009 [(store i32:$rS, XForm:$dst)]>, 2010 PPC970_DGroup_Cracked; 2011 2012def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2013 "sthbrx $rS, $dst", IIC_LdStStore, 2014 [(PPCstbrx i32:$rS, ForceXForm:$dst, i16)]>, 2015 PPC970_DGroup_Cracked; 2016def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2017 "stwbrx $rS, $dst", IIC_LdStStore, 2018 [(PPCstbrx i32:$rS, ForceXForm:$dst, i32)]>, 2019 PPC970_DGroup_Cracked; 2020 2021let Predicates = [HasFPU] in { 2022def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2023 "stfiwx $frS, $dst", IIC_LdStSTFD, 2024 [(PPCstfiwx f64:$frS, ForceXForm:$dst)]>; 2025 2026def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2027 "stfsx $frS, $dst", IIC_LdStSTFD, 2028 [(store f32:$frS, XForm:$dst)]>; 2029def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2030 "stfdx $frS, $dst", IIC_LdStSTFD, 2031 [(store f64:$frS, XForm:$dst)]>; 2032} 2033} 2034 2035// Indexed (r+r) Stores with Update (preinc). 2036let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2037def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2038 (ins gprc:$rS, memrr:$dst), 2039 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2040 RegConstraint<"$dst.ptrreg = $ea_res">, 2041 NoEncode<"$ea_res">, 2042 PPC970_DGroup_Cracked; 2043def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2044 (ins gprc:$rS, memrr:$dst), 2045 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2046 RegConstraint<"$dst.ptrreg = $ea_res">, 2047 NoEncode<"$ea_res">, 2048 PPC970_DGroup_Cracked; 2049def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2050 (ins gprc:$rS, memrr:$dst), 2051 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2052 RegConstraint<"$dst.ptrreg = $ea_res">, 2053 NoEncode<"$ea_res">, 2054 PPC970_DGroup_Cracked; 2055let Predicates = [HasFPU] in { 2056def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2057 (ins f4rc:$rS, memrr:$dst), 2058 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2059 RegConstraint<"$dst.ptrreg = $ea_res">, 2060 NoEncode<"$ea_res">, 2061 PPC970_DGroup_Cracked; 2062def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2063 (ins f8rc:$rS, memrr:$dst), 2064 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2065 RegConstraint<"$dst.ptrreg = $ea_res">, 2066 NoEncode<"$ea_res">, 2067 PPC970_DGroup_Cracked; 2068} 2069} 2070 2071// Patterns to match the pre-inc stores. We can't put the patterns on 2072// the instruction definitions directly as ISel wants the address base 2073// and offset to be separate operands, not a single complex operand. 2074def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2075 (STBUX $rS, $ptrreg, $ptroff)>; 2076def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2077 (STHUX $rS, $ptrreg, $ptroff)>; 2078def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2079 (STWUX $rS, $ptrreg, $ptroff)>; 2080let Predicates = [HasFPU] in { 2081def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2082 (STFSUX $rS, $ptrreg, $ptroff)>; 2083def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2084 (STFDUX $rS, $ptrreg, $ptroff)>; 2085} 2086 2087// Store Multiple 2088let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2089def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2090 "stmw $rS, $dst", IIC_LdStLMW, []>; 2091 2092def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2093 "sync $L", IIC_LdStSync, []>; 2094 2095let isCodeGenOnly = 1 in { 2096 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2097 "msync", IIC_LdStSync, []> { 2098 let L = 0; 2099 } 2100} 2101 2102// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2103def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2104 "eieio", IIC_LdStLoad, []>; 2105 2106def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2107 [(int_ppc_eieio)]>; 2108 2109def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2110def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2111def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2112def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2113def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2114def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2115def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2116def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2117def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2118def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2119 2120//===----------------------------------------------------------------------===// 2121// PPC32 Arithmetic Instructions. 2122// 2123 2124let PPC970_Unit = 1 in { // FXU Operations. 2125def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2126 "addi $rD, $rA, $imm", IIC_IntSimple, 2127 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2128let BaseName = "addic" in { 2129let Defs = [CARRY] in 2130def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2131 "addic $rD, $rA, $imm", IIC_IntGeneral, 2132 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2133 RecFormRel, PPC970_DGroup_Cracked; 2134let Defs = [CARRY, CR0] in 2135def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2136 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2137 []>, isRecordForm, RecFormRel; 2138} 2139def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2140 "addis $rD, $rA, $imm", IIC_IntSimple, 2141 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2142let isCodeGenOnly = 1 in 2143def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2144 "la $rD, $sym($rA)", IIC_IntGeneral, 2145 [(set i32:$rD, (add i32:$rA, 2146 (PPClo tglobaladdr:$sym, 0)))]>; 2147def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2148 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2149 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2150let Defs = [CARRY] in 2151def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2152 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2153 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2154 2155let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2156 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2157 "li $rD, $imm", IIC_IntSimple, 2158 [(set i32:$rD, imm32SExt16:$imm)]>; 2159 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2160 "lis $rD, $imm", IIC_IntSimple, 2161 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2162} 2163} 2164 2165def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2166def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2167 2168let PPC970_Unit = 1 in { // FXU Operations. 2169let Defs = [CR0] in { 2170def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2171 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2172 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2173 isRecordForm; 2174def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2175 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2176 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2177 isRecordForm; 2178} 2179def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2180 "ori $dst, $src1, $src2", IIC_IntSimple, 2181 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2182def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2183 "oris $dst, $src1, $src2", IIC_IntSimple, 2184 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2185def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2186 "xori $dst, $src1, $src2", IIC_IntSimple, 2187 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2188def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2189 "xoris $dst, $src1, $src2", IIC_IntSimple, 2190 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2191 2192def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2193 []>; 2194let isCodeGenOnly = 1 in { 2195// The POWER6 and POWER7 have special group-terminating nops. 2196def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2197 "ori 1, 1, 0", IIC_IntSimple, []>; 2198def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2199 "ori 2, 2, 0", IIC_IntSimple, []>; 2200} 2201 2202let isCompare = 1, hasSideEffects = 0 in { 2203 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2204 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2205 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2206 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2207 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2208 (ins u1imm:$L, gprc:$rA, gprc:$rB), 2209 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2210 Requires<[IsISA3_0]>; 2211} 2212} 2213 2214let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2215let isCommutable = 1 in { 2216defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2217 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2218 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2219defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2220 "and", "$rA, $rS, $rB", IIC_IntSimple, 2221 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2222} // isCommutable 2223defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2224 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2225 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2226let isCommutable = 1 in { 2227defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2228 "or", "$rA, $rS, $rB", IIC_IntSimple, 2229 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2230defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2231 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2232 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2233} // isCommutable 2234defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2235 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2236 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2237let isCommutable = 1 in { 2238defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2239 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2240 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2241defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2242 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2243 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2244} // isCommutable 2245defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2246 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2247 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2248defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2249 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2250 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2251defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2252 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2253 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2254} 2255 2256def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2257def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2258 2259def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2260def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2261 2262def : InstAlias<"nop", (ORI R0, R0, 0)>; 2263 2264let PPC970_Unit = 1 in { // FXU Operations. 2265let hasSideEffects = 0 in { 2266defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2267 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2268 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2269defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2270 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2271 [(set i32:$rA, (ctlz i32:$rS))]>; 2272defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2273 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2274 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2275defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2276 "extsb", "$rA, $rS", IIC_IntSimple, 2277 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2278defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2279 "extsh", "$rA, $rS", IIC_IntSimple, 2280 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2281 2282let isCommutable = 1 in 2283def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2284 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2285 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2286} 2287let isCompare = 1, hasSideEffects = 0 in { 2288 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2289 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2290 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2291 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2292} 2293} 2294let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2295let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2296 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2297 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2298 def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2299 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2300 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2301 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2302 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2303 def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2304 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2305 } 2306} 2307 2308def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2309 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2310def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2311 "ftsqrt $crD, $fB", IIC_FPCompare, 2312 [(set i32:$crD, (PPCftsqrt f64:$fB))]>; 2313 2314let mayRaiseFPException = 1, hasSideEffects = 0 in { 2315 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2316 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2317 "frin", "$frD, $frB", IIC_FPGeneral, 2318 [(set f64:$frD, (any_fround f64:$frB))]>; 2319 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2320 "frin", "$frD, $frB", IIC_FPGeneral, 2321 [(set f32:$frD, (any_fround f32:$frB))]>; 2322 2323 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2324 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2325 "frip", "$frD, $frB", IIC_FPGeneral, 2326 [(set f64:$frD, (any_fceil f64:$frB))]>; 2327 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2328 "frip", "$frD, $frB", IIC_FPGeneral, 2329 [(set f32:$frD, (any_fceil f32:$frB))]>; 2330 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2331 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2332 "friz", "$frD, $frB", IIC_FPGeneral, 2333 [(set f64:$frD, (any_ftrunc f64:$frB))]>; 2334 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2335 "friz", "$frD, $frB", IIC_FPGeneral, 2336 [(set f32:$frD, (any_ftrunc f32:$frB))]>; 2337 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2338 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2339 "frim", "$frD, $frB", IIC_FPGeneral, 2340 [(set f64:$frD, (any_ffloor f64:$frB))]>; 2341 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2342 "frim", "$frD, $frB", IIC_FPGeneral, 2343 [(set f32:$frD, (any_ffloor f32:$frB))]>; 2344} 2345 2346let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2347 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2348 "fctiw", "$frD, $frB", IIC_FPGeneral, 2349 []>; 2350 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2351 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2352 []>; 2353 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2354 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2355 [(set f64:$frD, (PPCany_fctiwz f64:$frB))]>; 2356 2357 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2358 "frsp", "$frD, $frB", IIC_FPGeneral, 2359 [(set f32:$frD, (any_fpround f64:$frB))]>; 2360 2361 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2362 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2363 [(set f64:$frD, (any_fsqrt f64:$frB))]>; 2364 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2365 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2366 [(set f32:$frD, (any_fsqrt f32:$frB))]>; 2367} 2368} 2369 2370def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2371 2372/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2373/// often coalesced away and we don't want the dispatch group builder to think 2374/// that they will fill slots (which could cause the load of a LSU reject to 2375/// sneak into a d-group with a store). 2376let hasSideEffects = 0, Predicates = [HasFPU] in 2377defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2378 "fmr", "$frD, $frB", IIC_FPGeneral, 2379 []>, // (set f32:$frD, f32:$frB) 2380 PPC970_Unit_Pseudo; 2381 2382let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2383// These are artificially split into two different forms, for 4/8 byte FP. 2384defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2385 "fabs", "$frD, $frB", IIC_FPGeneral, 2386 [(set f32:$frD, (fabs f32:$frB))]>; 2387let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2388defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2389 "fabs", "$frD, $frB", IIC_FPGeneral, 2390 [(set f64:$frD, (fabs f64:$frB))]>; 2391defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2392 "fnabs", "$frD, $frB", IIC_FPGeneral, 2393 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2394let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2395defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2396 "fnabs", "$frD, $frB", IIC_FPGeneral, 2397 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2398defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2399 "fneg", "$frD, $frB", IIC_FPGeneral, 2400 [(set f32:$frD, (fneg f32:$frB))]>; 2401let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2402defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2403 "fneg", "$frD, $frB", IIC_FPGeneral, 2404 [(set f64:$frD, (fneg f64:$frB))]>; 2405 2406defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2407 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2408 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2409let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2410defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2411 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2412 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2413 2414// Reciprocal estimates. 2415let mayRaiseFPException = 1 in { 2416defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2417 "fre", "$frD, $frB", IIC_FPGeneral, 2418 [(set f64:$frD, (PPCfre f64:$frB))]>; 2419defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2420 "fres", "$frD, $frB", IIC_FPGeneral, 2421 [(set f32:$frD, (PPCfre f32:$frB))]>; 2422defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2423 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2424 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2425defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2426 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2427 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2428} 2429} 2430 2431// XL-Form instructions. condition register logical ops. 2432// 2433let hasSideEffects = 0 in 2434def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2435 "mcrf $BF, $BFA", IIC_BrMCR>, 2436 PPC970_DGroup_First, PPC970_Unit_CRU; 2437 2438// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2439// condition-register logical instructions have preferred forms. Specifically, 2440// it is preferred that the bit specified by the BT field be in the same 2441// condition register as that specified by the bit BB. We might want to account 2442// for this via hinting the register allocator and anti-dep breakers, or we 2443// could constrain the register class to force this constraint and then loosen 2444// it during register allocation via convertToThreeAddress or some similar 2445// mechanism. 2446 2447let isCommutable = 1 in { 2448def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2449 (ins crbitrc:$CRA, crbitrc:$CRB), 2450 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2451 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2452 2453def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2454 (ins crbitrc:$CRA, crbitrc:$CRB), 2455 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2456 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2457 2458def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2459 (ins crbitrc:$CRA, crbitrc:$CRB), 2460 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2461 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2462 2463def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2464 (ins crbitrc:$CRA, crbitrc:$CRB), 2465 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2466 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2467 2468def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2469 (ins crbitrc:$CRA, crbitrc:$CRB), 2470 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2471 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2472 2473def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2474 (ins crbitrc:$CRA, crbitrc:$CRB), 2475 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2476 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2477} // isCommutable 2478 2479def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2480 (ins crbitrc:$CRA, crbitrc:$CRB), 2481 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2482 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2483 2484def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2485 (ins crbitrc:$CRA, crbitrc:$CRB), 2486 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2487 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2488 2489let isCodeGenOnly = 1 in { 2490let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2491def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2492 "creqv $dst, $dst, $dst", IIC_BrCR, 2493 [(set i1:$dst, 1)]>; 2494 2495def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2496 "crxor $dst, $dst, $dst", IIC_BrCR, 2497 [(set i1:$dst, 0)]>; 2498} 2499 2500let Defs = [CR1EQ], CRD = 6 in { 2501def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2502 "creqv 6, 6, 6", IIC_BrCR, 2503 [(PPCcr6set)]>; 2504 2505def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2506 "crxor 6, 6, 6", IIC_BrCR, 2507 [(PPCcr6unset)]>; 2508} 2509} 2510 2511// XFX-Form instructions. Instructions that deal with SPRs. 2512// 2513 2514def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2515 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2516def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2517 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2518 2519def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2520 "mftb $RT, $SPR", IIC_SprMFTB>; 2521 2522def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2523 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2524 2525def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2526 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 2527 2528 2529// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2530// on a 32-bit target. 2531let hasSideEffects = 1 in 2532def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2533 "#ReadTB", []>; 2534 2535let Uses = [CTR] in { 2536def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2537 "mfctr $rT", IIC_SprMFSPR>, 2538 PPC970_DGroup_First, PPC970_Unit_FXU; 2539} 2540let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2541def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2542 "mtctr $rS", IIC_SprMTSPR>, 2543 PPC970_DGroup_First, PPC970_Unit_FXU; 2544} 2545let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2546let Pattern = [(int_set_loop_iterations i32:$rS)] in 2547def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2548 "mtctr $rS", IIC_SprMTSPR>, 2549 PPC970_DGroup_First, PPC970_Unit_FXU; 2550} 2551 2552let hasSideEffects = 1, Defs = [CTR] in 2553def MTCTRPseudo : PPCEmitTimePseudo<(outs), (ins gprc:$rS), "#MTCTRPseudo", []>; 2554 2555let hasSideEffects = 1, Uses = [CTR], Defs = [CTR] in 2556def DecreaseCTRPseudo : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), 2557 "#DecreaseCTRPseudo", []>; 2558 2559let hasSideEffects = 0 in { 2560let Defs = [LR] in { 2561def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2562 "mtlr $rS", IIC_SprMTSPR>, 2563 PPC970_DGroup_First, PPC970_Unit_FXU; 2564} 2565let Uses = [LR] in { 2566def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2567 "mflr $rT", IIC_SprMFSPR>, 2568 PPC970_DGroup_First, PPC970_Unit_FXU; 2569} 2570} 2571 2572let hasSideEffects = 1 in { 2573 def MTUDSCR : XFXForm_7_ext<31, 467, 3, (outs), (ins gprc:$rX), 2574 "mtspr 3, $rX", IIC_SprMTSPR>, 2575 PPC970_DGroup_Single, PPC970_Unit_FXU; 2576 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$rX), (ins), 2577 "mfspr $rX, 3", IIC_SprMFSPR>, 2578 PPC970_DGroup_First, PPC970_Unit_FXU; 2579} 2580 2581// Disable these alias on AIX since they are not supported. 2582let Predicates = [ModernAs] in { 2583// Aliases for moving to/from dscr to mtspr/mfspr 2584def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2585def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2586} 2587 2588let isCodeGenOnly = 1 in { 2589 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2590 // like a GPR on the PPC970. As such, copies in and out have the same 2591 // performance characteristics as an OR instruction. 2592 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2593 "mtspr 256, $rS", IIC_IntGeneral>, 2594 PPC970_DGroup_Single, PPC970_Unit_FXU; 2595 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2596 "mfspr $rT, 256", IIC_IntGeneral>, 2597 PPC970_DGroup_First, PPC970_Unit_FXU; 2598 2599 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2600 (outs VRSAVERC:$reg), (ins gprc:$rS), 2601 "mtspr 256, $rS", IIC_IntGeneral>, 2602 PPC970_DGroup_Single, PPC970_Unit_FXU; 2603 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2604 (ins VRSAVERC:$reg), 2605 "mfspr $rT, 256", IIC_IntGeneral>, 2606 PPC970_DGroup_First, PPC970_Unit_FXU; 2607} 2608 2609// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2610def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2611def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2612 2613let hasSideEffects = 0 in { 2614// mtocrf's input needs to be prepared by shifting by an amount dependent 2615// on the cr register selected. Thus, post-ra anti-dep breaking must not 2616// later change that register assignment. 2617let hasExtraDefRegAllocReq = 1 in { 2618def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2619 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2620 PPC970_DGroup_First, PPC970_Unit_CRU; 2621 2622// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2623// is dependent on the cr fields being set. 2624def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2625 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2626 PPC970_MicroCode, PPC970_Unit_CRU; 2627} // hasExtraDefRegAllocReq = 1 2628 2629// mfocrf's input needs to be prepared by shifting by an amount dependent 2630// on the cr register selected. Thus, post-ra anti-dep breaking must not 2631// later change that register assignment. 2632let hasExtraSrcRegAllocReq = 1 in { 2633def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2634 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2635 PPC970_DGroup_First, PPC970_Unit_CRU; 2636 2637// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2638// is dependent on the cr fields being copied. 2639def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2640 "mfcr $rT", IIC_SprMFCR>, 2641 PPC970_MicroCode, PPC970_Unit_CRU; 2642} // hasExtraSrcRegAllocReq = 1 2643 2644def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2645 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2646} // hasSideEffects = 0 2647 2648def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2649 2650let Predicates = [HasFPU] in { 2651// Custom inserter instruction to perform FADD in round-to-zero mode. 2652let Uses = [RM], mayRaiseFPException = 1 in { 2653 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2654 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2655} 2656 2657// The above pseudo gets expanded to make use of the following instructions 2658// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2659 2660// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2661// RM should be set. 2662let hasSideEffects = 1, Defs = [RM] in { 2663def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2664 "mtfsb0 $FM", IIC_IntMTFSB0, 2665 [(int_ppc_mtfsb0 timm:$FM)]>, 2666 PPC970_DGroup_Single, PPC970_Unit_FPU; 2667def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2668 "mtfsb1 $FM", IIC_IntMTFSB0, 2669 [(int_ppc_mtfsb1 timm:$FM)]>, 2670 PPC970_DGroup_Single, PPC970_Unit_FPU; 2671} 2672 2673let Defs = [RM], hasSideEffects = 1 in { 2674 let isCodeGenOnly = 1 in 2675 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2676 "mtfsf $FM, $rT", IIC_IntMTFSB0, 2677 [(int_ppc_mtfsf timm:$FM, f64:$rT)]>, 2678 PPC970_DGroup_Single, PPC970_Unit_FPU; 2679} 2680let Uses = [RM], hasSideEffects = 1 in { 2681 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2682 "mffs $rT", IIC_IntMFFS, 2683 [(set f64:$rT, (PPCmffs))]>, 2684 PPC970_DGroup_Single, PPC970_Unit_FPU; 2685 2686 let Defs = [CR1] in 2687 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2688 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 2689 2690 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 2691 "mffsce $rT", IIC_IntMFFS, []>, 2692 PPC970_DGroup_Single, PPC970_Unit_FPU; 2693 2694 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 2695 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 2696 IIC_IntMFFS, []>, 2697 PPC970_DGroup_Single, PPC970_Unit_FPU; 2698 2699 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 2700 (ins u3imm:$DRM), 2701 "mffscdrni $rT, $DRM", 2702 IIC_IntMFFS, []>, 2703 PPC970_DGroup_Single, PPC970_Unit_FPU; 2704 2705 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 2706 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 2707 IIC_IntMFFS, []>, 2708 PPC970_DGroup_Single, PPC970_Unit_FPU; 2709 2710 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 2711 (ins u2imm:$RM), "mffscrni $rT, $RM", 2712 IIC_IntMFFS, []>, 2713 PPC970_DGroup_Single, PPC970_Unit_FPU; 2714 2715 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 2716 "mffsl $rT", IIC_IntMFFS, []>, 2717 PPC970_DGroup_Single, PPC970_Unit_FPU; 2718} 2719} 2720 2721let Predicates = [IsISA3_0] in { 2722def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2723 "modsw $rT, $rA, $rB", IIC_IntDivW, 2724 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 2725def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2726 "moduw $rT, $rA, $rB", IIC_IntDivW, 2727 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 2728let hasSideEffects = 1 in 2729def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), 2730 (ins gprc:$rA, gprc:$rB, u2imm:$CY), 2731 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>; 2732} 2733 2734let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2735// XO-Form instructions. Arithmetic instructions that can set overflow bit 2736let isCommutable = 1 in 2737defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2738 "add", "$rT, $rA, $rB", IIC_IntSimple, 2739 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2740let isCodeGenOnly = 1 in 2741def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2742 "add $rT, $rA, $rB", IIC_IntSimple, 2743 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2744let isCommutable = 1 in 2745defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2746 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2747 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2748 PPC970_DGroup_Cracked; 2749 2750defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2751 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2752 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2753defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2754 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2755 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 2756defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2757 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 2758 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 2759 Requires<[HasExtDiv]>; 2760defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2761 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 2762 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 2763 Requires<[HasExtDiv]>; 2764let isCommutable = 1 in { 2765defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2766 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2767 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2768defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2769 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2770 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2771defm MULLW : XOForm_1rx<31, 235, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2772 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2773 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2774} // isCommutable 2775defm SUBF : XOForm_1rx<31, 40, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2776 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2777 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2778defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2779 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2780 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2781 PPC970_DGroup_Cracked; 2782defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2783 "neg", "$rT, $rA", IIC_IntSimple, 2784 [(set i32:$rT, (ineg i32:$rA))]>; 2785let Uses = [CARRY] in { 2786let isCommutable = 1 in 2787defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2788 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2789 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2790defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2791 "addme", "$rT, $rA", IIC_IntGeneral, 2792 [(set i32:$rT, (adde i32:$rA, -1))]>; 2793defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2794 "addze", "$rT, $rA", IIC_IntGeneral, 2795 [(set i32:$rT, (adde i32:$rA, 0))]>; 2796defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2797 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2798 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2799defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2800 "subfme", "$rT, $rA", IIC_IntGeneral, 2801 [(set i32:$rT, (sube -1, i32:$rA))]>; 2802defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2803 "subfze", "$rT, $rA", IIC_IntGeneral, 2804 [(set i32:$rT, (sube 0, i32:$rA))]>; 2805} 2806} 2807 2808def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2809def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2810def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 2811def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2812 2813// A-Form instructions. Most of the instructions executed in the FPU are of 2814// this type. 2815// 2816let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2817let mayRaiseFPException = 1, Uses = [RM] in { 2818let isCommutable = 1 in { 2819 defm FMADD : AForm_1r<63, 29, 2820 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2821 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2822 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2823 defm FMADDS : AForm_1r<59, 29, 2824 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2825 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2826 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2827 defm FMSUB : AForm_1r<63, 28, 2828 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2829 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2830 [(set f64:$FRT, 2831 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2832 defm FMSUBS : AForm_1r<59, 28, 2833 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2834 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2835 [(set f32:$FRT, 2836 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2837 defm FNMADD : AForm_1r<63, 31, 2838 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2839 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2840 [(set f64:$FRT, 2841 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2842 defm FNMADDS : AForm_1r<59, 31, 2843 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2844 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2845 [(set f32:$FRT, 2846 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2847 defm FNMSUB : AForm_1r<63, 30, 2848 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2849 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2850 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 2851 (fneg f64:$FRB))))]>; 2852 defm FNMSUBS : AForm_1r<59, 30, 2853 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2854 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2855 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 2856 (fneg f32:$FRB))))]>; 2857} // isCommutable 2858} 2859// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2860// having 4 of these, force the comparison to always be an 8-byte double (code 2861// should use an FMRSD if the input comparison value really wants to be a float) 2862// and 4/8 byte forms for the result and operand type.. 2863let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2864defm FSELD : AForm_1r<63, 23, 2865 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2866 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2867 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2868defm FSELS : AForm_1r<63, 23, 2869 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2870 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2871 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2872let Uses = [RM], mayRaiseFPException = 1 in { 2873 let isCommutable = 1 in { 2874 defm FADD : AForm_2r<63, 21, 2875 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2876 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2877 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 2878 defm FADDS : AForm_2r<59, 21, 2879 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2880 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2881 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 2882 } // isCommutable 2883 defm FDIV : AForm_2r<63, 18, 2884 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2885 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 2886 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 2887 defm FDIVS : AForm_2r<59, 18, 2888 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2889 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 2890 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 2891 let isCommutable = 1 in { 2892 defm FMUL : AForm_3r<63, 25, 2893 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2894 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 2895 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 2896 defm FMULS : AForm_3r<59, 25, 2897 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2898 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 2899 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 2900 } // isCommutable 2901 defm FSUB : AForm_2r<63, 20, 2902 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2903 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2904 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 2905 defm FSUBS : AForm_2r<59, 20, 2906 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2907 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2908 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 2909 } 2910} 2911 2912let hasSideEffects = 0 in { 2913let PPC970_Unit = 1 in { // FXU Operations. 2914 let isSelect = 1 in 2915 def ISEL : AForm_4<31, 15, 2916 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2917 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 2918 []>; 2919} 2920 2921let PPC970_Unit = 1 in { // FXU Operations. 2922// M-Form instructions. rotate and mask instructions. 2923// 2924let isCommutable = 1 in { 2925// RLWIMI can be commuted if the rotate amount is zero. 2926defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2927 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2928 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 2929 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 2930 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 2931} 2932let BaseName = "rlwinm" in { 2933def RLWINM : MForm_2<21, 2934 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2935 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2936 []>, RecFormRel; 2937let Defs = [CR0] in 2938def RLWINM_rec : MForm_2<21, 2939 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2940 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2941 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 2942} 2943defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2944 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2945 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 2946 []>; 2947} 2948} // hasSideEffects = 0 2949 2950//===----------------------------------------------------------------------===// 2951// PowerPC Instruction Patterns 2952// 2953 2954// Arbitrary immediate support. Implement in terms of LIS/ORI. 2955def : Pat<(i32 imm:$imm), 2956 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2957 2958// Implement the 'not' operation with the NOR instruction. 2959def i32not : OutPatFrag<(ops node:$in), 2960 (NOR $in, $in)>; 2961def : Pat<(not i32:$in), 2962 (i32not $in)>; 2963 2964// ADD an arbitrary immediate. 2965def : Pat<(add i32:$in, imm:$imm), 2966 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2967// OR an arbitrary immediate. 2968def : Pat<(or i32:$in, imm:$imm), 2969 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2970// XOR an arbitrary immediate. 2971def : Pat<(xor i32:$in, imm:$imm), 2972 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2973// SUBFIC 2974def : Pat<(sub imm32SExt16:$imm, i32:$in), 2975 (SUBFIC $in, imm:$imm)>; 2976 2977// SHL/SRL 2978def : Pat<(shl i32:$in, (i32 imm:$imm)), 2979 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2980def : Pat<(srl i32:$in, (i32 imm:$imm)), 2981 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2982 2983// ROTL 2984def : Pat<(rotl i32:$in, i32:$sh), 2985 (RLWNM $in, $sh, 0, 31)>; 2986def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2987 (RLWINM $in, imm:$imm, 0, 31)>; 2988 2989// RLWNM 2990def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2991 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2992 2993// Calls 2994def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2995 (BL tglobaladdr:$dst)>; 2996 2997def : Pat<(PPCcall (i32 texternalsym:$dst)), 2998 (BL texternalsym:$dst)>; 2999 3000def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3001 (BL_RM tglobaladdr:$dst)>; 3002 3003def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3004 (BL_RM texternalsym:$dst)>; 3005 3006// Calls for AIX only 3007def : Pat<(PPCcall (i32 mcsym:$dst)), 3008 (BL mcsym:$dst)>; 3009 3010def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3011 (BL_NOP mcsym:$dst)>; 3012 3013def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3014 (BL_NOP texternalsym:$dst)>; 3015 3016def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3017 (BL_RM mcsym:$dst)>; 3018 3019def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3020 (BL_NOP_RM mcsym:$dst)>; 3021 3022def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3023 (BL_NOP_RM texternalsym:$dst)>; 3024 3025def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3026 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3027 3028def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3029 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3030 3031def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3032 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3033 3034def : Pat<(int_ppc_readflm), (MFFS)>; 3035 3036// Hi and Lo for Darwin Global Addresses. 3037def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3038def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3039def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3040def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3041def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3042def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3043def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3044def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3045def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3046 (ADDIS $in, tglobaltlsaddr:$g)>; 3047def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3048 (ADDI $in, tglobaltlsaddr:$g)>; 3049def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3050 (ADDIS $in, tglobaladdr:$g)>; 3051def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3052 (ADDIS $in, tconstpool:$g)>; 3053def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3054 (ADDIS $in, tjumptable:$g)>; 3055def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3056 (ADDIS $in, tblockaddress:$g)>; 3057 3058// Support for thread-local storage. 3059def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3060 [(set i32:$rD, (PPCppc32GOT))]>; 3061 3062// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3063// This uses two output registers, the first as the real output, the second as a 3064// temporary register, used internally in code generation. 3065def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3066 []>, NoEncode<"$rT">; 3067 3068def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3069 "#LDgotTprelL32", 3070 [(set i32:$rD, 3071 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3072def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3073 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3074 3075def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3076 "#ADDItlsgdL32", 3077 [(set i32:$rD, 3078 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3079// LR is a true define, while the rest of the Defs are clobbers. R3 is 3080// explicitly defined when this op is created, so not mentioned here. 3081let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3082 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3083def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3084 "GETtlsADDR32", 3085 [(set i32:$rD, 3086 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3087// R3 is explicitly defined when this op is created, so not mentioned here. 3088// The rest of the Defs are the exact set of registers that will be clobbered by 3089// the call. 3090let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3091 Defs = [R0,R4,R5,R11,LR,CR0] in 3092def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3093 "GETtlsADDR32AIX", 3094 [(set i32:$rD, 3095 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3096// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3097// are true defines while the rest of the Defs are clobbers. 3098let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3099 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3100def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3101 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3102 "#ADDItlsgdLADDR32", 3103 [(set i32:$rD, 3104 (PPCaddiTlsgdLAddr i32:$reg, 3105 tglobaltlsaddr:$disp, 3106 tglobaltlsaddr:$sym))]>; 3107def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3108 "#ADDItlsldL32", 3109 [(set i32:$rD, 3110 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3111// This pseudo is expanded to two copies to put the variable offset in R4 and 3112// the region handle in R3 and GETtlsADDR32AIX. 3113def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3114 "#TLSGDAIX", 3115 [(set i32:$rD, 3116 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3117// LR is a true define, while the rest of the Defs are clobbers. R3 is 3118// explicitly defined when this op is created, so not mentioned here. 3119let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3120 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3121def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3122 "GETtlsldADDR32", 3123 [(set i32:$rD, 3124 (PPCgetTlsldAddr i32:$reg, 3125 tglobaltlsaddr:$sym))]>; 3126// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3127// are true defines while the rest of the Defs are clobbers. 3128let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3129 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3130def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3131 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3132 "#ADDItlsldLADDR32", 3133 [(set i32:$rD, 3134 (PPCaddiTlsldLAddr i32:$reg, 3135 tglobaltlsaddr:$disp, 3136 tglobaltlsaddr:$sym))]>; 3137def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3138 "#ADDIdtprelL32", 3139 [(set i32:$rD, 3140 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3141def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3142 "#ADDISdtprelHA32", 3143 [(set i32:$rD, 3144 (PPCaddisDtprelHA i32:$reg, 3145 tglobaltlsaddr:$disp))]>; 3146 3147// Support for Position-independent code 3148def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3149 "#LWZtoc", 3150 [(set i32:$rD, 3151 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3152def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3153 "#LWZtocL", 3154 [(set i32:$rD, 3155 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3156def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3157 "#ADDIStocHA", 3158 [(set i32:$rD, 3159 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3160// Local Data Transform 3161def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3162 "#ADDItoc", 3163 [(set i32:$rD, 3164 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3165 3166// Get Global (GOT) Base Register offset, from the word immediately preceding 3167// the function label. 3168def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3169 3170// Pseudo-instruction marked for deletion. When deleting the instruction would 3171// cause iterator invalidation in MIR transformation passes, this pseudo can be 3172// used instead. It will be removed unconditionally at pre-emit time (prior to 3173// branch selection). 3174def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3175 3176// Standard shifts. These are represented separately from the real shifts above 3177// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3178// amounts. 3179def : Pat<(sra i32:$rS, i32:$rB), 3180 (SRAW $rS, $rB)>; 3181def : Pat<(srl i32:$rS, i32:$rB), 3182 (SRW $rS, $rB)>; 3183def : Pat<(shl i32:$rS, i32:$rB), 3184 (SLW $rS, $rB)>; 3185 3186def : Pat<(i32 (zextloadi1 DForm:$src)), 3187 (LBZ DForm:$src)>; 3188def : Pat<(i32 (zextloadi1 XForm:$src)), 3189 (LBZX XForm:$src)>; 3190def : Pat<(i32 (extloadi1 DForm:$src)), 3191 (LBZ DForm:$src)>; 3192def : Pat<(i32 (extloadi1 XForm:$src)), 3193 (LBZX XForm:$src)>; 3194def : Pat<(i32 (extloadi8 DForm:$src)), 3195 (LBZ DForm:$src)>; 3196def : Pat<(i32 (extloadi8 XForm:$src)), 3197 (LBZX XForm:$src)>; 3198def : Pat<(i32 (extloadi16 DForm:$src)), 3199 (LHZ DForm:$src)>; 3200def : Pat<(i32 (extloadi16 XForm:$src)), 3201 (LHZX XForm:$src)>; 3202let Predicates = [HasFPU] in { 3203def : Pat<(f64 (extloadf32 DForm:$src)), 3204 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3205def : Pat<(f64 (extloadf32 XForm:$src)), 3206 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3207 3208def : Pat<(f64 (any_fpextend f32:$src)), 3209 (COPY_TO_REGCLASS $src, F8RC)>; 3210} 3211 3212// Only seq_cst fences require the heavyweight sync (SYNC 0). 3213// All others can use the lightweight sync (SYNC 1). 3214// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3215// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3216// versions of Power. 3217def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3218def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3219def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3220def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3221 3222let Predicates = [HasFPU] in { 3223// Additional fnmsub patterns for custom node 3224def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3225 (FNMSUB $A, $B, $C)>; 3226def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3227 (FNMSUBS $A, $B, $C)>; 3228def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3229 (FMSUB $A, $B, $C)>; 3230def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3231 (FMSUBS $A, $B, $C)>; 3232def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3233 (FNMADD $A, $B, $C)>; 3234def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3235 (FNMADDS $A, $B, $C)>; 3236 3237// FCOPYSIGN's operand types need not agree. 3238def : Pat<(fcopysign f64:$frB, f32:$frA), 3239 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3240def : Pat<(fcopysign f32:$frB, f64:$frA), 3241 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3242} 3243 3244// XL Compat intrinsics. 3245def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3246def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3247def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3248def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3249def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3250def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3251def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3252def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3253 3254include "PPCInstrAltivec.td" 3255include "PPCInstrSPE.td" 3256include "PPCInstr64Bit.td" 3257include "PPCInstrVSX.td" 3258include "PPCInstrHTM.td" 3259 3260def crnot : OutPatFrag<(ops node:$in), 3261 (CRNOR $in, $in)>; 3262def : Pat<(not i1:$in), 3263 (crnot $in)>; 3264 3265// Prefixed instructions may require access to the above defs at a later 3266// time so we include this after the def. 3267include "PPCInstrP10.td" 3268include "PPCInstrMMA.td" 3269 3270// Patterns for arithmetic i1 operations. 3271def : Pat<(add i1:$a, i1:$b), 3272 (CRXOR $a, $b)>; 3273def : Pat<(sub i1:$a, i1:$b), 3274 (CRXOR $a, $b)>; 3275def : Pat<(mul i1:$a, i1:$b), 3276 (CRAND $a, $b)>; 3277 3278// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3279// (-1 is used to mean all bits set). 3280def : Pat<(i1 -1), (CRSET)>; 3281 3282// i1 extensions, implemented in terms of isel. 3283def : Pat<(i32 (zext i1:$in)), 3284 (SELECT_I4 $in, (LI 1), (LI 0))>; 3285def : Pat<(i32 (sext i1:$in)), 3286 (SELECT_I4 $in, (LI -1), (LI 0))>; 3287 3288def : Pat<(i64 (zext i1:$in)), 3289 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3290def : Pat<(i64 (sext i1:$in)), 3291 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3292 3293// FIXME: We should choose either a zext or a sext based on other constants 3294// already around. 3295def : Pat<(i32 (anyext i1:$in)), 3296 (SELECT_I4 $in, (LI 1), (LI 0))>; 3297def : Pat<(i64 (anyext i1:$in)), 3298 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3299 3300// match setcc on i1 variables. 3301// CRANDC is: 3302// 1 1 : F 3303// 1 0 : T 3304// 0 1 : F 3305// 0 0 : F 3306// 3307// LT is: 3308// -1 -1 : F 3309// -1 0 : T 3310// 0 -1 : F 3311// 0 0 : F 3312// 3313// ULT is: 3314// 1 1 : F 3315// 1 0 : F 3316// 0 1 : T 3317// 0 0 : F 3318def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3319 (CRANDC $s1, $s2)>; 3320def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3321 (CRANDC $s2, $s1)>; 3322// CRORC is: 3323// 1 1 : T 3324// 1 0 : T 3325// 0 1 : F 3326// 0 0 : T 3327// 3328// LE is: 3329// -1 -1 : T 3330// -1 0 : T 3331// 0 -1 : F 3332// 0 0 : T 3333// 3334// ULE is: 3335// 1 1 : T 3336// 1 0 : F 3337// 0 1 : T 3338// 0 0 : T 3339def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3340 (CRORC $s1, $s2)>; 3341def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3342 (CRORC $s2, $s1)>; 3343 3344def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3345 (CREQV $s1, $s2)>; 3346 3347// GE is: 3348// -1 -1 : T 3349// -1 0 : F 3350// 0 -1 : T 3351// 0 0 : T 3352// 3353// UGE is: 3354// 1 1 : T 3355// 1 0 : T 3356// 0 1 : F 3357// 0 0 : T 3358def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3359 (CRORC $s2, $s1)>; 3360def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3361 (CRORC $s1, $s2)>; 3362 3363// GT is: 3364// -1 -1 : F 3365// -1 0 : F 3366// 0 -1 : T 3367// 0 0 : F 3368// 3369// UGT is: 3370// 1 1 : F 3371// 1 0 : T 3372// 0 1 : F 3373// 0 0 : F 3374def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3375 (CRANDC $s2, $s1)>; 3376def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3377 (CRANDC $s1, $s2)>; 3378 3379def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3380 (CRXOR $s1, $s2)>; 3381 3382// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3383// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3384// floating-point types. 3385 3386multiclass CRNotPat<dag pattern, dag result> { 3387 def : Pat<pattern, (crnot result)>; 3388 def : Pat<(not pattern), result>; 3389 3390 // We can also fold the crnot into an extension: 3391 def : Pat<(i32 (zext pattern)), 3392 (SELECT_I4 result, (LI 0), (LI 1))>; 3393 def : Pat<(i32 (sext pattern)), 3394 (SELECT_I4 result, (LI 0), (LI -1))>; 3395 3396 // We can also fold the crnot into an extension: 3397 def : Pat<(i64 (zext pattern)), 3398 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3399 def : Pat<(i64 (sext pattern)), 3400 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3401 3402 // FIXME: We should choose either a zext or a sext based on other constants 3403 // already around. 3404 def : Pat<(i32 (anyext pattern)), 3405 (SELECT_I4 result, (LI 0), (LI 1))>; 3406 3407 def : Pat<(i64 (anyext pattern)), 3408 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3409} 3410 3411// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3412// we need to write imm:$imm in the output patterns below, not just $imm, or 3413// else the resulting matcher will not correctly add the immediate operand 3414// (making it a register operand instead). 3415 3416// extended SETCC. 3417multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3418 OutPatFrag rfrag, OutPatFrag rfrag8> { 3419 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3420 (rfrag $s1)>; 3421 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3422 (rfrag8 $s1)>; 3423 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3424 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3425 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3426 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3427 3428 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3429 (rfrag $s1)>; 3430 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3431 (rfrag8 $s1)>; 3432 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3433 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3434 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3435 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3436} 3437 3438// Note that we do all inversions below with i(32|64)not, instead of using 3439// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3440// has 2-cycle latency. 3441 3442defm : ExtSetCCPat<SETEQ, 3443 PatFrag<(ops node:$in, node:$cc), 3444 (setcc $in, 0, $cc)>, 3445 OutPatFrag<(ops node:$in), 3446 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3447 OutPatFrag<(ops node:$in), 3448 (RLDICL (CNTLZD $in), 58, 63)> >; 3449 3450defm : ExtSetCCPat<SETNE, 3451 PatFrag<(ops node:$in, node:$cc), 3452 (setcc $in, 0, $cc)>, 3453 OutPatFrag<(ops node:$in), 3454 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3455 OutPatFrag<(ops node:$in), 3456 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3457 3458defm : ExtSetCCPat<SETLT, 3459 PatFrag<(ops node:$in, node:$cc), 3460 (setcc $in, 0, $cc)>, 3461 OutPatFrag<(ops node:$in), 3462 (RLWINM $in, 1, 31, 31)>, 3463 OutPatFrag<(ops node:$in), 3464 (RLDICL $in, 1, 63)> >; 3465 3466defm : ExtSetCCPat<SETGE, 3467 PatFrag<(ops node:$in, node:$cc), 3468 (setcc $in, 0, $cc)>, 3469 OutPatFrag<(ops node:$in), 3470 (RLWINM (i32not $in), 1, 31, 31)>, 3471 OutPatFrag<(ops node:$in), 3472 (RLDICL (i64not $in), 1, 63)> >; 3473 3474defm : ExtSetCCPat<SETGT, 3475 PatFrag<(ops node:$in, node:$cc), 3476 (setcc $in, 0, $cc)>, 3477 OutPatFrag<(ops node:$in), 3478 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3479 OutPatFrag<(ops node:$in), 3480 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3481 3482defm : ExtSetCCPat<SETLE, 3483 PatFrag<(ops node:$in, node:$cc), 3484 (setcc $in, 0, $cc)>, 3485 OutPatFrag<(ops node:$in), 3486 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3487 OutPatFrag<(ops node:$in), 3488 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3489 3490defm : ExtSetCCPat<SETLT, 3491 PatFrag<(ops node:$in, node:$cc), 3492 (setcc $in, -1, $cc)>, 3493 OutPatFrag<(ops node:$in), 3494 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3495 OutPatFrag<(ops node:$in), 3496 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3497 3498defm : ExtSetCCPat<SETGE, 3499 PatFrag<(ops node:$in, node:$cc), 3500 (setcc $in, -1, $cc)>, 3501 OutPatFrag<(ops node:$in), 3502 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3503 OutPatFrag<(ops node:$in), 3504 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3505 3506defm : ExtSetCCPat<SETGT, 3507 PatFrag<(ops node:$in, node:$cc), 3508 (setcc $in, -1, $cc)>, 3509 OutPatFrag<(ops node:$in), 3510 (RLWINM (i32not $in), 1, 31, 31)>, 3511 OutPatFrag<(ops node:$in), 3512 (RLDICL (i64not $in), 1, 63)> >; 3513 3514defm : ExtSetCCPat<SETLE, 3515 PatFrag<(ops node:$in, node:$cc), 3516 (setcc $in, -1, $cc)>, 3517 OutPatFrag<(ops node:$in), 3518 (RLWINM $in, 1, 31, 31)>, 3519 OutPatFrag<(ops node:$in), 3520 (RLDICL $in, 1, 63)> >; 3521 3522// An extended SETCC with shift amount. 3523multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3524 OutPatFrag rfrag, OutPatFrag rfrag8> { 3525 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3526 (rfrag $s1, $sa)>; 3527 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3528 (rfrag8 $s1, $sa)>; 3529 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3530 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3531 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3532 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3533 3534 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3535 (rfrag $s1, $sa)>; 3536 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3537 (rfrag8 $s1, $sa)>; 3538 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3539 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3540 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3541 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3542} 3543 3544defm : ExtSetCCShiftPat<SETNE, 3545 PatFrag<(ops node:$in, node:$sa, node:$cc), 3546 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3547 OutPatFrag<(ops node:$in, node:$sa), 3548 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3549 OutPatFrag<(ops node:$in, node:$sa), 3550 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3551 3552defm : ExtSetCCShiftPat<SETEQ, 3553 PatFrag<(ops node:$in, node:$sa, node:$cc), 3554 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3555 OutPatFrag<(ops node:$in, node:$sa), 3556 (RLWNM (i32not $in), 3557 (SUBFIC $sa, 32), 31, 31)>, 3558 OutPatFrag<(ops node:$in, node:$sa), 3559 (RLDCL (i64not $in), 3560 (SUBFIC $sa, 64), 63)> >; 3561 3562// SETCC for i32. 3563def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3564 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3565def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3566 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3567def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3568 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3569def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3570 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3571def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3572 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3573def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3574 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3575 3576// For non-equality comparisons, the default code would materialize the 3577// constant, then compare against it, like this: 3578// lis r2, 4660 3579// ori r2, r2, 22136 3580// cmpw cr0, r3, r2 3581// beq cr0,L6 3582// Since we are just comparing for equality, we can emit this instead: 3583// xoris r0,r3,0x1234 3584// cmplwi cr0,r0,0x5678 3585// beq cr0,L6 3586 3587def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3588 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3589 (LO16 imm:$imm)), sub_eq)>; 3590 3591def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3592 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3593def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3594 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3595def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3596 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3597def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3598 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3599def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3600 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3601 3602// SETCC for i64. 3603def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3604 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3605def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3606 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3607def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3608 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3609def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3610 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3611def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3612 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3613def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3614 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3615 3616// For non-equality comparisons, the default code would materialize the 3617// constant, then compare against it, like this: 3618// lis r2, 4660 3619// ori r2, r2, 22136 3620// cmpd cr0, r3, r2 3621// beq cr0,L6 3622// Since we are just comparing for equality, we can emit this instead: 3623// xoris r0,r3,0x1234 3624// cmpldi cr0,r0,0x5678 3625// beq cr0,L6 3626 3627def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3628 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3629 (LO16 imm:$imm)), sub_eq)>; 3630 3631def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3632 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3633def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3634 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3635def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3636 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3637def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3638 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3639def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3640 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3641 3642let Predicates = [IsNotISA3_1] in { 3643// Instantiations of CRNotPat for i32. 3644defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3645 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3646defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3647 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3648defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3649 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3650defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3651 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3652defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3653 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3654defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3655 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3656 3657defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3658 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3659 (LO16 imm:$imm)), sub_eq)>; 3660 3661defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3662 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3663defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3664 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3665defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3666 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3667defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3668 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3669defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3670 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3671 3672// Instantiations of CRNotPat for i64. 3673defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3674 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3675defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3676 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3677defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3678 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3679defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3680 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3681defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3682 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3683defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3684 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3685 3686defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3687 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3688 (LO16 imm:$imm)), sub_eq)>; 3689 3690defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3691 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3692defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3693 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3694defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3695 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3696defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3697 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3698defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3699 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3700} 3701 3702multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3703 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3704 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3705 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3706 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3707 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3708 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3709 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3710 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3711 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3712 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3713 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3714 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3715 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3716 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3717 3718 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3719 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3720 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3721 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3722 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3723 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3724 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3725 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3726 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3727 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3728 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3729 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3730 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3731 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3732} 3733 3734let Predicates = [HasFPU] in { 3735// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3736// SETCC for f32. 3737defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3738 3739// SETCC for f64. 3740defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3741 3742// SETCC for f128. 3743defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3744 3745// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3746// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3747// then VXVC is set. 3748// SETCCS for f32. 3749defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3750 3751// SETCCS for f64. 3752defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 3753 3754// SETCCS for f128. 3755defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 3756} 3757 3758// This must be in this file because it relies on patterns defined in this file 3759// after the inclusion of the instruction sets. 3760let Predicates = [HasSPE] in { 3761// SETCC for f32. 3762def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 3763 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3764def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 3765 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3766def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 3767 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3768def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 3769 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3770def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 3771 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3772def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 3773 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3774 3775defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 3776 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3777defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 3778 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3779defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 3780 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3781defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 3782 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3783defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 3784 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3785defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 3786 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3787 3788// SETCC for f64. 3789def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 3790 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3791def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 3792 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3793def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 3794 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3795def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 3796 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3797def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 3798 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3799def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 3800 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3801 3802defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 3803 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3804defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 3805 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3806defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 3807 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3808defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 3809 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3810defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 3811 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3812defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 3813 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3814} 3815// match select on i1 variables: 3816def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 3817 (CROR (CRAND $cond , $tval), 3818 (CRAND (crnot $cond), $fval))>; 3819 3820// match selectcc on i1 variables: 3821// select (lhs == rhs), tval, fval is: 3822// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 3823def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 3824 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3825 (CRAND (CRORC $rhs, $lhs), $fval))>; 3826def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 3827 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3828 (CRAND (CRORC $lhs, $rhs), $fval))>; 3829def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 3830 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3831 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3832def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 3833 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3834 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3835def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 3836 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 3837 (CRAND (CRXOR $lhs, $rhs), $fval))>; 3838def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 3839 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3840 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3841def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 3842 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3843 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3844def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 3845 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3846 (CRAND (CRORC $lhs, $rhs), $fval))>; 3847def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 3848 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3849 (CRAND (CRORC $rhs, $lhs), $fval))>; 3850def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 3851 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 3852 (CRAND (CRXOR $lhs, $rhs), $tval))>; 3853 3854// match selectcc on i1 variables with non-i1 output. 3855def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 3856 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3857def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 3858 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3859def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 3860 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3861def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 3862 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3863def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 3864 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 3865def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 3866 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3867def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 3868 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3869def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 3870 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3871def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 3872 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3873def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 3874 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3875 3876def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 3877 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3878def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 3879 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3880def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 3881 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3882def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 3883 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3884def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 3885 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 3886def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 3887 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3888def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 3889 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3890def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 3891 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3892def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 3893 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3894def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 3895 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3896 3897let Predicates = [HasFPU] in { 3898def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 3899 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3900def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 3901 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3902def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 3903 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3904def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 3905 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3906def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 3907 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 3908def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 3909 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3910def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 3911 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3912def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 3913 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3914def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 3915 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3916def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 3917 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3918 3919def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 3920 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3921def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 3922 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3923def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 3924 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3925def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 3926 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3927def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 3928 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 3929def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 3930 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3931def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 3932 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3933def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 3934 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3935def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 3936 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3937def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 3938 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3939} 3940 3941def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 3942 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 3943def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 3944 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 3945def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 3946 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 3947def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 3948 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 3949def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 3950 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 3951def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 3952 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 3953def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 3954 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 3955def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 3956 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 3957def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 3958 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 3959def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 3960 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 3961 3962def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 3963 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3964def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 3965 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3966def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 3967 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3968def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 3969 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3970def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 3971 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 3972def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 3973 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3974def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 3975 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3976def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 3977 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3978def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 3979 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3980def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 3981 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 3982 3983def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 3984 "#ANDI_rec_1_EQ_BIT", 3985 [(set i1:$dst, (trunc (not i32:$in)))]>; 3986def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 3987 "#ANDI_rec_1_GT_BIT", 3988 [(set i1:$dst, (trunc i32:$in))]>; 3989 3990def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3991 "#ANDI_rec_1_EQ_BIT8", 3992 [(set i1:$dst, (trunc (not i64:$in)))]>; 3993def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3994 "#ANDI_rec_1_GT_BIT8", 3995 [(set i1:$dst, (trunc i64:$in))]>; 3996 3997def : Pat<(i1 (not (trunc i32:$in))), 3998 (ANDI_rec_1_EQ_BIT $in)>; 3999def : Pat<(i1 (not (trunc i64:$in))), 4000 (ANDI_rec_1_EQ_BIT8 $in)>; 4001 4002def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4003def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4004def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4005 4006//===----------------------------------------------------------------------===// 4007// PowerPC Instructions used for assembler/disassembler only 4008// 4009 4010// FIXME: For B=0 or B > 8, the registers following RT are used. 4011// WARNING: Do not add patterns for this instruction without fixing this. 4012def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4013 (ins gprc:$A, u5imm:$B), 4014 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4015 4016// FIXME: For B=0 or B > 8, the registers following RT are used. 4017// WARNING: Do not add patterns for this instruction without fixing this. 4018def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4019 (ins gprc:$RT, gprc:$A, u5imm:$B), 4020 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4021 4022def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4023 "isync", IIC_SprISYNC, []>; 4024 4025def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4026 "icbi $src", IIC_LdStICBI, []>; 4027 4028def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4029 "wait $L", IIC_LdStLoad, []>; 4030 4031def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4032 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4033 4034def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4035 "mtsr $SR, $RS", IIC_SprMTSR>; 4036 4037def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4038 "mfsr $RS, $SR", IIC_SprMFSR>; 4039 4040def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4041 "mtsrin $RS, $RB", IIC_SprMTSR>; 4042 4043def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4044 "mfsrin $RS, $RB", IIC_SprMFSR>; 4045 4046def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4047 "mtmsr $RS, $L", IIC_SprMTMSR>; 4048 4049def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4050 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4051 let L = 0; 4052} 4053 4054def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4055 Requires<[IsBookE]> { 4056 bits<1> E; 4057 4058 let Inst{16} = E; 4059 let Inst{21-30} = 163; 4060} 4061 4062def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4063 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4064def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4065 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4066 4067def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4068def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4069def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4070def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4071 4072def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4073 "mfmsr $RT", IIC_SprMFMSR, []>; 4074 4075def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4076 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4077 4078def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4079 "mcrfs $BF, $BFA", IIC_BrMCR>; 4080 4081// All MTFSF variants may change the rounding mode so conservatively set it 4082// as an implicit def for all of them. 4083let Predicates = [HasFPU] in { 4084let Defs = [RM], hasSideEffects = 1 in { 4085let isCodeGenOnly = 1, 4086 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4087def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4088 "mtfsfi $BF, $U", IIC_IntMFFS>; 4089def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4090 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4091let Defs = [CR1] in 4092def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4093 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4094 4095def MTFSF : XFLForm_1<63, 711, (outs), 4096 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4097 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4098let Defs = [CR1] in 4099def MTFSF_rec : XFLForm_1<63, 711, (outs), 4100 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4101 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4102} 4103 4104def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4105def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4106def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4107def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4108} 4109 4110def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4111 "slbie $RB", IIC_SprSLBIE, []>; 4112 4113def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4114 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4115 4116def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4117 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4118 4119def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4120 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4121 4122def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4123 4124let Defs = [CR0] in 4125def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4126 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4127 4128def TLBIA : XForm_0<31, 370, (outs), (ins), 4129 "tlbia", IIC_SprTLBIA, []>; 4130 4131def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4132 "tlbsync", IIC_SprTLBSYNC, []>; 4133 4134def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4135 "tlbiel $RB", IIC_SprTLBIEL, []>; 4136 4137def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4138 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4139def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4140 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4141 4142def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4143 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4144 4145def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4146 IIC_LdStLoad>, Requires<[IsBookE]>; 4147 4148def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4149 IIC_LdStLoad>, Requires<[IsBookE]>; 4150 4151def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4152 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4153 4154def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4155 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4156 4157def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4158 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4159 4160def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4161 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4162 4163def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4164 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4165 Requires<[IsPPC4xx]>; 4166def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4167 (ins gprc:$RST, gprc:$A, gprc:$B), 4168 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4169 Requires<[IsPPC4xx]>, isRecordForm; 4170 4171def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4172 4173def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4174 Requires<[IsBookE]>; 4175def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4176 Requires<[IsBookE]>; 4177 4178def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4179 Requires<[IsE500]>; 4180def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4181 Requires<[IsE500]>; 4182 4183def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4184 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4185def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4186 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4187 4188def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4189def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4190 4191def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4192 4193def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4194 (ins gprc:$A, gprc:$B), 4195 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4196def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4197 (ins gprc:$A, gprc:$B), 4198 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4199def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4200 (ins gprc:$A, gprc:$B), 4201 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4202def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4203 (ins gprc:$A, gprc:$B), 4204 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4205 4206def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4207 (ins gprc:$RST, gprc:$A, gprc:$B), 4208 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4209def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4210 (ins gprc:$RST, gprc:$A, gprc:$B), 4211 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4212def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4213 (ins gprc:$RST, gprc:$A, gprc:$B), 4214 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4215def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4216 (ins gprc:$RST, gprc:$A, gprc:$B), 4217 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4218 4219// External PID Load Store Instructions 4220 4221def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4222 "lbepx $rD, $src", IIC_LdStLoad, []>, 4223 Requires<[IsE500]>; 4224 4225def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4226 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4227 Requires<[IsE500]>; 4228 4229def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4230 "lhepx $rD, $src", IIC_LdStLoad, []>, 4231 Requires<[IsE500]>; 4232 4233def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4234 "lwepx $rD, $src", IIC_LdStLoad, []>, 4235 Requires<[IsE500]>; 4236 4237def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4238 "stbepx $rS, $dst", IIC_LdStStore, []>, 4239 Requires<[IsE500]>; 4240 4241def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4242 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4243 Requires<[IsE500]>; 4244 4245def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4246 "sthepx $rS, $dst", IIC_LdStStore, []>, 4247 Requires<[IsE500]>; 4248 4249def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4250 "stwepx $rS, $dst", IIC_LdStStore, []>, 4251 Requires<[IsE500]>; 4252 4253def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4254 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4255 4256def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4257 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4258 4259def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4260 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4261 Requires<[IsE500]>; 4262 4263def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4264 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4265 Requires<[IsE500]>; 4266 4267def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4268 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4269 4270def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4271 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4272 4273def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4274 IIC_LdStICBI, []>, Requires<[IsE500]>; 4275 4276//===----------------------------------------------------------------------===// 4277// PowerPC Assembler Instruction Aliases 4278// 4279 4280// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4281// These are aliases that require C++ handling to convert to the target 4282// instruction, while InstAliases can be handled directly by tblgen. 4283class PPCAsmPseudo<string asm, dag iops> 4284 : Instruction { 4285 let Namespace = "PPC"; 4286 bit PPC64 = 0; // Default value, override with isPPC64 4287 4288 let OutOperandList = (outs); 4289 let InOperandList = iops; 4290 let Pattern = []; 4291 let AsmString = asm; 4292 let isAsmParserOnly = 1; 4293 let isPseudo = 1; 4294 let hasNoSchedulingInfo = 1; 4295} 4296 4297def : InstAlias<"sc", (SC 0)>; 4298 4299def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4300def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4301def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4302def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4303def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4304 4305def : InstAlias<"wait", (WAIT 0)>; 4306def : InstAlias<"waitrsv", (WAIT 1)>; 4307def : InstAlias<"waitimpl", (WAIT 2)>; 4308 4309def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4310 4311def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4312def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4313 4314def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4315def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4316def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4317 4318def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4319def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4320def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4321 4322def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4323def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4324def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4325 4326def : Pat<(int_ppc_isync), (ISYNC)>; 4327def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4328 (DCBF 1, xoaddr:$dst)>; 4329def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4330 (DCBF 3, xoaddr:$dst)>; 4331 4332let Predicates = [IsISA3_1] in { 4333 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4334 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4335 4336 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4337 (DCBF 4, xoaddr:$dst)>; 4338 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4339 (DCBF 6, xoaddr:$dst)>; 4340} 4341 4342def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4343def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4344def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4345def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4346 4347def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4348def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4349def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4350 4351def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4352 4353def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4354def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4355 4356//Disable this alias on AIX for now because as does not support them. 4357let Predicates = [ModernAs] in { 4358 4359foreach BR = 0-7 in { 4360 def : InstAlias<"mfbr"#BR#" $Rx", 4361 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4362 Requires<[IsPPC4xx]>; 4363 def : InstAlias<"mtbr"#BR#" $Rx", 4364 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4365 Requires<[IsPPC4xx]>; 4366} 4367 4368def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4369def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4370def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4371def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4372 4373def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4374def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4375 4376def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4377def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4378 4379def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4380def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4381 4382def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4383def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4384 4385def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4386def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4387 4388def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4389def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4390 4391def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4392def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4393 4394def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4395def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4396 4397def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4398def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4399 4400def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4401def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4402 4403def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4404def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4405 4406def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4407def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4408 4409def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4410def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4411 4412def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4413def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4414 4415foreach SPRG = 4-7 in { 4416 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4417 Requires<[IsBookE]>; 4418 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4419 Requires<[IsBookE]>; 4420 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4421 Requires<[IsBookE]>; 4422 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4423 Requires<[IsBookE]>; 4424} 4425 4426foreach SPRG = 0-3 in { 4427 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4428 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4429 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4430 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4431} 4432 4433def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4434def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4435 4436def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4437def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4438 4439def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4440 4441def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4442def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4443 4444foreach BATR = 0-3 in { 4445 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4446 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4447 Requires<[IsPPC6xx]>; 4448 def : InstAlias<"mfdbatu $Rx, "#BATR, 4449 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4450 Requires<[IsPPC6xx]>; 4451 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4452 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4453 Requires<[IsPPC6xx]>; 4454 def : InstAlias<"mfdbatl $Rx, "#BATR, 4455 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4456 Requires<[IsPPC6xx]>; 4457 def : InstAlias<"mtibatu "#BATR#", $Rx", 4458 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4459 Requires<[IsPPC6xx]>; 4460 def : InstAlias<"mfibatu $Rx, "#BATR, 4461 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4462 Requires<[IsPPC6xx]>; 4463 def : InstAlias<"mtibatl "#BATR#", $Rx", 4464 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4465 Requires<[IsPPC6xx]>; 4466 def : InstAlias<"mfibatl $Rx, "#BATR, 4467 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4468 Requires<[IsPPC6xx]>; 4469} 4470 4471def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4472def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4473 4474def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4475def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4476 4477def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4478def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4479 4480def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4481def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4482 4483def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4484def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4485 4486def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4487def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4488 4489def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4490def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4491 4492def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4493def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4494 4495def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4496def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4497 4498def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4499def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4500 4501} 4502 4503def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4504 4505def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4506 Requires<[IsPPC4xx]>; 4507def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4508 Requires<[IsPPC4xx]>; 4509def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4510 Requires<[IsPPC4xx]>; 4511def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4512 Requires<[IsPPC4xx]>; 4513 4514def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4515 4516def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4517 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4518def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4519 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4520def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4521 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4522def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4523 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4524 4525def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4526 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4527def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4528 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4529def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4530 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4531def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4532 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4533def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4534 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4535def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4536 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4537def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4538 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4539def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4540 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4541def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4542 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4543def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4544 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4545def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4546 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4547def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4548 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4549def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4550 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4551def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4552 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4553def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4554 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4555def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4556 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4557def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4558 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4559def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4560 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4561 4562def : InstAlias<"isellt $rT, $rA, $rB", 4563 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4564def : InstAlias<"iselgt $rT, $rA, $rB", 4565 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4566def : InstAlias<"iseleq $rT, $rA, $rB", 4567 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4568 4569def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4570def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4571def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4572def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4573def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4574def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4575 4576def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4577def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4578// The POWER variant 4579def : MnemonicAlias<"cntlz", "cntlzw">; 4580def : MnemonicAlias<"cntlz.", "cntlzw.">; 4581 4582def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4583 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4584def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4585 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4586def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4587 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4588def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4589 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4590def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4591 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4592def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4593 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4594def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4595 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4596def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4597 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4598def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4599 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4600def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4601 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4602def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4603 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4604def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4605 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4606def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4607 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4608def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4609 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4610def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4611 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4612def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4613 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4614def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4615 4616def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4617def : InstAlias<"rotldi $rA, $rS, $n", 4618 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4619def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4620def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4621def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4622def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4623def : InstAlias<"clrldi $rA, $rS, $n", 4624 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4625def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4626def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4627 4628def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4629 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4630def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4631 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4632def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4633 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4634def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4635 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4636def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4637 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4638def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4639 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4640 4641// These generic branch instruction forms are used for the assembler parser only. 4642// Defs and Uses are conservative, since we don't know the BO value. 4643let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4644 let Defs = [CTR], Uses = [CTR, RM] in { 4645 def gBC : BForm_3<16, 0, 0, (outs), 4646 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4647 "bc $bo, $bi, $dst">; 4648 def gBCA : BForm_3<16, 1, 0, (outs), 4649 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4650 "bca $bo, $bi, $dst">; 4651 let isAsmParserOnly = 1 in { 4652 def gBCat : BForm_3_at<16, 0, 0, (outs), 4653 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4654 condbrtarget:$dst), 4655 "bc$at $bo, $bi, $dst">; 4656 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4657 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4658 abscondbrtarget:$dst), 4659 "bca$at $bo, $bi, $dst">; 4660 } // isAsmParserOnly = 1 4661 } 4662 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4663 def gBCL : BForm_3<16, 0, 1, (outs), 4664 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4665 "bcl $bo, $bi, $dst">; 4666 def gBCLA : BForm_3<16, 1, 1, (outs), 4667 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4668 "bcla $bo, $bi, $dst">; 4669 let isAsmParserOnly = 1 in { 4670 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4671 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4672 condbrtarget:$dst), 4673 "bcl$at $bo, $bi, $dst">; 4674 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4675 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4676 abscondbrtarget:$dst), 4677 "bcla$at $bo, $bi, $dst">; 4678 } // // isAsmParserOnly = 1 4679 } 4680 let Defs = [CTR], Uses = [CTR, LR, RM] in 4681 def gBCLR : XLForm_2<19, 16, 0, (outs), 4682 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4683 "bclr $bo, $bi, $bh", IIC_BrB, []>; 4684 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4685 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4686 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4687 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 4688 let Defs = [CTR], Uses = [CTR, LR, RM] in 4689 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4690 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4691 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 4692 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4693 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4694 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4695 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 4696} 4697 4698multiclass BranchSimpleMnemonicAT<string pm, int at> { 4699 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4700 condbrtarget:$dst)>; 4701 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4702 condbrtarget:$dst)>; 4703 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4704 condbrtarget:$dst)>; 4705 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4706 condbrtarget:$dst)>; 4707} 4708defm : BranchSimpleMnemonicAT<"+", 3>; 4709defm : BranchSimpleMnemonicAT<"-", 2>; 4710 4711def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4712def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4713def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4714def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4715 4716multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4717 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4718 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4719 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4720 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4721 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4722 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4723} 4724multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4725 : BranchSimpleMnemonic1<name, pm, bo> { 4726 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4727 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4728} 4729defm : BranchSimpleMnemonic2<"t", "", 12>; 4730defm : BranchSimpleMnemonic2<"f", "", 4>; 4731defm : BranchSimpleMnemonic2<"t", "-", 14>; 4732defm : BranchSimpleMnemonic2<"f", "-", 6>; 4733defm : BranchSimpleMnemonic2<"t", "+", 15>; 4734defm : BranchSimpleMnemonic2<"f", "+", 7>; 4735defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4736defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4737defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4738defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4739 4740multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4741 def : InstAlias<"b"#name#pm#" $cc, $dst", 4742 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4743 def : InstAlias<"b"#name#pm#" $dst", 4744 (BCC bibo, CR0, condbrtarget:$dst)>; 4745 4746 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4747 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4748 def : InstAlias<"b"#name#"a"#pm#" $dst", 4749 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4750 4751 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4752 (BCCLR bibo, crrc:$cc)>; 4753 def : InstAlias<"b"#name#"lr"#pm, 4754 (BCCLR bibo, CR0)>; 4755 4756 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4757 (BCCCTR bibo, crrc:$cc)>; 4758 def : InstAlias<"b"#name#"ctr"#pm, 4759 (BCCCTR bibo, CR0)>; 4760 4761 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4762 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4763 def : InstAlias<"b"#name#"l"#pm#" $dst", 4764 (BCCL bibo, CR0, condbrtarget:$dst)>; 4765 4766 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4767 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4768 def : InstAlias<"b"#name#"la"#pm#" $dst", 4769 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4770 4771 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4772 (BCCLRL bibo, crrc:$cc)>; 4773 def : InstAlias<"b"#name#"lrl"#pm, 4774 (BCCLRL bibo, CR0)>; 4775 4776 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4777 (BCCCTRL bibo, crrc:$cc)>; 4778 def : InstAlias<"b"#name#"ctrl"#pm, 4779 (BCCCTRL bibo, CR0)>; 4780} 4781multiclass BranchExtendedMnemonic<string name, int bibo> { 4782 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4783 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4784 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4785} 4786defm : BranchExtendedMnemonic<"lt", 12>; 4787defm : BranchExtendedMnemonic<"gt", 44>; 4788defm : BranchExtendedMnemonic<"eq", 76>; 4789defm : BranchExtendedMnemonic<"un", 108>; 4790defm : BranchExtendedMnemonic<"so", 108>; 4791defm : BranchExtendedMnemonic<"ge", 4>; 4792defm : BranchExtendedMnemonic<"nl", 4>; 4793defm : BranchExtendedMnemonic<"le", 36>; 4794defm : BranchExtendedMnemonic<"ng", 36>; 4795defm : BranchExtendedMnemonic<"ne", 68>; 4796defm : BranchExtendedMnemonic<"nu", 100>; 4797defm : BranchExtendedMnemonic<"ns", 100>; 4798 4799def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4800def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4801def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4802def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4803def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4804def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4805def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4806def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4807 4808def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4809def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4810def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 4811def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 4812def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 4813def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4814def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 4815def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4816 4817def : InstAlias<"trap", (TW 31, R0, R0)>; 4818 4819multiclass TrapExtendedMnemonic<string name, int to> { 4820 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 4821 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 4822 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 4823 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 4824} 4825defm : TrapExtendedMnemonic<"lt", 16>; 4826defm : TrapExtendedMnemonic<"le", 20>; 4827defm : TrapExtendedMnemonic<"eq", 4>; 4828defm : TrapExtendedMnemonic<"ge", 12>; 4829defm : TrapExtendedMnemonic<"gt", 8>; 4830defm : TrapExtendedMnemonic<"nl", 12>; 4831defm : TrapExtendedMnemonic<"ne", 24>; 4832defm : TrapExtendedMnemonic<"ng", 20>; 4833defm : TrapExtendedMnemonic<"llt", 2>; 4834defm : TrapExtendedMnemonic<"lle", 6>; 4835defm : TrapExtendedMnemonic<"lge", 5>; 4836defm : TrapExtendedMnemonic<"lgt", 1>; 4837defm : TrapExtendedMnemonic<"lnl", 5>; 4838defm : TrapExtendedMnemonic<"lng", 6>; 4839defm : TrapExtendedMnemonic<"u", 31>; 4840 4841// Atomic loads 4842def : Pat<(atomic_load_8 DForm:$src), (LBZ memri:$src)>; 4843def : Pat<(atomic_load_16 DForm:$src), (LHZ memri:$src)>; 4844def : Pat<(atomic_load_32 DForm:$src), (LWZ memri:$src)>; 4845def : Pat<(atomic_load_8 XForm:$src), (LBZX memrr:$src)>; 4846def : Pat<(atomic_load_16 XForm:$src), (LHZX memrr:$src)>; 4847def : Pat<(atomic_load_32 XForm:$src), (LWZX memrr:$src)>; 4848 4849// Atomic stores 4850def : Pat<(atomic_store_8 DForm:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 4851def : Pat<(atomic_store_16 DForm:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 4852def : Pat<(atomic_store_32 DForm:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 4853def : Pat<(atomic_store_8 XForm:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 4854def : Pat<(atomic_store_16 XForm:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 4855def : Pat<(atomic_store_32 XForm:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 4856 4857let Predicates = [IsISA3_0] in { 4858 4859// Copy-Paste Facility 4860// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 4861// PASTE for naming consistency. 4862let mayLoad = 1 in 4863def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 4864 4865let mayStore = 1, Defs = [CR0] in 4866def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 4867 4868def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 4869def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 4870 4871// Message Synchronize 4872def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 4873 4874// Power-Saving Mode Instruction: 4875def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 4876 4877def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 4878 "setb $RT, $BFA", IIC_IntGeneral>; 4879} // IsISA3_0 4880 4881let Predicates = [IsISA3_0] in { 4882def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 4883 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 4884} 4885def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 4886 (i32 (MULHW $a, $b))>; 4887def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 4888 (i32 (MULHWU $a, $b))>; 4889def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 4890 (i32 (CMPB $a, $b))>; 4891 4892def : Pat<(int_ppc_load2r ForceXForm:$ptr), 4893 (LHBRX ForceXForm:$ptr)>; 4894def : Pat<(int_ppc_load4r ForceXForm:$ptr), 4895 (LWBRX ForceXForm:$ptr)>; 4896def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 4897 (STHBRX gprc:$a, ForceXForm:$ptr)>; 4898def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 4899 (STWBRX gprc:$a, ForceXForm:$ptr)>; 4900 4901 4902// Fast 32-bit reverse bits algorithm: 4903// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 4904// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 4905// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 4906// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 4907// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 4908// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 4909// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 4910// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 4911// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 4912// Step 4.2: Insert B3 to the right position: 4913// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 4914// Step 4.3: Insert B1 to the right position: 4915// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 4916def MaskValues { 4917 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 4918 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 4919 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 4920 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 4921 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 4922 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 4923} 4924 4925def Shift1 { 4926 dag Right = (RLWINM $A, 31, 1, 31); 4927 dag Left = (RLWINM $A, 1, 0, 30); 4928} 4929 4930def Swap1 { 4931 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 4932 (AND Shift1.Left, MaskValues.Hi1)); 4933} 4934 4935def Shift2 { 4936 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 4937 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 4938} 4939 4940def Swap2 { 4941 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 4942 (AND Shift2.Left, MaskValues.Hi2)); 4943} 4944 4945def Shift4 { 4946 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 4947 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 4948} 4949 4950def Swap4 { 4951 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 4952 (AND Shift4.Left, MaskValues.Hi4)); 4953} 4954 4955def Rotate { 4956 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 4957} 4958 4959def RotateInsertByte3 { 4960 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 4961} 4962 4963def RotateInsertByte1 { 4964 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 4965} 4966 4967// Clear the upper half of the register when in 64-bit mode 4968let Predicates = [In64BitMode] in 4969def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 4970let Predicates = [In32BitMode] in 4971def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 4972 4973// Fast 64-bit reverse bits algorithm: 4974// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 4975// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 4976// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 4977// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 4978// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 4979// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 4980// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 4981// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 4982// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 4983// then OR them together to get the final result. 4984def MaskValues64 { 4985 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 4986 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 4987 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 4988 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 4989 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 4990 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 4991} 4992 4993def DWMaskValues { 4994 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 4995 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 4996 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 4997 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 4998 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 4999 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5000} 5001 5002def DWSwapInByte { 5003 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5004 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5005 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5006 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5007 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5008 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5009} 5010 5011// Intra-byte swap is done, now start inter-byte swap. 5012def DWBytes4567 { 5013 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5014} 5015 5016def DWBytes7456 { 5017 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5018} 5019 5020def DWBytes7656 { 5021 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5022} 5023 5024// B7 B6 B5 B4 in the right order 5025def DWBytes7654 { 5026 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5027 dag DWord = 5028 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5029} 5030 5031def DWBytes0123 { 5032 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5033} 5034 5035def DWBytes3012 { 5036 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5037} 5038 5039def DWBytes3212 { 5040 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5041} 5042 5043// B3 B2 B1 B0 in the right order 5044def DWBytes3210 { 5045 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5046 dag DWord = 5047 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5048} 5049 5050// These instructions store a hash computed from the value of the link register 5051// and the value of the stack pointer. 5052let mayStore = 1 in { 5053def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5054 (ins gprc:$RB, memrihash:$D_RA_XD), 5055 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 5056def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5057 (ins gprc:$RB, memrihash:$D_RA_XD), 5058 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 5059} 5060 5061// These instructions check a hash computed from the value of the link register 5062// and the value of the stack pointer. The hasSideEffects flag is needed as the 5063// instruction may TRAP if the hash does not match the hash stored at the 5064// specified address. 5065let mayLoad = 1, hasSideEffects = 1 in { 5066def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5067 (ins gprc:$RB, memrihash:$D_RA_XD), 5068 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 5069def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5070 (ins gprc:$RB, memrihash:$D_RA_XD), 5071 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 5072} 5073 5074// Now both high word and low word are reversed, next 5075// swap the high word and low word. 5076def : Pat<(i64 (bitreverse i64:$A)), 5077 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5078 5079def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5080 (STWCX gprc:$A, ForceXForm:$dst)>; 5081def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5082 (STBCX gprc:$A, ForceXForm:$dst)>; 5083def : Pat<(int_ppc_trap gprc:$A), 5084 (TWI 24, $A, 0)>; 5085 5086def : Pat<(int_ppc_fcfid f64:$A), 5087 (XSCVSXDDP $A)>; 5088def : Pat<(int_ppc_fcfud f64:$A), 5089 (XSCVUXDDP $A)>; 5090def : Pat<(int_ppc_fctid f64:$A), 5091 (FCTID $A)>; 5092def : Pat<(int_ppc_fctidz f64:$A), 5093 (XSCVDPSXDS $A)>; 5094def : Pat<(int_ppc_fctiw f64:$A), 5095 (FCTIW $A)>; 5096def : Pat<(int_ppc_fctiwz f64:$A), 5097 (XSCVDPSXWS $A)>; 5098def : Pat<(int_ppc_fctudz f64:$A), 5099 (XSCVDPUXDS $A)>; 5100def : Pat<(int_ppc_fctuwz f64:$A), 5101 (XSCVDPUXWS $A)>; 5102 5103def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5104def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5105def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5106 (MFSPR $SPR)>; 5107def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5108 (MTSPR $SPR, $RT)>; 5109def : Pat<(int_ppc_mtmsr gprc:$RS), 5110 (MTMSR $RS, 0)>; 5111 5112let Predicates = [IsISA2_07] in { 5113 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5114 (STHCX gprc:$A, ForceXForm:$dst)>; 5115} 5116def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5117 (DCBTST 16, ForceXForm:$dst)>; 5118def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5119 (DCBT 16, ForceXForm:$dst)>; 5120 5121def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5122 (STFIWX f64:$XT, ForceXForm:$dst)>; 5123