1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40def SDT_PPCSExtVElems : SDTypeProfile<1, 1, [ 41 SDTCisVec<0>, SDTCisVec<1> 42]>; 43 44def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 45 SDTCisVT<1, i32> ]>; 46def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 47 SDTCisVT<1, i32> ]>; 48def SDT_PPCvperm : SDTypeProfile<1, 3, [ 49 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 50]>; 51 52def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 53 SDTCisVec<1>, SDTCisInt<2> 54]>; 55 56def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 57 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 58]>; 59 60def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 61 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 62]>; 63 64def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 65 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 66]>; 67 68def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 69 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 70]>; 71 72def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 73 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 74]>; 75 76def SDT_PPClbrx : SDTypeProfile<1, 2, [ 77 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 78]>; 79def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 80 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 81]>; 82 83def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 84 SDTCisPtrTy<0>, SDTCisVT<1, i32> 85]>; 86 87def tocentry32 : Operand<iPTR> { 88 let MIOperandInfo = (ops i32imm:$imm); 89} 90 91def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 92 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 93]>; 94def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 95 SDTCisVec<0>, SDTCisInt<1> 96]>; 97def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 98 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 99]>; 100def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 101 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 102]>; 103 104def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 105 SDTCisVec<0>, SDTCisVec<1> 106]>; 107 108def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 109 SDTCisVec<0>, SDTCisPtrTy<1> 110]>; 111 112def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 113 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 114]>; 115 116def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 117 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 118]>; 119 120//===----------------------------------------------------------------------===// 121// PowerPC specific DAG Nodes. 122// 123 124def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 125def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 126 127def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 128def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 129def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 130def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 131def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 132def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 133def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 134def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 135 136def PPCcv_fp_to_uint_in_vsr: 137 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 138def PPCcv_fp_to_sint_in_vsr: 139 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 140def PPCstore_scal_int_from_vsr: 141 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 142 [SDNPHasChain, SDNPMayStore]>; 143def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 144 [SDNPHasChain, SDNPMayStore]>; 145def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 146 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 147def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 148 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 149def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 150 [SDNPHasChain, SDNPMayLoad]>; 151def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 152 [SDNPHasChain, SDNPMayStore]>; 153def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 154def PPCSExtVElems : SDNode<"PPCISD::SExtVElems", SDT_PPCSExtVElems, []>; 155 156// Extract FPSCR (not modeled at the DAG level). 157def PPCmffs : SDNode<"PPCISD::MFFS", 158 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 159 160// Perform FADD in round-to-zero mode. 161def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 162 163 164def PPCfsel : SDNode<"PPCISD::FSEL", 165 // Type constraint for fsel. 166 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 167 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 168def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; 169def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; 170def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 171def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 172def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 173 [SDNPMayLoad, SDNPMemOperand]>; 174def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 175def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 176 177def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 178 179def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 180def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 181 [SDNPMayLoad]>; 182def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 183def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 184def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 185def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 186def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 187 SDTypeProfile<1, 3, [ 188 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 189 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 190def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 191def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 192def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 193def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 194 SDTypeProfile<1, 3, [ 195 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 196 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 197def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 198def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 199 200def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 201def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 202def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 203def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 204def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 205 206def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>; 207def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>; 208def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>; 209def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>; 210 211def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>; 212 213def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb, 214 [SDNPHasChain, SDNPMayLoad]>; 215 216def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 217 218// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 219// amounts. These nodes are generated by the multi-precision shift code. 220def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 221def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 222def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 223 224def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 225 226// Move 2 i64 values into a VSX register 227def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 228 SDTypeProfile<1, 2, 229 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 230 SDTCisSameAs<1,2>]>, 231 []>; 232 233def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 234 SDTypeProfile<1, 2, 235 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 236 SDTCisVT<1,i32>]>, 237 []>; 238 239def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 240 SDTypeProfile<1, 2, 241 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 242 SDTCisPtrTy<2>]>, 243 []>; 244 245// These are target-independent nodes, but have target-specific formats. 246def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 247 [SDNPHasChain, SDNPOutGlue]>; 248def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 249 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 250 251def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 252def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 253 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 254 SDNPVariadic]>; 255def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 256 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 257 SDNPVariadic]>; 258def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 259 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 260def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 261 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 262 SDNPVariadic]>; 263def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 264 SDTypeProfile<0, 1, []>, 265 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 266 SDNPVariadic]>; 267 268def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 269 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 270 271def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 272 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 273 274def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 275 SDTypeProfile<1, 1, [SDTCisInt<0>, 276 SDTCisPtrTy<1>]>, 277 [SDNPHasChain, SDNPSideEffect]>; 278def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 279 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 280 [SDNPHasChain, SDNPSideEffect]>; 281 282def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 283def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 284 [SDNPHasChain, SDNPSideEffect]>; 285 286def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 287 [SDNPHasChain, SDNPSideEffect]>; 288def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 289def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 290 [SDNPHasChain, SDNPSideEffect]>; 291 292def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 293def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 294 295def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 296 [SDNPHasChain, SDNPOptInGlue]>; 297 298// PPC-specific atomic operations. 299def PPCatomicCmpSwap_8 : 300 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 301 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 302def PPCatomicCmpSwap_16 : 303 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 304 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 305def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 306 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 307def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 308 [SDNPHasChain, SDNPMayStore]>; 309 310// Instructions to set/unset CR bit 6 for SVR4 vararg calls 311def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 313def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 314 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 315 316// Instructions to support dynamic alloca. 317def SDTDynOp : SDTypeProfile<1, 2, []>; 318def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 319def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 320def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 321 322//===----------------------------------------------------------------------===// 323// PowerPC specific transformation functions and pattern fragments. 324// 325 326def SHL32 : SDNodeXForm<imm, [{ 327 // Transformation function: 31 - imm 328 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 329}]>; 330 331def SRL32 : SDNodeXForm<imm, [{ 332 // Transformation function: 32 - imm 333 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 334 : getI32Imm(0, SDLoc(N)); 335}]>; 336 337def LO16 : SDNodeXForm<imm, [{ 338 // Transformation function: get the low 16 bits. 339 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 340}]>; 341 342def HI16 : SDNodeXForm<imm, [{ 343 // Transformation function: shift the immediate value down into the low bits. 344 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 345}]>; 346 347def HA16 : SDNodeXForm<imm, [{ 348 // Transformation function: shift the immediate value down into the low bits. 349 long Val = N->getZExtValue(); 350 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 351}]>; 352def MB : SDNodeXForm<imm, [{ 353 // Transformation function: get the start bit of a mask 354 unsigned mb = 0, me; 355 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 356 return getI32Imm(mb, SDLoc(N)); 357}]>; 358 359def ME : SDNodeXForm<imm, [{ 360 // Transformation function: get the end bit of a mask 361 unsigned mb, me = 0; 362 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 363 return getI32Imm(me, SDLoc(N)); 364}]>; 365def maskimm32 : PatLeaf<(imm), [{ 366 // maskImm predicate - True if immediate is a run of ones. 367 unsigned mb, me; 368 if (N->getValueType(0) == MVT::i32) 369 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 370 else 371 return false; 372}]>; 373 374def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 375 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 376 // sign extended field. Used by instructions like 'addi'. 377 return (int32_t)Imm == (short)Imm; 378}]>; 379def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 380 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 381 // sign extended field. Used by instructions like 'addi'. 382 return (int64_t)Imm == (short)Imm; 383}]>; 384def immZExt16 : PatLeaf<(imm), [{ 385 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 386 // field. Used by instructions like 'ori'. 387 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 388}], LO16>; 389def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 390 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 391}]>; 392def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 393 394// imm16Shifted* - These match immediates where the low 16-bits are zero. There 395// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 396// identical in 32-bit mode, but in 64-bit mode, they return true if the 397// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 398// clear). 399def imm16ShiftedZExt : PatLeaf<(imm), [{ 400 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 401 // immediate are set. Used by instructions like 'xoris'. 402 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 403}], HI16>; 404 405def imm16ShiftedSExt : PatLeaf<(imm), [{ 406 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 407 // immediate are set. Used by instructions like 'addis'. Identical to 408 // imm16ShiftedZExt in 32-bit mode. 409 if (N->getZExtValue() & 0xFFFF) return false; 410 if (N->getValueType(0) == MVT::i32) 411 return true; 412 // For 64-bit, make sure it is sext right. 413 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 414}], HI16>; 415 416def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 417 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 418 // zero extended field. 419 return isUInt<32>(Imm); 420}]>; 421 422// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 423// restricted memrix (4-aligned) constants are alignment sensitive. If these 424// offsets are hidden behind TOC entries than the values of the lower-order 425// bits cannot be checked directly. As a result, we need to also incorporate 426// an alignment check into the relevant patterns. 427 428def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 429 return cast<LoadSDNode>(N)->getAlignment() >= 4; 430}]>; 431def aligned4store : PatFrag<(ops node:$val, node:$ptr), 432 (store node:$val, node:$ptr), [{ 433 return cast<StoreSDNode>(N)->getAlignment() >= 4; 434}]>; 435def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 436 return cast<LoadSDNode>(N)->getAlignment() >= 4; 437}]>; 438def aligned4pre_store : PatFrag< 439 (ops node:$val, node:$base, node:$offset), 440 (pre_store node:$val, node:$base, node:$offset), [{ 441 return cast<StoreSDNode>(N)->getAlignment() >= 4; 442}]>; 443 444def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 445 return cast<LoadSDNode>(N)->getAlignment() < 4; 446}]>; 447def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 448 (store node:$val, node:$ptr), [{ 449 return cast<StoreSDNode>(N)->getAlignment() < 4; 450}]>; 451def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 452 return cast<LoadSDNode>(N)->getAlignment() < 4; 453}]>; 454 455// This is a somewhat weaker condition than actually checking for 16-byte 456// alignment. It is simply checking that the displacement can be represented 457// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 458// instructions). 459def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 460 return isOffsetMultipleOf(N, 16); 461}]>; 462def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 463 (store node:$val, node:$ptr), [{ 464 return isOffsetMultipleOf(N, 16); 465}]>; 466def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 467 return !isOffsetMultipleOf(N, 16); 468}]>; 469def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 470 (store node:$val, node:$ptr), [{ 471 return !isOffsetMultipleOf(N, 16); 472}]>; 473 474// PatFrag for binary operation whose operands are both non-constant 475class BinOpWithoutSImm16Operand<SDNode opcode> : 476 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 477 int16_t Imm; 478 return !isIntS16Immediate(N->getOperand(0), Imm) 479 && !isIntS16Immediate(N->getOperand(1), Imm); 480}]>; 481 482def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 483def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 484 485//===----------------------------------------------------------------------===// 486// PowerPC Flag Definitions. 487 488class isPPC64 { bit PPC64 = 1; } 489class isRecordForm { bit RC = 1; } 490 491class RegConstraint<string C> { 492 string Constraints = C; 493} 494class NoEncode<string E> { 495 string DisableEncoding = E; 496} 497 498 499//===----------------------------------------------------------------------===// 500// PowerPC Operand Definitions. 501 502// In the default PowerPC assembler syntax, registers are specified simply 503// by number, so they cannot be distinguished from immediate values (without 504// looking at the opcode). This means that the default operand matching logic 505// for the asm parser does not work, and we need to specify custom matchers. 506// Since those can only be specified with RegisterOperand classes and not 507// directly on the RegisterClass, all instructions patterns used by the asm 508// parser need to use a RegisterOperand (instead of a RegisterClass) for 509// all their register operands. 510// For this purpose, we define one RegisterOperand for each RegisterClass, 511// using the same name as the class, just in lower case. 512 513def PPCRegGPRCAsmOperand : AsmOperandClass { 514 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 515} 516def gprc : RegisterOperand<GPRC> { 517 let ParserMatchClass = PPCRegGPRCAsmOperand; 518} 519def PPCRegG8RCAsmOperand : AsmOperandClass { 520 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 521} 522def g8rc : RegisterOperand<G8RC> { 523 let ParserMatchClass = PPCRegG8RCAsmOperand; 524} 525def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 526 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 527} 528def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 529 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 530} 531def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 532 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 533} 534def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 535 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 536} 537def PPCRegF8RCAsmOperand : AsmOperandClass { 538 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 539} 540def f8rc : RegisterOperand<F8RC> { 541 let ParserMatchClass = PPCRegF8RCAsmOperand; 542} 543def PPCRegF4RCAsmOperand : AsmOperandClass { 544 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 545} 546def f4rc : RegisterOperand<F4RC> { 547 let ParserMatchClass = PPCRegF4RCAsmOperand; 548} 549def PPCRegVRRCAsmOperand : AsmOperandClass { 550 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 551} 552def vrrc : RegisterOperand<VRRC> { 553 let ParserMatchClass = PPCRegVRRCAsmOperand; 554} 555def PPCRegVFRCAsmOperand : AsmOperandClass { 556 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 557} 558def vfrc : RegisterOperand<VFRC> { 559 let ParserMatchClass = PPCRegVFRCAsmOperand; 560} 561def PPCRegCRBITRCAsmOperand : AsmOperandClass { 562 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 563} 564def crbitrc : RegisterOperand<CRBITRC> { 565 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 566} 567def PPCRegCRRCAsmOperand : AsmOperandClass { 568 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 569} 570def crrc : RegisterOperand<CRRC> { 571 let ParserMatchClass = PPCRegCRRCAsmOperand; 572} 573def PPCRegSPERCAsmOperand : AsmOperandClass { 574 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 575} 576def sperc : RegisterOperand<SPERC> { 577 let ParserMatchClass = PPCRegSPERCAsmOperand; 578} 579def PPCRegSPE4RCAsmOperand : AsmOperandClass { 580 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 581} 582def spe4rc : RegisterOperand<GPRC> { 583 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 584} 585 586def PPCU1ImmAsmOperand : AsmOperandClass { 587 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 588 let RenderMethod = "addImmOperands"; 589} 590def u1imm : Operand<i32> { 591 let PrintMethod = "printU1ImmOperand"; 592 let ParserMatchClass = PPCU1ImmAsmOperand; 593} 594 595def PPCU2ImmAsmOperand : AsmOperandClass { 596 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 597 let RenderMethod = "addImmOperands"; 598} 599def u2imm : Operand<i32> { 600 let PrintMethod = "printU2ImmOperand"; 601 let ParserMatchClass = PPCU2ImmAsmOperand; 602} 603 604def PPCATBitsAsHintAsmOperand : AsmOperandClass { 605 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 606 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 607} 608def atimm : Operand<i32> { 609 let PrintMethod = "printATBitsAsHint"; 610 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 611} 612 613def PPCU3ImmAsmOperand : AsmOperandClass { 614 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 615 let RenderMethod = "addImmOperands"; 616} 617def u3imm : Operand<i32> { 618 let PrintMethod = "printU3ImmOperand"; 619 let ParserMatchClass = PPCU3ImmAsmOperand; 620} 621 622def PPCU4ImmAsmOperand : AsmOperandClass { 623 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 624 let RenderMethod = "addImmOperands"; 625} 626def u4imm : Operand<i32> { 627 let PrintMethod = "printU4ImmOperand"; 628 let ParserMatchClass = PPCU4ImmAsmOperand; 629} 630def PPCS5ImmAsmOperand : AsmOperandClass { 631 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 632 let RenderMethod = "addImmOperands"; 633} 634def s5imm : Operand<i32> { 635 let PrintMethod = "printS5ImmOperand"; 636 let ParserMatchClass = PPCS5ImmAsmOperand; 637 let DecoderMethod = "decodeSImmOperand<5>"; 638} 639def PPCU5ImmAsmOperand : AsmOperandClass { 640 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 641 let RenderMethod = "addImmOperands"; 642} 643def u5imm : Operand<i32> { 644 let PrintMethod = "printU5ImmOperand"; 645 let ParserMatchClass = PPCU5ImmAsmOperand; 646 let DecoderMethod = "decodeUImmOperand<5>"; 647} 648def PPCU6ImmAsmOperand : AsmOperandClass { 649 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 650 let RenderMethod = "addImmOperands"; 651} 652def u6imm : Operand<i32> { 653 let PrintMethod = "printU6ImmOperand"; 654 let ParserMatchClass = PPCU6ImmAsmOperand; 655 let DecoderMethod = "decodeUImmOperand<6>"; 656} 657def PPCU7ImmAsmOperand : AsmOperandClass { 658 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 659 let RenderMethod = "addImmOperands"; 660} 661def u7imm : Operand<i32> { 662 let PrintMethod = "printU7ImmOperand"; 663 let ParserMatchClass = PPCU7ImmAsmOperand; 664 let DecoderMethod = "decodeUImmOperand<7>"; 665} 666def PPCU8ImmAsmOperand : AsmOperandClass { 667 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 668 let RenderMethod = "addImmOperands"; 669} 670def u8imm : Operand<i32> { 671 let PrintMethod = "printU8ImmOperand"; 672 let ParserMatchClass = PPCU8ImmAsmOperand; 673 let DecoderMethod = "decodeUImmOperand<8>"; 674} 675def PPCU10ImmAsmOperand : AsmOperandClass { 676 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 677 let RenderMethod = "addImmOperands"; 678} 679def u10imm : Operand<i32> { 680 let PrintMethod = "printU10ImmOperand"; 681 let ParserMatchClass = PPCU10ImmAsmOperand; 682 let DecoderMethod = "decodeUImmOperand<10>"; 683} 684def PPCU12ImmAsmOperand : AsmOperandClass { 685 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 686 let RenderMethod = "addImmOperands"; 687} 688def u12imm : Operand<i32> { 689 let PrintMethod = "printU12ImmOperand"; 690 let ParserMatchClass = PPCU12ImmAsmOperand; 691 let DecoderMethod = "decodeUImmOperand<12>"; 692} 693def PPCS16ImmAsmOperand : AsmOperandClass { 694 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 695 let RenderMethod = "addS16ImmOperands"; 696} 697def s16imm : Operand<i32> { 698 let PrintMethod = "printS16ImmOperand"; 699 let EncoderMethod = "getImm16Encoding"; 700 let ParserMatchClass = PPCS16ImmAsmOperand; 701 let DecoderMethod = "decodeSImmOperand<16>"; 702} 703def PPCU16ImmAsmOperand : AsmOperandClass { 704 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 705 let RenderMethod = "addU16ImmOperands"; 706} 707def u16imm : Operand<i32> { 708 let PrintMethod = "printU16ImmOperand"; 709 let EncoderMethod = "getImm16Encoding"; 710 let ParserMatchClass = PPCU16ImmAsmOperand; 711 let DecoderMethod = "decodeUImmOperand<16>"; 712} 713def PPCS17ImmAsmOperand : AsmOperandClass { 714 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 715 let RenderMethod = "addS16ImmOperands"; 716} 717def s17imm : Operand<i32> { 718 // This operand type is used for addis/lis to allow the assembler parser 719 // to accept immediates in the range -65536..65535 for compatibility with 720 // the GNU assembler. The operand is treated as 16-bit otherwise. 721 let PrintMethod = "printS16ImmOperand"; 722 let EncoderMethod = "getImm16Encoding"; 723 let ParserMatchClass = PPCS17ImmAsmOperand; 724 let DecoderMethod = "decodeSImmOperand<16>"; 725} 726 727def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 728 729def PPCDirectBrAsmOperand : AsmOperandClass { 730 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 731 let RenderMethod = "addBranchTargetOperands"; 732} 733def directbrtarget : Operand<OtherVT> { 734 let PrintMethod = "printBranchOperand"; 735 let EncoderMethod = "getDirectBrEncoding"; 736 let ParserMatchClass = PPCDirectBrAsmOperand; 737} 738def absdirectbrtarget : Operand<OtherVT> { 739 let PrintMethod = "printAbsBranchOperand"; 740 let EncoderMethod = "getAbsDirectBrEncoding"; 741 let ParserMatchClass = PPCDirectBrAsmOperand; 742} 743def PPCCondBrAsmOperand : AsmOperandClass { 744 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 745 let RenderMethod = "addBranchTargetOperands"; 746} 747def condbrtarget : Operand<OtherVT> { 748 let PrintMethod = "printBranchOperand"; 749 let EncoderMethod = "getCondBrEncoding"; 750 let ParserMatchClass = PPCCondBrAsmOperand; 751} 752def abscondbrtarget : Operand<OtherVT> { 753 let PrintMethod = "printAbsBranchOperand"; 754 let EncoderMethod = "getAbsCondBrEncoding"; 755 let ParserMatchClass = PPCCondBrAsmOperand; 756} 757def calltarget : Operand<iPTR> { 758 let PrintMethod = "printBranchOperand"; 759 let EncoderMethod = "getDirectBrEncoding"; 760 let DecoderMethod = "DecodePCRel24BranchTarget"; 761 let ParserMatchClass = PPCDirectBrAsmOperand; 762 let OperandType = "OPERAND_PCREL"; 763} 764def abscalltarget : Operand<iPTR> { 765 let PrintMethod = "printAbsBranchOperand"; 766 let EncoderMethod = "getAbsDirectBrEncoding"; 767 let ParserMatchClass = PPCDirectBrAsmOperand; 768} 769def PPCCRBitMaskOperand : AsmOperandClass { 770 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 771} 772def crbitm: Operand<i8> { 773 let PrintMethod = "printcrbitm"; 774 let EncoderMethod = "get_crbitm_encoding"; 775 let DecoderMethod = "decodeCRBitMOperand"; 776 let ParserMatchClass = PPCCRBitMaskOperand; 777} 778// Address operands 779// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 780def PPCRegGxRCNoR0Operand : AsmOperandClass { 781 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 782} 783def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 784 let ParserMatchClass = PPCRegGxRCNoR0Operand; 785} 786// A version of ptr_rc usable with the asm parser. 787def PPCRegGxRCOperand : AsmOperandClass { 788 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 789} 790def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 791 let ParserMatchClass = PPCRegGxRCOperand; 792} 793 794def PPCDispRIOperand : AsmOperandClass { 795 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 796 let RenderMethod = "addS16ImmOperands"; 797} 798def dispRI : Operand<iPTR> { 799 let ParserMatchClass = PPCDispRIOperand; 800} 801def PPCDispRIXOperand : AsmOperandClass { 802 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 803 let RenderMethod = "addImmOperands"; 804} 805def dispRIX : Operand<iPTR> { 806 let ParserMatchClass = PPCDispRIXOperand; 807} 808def PPCDispRIX16Operand : AsmOperandClass { 809 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 810 let RenderMethod = "addImmOperands"; 811} 812def dispRIX16 : Operand<iPTR> { 813 let ParserMatchClass = PPCDispRIX16Operand; 814} 815def PPCDispSPE8Operand : AsmOperandClass { 816 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 817 let RenderMethod = "addImmOperands"; 818} 819def dispSPE8 : Operand<iPTR> { 820 let ParserMatchClass = PPCDispSPE8Operand; 821} 822def PPCDispSPE4Operand : AsmOperandClass { 823 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 824 let RenderMethod = "addImmOperands"; 825} 826def dispSPE4 : Operand<iPTR> { 827 let ParserMatchClass = PPCDispSPE4Operand; 828} 829def PPCDispSPE2Operand : AsmOperandClass { 830 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 831 let RenderMethod = "addImmOperands"; 832} 833def dispSPE2 : Operand<iPTR> { 834 let ParserMatchClass = PPCDispSPE2Operand; 835} 836 837def memri : Operand<iPTR> { 838 let PrintMethod = "printMemRegImm"; 839 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 840 let EncoderMethod = "getMemRIEncoding"; 841 let DecoderMethod = "decodeMemRIOperands"; 842} 843def memrr : Operand<iPTR> { 844 let PrintMethod = "printMemRegReg"; 845 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 846} 847def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 848 let PrintMethod = "printMemRegImm"; 849 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 850 let EncoderMethod = "getMemRIXEncoding"; 851 let DecoderMethod = "decodeMemRIXOperands"; 852} 853def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 854 let PrintMethod = "printMemRegImm"; 855 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 856 let EncoderMethod = "getMemRIX16Encoding"; 857 let DecoderMethod = "decodeMemRIX16Operands"; 858} 859def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 860 let PrintMethod = "printMemRegImm"; 861 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 862 let EncoderMethod = "getSPE8DisEncoding"; 863 let DecoderMethod = "decodeSPE8Operands"; 864} 865def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 866 let PrintMethod = "printMemRegImm"; 867 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 868 let EncoderMethod = "getSPE4DisEncoding"; 869 let DecoderMethod = "decodeSPE4Operands"; 870} 871def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 872 let PrintMethod = "printMemRegImm"; 873 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 874 let EncoderMethod = "getSPE2DisEncoding"; 875 let DecoderMethod = "decodeSPE2Operands"; 876} 877 878// A single-register address. This is used with the SjLj 879// pseudo-instructions which tranlates to LD/LWZ. These instructions requires 880// G8RC_NOX0 registers. 881def memr : Operand<iPTR> { 882 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 883} 884def PPCTLSRegOperand : AsmOperandClass { 885 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 886 let RenderMethod = "addTLSRegOperands"; 887} 888def tlsreg32 : Operand<i32> { 889 let EncoderMethod = "getTLSRegEncoding"; 890 let ParserMatchClass = PPCTLSRegOperand; 891} 892def tlsgd32 : Operand<i32> {} 893def tlscall32 : Operand<i32> { 894 let PrintMethod = "printTLSCall"; 895 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 896 let EncoderMethod = "getTLSCallEncoding"; 897} 898 899// PowerPC Predicate operand. 900def pred : Operand<OtherVT> { 901 let PrintMethod = "printPredicateOperand"; 902 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 903} 904 905// Define PowerPC specific addressing mode. 906 907// d-form 908def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 909// ds-form 910def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 911// dq-form 912def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 913 914// Below forms are all x-form addressing mode, use three different ones so we 915// can make a accurate check for x-form instructions in ISEL. 916// x-form addressing mode whose associated diplacement form is D. 917def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 918// x-form addressing mode whose associated diplacement form is DS. 919def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 920// x-form addressing mode whose associated diplacement form is DQ. 921def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 922 923def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 924 925// The address in a single register. This is used with the SjLj 926// pseudo-instructions. 927def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 928 929/// This is just the offset part of iaddr, used for preinc. 930def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 931 932//===----------------------------------------------------------------------===// 933// PowerPC Instruction Predicate Definitions. 934def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; 935def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; 936def IsBookE : Predicate<"PPCSubTarget->isBookE()">; 937def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; 938def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">; 939def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">; 940def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; 941def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; 942def IsE500 : Predicate<"PPCSubTarget->isE500()">; 943def HasSPE : Predicate<"PPCSubTarget->hasSPE()">; 944def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; 945def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">; 946def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 947def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">; 948def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">; 949def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">; 950def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">; 951def HasFPU : Predicate<"PPCSubTarget->hasFPU()">; 952 953//===----------------------------------------------------------------------===// 954// PowerPC Multiclass Definitions. 955 956multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 957 string asmbase, string asmstr, InstrItinClass itin, 958 list<dag> pattern> { 959 let BaseName = asmbase in { 960 def NAME : XForm_6<opcode, xo, OOL, IOL, 961 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 962 pattern>, RecFormRel; 963 let Defs = [CR0] in 964 def _rec : XForm_6<opcode, xo, OOL, IOL, 965 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 966 []>, isRecordForm, RecFormRel; 967 } 968} 969 970multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 971 string asmbase, string asmstr, InstrItinClass itin, 972 list<dag> pattern> { 973 let BaseName = asmbase in { 974 let Defs = [CARRY] in 975 def NAME : XForm_6<opcode, xo, OOL, IOL, 976 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 977 pattern>, RecFormRel; 978 let Defs = [CARRY, CR0] in 979 def _rec : XForm_6<opcode, xo, OOL, IOL, 980 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 981 []>, isRecordForm, RecFormRel; 982 } 983} 984 985multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 986 string asmbase, string asmstr, InstrItinClass itin, 987 list<dag> pattern> { 988 let BaseName = asmbase in { 989 let Defs = [CARRY] in 990 def NAME : XForm_10<opcode, xo, OOL, IOL, 991 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 992 pattern>, RecFormRel; 993 let Defs = [CARRY, CR0] in 994 def _rec : XForm_10<opcode, xo, OOL, IOL, 995 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 996 []>, isRecordForm, RecFormRel; 997 } 998} 999 1000multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1001 string asmbase, string asmstr, InstrItinClass itin, 1002 list<dag> pattern> { 1003 let BaseName = asmbase in { 1004 def NAME : XForm_11<opcode, xo, OOL, IOL, 1005 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1006 pattern>, RecFormRel; 1007 let Defs = [CR0] in 1008 def _rec : XForm_11<opcode, xo, OOL, IOL, 1009 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1010 []>, isRecordForm, RecFormRel; 1011 } 1012} 1013 1014multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1015 string asmbase, string asmstr, InstrItinClass itin, 1016 list<dag> pattern> { 1017 let BaseName = asmbase in { 1018 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1019 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1020 pattern>, RecFormRel; 1021 let Defs = [CR0] in 1022 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1023 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1024 []>, isRecordForm, RecFormRel; 1025 } 1026} 1027 1028// Multiclass for instructions which have a record overflow form as well 1029// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 1030multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1031 string asmbase, string asmstr, InstrItinClass itin, 1032 list<dag> pattern> { 1033 let BaseName = asmbase in { 1034 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 1035 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1036 pattern>, RecFormRel; 1037 let Defs = [CR0] in 1038 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 1039 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1040 []>, isRecordForm, RecFormRel; 1041 } 1042 let BaseName = !strconcat(asmbase, "O") in { 1043 let Defs = [XER] in 1044 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1045 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1046 []>, RecFormRel; 1047 let Defs = [XER, CR0] in 1048 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1049 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1050 []>, isRecordForm, RecFormRel; 1051 } 1052} 1053 1054// Multiclass for instructions for which the non record form is not cracked 1055// and the record form is cracked (i.e. divw, mullw, etc.) 1056multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1057 string asmbase, string asmstr, InstrItinClass itin, 1058 list<dag> pattern> { 1059 let BaseName = asmbase in { 1060 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1061 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1062 pattern>, RecFormRel; 1063 let Defs = [CR0] in 1064 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1065 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1066 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 1067 PPC970_DGroup_Cracked; 1068 } 1069 let BaseName = !strconcat(asmbase, "O") in { 1070 let Defs = [XER] in 1071 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1072 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1073 []>, RecFormRel; 1074 let Defs = [XER, CR0] in 1075 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1076 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1077 []>, isRecordForm, RecFormRel; 1078 } 1079} 1080 1081multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1082 string asmbase, string asmstr, InstrItinClass itin, 1083 list<dag> pattern> { 1084 let BaseName = asmbase in { 1085 let Defs = [CARRY] in 1086 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1087 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1088 pattern>, RecFormRel; 1089 let Defs = [CARRY, CR0] in 1090 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1091 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1092 []>, isRecordForm, RecFormRel; 1093 } 1094 let BaseName = !strconcat(asmbase, "O") in { 1095 let Defs = [CARRY, XER] in 1096 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1097 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1098 []>, RecFormRel; 1099 let Defs = [CARRY, XER, CR0] in 1100 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1101 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1102 []>, isRecordForm, RecFormRel; 1103 } 1104} 1105 1106multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1107 string asmbase, string asmstr, InstrItinClass itin, 1108 list<dag> pattern> { 1109 let BaseName = asmbase in { 1110 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1111 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1112 pattern>, RecFormRel; 1113 let Defs = [CR0] in 1114 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1115 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1116 []>, isRecordForm, RecFormRel; 1117 } 1118 let BaseName = !strconcat(asmbase, "O") in { 1119 let Defs = [XER] in 1120 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1121 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1122 []>, RecFormRel; 1123 let Defs = [XER, CR0] in 1124 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1125 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1126 []>, isRecordForm, RecFormRel; 1127 } 1128} 1129 1130multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1131 string asmbase, string asmstr, InstrItinClass itin, 1132 list<dag> pattern> { 1133 let BaseName = asmbase in { 1134 let Defs = [CARRY] in 1135 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1136 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1137 pattern>, RecFormRel; 1138 let Defs = [CARRY, CR0] in 1139 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1140 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1141 []>, isRecordForm, RecFormRel; 1142 } 1143 let BaseName = !strconcat(asmbase, "O") in { 1144 let Defs = [CARRY, XER] in 1145 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1146 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1147 []>, RecFormRel; 1148 let Defs = [CARRY, XER, CR0] in 1149 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1150 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1151 []>, isRecordForm, RecFormRel; 1152 } 1153} 1154 1155multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 1156 string asmbase, string asmstr, InstrItinClass itin, 1157 list<dag> pattern> { 1158 let BaseName = asmbase in { 1159 def NAME : MForm_2<opcode, OOL, IOL, 1160 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1161 pattern>, RecFormRel; 1162 let Defs = [CR0] in 1163 def _rec : MForm_2<opcode, OOL, IOL, 1164 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1165 []>, isRecordForm, RecFormRel; 1166 } 1167} 1168 1169multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 1170 string asmbase, string asmstr, InstrItinClass itin, 1171 list<dag> pattern> { 1172 let BaseName = asmbase in { 1173 def NAME : MDForm_1<opcode, xo, OOL, IOL, 1174 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1175 pattern>, RecFormRel; 1176 let Defs = [CR0] in 1177 def _rec : MDForm_1<opcode, xo, OOL, IOL, 1178 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1179 []>, isRecordForm, RecFormRel; 1180 } 1181} 1182 1183multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 1184 string asmbase, string asmstr, InstrItinClass itin, 1185 list<dag> pattern> { 1186 let BaseName = asmbase in { 1187 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 1188 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1189 pattern>, RecFormRel; 1190 let Defs = [CR0] in 1191 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1192 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1193 []>, isRecordForm, RecFormRel; 1194 } 1195} 1196 1197multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1198 string asmbase, string asmstr, InstrItinClass itin, 1199 list<dag> pattern> { 1200 let BaseName = asmbase in { 1201 let Defs = [CARRY] in 1202 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1203 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1204 pattern>, RecFormRel; 1205 let Defs = [CARRY, CR0] in 1206 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1207 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1208 []>, isRecordForm, RecFormRel; 1209 } 1210} 1211 1212multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1213 string asmbase, string asmstr, InstrItinClass itin, 1214 list<dag> pattern> { 1215 let BaseName = asmbase in { 1216 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1217 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1218 pattern>, RecFormRel; 1219 let Defs = [CR0] in 1220 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1221 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1222 []>, isRecordForm, RecFormRel; 1223 } 1224} 1225 1226multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1227 string asmbase, string asmstr, InstrItinClass itin, 1228 list<dag> pattern> { 1229 let BaseName = asmbase in { 1230 def NAME : XForm_26<opcode, xo, OOL, IOL, 1231 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1232 pattern>, RecFormRel; 1233 let Defs = [CR1] in 1234 def _rec : XForm_26<opcode, xo, OOL, IOL, 1235 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1236 []>, isRecordForm, RecFormRel; 1237 } 1238} 1239 1240multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1241 string asmbase, string asmstr, InstrItinClass itin, 1242 list<dag> pattern> { 1243 let BaseName = asmbase in { 1244 def NAME : XForm_28<opcode, xo, OOL, IOL, 1245 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1246 pattern>, RecFormRel; 1247 let Defs = [CR1] in 1248 def _rec : XForm_28<opcode, xo, OOL, IOL, 1249 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1250 []>, isRecordForm, RecFormRel; 1251 } 1252} 1253 1254multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1255 string asmbase, string asmstr, InstrItinClass itin, 1256 list<dag> pattern> { 1257 let BaseName = asmbase in { 1258 def NAME : AForm_1<opcode, xo, OOL, IOL, 1259 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1260 pattern>, RecFormRel; 1261 let Defs = [CR1] in 1262 def _rec : AForm_1<opcode, xo, OOL, IOL, 1263 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1264 []>, isRecordForm, RecFormRel; 1265 } 1266} 1267 1268multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1269 string asmbase, string asmstr, InstrItinClass itin, 1270 list<dag> pattern> { 1271 let BaseName = asmbase in { 1272 def NAME : AForm_2<opcode, xo, OOL, IOL, 1273 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1274 pattern>, RecFormRel; 1275 let Defs = [CR1] in 1276 def _rec : AForm_2<opcode, xo, OOL, IOL, 1277 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1278 []>, isRecordForm, RecFormRel; 1279 } 1280} 1281 1282multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1283 string asmbase, string asmstr, InstrItinClass itin, 1284 list<dag> pattern> { 1285 let BaseName = asmbase in { 1286 def NAME : AForm_3<opcode, xo, OOL, IOL, 1287 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1288 pattern>, RecFormRel; 1289 let Defs = [CR1] in 1290 def _rec : AForm_3<opcode, xo, OOL, IOL, 1291 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1292 []>, isRecordForm, RecFormRel; 1293 } 1294} 1295 1296//===----------------------------------------------------------------------===// 1297// PowerPC Instruction Definitions. 1298 1299// Pseudo instructions: 1300 1301let hasCtrlDep = 1 in { 1302let Defs = [R1], Uses = [R1] in { 1303def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1304 "#ADJCALLSTACKDOWN $amt1 $amt2", 1305 [(callseq_start timm:$amt1, timm:$amt2)]>; 1306def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1307 "#ADJCALLSTACKUP $amt1 $amt2", 1308 [(callseq_end timm:$amt1, timm:$amt2)]>; 1309} 1310 1311def UPDATE_VRSAVE : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$rS), 1312 "UPDATE_VRSAVE $rD, $rS", []>; 1313} 1314 1315let Defs = [R1], Uses = [R1] in 1316def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1317 [(set i32:$result, 1318 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1319def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1320 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1321 1322// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1323// instruction selection into a branch sequence. 1324let PPC970_Single = 1 in { 1325 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1326 // because either operand might become the first operand in an isel, and 1327 // that operand cannot be r0. 1328 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1329 gprc_nor0:$T, gprc_nor0:$F, 1330 i32imm:$BROPC), "#SELECT_CC_I4", 1331 []>; 1332 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1333 g8rc_nox0:$T, g8rc_nox0:$F, 1334 i32imm:$BROPC), "#SELECT_CC_I8", 1335 []>; 1336 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1337 i32imm:$BROPC), "#SELECT_CC_F4", 1338 []>; 1339 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1340 i32imm:$BROPC), "#SELECT_CC_F8", 1341 []>; 1342 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1343 i32imm:$BROPC), "#SELECT_CC_F16", 1344 []>; 1345 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1346 i32imm:$BROPC), "#SELECT_CC_VRRC", 1347 []>; 1348 1349 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1350 // register bit directly. 1351 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1352 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1353 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1354 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1355 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1356 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1357let Predicates = [HasFPU] in { 1358 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1359 f4rc:$T, f4rc:$F), "#SELECT_F4", 1360 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1361 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1362 f8rc:$T, f8rc:$F), "#SELECT_F8", 1363 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1364 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1365 vrrc:$T, vrrc:$F), "#SELECT_F16", 1366 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1367} 1368 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1369 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1370 [(set v4i32:$dst, 1371 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1372} 1373 1374// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1375// scavenge a register for it. 1376let mayStore = 1 in { 1377def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1378 "#SPILL_CR", []>; 1379def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1380 "#SPILL_CRBIT", []>; 1381} 1382 1383// RESTORE_CR - Indicate that we're restoring the CR register (previously 1384// spilled), so we'll need to scavenge a register for it. 1385let mayLoad = 1 in { 1386def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1387 "#RESTORE_CR", []>; 1388def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1389 "#RESTORE_CRBIT", []>; 1390} 1391 1392let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 1393 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1394 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1395 [(retflag)]>, Requires<[In32BitMode]>; 1396 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1397 let isPredicable = 1 in 1398 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1399 []>; 1400 1401 let isCodeGenOnly = 1 in { 1402 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1403 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1404 []>; 1405 1406 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1407 "bcctr 12, $bi, 0", IIC_BrB, []>; 1408 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1409 "bcctr 4, $bi, 0", IIC_BrB, []>; 1410 } 1411 } 1412} 1413 1414// Set the float rounding mode. 1415let Uses = [RM], Defs = [RM] in { 1416def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1417 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1418 1419def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1420 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1421} 1422 1423let Defs = [LR] in 1424 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1425 PPC970_Unit_BRU; 1426let Defs = [LR] in 1427 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1428 PPC970_Unit_BRU; 1429 1430let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 1431 let isBarrier = 1 in { 1432 let isPredicable = 1 in 1433 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1434 "b $dst", IIC_BrB, 1435 [(br bb:$dst)]>; 1436 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1437 "ba $dst", IIC_BrB, []>; 1438 } 1439 1440 // BCC represents an arbitrary conditional branch on a predicate. 1441 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1442 // a two-value operand where a dag node expects two operands. :( 1443 let isCodeGenOnly = 1 in { 1444 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1445 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1446 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1447 def BCC : BCC_class; 1448 1449 // The same as BCC, except that it's not a terminator. Used for introducing 1450 // control flow dependency without creating new blocks. 1451 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1452 1453 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1454 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1455 1456 let isReturn = 1, Uses = [LR, RM] in 1457 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1458 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1459 } 1460 1461 let isCodeGenOnly = 1 in { 1462 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1463 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1464 "bc 12, $bi, $dst">; 1465 1466 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1467 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1468 "bc 4, $bi, $dst">; 1469 1470 let isReturn = 1, Uses = [LR, RM] in 1471 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1472 "bclr 12, $bi, 0", IIC_BrB, []>; 1473 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1474 "bclr 4, $bi, 0", IIC_BrB, []>; 1475 } 1476 1477 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1478 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1479 "bdzlr", IIC_BrB, []>; 1480 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1481 "bdnzlr", IIC_BrB, []>; 1482 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1483 "bdzlr+", IIC_BrB, []>; 1484 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1485 "bdnzlr+", IIC_BrB, []>; 1486 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1487 "bdzlr-", IIC_BrB, []>; 1488 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1489 "bdnzlr-", IIC_BrB, []>; 1490 } 1491 1492 let Defs = [CTR], Uses = [CTR] in { 1493 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1494 "bdz $dst">; 1495 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1496 "bdnz $dst">; 1497 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1498 "bdza $dst">; 1499 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1500 "bdnza $dst">; 1501 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1502 "bdz+ $dst">; 1503 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1504 "bdnz+ $dst">; 1505 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1506 "bdza+ $dst">; 1507 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1508 "bdnza+ $dst">; 1509 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1510 "bdz- $dst">; 1511 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1512 "bdnz- $dst">; 1513 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1514 "bdza- $dst">; 1515 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1516 "bdnza- $dst">; 1517 } 1518} 1519 1520// The unconditional BCL used by the SjLj setjmp code. 1521let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1522 let Defs = [LR], Uses = [RM] in { 1523 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1524 "bcl 20, 31, $dst">; 1525 } 1526} 1527 1528let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1529 // Convenient aliases for call instructions 1530 let Uses = [RM] in { 1531 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1532 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1533 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1534 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1535 1536 let isCodeGenOnly = 1 in { 1537 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1538 "bl $func", IIC_BrB, []>; 1539 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1540 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1541 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1542 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1543 1544 def BCL : BForm_4<16, 12, 0, 1, (outs), 1545 (ins crbitrc:$bi, condbrtarget:$dst), 1546 "bcl 12, $bi, $dst">; 1547 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1548 (ins crbitrc:$bi, condbrtarget:$dst), 1549 "bcl 4, $bi, $dst">; 1550 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1551 (outs), (ins calltarget:$func), 1552 "bl $func\n\tnop", IIC_BrB, []>; 1553 } 1554 } 1555 let Uses = [CTR, RM] in { 1556 let isPredicable = 1 in 1557 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1558 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1559 Requires<[In32BitMode]>; 1560 1561 let isCodeGenOnly = 1 in { 1562 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1563 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1564 []>; 1565 1566 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1567 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1568 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1569 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1570 } 1571 } 1572 let Uses = [LR, RM] in { 1573 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1574 "blrl", IIC_BrB, []>; 1575 1576 let isCodeGenOnly = 1 in { 1577 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1578 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1579 []>; 1580 1581 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1582 "bclrl 12, $bi, 0", IIC_BrB, []>; 1583 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1584 "bclrl 4, $bi, 0", IIC_BrB, []>; 1585 } 1586 } 1587 let Defs = [CTR], Uses = [CTR, RM] in { 1588 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1589 "bdzl $dst">; 1590 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1591 "bdnzl $dst">; 1592 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1593 "bdzla $dst">; 1594 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1595 "bdnzla $dst">; 1596 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1597 "bdzl+ $dst">; 1598 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1599 "bdnzl+ $dst">; 1600 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1601 "bdzla+ $dst">; 1602 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1603 "bdnzla+ $dst">; 1604 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1605 "bdzl- $dst">; 1606 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1607 "bdnzl- $dst">; 1608 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1609 "bdzla- $dst">; 1610 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1611 "bdnzla- $dst">; 1612 } 1613 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1614 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1615 "bdzlrl", IIC_BrB, []>; 1616 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1617 "bdnzlrl", IIC_BrB, []>; 1618 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1619 "bdzlrl+", IIC_BrB, []>; 1620 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1621 "bdnzlrl+", IIC_BrB, []>; 1622 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1623 "bdzlrl-", IIC_BrB, []>; 1624 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1625 "bdnzlrl-", IIC_BrB, []>; 1626 } 1627} 1628 1629let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1630def TCRETURNdi :PPCEmitTimePseudo< (outs), 1631 (ins calltarget:$dst, i32imm:$offset), 1632 "#TC_RETURNd $dst $offset", 1633 []>; 1634 1635 1636let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1637def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1638 "#TC_RETURNa $func $offset", 1639 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1640 1641let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1642def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1643 "#TC_RETURNr $dst $offset", 1644 []>; 1645 1646let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1647 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1648 def BCTRL_LWZinto_toc: 1649 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1650 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1651 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1652 1653} 1654 1655 1656let isCodeGenOnly = 1 in { 1657 1658let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1659 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1660def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1661 []>, Requires<[In32BitMode]>; 1662 1663let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1664 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1665def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1666 "b $dst", IIC_BrB, 1667 []>; 1668 1669let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1670 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1671def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1672 "ba $dst", IIC_BrB, 1673 []>; 1674 1675} 1676 1677// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1678// is not. 1679let hasSideEffects = 1 in { 1680 let Defs = [CTR] in 1681 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1682 "#EH_SJLJ_SETJMP32", 1683 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1684 Requires<[In32BitMode]>; 1685} 1686 1687let hasSideEffects = 1, isBarrier = 1 in { 1688 let isTerminator = 1 in 1689 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1690 "#EH_SJLJ_LONGJMP32", 1691 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1692 Requires<[In32BitMode]>; 1693} 1694 1695// This pseudo is never removed from the function, as it serves as 1696// a terminator. Size is set to 0 to prevent the builtin assembler 1697// from emitting it. 1698let isBranch = 1, isTerminator = 1, Size = 0 in { 1699 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1700 "#EH_SjLj_Setup\t$dst", []>; 1701} 1702 1703// System call. 1704let PPC970_Unit = 7 in { 1705 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1706 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1707} 1708 1709// Branch history rolling buffer. 1710def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1711 [(PPCclrbhrb)]>, 1712 PPC970_DGroup_Single; 1713// The $dmy argument used for MFBHRBE is not needed; however, including 1714// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1715// interferes with necessary special handling (see PPCFastISel.cpp). 1716def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1717 (ins u10imm:$imm, u10imm:$dmy), 1718 "mfbhrbe $rD, $imm", IIC_BrB, 1719 [(set i32:$rD, 1720 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1721 PPC970_DGroup_First; 1722 1723def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1724 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1725 PPC970_DGroup_Single; 1726 1727// DCB* instructions. 1728def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1729 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1730 PPC970_DGroup_Single; 1731def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1732 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1733 PPC970_DGroup_Single; 1734def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1735 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1736 PPC970_DGroup_Single; 1737def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1738 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1739 PPC970_DGroup_Single; 1740def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1741 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1742 PPC970_DGroup_Single; 1743 1744def DCBF : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst), 1745 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 1746 PPC970_DGroup_Single; 1747 1748let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1749def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1750 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1751 PPC970_DGroup_Single; 1752def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1753 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1754 PPC970_DGroup_Single; 1755} // hasSideEffects = 0 1756 1757def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 1758 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 1759def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 1760 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1761def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1762 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1763def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 1764 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1765 1766def : Pat<(int_ppc_dcbt xoaddr:$dst), 1767 (DCBT 0, xoaddr:$dst)>; 1768def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1769 (DCBTST 0, xoaddr:$dst)>; 1770def : Pat<(int_ppc_dcbf xoaddr:$dst), 1771 (DCBF 0, xoaddr:$dst)>; 1772 1773def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1774 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1775def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1776 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1777def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1778 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1779 1780// Atomic operations 1781// FIXME: some of these might be used with constant operands. This will result 1782// in constant materialization instructions that may be redundant. We currently 1783// clean this up in PPCMIPeephole with calls to 1784// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1785// in the first place. 1786let Defs = [CR0] in { 1787 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1788 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1789 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1790 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1791 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1792 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1793 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1794 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1795 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1796 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1797 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1798 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1799 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1800 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1801 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1802 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1803 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1804 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1805 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1806 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1807 [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>; 1808 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1809 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1810 [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>; 1811 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1812 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1813 [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>; 1814 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1815 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1816 [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>; 1817 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1818 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1819 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1820 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1821 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1822 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1823 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1824 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1825 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1826 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1827 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1828 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1829 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1830 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1831 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1832 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1833 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1834 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1835 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1836 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1837 [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>; 1838 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1839 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1840 [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>; 1841 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1842 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1843 [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>; 1844 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1845 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1846 [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>; 1847 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1848 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1849 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1850 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1851 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1852 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1853 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1854 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1855 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1856 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1857 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1858 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1859 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1860 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1861 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1862 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1863 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1864 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1865 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1866 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1867 [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>; 1868 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1869 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1870 [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>; 1871 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1872 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1873 [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>; 1874 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1875 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1876 [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>; 1877 1878 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1879 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1880 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1881 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1882 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1883 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1884 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1885 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1886 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1887 1888 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1889 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1890 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1891 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1892 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1893 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1894 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1895 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1896 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1897} 1898 1899def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new), 1900 (ATOMIC_CMP_SWAP_I8 xoaddr:$ptr, i32:$old, i32:$new)>; 1901def : Pat<(PPCatomicCmpSwap_16 xoaddr:$ptr, i32:$old, i32:$new), 1902 (ATOMIC_CMP_SWAP_I16 xoaddr:$ptr, i32:$old, i32:$new)>; 1903 1904// Instructions to support atomic operations 1905let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1906def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1907 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1908 Requires<[HasPartwordAtomics]>; 1909 1910def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1911 "lharx $rD, $src", IIC_LdStLWARX, []>, 1912 Requires<[HasPartwordAtomics]>; 1913 1914def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1915 "lwarx $rD, $src", IIC_LdStLWARX, []>; 1916 1917// Instructions to support lock versions of atomics 1918// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1919def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1920 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1921 Requires<[HasPartwordAtomics]>; 1922 1923def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1924 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1925 Requires<[HasPartwordAtomics]>; 1926 1927def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1928 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 1929 1930// The atomic instructions use the destination register as well as the next one 1931// or two registers in order (modulo 31). 1932let hasExtraSrcRegAllocReq = 1 in 1933def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 1934 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 1935 Requires<[IsISA3_0]>; 1936} 1937 1938let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1939def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 1940 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 1941 isRecordForm, Requires<[HasPartwordAtomics]>; 1942 1943def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 1944 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 1945 isRecordForm, Requires<[HasPartwordAtomics]>; 1946 1947def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1948 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 1949} 1950 1951let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1952def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 1953 "stwat $rS, $rA, $FC", IIC_LdStStore>, 1954 Requires<[IsISA3_0]>; 1955 1956let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1957def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1958 1959def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1960 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1961def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1962 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1963def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1964 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1965def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1966 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1967 1968//===----------------------------------------------------------------------===// 1969// PPC32 Load Instructions. 1970// 1971 1972// Unindexed (r+i) Loads. 1973let PPC970_Unit = 2 in { 1974def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1975 "lbz $rD, $src", IIC_LdStLoad, 1976 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 1977def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1978 "lha $rD, $src", IIC_LdStLHA, 1979 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 1980 PPC970_DGroup_Cracked; 1981def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1982 "lhz $rD, $src", IIC_LdStLoad, 1983 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 1984def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1985 "lwz $rD, $src", IIC_LdStLoad, 1986 [(set i32:$rD, (load iaddr:$src))]>; 1987 1988let Predicates = [HasFPU] in { 1989def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1990 "lfs $rD, $src", IIC_LdStLFD, 1991 [(set f32:$rD, (load iaddr:$src))]>; 1992def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1993 "lfd $rD, $src", IIC_LdStLFD, 1994 [(set f64:$rD, (load iaddr:$src))]>; 1995} 1996 1997 1998// Unindexed (r+i) Loads with Update (preinc). 1999let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2000def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2001 "lbzu $rD, $addr", IIC_LdStLoadUpd, 2002 []>, RegConstraint<"$addr.reg = $ea_result">, 2003 NoEncode<"$ea_result">; 2004 2005def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2006 "lhau $rD, $addr", IIC_LdStLHAU, 2007 []>, RegConstraint<"$addr.reg = $ea_result">, 2008 NoEncode<"$ea_result">; 2009 2010def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2011 "lhzu $rD, $addr", IIC_LdStLoadUpd, 2012 []>, RegConstraint<"$addr.reg = $ea_result">, 2013 NoEncode<"$ea_result">; 2014 2015def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2016 "lwzu $rD, $addr", IIC_LdStLoadUpd, 2017 []>, RegConstraint<"$addr.reg = $ea_result">, 2018 NoEncode<"$ea_result">; 2019 2020let Predicates = [HasFPU] in { 2021def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2022 "lfsu $rD, $addr", IIC_LdStLFDU, 2023 []>, RegConstraint<"$addr.reg = $ea_result">, 2024 NoEncode<"$ea_result">; 2025 2026def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2027 "lfdu $rD, $addr", IIC_LdStLFDU, 2028 []>, RegConstraint<"$addr.reg = $ea_result">, 2029 NoEncode<"$ea_result">; 2030} 2031 2032 2033// Indexed (r+r) Loads with Update (preinc). 2034def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2035 (ins memrr:$addr), 2036 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 2037 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2038 NoEncode<"$ea_result">; 2039 2040def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2041 (ins memrr:$addr), 2042 "lhaux $rD, $addr", IIC_LdStLHAUX, 2043 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2044 NoEncode<"$ea_result">; 2045 2046def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2047 (ins memrr:$addr), 2048 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 2049 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2050 NoEncode<"$ea_result">; 2051 2052def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2053 (ins memrr:$addr), 2054 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 2055 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2056 NoEncode<"$ea_result">; 2057 2058let Predicates = [HasFPU] in { 2059def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 2060 (ins memrr:$addr), 2061 "lfsux $rD, $addr", IIC_LdStLFDUX, 2062 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2063 NoEncode<"$ea_result">; 2064 2065def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 2066 (ins memrr:$addr), 2067 "lfdux $rD, $addr", IIC_LdStLFDUX, 2068 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2069 NoEncode<"$ea_result">; 2070} 2071} 2072} 2073 2074// Indexed (r+r) Loads. 2075// 2076let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2077def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 2078 "lbzx $rD, $src", IIC_LdStLoad, 2079 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 2080def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 2081 "lhax $rD, $src", IIC_LdStLHA, 2082 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 2083 PPC970_DGroup_Cracked; 2084def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 2085 "lhzx $rD, $src", IIC_LdStLoad, 2086 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 2087def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 2088 "lwzx $rD, $src", IIC_LdStLoad, 2089 [(set i32:$rD, (load xaddr:$src))]>; 2090def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 2091 "lhbrx $rD, $src", IIC_LdStLoad, 2092 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 2093def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 2094 "lwbrx $rD, $src", IIC_LdStLoad, 2095 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 2096 2097let Predicates = [HasFPU] in { 2098def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 2099 "lfsx $frD, $src", IIC_LdStLFD, 2100 [(set f32:$frD, (load xaddr:$src))]>; 2101def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 2102 "lfdx $frD, $src", IIC_LdStLFD, 2103 [(set f64:$frD, (load xaddr:$src))]>; 2104 2105def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 2106 "lfiwax $frD, $src", IIC_LdStLFD, 2107 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 2108def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 2109 "lfiwzx $frD, $src", IIC_LdStLFD, 2110 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 2111} 2112} 2113 2114// Load Multiple 2115let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2116def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 2117 "lmw $rD, $src", IIC_LdStLMW, []>; 2118 2119//===----------------------------------------------------------------------===// 2120// PPC32 Store Instructions. 2121// 2122 2123// Unindexed (r+i) Stores. 2124let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2125def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 2126 "stb $rS, $dst", IIC_LdStStore, 2127 [(truncstorei8 i32:$rS, iaddr:$dst)]>; 2128def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 2129 "sth $rS, $dst", IIC_LdStStore, 2130 [(truncstorei16 i32:$rS, iaddr:$dst)]>; 2131def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 2132 "stw $rS, $dst", IIC_LdStStore, 2133 [(store i32:$rS, iaddr:$dst)]>; 2134let Predicates = [HasFPU] in { 2135def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 2136 "stfs $rS, $dst", IIC_LdStSTFD, 2137 [(store f32:$rS, iaddr:$dst)]>; 2138def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 2139 "stfd $rS, $dst", IIC_LdStSTFD, 2140 [(store f64:$rS, iaddr:$dst)]>; 2141} 2142} 2143 2144// Unindexed (r+i) Stores with Update (preinc). 2145let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2146def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2147 "stbu $rS, $dst", IIC_LdStSTU, []>, 2148 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2149def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2150 "sthu $rS, $dst", IIC_LdStSTU, []>, 2151 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2152def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2153 "stwu $rS, $dst", IIC_LdStSTU, []>, 2154 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2155let Predicates = [HasFPU] in { 2156def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 2157 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 2158 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2159def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 2160 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 2161 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2162} 2163} 2164 2165// Patterns to match the pre-inc stores. We can't put the patterns on 2166// the instruction definitions directly as ISel wants the address base 2167// and offset to be separate operands, not a single complex operand. 2168def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2169 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2170def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2171 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2172def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2173 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2174def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2175 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2176def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2177 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2178 2179// Indexed (r+r) Stores. 2180let PPC970_Unit = 2 in { 2181def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 2182 "stbx $rS, $dst", IIC_LdStStore, 2183 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 2184 PPC970_DGroup_Cracked; 2185def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2186 "sthx $rS, $dst", IIC_LdStStore, 2187 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 2188 PPC970_DGroup_Cracked; 2189def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2190 "stwx $rS, $dst", IIC_LdStStore, 2191 [(store i32:$rS, xaddr:$dst)]>, 2192 PPC970_DGroup_Cracked; 2193 2194def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2195 "sthbrx $rS, $dst", IIC_LdStStore, 2196 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 2197 PPC970_DGroup_Cracked; 2198def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2199 "stwbrx $rS, $dst", IIC_LdStStore, 2200 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 2201 PPC970_DGroup_Cracked; 2202 2203let Predicates = [HasFPU] in { 2204def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2205 "stfiwx $frS, $dst", IIC_LdStSTFD, 2206 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 2207 2208def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2209 "stfsx $frS, $dst", IIC_LdStSTFD, 2210 [(store f32:$frS, xaddr:$dst)]>; 2211def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2212 "stfdx $frS, $dst", IIC_LdStSTFD, 2213 [(store f64:$frS, xaddr:$dst)]>; 2214} 2215} 2216 2217// Indexed (r+r) Stores with Update (preinc). 2218let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2219def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2220 (ins gprc:$rS, memrr:$dst), 2221 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2222 RegConstraint<"$dst.ptrreg = $ea_res">, 2223 NoEncode<"$ea_res">, 2224 PPC970_DGroup_Cracked; 2225def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2226 (ins gprc:$rS, memrr:$dst), 2227 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2228 RegConstraint<"$dst.ptrreg = $ea_res">, 2229 NoEncode<"$ea_res">, 2230 PPC970_DGroup_Cracked; 2231def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2232 (ins gprc:$rS, memrr:$dst), 2233 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2234 RegConstraint<"$dst.ptrreg = $ea_res">, 2235 NoEncode<"$ea_res">, 2236 PPC970_DGroup_Cracked; 2237let Predicates = [HasFPU] in { 2238def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2239 (ins f4rc:$rS, memrr:$dst), 2240 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2241 RegConstraint<"$dst.ptrreg = $ea_res">, 2242 NoEncode<"$ea_res">, 2243 PPC970_DGroup_Cracked; 2244def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2245 (ins f8rc:$rS, memrr:$dst), 2246 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2247 RegConstraint<"$dst.ptrreg = $ea_res">, 2248 NoEncode<"$ea_res">, 2249 PPC970_DGroup_Cracked; 2250} 2251} 2252 2253// Patterns to match the pre-inc stores. We can't put the patterns on 2254// the instruction definitions directly as ISel wants the address base 2255// and offset to be separate operands, not a single complex operand. 2256def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2257 (STBUX $rS, $ptrreg, $ptroff)>; 2258def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2259 (STHUX $rS, $ptrreg, $ptroff)>; 2260def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2261 (STWUX $rS, $ptrreg, $ptroff)>; 2262let Predicates = [HasFPU] in { 2263def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2264 (STFSUX $rS, $ptrreg, $ptroff)>; 2265def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2266 (STFDUX $rS, $ptrreg, $ptroff)>; 2267} 2268 2269// Store Multiple 2270let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2271def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2272 "stmw $rS, $dst", IIC_LdStLMW, []>; 2273 2274def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 2275 "sync $L", IIC_LdStSync, []>; 2276 2277let isCodeGenOnly = 1 in { 2278 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2279 "msync", IIC_LdStSync, []> { 2280 let L = 0; 2281 } 2282} 2283 2284def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2285def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2286def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2287def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2288 2289//===----------------------------------------------------------------------===// 2290// PPC32 Arithmetic Instructions. 2291// 2292 2293let PPC970_Unit = 1 in { // FXU Operations. 2294def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2295 "addi $rD, $rA, $imm", IIC_IntSimple, 2296 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2297let BaseName = "addic" in { 2298let Defs = [CARRY] in 2299def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2300 "addic $rD, $rA, $imm", IIC_IntGeneral, 2301 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2302 RecFormRel, PPC970_DGroup_Cracked; 2303let Defs = [CARRY, CR0] in 2304def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2305 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2306 []>, isRecordForm, RecFormRel; 2307} 2308def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2309 "addis $rD, $rA, $imm", IIC_IntSimple, 2310 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2311let isCodeGenOnly = 1 in 2312def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2313 "la $rD, $sym($rA)", IIC_IntGeneral, 2314 [(set i32:$rD, (add i32:$rA, 2315 (PPClo tglobaladdr:$sym, 0)))]>; 2316def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2317 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2318 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2319let Defs = [CARRY] in 2320def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2321 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2322 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2323 2324let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2325 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2326 "li $rD, $imm", IIC_IntSimple, 2327 [(set i32:$rD, imm32SExt16:$imm)]>; 2328 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2329 "lis $rD, $imm", IIC_IntSimple, 2330 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2331} 2332} 2333 2334let PPC970_Unit = 1 in { // FXU Operations. 2335let Defs = [CR0] in { 2336def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2337 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2338 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2339 isRecordForm; 2340def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2341 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2342 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2343 isRecordForm; 2344} 2345def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2346 "ori $dst, $src1, $src2", IIC_IntSimple, 2347 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2348def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2349 "oris $dst, $src1, $src2", IIC_IntSimple, 2350 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2351def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2352 "xori $dst, $src1, $src2", IIC_IntSimple, 2353 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2354def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2355 "xoris $dst, $src1, $src2", IIC_IntSimple, 2356 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2357 2358def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2359 []>; 2360let isCodeGenOnly = 1 in { 2361// The POWER6 and POWER7 have special group-terminating nops. 2362def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2363 "ori 1, 1, 0", IIC_IntSimple, []>; 2364def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2365 "ori 2, 2, 0", IIC_IntSimple, []>; 2366} 2367 2368let isCompare = 1, hasSideEffects = 0 in { 2369 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2370 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2371 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2372 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2373 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 2374 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 2375 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2376 Requires<[IsISA3_0]>; 2377} 2378} 2379 2380let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2381let isCommutable = 1 in { 2382defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2383 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2384 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2385defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2386 "and", "$rA, $rS, $rB", IIC_IntSimple, 2387 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2388} // isCommutable 2389defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2390 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2391 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2392let isCommutable = 1 in { 2393defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2394 "or", "$rA, $rS, $rB", IIC_IntSimple, 2395 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2396defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2397 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2398 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2399} // isCommutable 2400defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2401 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2402 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2403let isCommutable = 1 in { 2404defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2405 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2406 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2407defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2408 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2409 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2410} // isCommutable 2411defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2412 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2413 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2414defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2415 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2416 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2417defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2418 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2419 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2420} 2421 2422let PPC970_Unit = 1 in { // FXU Operations. 2423let hasSideEffects = 0 in { 2424defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2425 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2426 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2427defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2428 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2429 [(set i32:$rA, (ctlz i32:$rS))]>; 2430defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2431 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2432 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2433defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2434 "extsb", "$rA, $rS", IIC_IntSimple, 2435 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2436defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2437 "extsh", "$rA, $rS", IIC_IntSimple, 2438 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2439 2440let isCommutable = 1 in 2441def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2442 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2443 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2444} 2445let isCompare = 1, hasSideEffects = 0 in { 2446 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2447 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2448 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2449 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2450} 2451} 2452let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2453//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 2454// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2455let isCompare = 1, hasSideEffects = 0 in { 2456 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2457 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2458 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2459 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2460 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2461} 2462 2463def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2464 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2465def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2466 "ftsqrt $crD, $fB", IIC_FPCompare>; 2467 2468let Uses = [RM] in { 2469 let hasSideEffects = 0 in { 2470 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2471 "fctiw", "$frD, $frB", IIC_FPGeneral, 2472 []>; 2473 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2474 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2475 []>; 2476 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2477 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2478 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 2479 2480 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2481 "frsp", "$frD, $frB", IIC_FPGeneral, 2482 [(set f32:$frD, (fpround f64:$frB))]>; 2483 2484 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2485 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2486 "frin", "$frD, $frB", IIC_FPGeneral, 2487 [(set f64:$frD, (fround f64:$frB))]>; 2488 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2489 "frin", "$frD, $frB", IIC_FPGeneral, 2490 [(set f32:$frD, (fround f32:$frB))]>; 2491 } 2492 2493 let hasSideEffects = 0 in { 2494 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2495 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2496 "frip", "$frD, $frB", IIC_FPGeneral, 2497 [(set f64:$frD, (fceil f64:$frB))]>; 2498 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2499 "frip", "$frD, $frB", IIC_FPGeneral, 2500 [(set f32:$frD, (fceil f32:$frB))]>; 2501 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2502 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2503 "friz", "$frD, $frB", IIC_FPGeneral, 2504 [(set f64:$frD, (ftrunc f64:$frB))]>; 2505 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2506 "friz", "$frD, $frB", IIC_FPGeneral, 2507 [(set f32:$frD, (ftrunc f32:$frB))]>; 2508 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2509 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2510 "frim", "$frD, $frB", IIC_FPGeneral, 2511 [(set f64:$frD, (ffloor f64:$frB))]>; 2512 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2513 "frim", "$frD, $frB", IIC_FPGeneral, 2514 [(set f32:$frD, (ffloor f32:$frB))]>; 2515 2516 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2517 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2518 [(set f64:$frD, (fsqrt f64:$frB))]>; 2519 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2520 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2521 [(set f32:$frD, (fsqrt f32:$frB))]>; 2522 } 2523 } 2524} 2525 2526/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2527/// often coalesced away and we don't want the dispatch group builder to think 2528/// that they will fill slots (which could cause the load of a LSU reject to 2529/// sneak into a d-group with a store). 2530let hasSideEffects = 0, Predicates = [HasFPU] in 2531defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2532 "fmr", "$frD, $frB", IIC_FPGeneral, 2533 []>, // (set f32:$frD, f32:$frB) 2534 PPC970_Unit_Pseudo; 2535 2536let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2537// These are artificially split into two different forms, for 4/8 byte FP. 2538defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2539 "fabs", "$frD, $frB", IIC_FPGeneral, 2540 [(set f32:$frD, (fabs f32:$frB))]>; 2541let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2542defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2543 "fabs", "$frD, $frB", IIC_FPGeneral, 2544 [(set f64:$frD, (fabs f64:$frB))]>; 2545defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2546 "fnabs", "$frD, $frB", IIC_FPGeneral, 2547 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2548let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2549defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2550 "fnabs", "$frD, $frB", IIC_FPGeneral, 2551 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2552defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2553 "fneg", "$frD, $frB", IIC_FPGeneral, 2554 [(set f32:$frD, (fneg f32:$frB))]>; 2555let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2556defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2557 "fneg", "$frD, $frB", IIC_FPGeneral, 2558 [(set f64:$frD, (fneg f64:$frB))]>; 2559 2560defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2561 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2562 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2563let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2564defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2565 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2566 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2567 2568// Reciprocal estimates. 2569defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2570 "fre", "$frD, $frB", IIC_FPGeneral, 2571 [(set f64:$frD, (PPCfre f64:$frB))]>; 2572defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2573 "fres", "$frD, $frB", IIC_FPGeneral, 2574 [(set f32:$frD, (PPCfre f32:$frB))]>; 2575defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2576 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2577 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2578defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2579 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2580 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2581} 2582 2583// XL-Form instructions. condition register logical ops. 2584// 2585let hasSideEffects = 0 in 2586def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2587 "mcrf $BF, $BFA", IIC_BrMCR>, 2588 PPC970_DGroup_First, PPC970_Unit_CRU; 2589 2590// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2591// condition-register logical instructions have preferred forms. Specifically, 2592// it is preferred that the bit specified by the BT field be in the same 2593// condition register as that specified by the bit BB. We might want to account 2594// for this via hinting the register allocator and anti-dep breakers, or we 2595// could constrain the register class to force this constraint and then loosen 2596// it during register allocation via convertToThreeAddress or some similar 2597// mechanism. 2598 2599let isCommutable = 1 in { 2600def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2601 (ins crbitrc:$CRA, crbitrc:$CRB), 2602 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2603 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2604 2605def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2606 (ins crbitrc:$CRA, crbitrc:$CRB), 2607 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2608 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2609 2610def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2611 (ins crbitrc:$CRA, crbitrc:$CRB), 2612 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2613 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2614 2615def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2616 (ins crbitrc:$CRA, crbitrc:$CRB), 2617 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2618 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2619 2620def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2621 (ins crbitrc:$CRA, crbitrc:$CRB), 2622 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2623 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2624 2625def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2626 (ins crbitrc:$CRA, crbitrc:$CRB), 2627 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2628 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2629} // isCommutable 2630 2631def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2632 (ins crbitrc:$CRA, crbitrc:$CRB), 2633 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2634 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2635 2636def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2637 (ins crbitrc:$CRA, crbitrc:$CRB), 2638 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2639 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2640 2641let isCodeGenOnly = 1 in { 2642let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2643def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2644 "creqv $dst, $dst, $dst", IIC_BrCR, 2645 [(set i1:$dst, 1)]>; 2646 2647def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2648 "crxor $dst, $dst, $dst", IIC_BrCR, 2649 [(set i1:$dst, 0)]>; 2650} 2651 2652let Defs = [CR1EQ], CRD = 6 in { 2653def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2654 "creqv 6, 6, 6", IIC_BrCR, 2655 [(PPCcr6set)]>; 2656 2657def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2658 "crxor 6, 6, 6", IIC_BrCR, 2659 [(PPCcr6unset)]>; 2660} 2661} 2662 2663// XFX-Form instructions. Instructions that deal with SPRs. 2664// 2665 2666def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2667 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2668def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2669 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2670 2671def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2672 "mftb $RT, $SPR", IIC_SprMFTB>; 2673 2674def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2675 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2676 2677def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2678 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 2679 2680 2681// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2682// on a 32-bit target. 2683let hasSideEffects = 1 in 2684def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2685 "#ReadTB", []>; 2686 2687let Uses = [CTR] in { 2688def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2689 "mfctr $rT", IIC_SprMFSPR>, 2690 PPC970_DGroup_First, PPC970_Unit_FXU; 2691} 2692let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2693def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2694 "mtctr $rS", IIC_SprMTSPR>, 2695 PPC970_DGroup_First, PPC970_Unit_FXU; 2696} 2697let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2698let Pattern = [(int_set_loop_iterations i32:$rS)] in 2699def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2700 "mtctr $rS", IIC_SprMTSPR>, 2701 PPC970_DGroup_First, PPC970_Unit_FXU; 2702} 2703 2704let hasSideEffects = 0 in { 2705let Defs = [LR] in { 2706def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2707 "mtlr $rS", IIC_SprMTSPR>, 2708 PPC970_DGroup_First, PPC970_Unit_FXU; 2709} 2710let Uses = [LR] in { 2711def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2712 "mflr $rT", IIC_SprMFSPR>, 2713 PPC970_DGroup_First, PPC970_Unit_FXU; 2714} 2715} 2716 2717let isCodeGenOnly = 1 in { 2718 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2719 // like a GPR on the PPC970. As such, copies in and out have the same 2720 // performance characteristics as an OR instruction. 2721 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2722 "mtspr 256, $rS", IIC_IntGeneral>, 2723 PPC970_DGroup_Single, PPC970_Unit_FXU; 2724 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2725 "mfspr $rT, 256", IIC_IntGeneral>, 2726 PPC970_DGroup_First, PPC970_Unit_FXU; 2727 2728 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2729 (outs VRSAVERC:$reg), (ins gprc:$rS), 2730 "mtspr 256, $rS", IIC_IntGeneral>, 2731 PPC970_DGroup_Single, PPC970_Unit_FXU; 2732 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2733 (ins VRSAVERC:$reg), 2734 "mfspr $rT, 256", IIC_IntGeneral>, 2735 PPC970_DGroup_First, PPC970_Unit_FXU; 2736} 2737 2738// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2739def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2740def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2741 2742// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2743// so we'll need to scavenge a register for it. 2744let mayStore = 1 in 2745def SPILL_VRSAVE : PPCEmitTimePseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2746 "#SPILL_VRSAVE", []>; 2747 2748// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2749// spilled), so we'll need to scavenge a register for it. 2750let mayLoad = 1 in 2751def RESTORE_VRSAVE : PPCEmitTimePseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2752 "#RESTORE_VRSAVE", []>; 2753 2754let hasSideEffects = 0 in { 2755// mtocrf's input needs to be prepared by shifting by an amount dependent 2756// on the cr register selected. Thus, post-ra anti-dep breaking must not 2757// later change that register assignment. 2758let hasExtraDefRegAllocReq = 1 in { 2759def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2760 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2761 PPC970_DGroup_First, PPC970_Unit_CRU; 2762 2763// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2764// is dependent on the cr fields being set. 2765def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2766 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2767 PPC970_MicroCode, PPC970_Unit_CRU; 2768} // hasExtraDefRegAllocReq = 1 2769 2770// mfocrf's input needs to be prepared by shifting by an amount dependent 2771// on the cr register selected. Thus, post-ra anti-dep breaking must not 2772// later change that register assignment. 2773let hasExtraSrcRegAllocReq = 1 in { 2774def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2775 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2776 PPC970_DGroup_First, PPC970_Unit_CRU; 2777 2778// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2779// is dependent on the cr fields being copied. 2780def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2781 "mfcr $rT", IIC_SprMFCR>, 2782 PPC970_MicroCode, PPC970_Unit_CRU; 2783} // hasExtraSrcRegAllocReq = 1 2784 2785def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2786 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2787} // hasSideEffects = 0 2788 2789let Predicates = [HasFPU] in { 2790// Custom inserter instruction to perform FADD in round-to-zero mode. 2791let Uses = [RM] in { 2792 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2793 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2794} 2795 2796// The above pseudo gets expanded to make use of the following instructions 2797// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2798let Uses = [RM], Defs = [RM] in { 2799 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2800 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2801 PPC970_DGroup_Single, PPC970_Unit_FPU; 2802 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2803 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2804 PPC970_DGroup_Single, PPC970_Unit_FPU; 2805 let isCodeGenOnly = 1 in 2806 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2807 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2808 PPC970_DGroup_Single, PPC970_Unit_FPU; 2809} 2810let Uses = [RM] in { 2811 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2812 "mffs $rT", IIC_IntMFFS, 2813 [(set f64:$rT, (PPCmffs))]>, 2814 PPC970_DGroup_Single, PPC970_Unit_FPU; 2815 2816 let Defs = [CR1] in 2817 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2818 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 2819 2820 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 2821 "mffsce $rT", IIC_IntMFFS, []>, 2822 PPC970_DGroup_Single, PPC970_Unit_FPU; 2823 2824 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 2825 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 2826 IIC_IntMFFS, []>, 2827 PPC970_DGroup_Single, PPC970_Unit_FPU; 2828 2829 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 2830 (ins u3imm:$DRM), 2831 "mffscdrni $rT, $DRM", 2832 IIC_IntMFFS, []>, 2833 PPC970_DGroup_Single, PPC970_Unit_FPU; 2834 2835 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 2836 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 2837 IIC_IntMFFS, []>, 2838 PPC970_DGroup_Single, PPC970_Unit_FPU; 2839 2840 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 2841 (ins u2imm:$RM), "mffscrni $rT, $RM", 2842 IIC_IntMFFS, []>, 2843 PPC970_DGroup_Single, PPC970_Unit_FPU; 2844 2845 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 2846 "mffsl $rT", IIC_IntMFFS, []>, 2847 PPC970_DGroup_Single, PPC970_Unit_FPU; 2848} 2849} 2850 2851let Predicates = [IsISA3_0] in { 2852def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2853 "modsw $rT, $rA, $rB", IIC_IntDivW, 2854 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 2855def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2856 "moduw $rT, $rA, $rB", IIC_IntDivW, 2857 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 2858} 2859 2860let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2861// XO-Form instructions. Arithmetic instructions that can set overflow bit 2862let isCommutable = 1 in 2863defm ADD4 : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2864 "add", "$rT, $rA, $rB", IIC_IntSimple, 2865 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2866let isCodeGenOnly = 1 in 2867def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2868 "add $rT, $rA, $rB", IIC_IntSimple, 2869 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2870let isCommutable = 1 in 2871defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2872 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2873 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2874 PPC970_DGroup_Cracked; 2875 2876defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2877 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2878 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2879defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2880 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2881 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 2882defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2883 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 2884 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 2885 Requires<[HasExtDiv]>; 2886defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2887 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 2888 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 2889 Requires<[HasExtDiv]>; 2890let isCommutable = 1 in { 2891defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2892 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2893 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2894defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2895 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2896 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2897defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2898 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2899 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2900} // isCommutable 2901defm SUBF : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2902 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2903 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2904defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2905 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2906 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2907 PPC970_DGroup_Cracked; 2908defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2909 "neg", "$rT, $rA", IIC_IntSimple, 2910 [(set i32:$rT, (ineg i32:$rA))]>; 2911let Uses = [CARRY] in { 2912let isCommutable = 1 in 2913defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2914 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2915 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2916defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2917 "addme", "$rT, $rA", IIC_IntGeneral, 2918 [(set i32:$rT, (adde i32:$rA, -1))]>; 2919defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2920 "addze", "$rT, $rA", IIC_IntGeneral, 2921 [(set i32:$rT, (adde i32:$rA, 0))]>; 2922defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2923 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2924 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2925defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2926 "subfme", "$rT, $rA", IIC_IntGeneral, 2927 [(set i32:$rT, (sube -1, i32:$rA))]>; 2928defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2929 "subfze", "$rT, $rA", IIC_IntGeneral, 2930 [(set i32:$rT, (sube 0, i32:$rA))]>; 2931} 2932} 2933 2934// A-Form instructions. Most of the instructions executed in the FPU are of 2935// this type. 2936// 2937let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2938let Uses = [RM] in { 2939let isCommutable = 1 in { 2940 defm FMADD : AForm_1r<63, 29, 2941 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2942 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2943 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2944 defm FMADDS : AForm_1r<59, 29, 2945 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2946 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2947 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2948 defm FMSUB : AForm_1r<63, 28, 2949 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2950 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2951 [(set f64:$FRT, 2952 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2953 defm FMSUBS : AForm_1r<59, 28, 2954 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2955 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2956 [(set f32:$FRT, 2957 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2958 defm FNMADD : AForm_1r<63, 31, 2959 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2960 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2961 [(set f64:$FRT, 2962 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2963 defm FNMADDS : AForm_1r<59, 31, 2964 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2965 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2966 [(set f32:$FRT, 2967 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2968 defm FNMSUB : AForm_1r<63, 30, 2969 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2970 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2971 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 2972 (fneg f64:$FRB))))]>; 2973 defm FNMSUBS : AForm_1r<59, 30, 2974 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2975 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2976 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 2977 (fneg f32:$FRB))))]>; 2978} // isCommutable 2979} 2980// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2981// having 4 of these, force the comparison to always be an 8-byte double (code 2982// should use an FMRSD if the input comparison value really wants to be a float) 2983// and 4/8 byte forms for the result and operand type.. 2984let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2985defm FSELD : AForm_1r<63, 23, 2986 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2987 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2988 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2989defm FSELS : AForm_1r<63, 23, 2990 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2991 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2992 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2993let Uses = [RM] in { 2994 let isCommutable = 1 in { 2995 defm FADD : AForm_2r<63, 21, 2996 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2997 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2998 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 2999 defm FADDS : AForm_2r<59, 21, 3000 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3001 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3002 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 3003 } // isCommutable 3004 defm FDIV : AForm_2r<63, 18, 3005 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3006 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3007 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 3008 defm FDIVS : AForm_2r<59, 18, 3009 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3010 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3011 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 3012 let isCommutable = 1 in { 3013 defm FMUL : AForm_3r<63, 25, 3014 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3015 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3016 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 3017 defm FMULS : AForm_3r<59, 25, 3018 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3019 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3020 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 3021 } // isCommutable 3022 defm FSUB : AForm_2r<63, 20, 3023 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3024 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3025 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 3026 defm FSUBS : AForm_2r<59, 20, 3027 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3028 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3029 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 3030 } 3031} 3032 3033let hasSideEffects = 0 in { 3034let PPC970_Unit = 1 in { // FXU Operations. 3035 let isSelect = 1 in 3036 def ISEL : AForm_4<31, 15, 3037 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 3038 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 3039 []>; 3040} 3041 3042let PPC970_Unit = 1 in { // FXU Operations. 3043// M-Form instructions. rotate and mask instructions. 3044// 3045let isCommutable = 1 in { 3046// RLWIMI can be commuted if the rotate amount is zero. 3047defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 3048 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 3049 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 3050 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3051 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 3052} 3053let BaseName = "rlwinm" in { 3054def RLWINM : MForm_2<21, 3055 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3056 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3057 []>, RecFormRel; 3058let Defs = [CR0] in 3059def RLWINM_rec : MForm_2<21, 3060 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3061 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3062 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3063} 3064defm RLWNM : MForm_2r<23, (outs gprc:$rA), 3065 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 3066 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 3067 []>; 3068} 3069} // hasSideEffects = 0 3070 3071//===----------------------------------------------------------------------===// 3072// PowerPC Instruction Patterns 3073// 3074 3075// Arbitrary immediate support. Implement in terms of LIS/ORI. 3076def : Pat<(i32 imm:$imm), 3077 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3078 3079// Implement the 'not' operation with the NOR instruction. 3080def i32not : OutPatFrag<(ops node:$in), 3081 (NOR $in, $in)>; 3082def : Pat<(not i32:$in), 3083 (i32not $in)>; 3084 3085// ADD an arbitrary immediate. 3086def : Pat<(add i32:$in, imm:$imm), 3087 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3088// OR an arbitrary immediate. 3089def : Pat<(or i32:$in, imm:$imm), 3090 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3091// XOR an arbitrary immediate. 3092def : Pat<(xor i32:$in, imm:$imm), 3093 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3094// SUBFIC 3095def : Pat<(sub imm32SExt16:$imm, i32:$in), 3096 (SUBFIC $in, imm:$imm)>; 3097 3098// SHL/SRL 3099def : Pat<(shl i32:$in, (i32 imm:$imm)), 3100 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3101def : Pat<(srl i32:$in, (i32 imm:$imm)), 3102 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3103 3104// ROTL 3105def : Pat<(rotl i32:$in, i32:$sh), 3106 (RLWNM $in, $sh, 0, 31)>; 3107def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3108 (RLWINM $in, imm:$imm, 0, 31)>; 3109 3110// RLWNM 3111def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3112 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3113 3114// Calls 3115def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3116 (BL tglobaladdr:$dst)>; 3117 3118def : Pat<(PPCcall (i32 texternalsym:$dst)), 3119 (BL texternalsym:$dst)>; 3120 3121// Calls for AIX only 3122def : Pat<(PPCcall (i32 mcsym:$dst)), 3123 (BL mcsym:$dst)>; 3124def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3125 (BL_NOP mcsym:$dst)>; 3126 3127def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3128 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3129 3130def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3131 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3132 3133def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3134 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3135 3136 3137 3138// Hi and Lo for Darwin Global Addresses. 3139def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3140def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3141def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3142def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3143def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3144def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3145def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3146def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3147def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3148 (ADDIS $in, tglobaltlsaddr:$g)>; 3149def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3150 (ADDI $in, tglobaltlsaddr:$g)>; 3151def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3152 (ADDIS $in, tglobaladdr:$g)>; 3153def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3154 (ADDIS $in, tconstpool:$g)>; 3155def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3156 (ADDIS $in, tjumptable:$g)>; 3157def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3158 (ADDIS $in, tblockaddress:$g)>; 3159 3160// Support for thread-local storage. 3161def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3162 [(set i32:$rD, (PPCppc32GOT))]>; 3163 3164// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3165// This uses two output registers, the first as the real output, the second as a 3166// temporary register, used internally in code generation. 3167def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3168 []>, NoEncode<"$rT">; 3169 3170def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3171 "#LDgotTprelL32", 3172 [(set i32:$rD, 3173 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3174def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3175 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3176 3177def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3178 "#ADDItlsgdL32", 3179 [(set i32:$rD, 3180 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3181// LR is a true define, while the rest of the Defs are clobbers. R3 is 3182// explicitly defined when this op is created, so not mentioned here. 3183let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3184 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3185def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3186 "GETtlsADDR32", 3187 [(set i32:$rD, 3188 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3189// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3190// are true defines while the rest of the Defs are clobbers. 3191let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3192 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3193def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3194 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3195 "#ADDItlsgdLADDR32", 3196 [(set i32:$rD, 3197 (PPCaddiTlsgdLAddr i32:$reg, 3198 tglobaltlsaddr:$disp, 3199 tglobaltlsaddr:$sym))]>; 3200def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3201 "#ADDItlsldL32", 3202 [(set i32:$rD, 3203 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3204// LR is a true define, while the rest of the Defs are clobbers. R3 is 3205// explicitly defined when this op is created, so not mentioned here. 3206let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3207 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3208def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3209 "GETtlsldADDR32", 3210 [(set i32:$rD, 3211 (PPCgetTlsldAddr i32:$reg, 3212 tglobaltlsaddr:$sym))]>; 3213// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3214// are true defines while the rest of the Defs are clobbers. 3215let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3216 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3217def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3218 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3219 "#ADDItlsldLADDR32", 3220 [(set i32:$rD, 3221 (PPCaddiTlsldLAddr i32:$reg, 3222 tglobaltlsaddr:$disp, 3223 tglobaltlsaddr:$sym))]>; 3224def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3225 "#ADDIdtprelL32", 3226 [(set i32:$rD, 3227 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3228def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3229 "#ADDISdtprelHA32", 3230 [(set i32:$rD, 3231 (PPCaddisDtprelHA i32:$reg, 3232 tglobaltlsaddr:$disp))]>; 3233 3234// Support for Position-independent code 3235def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3236 "#LWZtoc", 3237 [(set i32:$rD, 3238 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3239def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3240 "#LWZtocL", 3241 [(set i32:$rD, 3242 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3243def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3244 "#ADDIStocHA", 3245 [(set i32:$rD, 3246 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3247 3248// Get Global (GOT) Base Register offset, from the word immediately preceding 3249// the function label. 3250def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3251 3252// Pseudo-instruction marked for deletion. When deleting the instruction would 3253// cause iterator invalidation in MIR transformation passes, this pseudo can be 3254// used instead. It will be removed unconditionally at pre-emit time (prior to 3255// branch selection). 3256def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3257 3258// Standard shifts. These are represented separately from the real shifts above 3259// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3260// amounts. 3261def : Pat<(sra i32:$rS, i32:$rB), 3262 (SRAW $rS, $rB)>; 3263def : Pat<(srl i32:$rS, i32:$rB), 3264 (SRW $rS, $rB)>; 3265def : Pat<(shl i32:$rS, i32:$rB), 3266 (SLW $rS, $rB)>; 3267 3268def : Pat<(i32 (zextloadi1 iaddr:$src)), 3269 (LBZ iaddr:$src)>; 3270def : Pat<(i32 (zextloadi1 xaddr:$src)), 3271 (LBZX xaddr:$src)>; 3272def : Pat<(i32 (extloadi1 iaddr:$src)), 3273 (LBZ iaddr:$src)>; 3274def : Pat<(i32 (extloadi1 xaddr:$src)), 3275 (LBZX xaddr:$src)>; 3276def : Pat<(i32 (extloadi8 iaddr:$src)), 3277 (LBZ iaddr:$src)>; 3278def : Pat<(i32 (extloadi8 xaddr:$src)), 3279 (LBZX xaddr:$src)>; 3280def : Pat<(i32 (extloadi16 iaddr:$src)), 3281 (LHZ iaddr:$src)>; 3282def : Pat<(i32 (extloadi16 xaddr:$src)), 3283 (LHZX xaddr:$src)>; 3284let Predicates = [HasFPU] in { 3285def : Pat<(f64 (extloadf32 iaddr:$src)), 3286 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 3287def : Pat<(f64 (extloadf32 xaddr:$src)), 3288 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 3289 3290def : Pat<(f64 (fpextend f32:$src)), 3291 (COPY_TO_REGCLASS $src, F8RC)>; 3292} 3293 3294// Only seq_cst fences require the heavyweight sync (SYNC 0). 3295// All others can use the lightweight sync (SYNC 1). 3296// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3297// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3298// versions of Power. 3299def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3300def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3301def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3302def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3303 3304let Predicates = [HasFPU] in { 3305// Additional FNMSUB patterns: -a*c + b == -(a*c - b) 3306def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 3307 (FNMSUB $A, $C, $B)>; 3308def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 3309 (FNMSUB $A, $C, $B)>; 3310def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 3311 (FNMSUBS $A, $C, $B)>; 3312def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 3313 (FNMSUBS $A, $C, $B)>; 3314 3315// FCOPYSIGN's operand types need not agree. 3316def : Pat<(fcopysign f64:$frB, f32:$frA), 3317 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3318def : Pat<(fcopysign f32:$frB, f64:$frA), 3319 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3320} 3321 3322include "PPCInstrAltivec.td" 3323include "PPCInstrSPE.td" 3324include "PPCInstr64Bit.td" 3325include "PPCInstrVSX.td" 3326include "PPCInstrQPX.td" 3327include "PPCInstrHTM.td" 3328 3329def crnot : OutPatFrag<(ops node:$in), 3330 (CRNOR $in, $in)>; 3331def : Pat<(not i1:$in), 3332 (crnot $in)>; 3333 3334// Patterns for arithmetic i1 operations. 3335def : Pat<(add i1:$a, i1:$b), 3336 (CRXOR $a, $b)>; 3337def : Pat<(sub i1:$a, i1:$b), 3338 (CRXOR $a, $b)>; 3339def : Pat<(mul i1:$a, i1:$b), 3340 (CRAND $a, $b)>; 3341 3342// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3343// (-1 is used to mean all bits set). 3344def : Pat<(i1 -1), (CRSET)>; 3345 3346// i1 extensions, implemented in terms of isel. 3347def : Pat<(i32 (zext i1:$in)), 3348 (SELECT_I4 $in, (LI 1), (LI 0))>; 3349def : Pat<(i32 (sext i1:$in)), 3350 (SELECT_I4 $in, (LI -1), (LI 0))>; 3351 3352def : Pat<(i64 (zext i1:$in)), 3353 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3354def : Pat<(i64 (sext i1:$in)), 3355 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3356 3357// FIXME: We should choose either a zext or a sext based on other constants 3358// already around. 3359def : Pat<(i32 (anyext i1:$in)), 3360 (SELECT_I4 $in, (LI 1), (LI 0))>; 3361def : Pat<(i64 (anyext i1:$in)), 3362 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3363 3364// match setcc on i1 variables. 3365// CRANDC is: 3366// 1 1 : F 3367// 1 0 : T 3368// 0 1 : F 3369// 0 0 : F 3370// 3371// LT is: 3372// -1 -1 : F 3373// -1 0 : T 3374// 0 -1 : F 3375// 0 0 : F 3376// 3377// ULT is: 3378// 1 1 : F 3379// 1 0 : F 3380// 0 1 : T 3381// 0 0 : F 3382def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3383 (CRANDC $s1, $s2)>; 3384def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3385 (CRANDC $s2, $s1)>; 3386// CRORC is: 3387// 1 1 : T 3388// 1 0 : T 3389// 0 1 : F 3390// 0 0 : T 3391// 3392// LE is: 3393// -1 -1 : T 3394// -1 0 : T 3395// 0 -1 : F 3396// 0 0 : T 3397// 3398// ULE is: 3399// 1 1 : T 3400// 1 0 : F 3401// 0 1 : T 3402// 0 0 : T 3403def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3404 (CRORC $s1, $s2)>; 3405def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3406 (CRORC $s2, $s1)>; 3407 3408def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3409 (CREQV $s1, $s2)>; 3410 3411// GE is: 3412// -1 -1 : T 3413// -1 0 : F 3414// 0 -1 : T 3415// 0 0 : T 3416// 3417// UGE is: 3418// 1 1 : T 3419// 1 0 : T 3420// 0 1 : F 3421// 0 0 : T 3422def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3423 (CRORC $s2, $s1)>; 3424def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3425 (CRORC $s1, $s2)>; 3426 3427// GT is: 3428// -1 -1 : F 3429// -1 0 : F 3430// 0 -1 : T 3431// 0 0 : F 3432// 3433// UGT is: 3434// 1 1 : F 3435// 1 0 : T 3436// 0 1 : F 3437// 0 0 : F 3438def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3439 (CRANDC $s2, $s1)>; 3440def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3441 (CRANDC $s1, $s2)>; 3442 3443def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3444 (CRXOR $s1, $s2)>; 3445 3446// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3447// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3448// floating-point types. 3449 3450multiclass CRNotPat<dag pattern, dag result> { 3451 def : Pat<pattern, (crnot result)>; 3452 def : Pat<(not pattern), result>; 3453 3454 // We can also fold the crnot into an extension: 3455 def : Pat<(i32 (zext pattern)), 3456 (SELECT_I4 result, (LI 0), (LI 1))>; 3457 def : Pat<(i32 (sext pattern)), 3458 (SELECT_I4 result, (LI 0), (LI -1))>; 3459 3460 // We can also fold the crnot into an extension: 3461 def : Pat<(i64 (zext pattern)), 3462 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3463 def : Pat<(i64 (sext pattern)), 3464 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3465 3466 // FIXME: We should choose either a zext or a sext based on other constants 3467 // already around. 3468 def : Pat<(i32 (anyext pattern)), 3469 (SELECT_I4 result, (LI 0), (LI 1))>; 3470 3471 def : Pat<(i64 (anyext pattern)), 3472 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3473} 3474 3475// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3476// we need to write imm:$imm in the output patterns below, not just $imm, or 3477// else the resulting matcher will not correctly add the immediate operand 3478// (making it a register operand instead). 3479 3480// extended SETCC. 3481multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3482 OutPatFrag rfrag, OutPatFrag rfrag8> { 3483 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3484 (rfrag $s1)>; 3485 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3486 (rfrag8 $s1)>; 3487 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3488 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3489 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3490 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3491 3492 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3493 (rfrag $s1)>; 3494 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3495 (rfrag8 $s1)>; 3496 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3497 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3498 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3499 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3500} 3501 3502// Note that we do all inversions below with i(32|64)not, instead of using 3503// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3504// has 2-cycle latency. 3505 3506defm : ExtSetCCPat<SETEQ, 3507 PatFrag<(ops node:$in, node:$cc), 3508 (setcc $in, 0, $cc)>, 3509 OutPatFrag<(ops node:$in), 3510 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3511 OutPatFrag<(ops node:$in), 3512 (RLDICL (CNTLZD $in), 58, 63)> >; 3513 3514defm : ExtSetCCPat<SETNE, 3515 PatFrag<(ops node:$in, node:$cc), 3516 (setcc $in, 0, $cc)>, 3517 OutPatFrag<(ops node:$in), 3518 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3519 OutPatFrag<(ops node:$in), 3520 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3521 3522defm : ExtSetCCPat<SETLT, 3523 PatFrag<(ops node:$in, node:$cc), 3524 (setcc $in, 0, $cc)>, 3525 OutPatFrag<(ops node:$in), 3526 (RLWINM $in, 1, 31, 31)>, 3527 OutPatFrag<(ops node:$in), 3528 (RLDICL $in, 1, 63)> >; 3529 3530defm : ExtSetCCPat<SETGE, 3531 PatFrag<(ops node:$in, node:$cc), 3532 (setcc $in, 0, $cc)>, 3533 OutPatFrag<(ops node:$in), 3534 (RLWINM (i32not $in), 1, 31, 31)>, 3535 OutPatFrag<(ops node:$in), 3536 (RLDICL (i64not $in), 1, 63)> >; 3537 3538defm : ExtSetCCPat<SETGT, 3539 PatFrag<(ops node:$in, node:$cc), 3540 (setcc $in, 0, $cc)>, 3541 OutPatFrag<(ops node:$in), 3542 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3543 OutPatFrag<(ops node:$in), 3544 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3545 3546defm : ExtSetCCPat<SETLE, 3547 PatFrag<(ops node:$in, node:$cc), 3548 (setcc $in, 0, $cc)>, 3549 OutPatFrag<(ops node:$in), 3550 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3551 OutPatFrag<(ops node:$in), 3552 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3553 3554defm : ExtSetCCPat<SETLT, 3555 PatFrag<(ops node:$in, node:$cc), 3556 (setcc $in, -1, $cc)>, 3557 OutPatFrag<(ops node:$in), 3558 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3559 OutPatFrag<(ops node:$in), 3560 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3561 3562defm : ExtSetCCPat<SETGE, 3563 PatFrag<(ops node:$in, node:$cc), 3564 (setcc $in, -1, $cc)>, 3565 OutPatFrag<(ops node:$in), 3566 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3567 OutPatFrag<(ops node:$in), 3568 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3569 3570defm : ExtSetCCPat<SETGT, 3571 PatFrag<(ops node:$in, node:$cc), 3572 (setcc $in, -1, $cc)>, 3573 OutPatFrag<(ops node:$in), 3574 (RLWINM (i32not $in), 1, 31, 31)>, 3575 OutPatFrag<(ops node:$in), 3576 (RLDICL (i64not $in), 1, 63)> >; 3577 3578defm : ExtSetCCPat<SETLE, 3579 PatFrag<(ops node:$in, node:$cc), 3580 (setcc $in, -1, $cc)>, 3581 OutPatFrag<(ops node:$in), 3582 (RLWINM $in, 1, 31, 31)>, 3583 OutPatFrag<(ops node:$in), 3584 (RLDICL $in, 1, 63)> >; 3585 3586// An extended SETCC with shift amount. 3587multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3588 OutPatFrag rfrag, OutPatFrag rfrag8> { 3589 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3590 (rfrag $s1, $sa)>; 3591 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3592 (rfrag8 $s1, $sa)>; 3593 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3594 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3595 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3596 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3597 3598 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3599 (rfrag $s1, $sa)>; 3600 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3601 (rfrag8 $s1, $sa)>; 3602 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3603 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3604 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3605 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3606} 3607 3608defm : ExtSetCCShiftPat<SETNE, 3609 PatFrag<(ops node:$in, node:$sa, node:$cc), 3610 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3611 OutPatFrag<(ops node:$in, node:$sa), 3612 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3613 OutPatFrag<(ops node:$in, node:$sa), 3614 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3615 3616defm : ExtSetCCShiftPat<SETEQ, 3617 PatFrag<(ops node:$in, node:$sa, node:$cc), 3618 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3619 OutPatFrag<(ops node:$in, node:$sa), 3620 (RLWNM (i32not $in), 3621 (SUBFIC $sa, 32), 31, 31)>, 3622 OutPatFrag<(ops node:$in, node:$sa), 3623 (RLDCL (i64not $in), 3624 (SUBFIC $sa, 64), 63)> >; 3625 3626// SETCC for i32. 3627def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3628 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3629def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3630 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3631def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3632 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3633def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3634 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3635def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3636 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3637def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3638 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3639 3640// For non-equality comparisons, the default code would materialize the 3641// constant, then compare against it, like this: 3642// lis r2, 4660 3643// ori r2, r2, 22136 3644// cmpw cr0, r3, r2 3645// beq cr0,L6 3646// Since we are just comparing for equality, we can emit this instead: 3647// xoris r0,r3,0x1234 3648// cmplwi cr0,r0,0x5678 3649// beq cr0,L6 3650 3651def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3652 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3653 (LO16 imm:$imm)), sub_eq)>; 3654 3655def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3656 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3657def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3658 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3659def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3660 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3661def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3662 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3663def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3664 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3665 3666// SETCC for i64. 3667def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3668 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3669def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3670 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3671def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3672 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3673def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3674 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3675def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3676 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3677def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3678 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3679 3680// For non-equality comparisons, the default code would materialize the 3681// constant, then compare against it, like this: 3682// lis r2, 4660 3683// ori r2, r2, 22136 3684// cmpd cr0, r3, r2 3685// beq cr0,L6 3686// Since we are just comparing for equality, we can emit this instead: 3687// xoris r0,r3,0x1234 3688// cmpldi cr0,r0,0x5678 3689// beq cr0,L6 3690 3691def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3692 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3693 (LO16 imm:$imm)), sub_eq)>; 3694 3695def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3696 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3697def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3698 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3699def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3700 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3701def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3702 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3703def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3704 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3705 3706// Instantiations of CRNotPat for i32. 3707defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3708 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3709defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3710 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3711defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3712 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3713defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3714 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3715defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3716 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3717defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3718 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3719 3720defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3721 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3722 (LO16 imm:$imm)), sub_eq)>; 3723 3724defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3725 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3726defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3727 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3728defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3729 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3730defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3731 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3732defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3733 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3734 3735// Instantiations of CRNotPat for i64. 3736defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3737 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3738defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3739 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3740defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3741 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3742defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3743 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3744defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3745 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3746defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3747 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3748 3749defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3750 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3751 (LO16 imm:$imm)), sub_eq)>; 3752 3753defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3754 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3755defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3756 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3757defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3758 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3759defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3760 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3761defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3762 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3763 3764let Predicates = [HasFPU] in { 3765// Instantiations of CRNotPat for f32. 3766defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3767 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3768defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3769 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3770defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3771 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3772defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3773 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3774defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3775 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3776defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3777 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3778defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 3779 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3780 3781// Instantiations of CRNotPat for f64. 3782defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3783 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3784defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3785 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3786defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3787 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3788defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3789 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3790defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3791 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3792defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3793 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3794defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 3795 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3796 3797// Instantiations of CRNotPat for f128. 3798defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)), 3799 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3800defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)), 3801 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3802defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)), 3803 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3804defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)), 3805 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3806defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)), 3807 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3808defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)), 3809 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3810defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)), 3811 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; 3812} 3813 3814// SETCC for f32. 3815let Predicates = [HasFPU] in { 3816def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3817 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3818def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3819 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3820def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3821 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3822def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3823 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3824def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3825 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3826def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3827 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3828def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 3829 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3830 3831// SETCC for f64. 3832def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3833 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3834def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3835 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3836def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3837 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3838def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3839 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3840def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3841 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3842def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3843 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3844def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 3845 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3846 3847// SETCC for f128. 3848def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOLT)), 3849 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3850def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETLT)), 3851 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3852def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOGT)), 3853 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3854def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETGT)), 3855 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3856def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOEQ)), 3857 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3858def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETEQ)), 3859 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3860def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETUO)), 3861 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; 3862 3863} 3864 3865// This must be in this file because it relies on patterns defined in this file 3866// after the inclusion of the instruction sets. 3867let Predicates = [HasSPE] in { 3868// SETCC for f32. 3869def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3870 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3871def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3872 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3873def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3874 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3875def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3876 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3877def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3878 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3879def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3880 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3881 3882defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3883 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3884defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3885 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3886defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3887 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3888defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3889 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3890defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3891 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3892defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3893 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3894 3895// SETCC for f64. 3896def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3897 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3898def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3899 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3900def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3901 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3902def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3903 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3904def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3905 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3906def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3907 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3908 3909defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3910 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3911defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3912 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3913defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3914 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3915defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3916 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3917defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3918 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3919defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3920 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3921} 3922// match select on i1 variables: 3923def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 3924 (CROR (CRAND $cond , $tval), 3925 (CRAND (crnot $cond), $fval))>; 3926 3927// match selectcc on i1 variables: 3928// select (lhs == rhs), tval, fval is: 3929// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 3930def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 3931 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3932 (CRAND (CRORC $rhs, $lhs), $fval))>; 3933def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 3934 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3935 (CRAND (CRORC $lhs, $rhs), $fval))>; 3936def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 3937 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3938 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3939def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 3940 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3941 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3942def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 3943 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 3944 (CRAND (CRXOR $lhs, $rhs), $fval))>; 3945def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 3946 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3947 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3948def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 3949 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3950 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3951def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 3952 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3953 (CRAND (CRORC $lhs, $rhs), $fval))>; 3954def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 3955 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3956 (CRAND (CRORC $rhs, $lhs), $fval))>; 3957def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 3958 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 3959 (CRAND (CRXOR $lhs, $rhs), $tval))>; 3960 3961// match selectcc on i1 variables with non-i1 output. 3962def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 3963 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3964def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 3965 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3966def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 3967 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3968def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 3969 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3970def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 3971 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 3972def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 3973 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3974def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 3975 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3976def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 3977 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3978def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 3979 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3980def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 3981 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3982 3983def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 3984 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3985def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 3986 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3987def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 3988 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3989def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 3990 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3991def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 3992 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 3993def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 3994 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3995def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 3996 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3997def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 3998 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3999def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4000 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4001def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4002 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4003 4004let Predicates = [HasFPU] in { 4005def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4006 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4007def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4008 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4009def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4010 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4011def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4012 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4013def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4014 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4015def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4016 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4017def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4018 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4019def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4020 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4021def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4022 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4023def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4024 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4025 4026def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4027 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4028def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4029 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4030def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4031 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4032def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4033 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4034def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4035 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4036def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4037 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4038def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4039 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4040def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4041 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4042def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4043 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4044def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4045 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4046} 4047 4048def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4049 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4050def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4051 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4052def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4053 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4054def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4055 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4056def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4057 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4058def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4059 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4060def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4061 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4062def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4063 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4064def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4065 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4066def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4067 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4068 4069def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4070 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4071def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4072 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4073def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4074 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4075def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4076 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4077def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4078 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4079def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4080 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4081def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4082 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4083def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4084 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4085def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4086 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4087def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4088 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4089 4090def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4091 "#ANDI_rec_1_EQ_BIT", 4092 [(set i1:$dst, (trunc (not i32:$in)))]>; 4093def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4094 "#ANDI_rec_1_GT_BIT", 4095 [(set i1:$dst, (trunc i32:$in))]>; 4096 4097def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4098 "#ANDI_rec_1_EQ_BIT8", 4099 [(set i1:$dst, (trunc (not i64:$in)))]>; 4100def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4101 "#ANDI_rec_1_GT_BIT8", 4102 [(set i1:$dst, (trunc i64:$in))]>; 4103 4104def : Pat<(i1 (not (trunc i32:$in))), 4105 (ANDI_rec_1_EQ_BIT $in)>; 4106def : Pat<(i1 (not (trunc i64:$in))), 4107 (ANDI_rec_1_EQ_BIT8 $in)>; 4108 4109//===----------------------------------------------------------------------===// 4110// PowerPC Instructions used for assembler/disassembler only 4111// 4112 4113// FIXME: For B=0 or B > 8, the registers following RT are used. 4114// WARNING: Do not add patterns for this instruction without fixing this. 4115def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4116 (ins gprc:$A, u5imm:$B), 4117 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4118 4119// FIXME: For B=0 or B > 8, the registers following RT are used. 4120// WARNING: Do not add patterns for this instruction without fixing this. 4121def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4122 (ins gprc:$RT, gprc:$A, u5imm:$B), 4123 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4124 4125def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4126 "isync", IIC_SprISYNC, []>; 4127 4128def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4129 "icbi $src", IIC_LdStICBI, []>; 4130 4131// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 4132def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 4133 "eieio", IIC_LdStLoad, []>; 4134 4135def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L), 4136 "wait $L", IIC_LdStLoad, []>; 4137 4138def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4139 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4140 4141def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4142 "mtsr $SR, $RS", IIC_SprMTSR>; 4143 4144def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4145 "mfsr $RS, $SR", IIC_SprMFSR>; 4146 4147def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4148 "mtsrin $RS, $RB", IIC_SprMTSR>; 4149 4150def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4151 "mfsrin $RS, $RB", IIC_SprMFSR>; 4152 4153def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 4154 "mtmsr $RS, $L", IIC_SprMTMSR>; 4155 4156def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4157 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4158 let L = 0; 4159} 4160 4161def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4162 Requires<[IsBookE]> { 4163 bits<1> E; 4164 4165 let Inst{16} = E; 4166 let Inst{21-30} = 163; 4167} 4168 4169def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4170 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4171def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4172 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4173 4174def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4175def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4176def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4177def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4178 4179def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4180 "mfmsr $RT", IIC_SprMFMSR, []>; 4181 4182def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 4183 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4184 4185def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4186 "mcrfs $BF, $BFA", IIC_BrMCR>; 4187 4188def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 4189 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4190 4191def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 4192 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4193 4194def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>; 4195def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>; 4196 4197let Predicates = [HasFPU] in { 4198def MTFSF : XFLForm_1<63, 711, (outs), 4199 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 4200 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4201def MTFSF_rec : XFLForm_1<63, 711, (outs), 4202 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 4203 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4204 4205def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4206def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4207} 4208 4209def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4210 "slbie $RB", IIC_SprSLBIE, []>; 4211 4212def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4213 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4214 4215def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4216 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4217 4218def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4219 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4220 4221def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4222 4223let Defs = [CR0] in 4224def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4225 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4226 4227def TLBIA : XForm_0<31, 370, (outs), (ins), 4228 "tlbia", IIC_SprTLBIA, []>; 4229 4230def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4231 "tlbsync", IIC_SprTLBSYNC, []>; 4232 4233def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4234 "tlbiel $RB", IIC_SprTLBIEL, []>; 4235 4236def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4237 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4238def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4239 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4240 4241def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4242 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4243 4244def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4245 IIC_LdStLoad>, Requires<[IsBookE]>; 4246 4247def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4248 IIC_LdStLoad>, Requires<[IsBookE]>; 4249 4250def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4251 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4252 4253def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4254 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4255 4256def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4257 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4258 4259def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4260 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4261 4262def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4263 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4264 Requires<[IsPPC4xx]>; 4265def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4266 (ins gprc:$RST, gprc:$A, gprc:$B), 4267 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4268 Requires<[IsPPC4xx]>, isRecordForm; 4269 4270def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4271 4272def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4273 Requires<[IsBookE]>; 4274def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4275 Requires<[IsBookE]>; 4276 4277def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4278 Requires<[IsE500]>; 4279def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4280 Requires<[IsE500]>; 4281 4282def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4283 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4284def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4285 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4286 4287def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4288def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4289 4290def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4291 4292def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4293 (ins gprc:$A, gprc:$B), 4294 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4295def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4296 (ins gprc:$A, gprc:$B), 4297 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4298def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4299 (ins gprc:$A, gprc:$B), 4300 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4301def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4302 (ins gprc:$A, gprc:$B), 4303 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4304 4305def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4306 (ins gprc:$RST, gprc:$A, gprc:$B), 4307 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4308def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4309 (ins gprc:$RST, gprc:$A, gprc:$B), 4310 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4311def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4312 (ins gprc:$RST, gprc:$A, gprc:$B), 4313 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4314def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4315 (ins gprc:$RST, gprc:$A, gprc:$B), 4316 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4317 4318// External PID Load Store Instructions 4319 4320def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4321 "lbepx $rD, $src", IIC_LdStLoad, []>, 4322 Requires<[IsE500]>; 4323 4324def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4325 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4326 Requires<[IsE500]>; 4327 4328def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4329 "lhepx $rD, $src", IIC_LdStLoad, []>, 4330 Requires<[IsE500]>; 4331 4332def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4333 "lwepx $rD, $src", IIC_LdStLoad, []>, 4334 Requires<[IsE500]>; 4335 4336def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4337 "stbepx $rS, $dst", IIC_LdStStore, []>, 4338 Requires<[IsE500]>; 4339 4340def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4341 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4342 Requires<[IsE500]>; 4343 4344def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4345 "sthepx $rS, $dst", IIC_LdStStore, []>, 4346 Requires<[IsE500]>; 4347 4348def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4349 "stwepx $rS, $dst", IIC_LdStStore, []>, 4350 Requires<[IsE500]>; 4351 4352def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4353 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4354 4355def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4356 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4357 4358def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4359 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4360 Requires<[IsE500]>; 4361 4362def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4363 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4364 Requires<[IsE500]>; 4365 4366def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4367 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4368 4369def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4370 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4371 4372def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4373 IIC_LdStICBI, []>, Requires<[IsE500]>; 4374 4375//===----------------------------------------------------------------------===// 4376// PowerPC Assembler Instruction Aliases 4377// 4378 4379// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4380// These are aliases that require C++ handling to convert to the target 4381// instruction, while InstAliases can be handled directly by tblgen. 4382class PPCAsmPseudo<string asm, dag iops> 4383 : Instruction { 4384 let Namespace = "PPC"; 4385 bit PPC64 = 0; // Default value, override with isPPC64 4386 4387 let OutOperandList = (outs); 4388 let InOperandList = iops; 4389 let Pattern = []; 4390 let AsmString = asm; 4391 let isAsmParserOnly = 1; 4392 let isPseudo = 1; 4393 let hasNoSchedulingInfo = 1; 4394} 4395 4396def : InstAlias<"sc", (SC 0)>; 4397 4398def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4399def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4400def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4401def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4402 4403def : InstAlias<"wait", (WAIT 0)>; 4404def : InstAlias<"waitrsv", (WAIT 1)>; 4405def : InstAlias<"waitimpl", (WAIT 2)>; 4406 4407def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4408 4409def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4410def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4411 4412def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4413def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4414def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4415 4416def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4417def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4418def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4419 4420def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4421def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4422def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4423 4424def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4425def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4426def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4427def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4428 4429def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4430def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4431 4432def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4433def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4434 4435def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4436def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4437 4438def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4439def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4440 4441def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4442def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4443 4444def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4445def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4446 4447def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4448def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4449 4450def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4451def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4452 4453def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4454def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4455 4456def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4457def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4458 4459def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4460def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4461 4462def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4463def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4464 4465def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4466def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4467 4468def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4469def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4470 4471def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4472def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4473def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4474 4475def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4476def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4477 4478def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4479def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4480def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4481def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4482 4483def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4484 4485def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 4486def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 4487 4488def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 4489def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 4490 4491def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 4492 4493foreach BATR = 0-3 in { 4494 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4495 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4496 Requires<[IsPPC6xx]>; 4497 def : InstAlias<"mfdbatu $Rx, "#BATR, 4498 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4499 Requires<[IsPPC6xx]>; 4500 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4501 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4502 Requires<[IsPPC6xx]>; 4503 def : InstAlias<"mfdbatl $Rx, "#BATR, 4504 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4505 Requires<[IsPPC6xx]>; 4506 def : InstAlias<"mtibatu "#BATR#", $Rx", 4507 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4508 Requires<[IsPPC6xx]>; 4509 def : InstAlias<"mfibatu $Rx, "#BATR, 4510 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4511 Requires<[IsPPC6xx]>; 4512 def : InstAlias<"mtibatl "#BATR#", $Rx", 4513 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4514 Requires<[IsPPC6xx]>; 4515 def : InstAlias<"mfibatl $Rx, "#BATR, 4516 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4517 Requires<[IsPPC6xx]>; 4518} 4519 4520foreach BR = 0-7 in { 4521 def : InstAlias<"mfbr"#BR#" $Rx", 4522 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4523 Requires<[IsPPC4xx]>; 4524 def : InstAlias<"mtbr"#BR#" $Rx", 4525 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4526 Requires<[IsPPC4xx]>; 4527} 4528 4529def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4530def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4531 4532def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4533def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4534 4535def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4536def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4537 4538def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4539def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4540 4541def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4542def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4543 4544def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4545def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4546 4547def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4548 4549def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4550 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4551def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4552 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4553def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4554 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4555def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4556 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4557 4558def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 4559def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 4560def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 4561def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 4562 4563def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4564def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4565 4566def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4567def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4568 4569foreach SPRG = 0-3 in { 4570 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4571 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4572 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4573 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4574} 4575foreach SPRG = 4-7 in { 4576 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4577 Requires<[IsBookE]>; 4578 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4579 Requires<[IsBookE]>; 4580 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4581 Requires<[IsBookE]>; 4582 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4583 Requires<[IsBookE]>; 4584} 4585 4586def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>; 4587 4588def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>; 4589def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>; 4590 4591def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4592 4593def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>; 4594def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>; 4595 4596def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>; 4597def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>; 4598def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>; 4599def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>; 4600 4601def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4602 4603def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4604 Requires<[IsPPC4xx]>; 4605def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4606 Requires<[IsPPC4xx]>; 4607def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4608 Requires<[IsPPC4xx]>; 4609def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4610 Requires<[IsPPC4xx]>; 4611 4612def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4613 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4614def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4615 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4616def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4617 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4618def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4619 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4620def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4621 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4622def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4623 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4624def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4625 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4626def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4627 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4628def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4629 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4630def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4631 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4632def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4633 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4634def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4635 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4636def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4637 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4638def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4639 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4640def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4641 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4642def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4643 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4644def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4645 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4646def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4647 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4648 4649def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4650def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4651def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4652def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4653def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4654def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4655 4656def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4657def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4658// The POWER variant 4659def : MnemonicAlias<"cntlz", "cntlzw">; 4660def : MnemonicAlias<"cntlz.", "cntlzw.">; 4661 4662def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4663 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4664def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4665 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4666def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4667 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4668def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4669 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4670def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4671 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4672def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4673 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4674def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4675 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4676def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4677 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4678def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4679 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4680def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4681 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4682def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4683 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4684def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4685 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4686def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4687 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4688def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4689 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4690def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4691 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4692def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4693 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4694def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4695 4696def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4697def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4698def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4699def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4700def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4701def : InstAlias<"clrldi $rA, $rS, $n", 4702 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4703def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4704def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4705 4706def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4707 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4708def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4709 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4710def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4711 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4712def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4713 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4714def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4715 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4716def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4717 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4718 4719// These generic branch instruction forms are used for the assembler parser only. 4720// Defs and Uses are conservative, since we don't know the BO value. 4721let PPC970_Unit = 7, isBranch = 1 in { 4722 let Defs = [CTR], Uses = [CTR, RM] in { 4723 def gBC : BForm_3<16, 0, 0, (outs), 4724 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4725 "bc $bo, $bi, $dst">; 4726 def gBCA : BForm_3<16, 1, 0, (outs), 4727 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4728 "bca $bo, $bi, $dst">; 4729 let isAsmParserOnly = 1 in { 4730 def gBCat : BForm_3_at<16, 0, 0, (outs), 4731 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4732 condbrtarget:$dst), 4733 "bc$at $bo, $bi, $dst">; 4734 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4735 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4736 abscondbrtarget:$dst), 4737 "bca$at $bo, $bi, $dst">; 4738 } // isAsmParserOnly = 1 4739 } 4740 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4741 def gBCL : BForm_3<16, 0, 1, (outs), 4742 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4743 "bcl $bo, $bi, $dst">; 4744 def gBCLA : BForm_3<16, 1, 1, (outs), 4745 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4746 "bcla $bo, $bi, $dst">; 4747 let isAsmParserOnly = 1 in { 4748 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4749 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4750 condbrtarget:$dst), 4751 "bcl$at $bo, $bi, $dst">; 4752 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4753 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4754 abscondbrtarget:$dst), 4755 "bcla$at $bo, $bi, $dst">; 4756 } // // isAsmParserOnly = 1 4757 } 4758 let Defs = [CTR], Uses = [CTR, LR, RM] in 4759 def gBCLR : XLForm_2<19, 16, 0, (outs), 4760 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4761 "bclr $bo, $bi, $bh", IIC_BrB, []>; 4762 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4763 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4764 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4765 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 4766 let Defs = [CTR], Uses = [CTR, LR, RM] in 4767 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4768 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4769 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 4770 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4771 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4772 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4773 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 4774} 4775 4776multiclass BranchSimpleMnemonicAT<string pm, int at> { 4777 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4778 condbrtarget:$dst)>; 4779 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4780 condbrtarget:$dst)>; 4781 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4782 condbrtarget:$dst)>; 4783 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4784 condbrtarget:$dst)>; 4785} 4786defm : BranchSimpleMnemonicAT<"+", 3>; 4787defm : BranchSimpleMnemonicAT<"-", 2>; 4788 4789def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4790def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4791def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4792def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4793 4794multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4795 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4796 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4797 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4798 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4799 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4800 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4801} 4802multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4803 : BranchSimpleMnemonic1<name, pm, bo> { 4804 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4805 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4806} 4807defm : BranchSimpleMnemonic2<"t", "", 12>; 4808defm : BranchSimpleMnemonic2<"f", "", 4>; 4809defm : BranchSimpleMnemonic2<"t", "-", 14>; 4810defm : BranchSimpleMnemonic2<"f", "-", 6>; 4811defm : BranchSimpleMnemonic2<"t", "+", 15>; 4812defm : BranchSimpleMnemonic2<"f", "+", 7>; 4813defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4814defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4815defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4816defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4817 4818multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4819 def : InstAlias<"b"#name#pm#" $cc, $dst", 4820 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4821 def : InstAlias<"b"#name#pm#" $dst", 4822 (BCC bibo, CR0, condbrtarget:$dst)>; 4823 4824 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4825 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4826 def : InstAlias<"b"#name#"a"#pm#" $dst", 4827 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4828 4829 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4830 (BCCLR bibo, crrc:$cc)>; 4831 def : InstAlias<"b"#name#"lr"#pm, 4832 (BCCLR bibo, CR0)>; 4833 4834 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4835 (BCCCTR bibo, crrc:$cc)>; 4836 def : InstAlias<"b"#name#"ctr"#pm, 4837 (BCCCTR bibo, CR0)>; 4838 4839 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4840 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4841 def : InstAlias<"b"#name#"l"#pm#" $dst", 4842 (BCCL bibo, CR0, condbrtarget:$dst)>; 4843 4844 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4845 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4846 def : InstAlias<"b"#name#"la"#pm#" $dst", 4847 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4848 4849 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4850 (BCCLRL bibo, crrc:$cc)>; 4851 def : InstAlias<"b"#name#"lrl"#pm, 4852 (BCCLRL bibo, CR0)>; 4853 4854 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4855 (BCCCTRL bibo, crrc:$cc)>; 4856 def : InstAlias<"b"#name#"ctrl"#pm, 4857 (BCCCTRL bibo, CR0)>; 4858} 4859multiclass BranchExtendedMnemonic<string name, int bibo> { 4860 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4861 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4862 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4863} 4864defm : BranchExtendedMnemonic<"lt", 12>; 4865defm : BranchExtendedMnemonic<"gt", 44>; 4866defm : BranchExtendedMnemonic<"eq", 76>; 4867defm : BranchExtendedMnemonic<"un", 108>; 4868defm : BranchExtendedMnemonic<"so", 108>; 4869defm : BranchExtendedMnemonic<"ge", 4>; 4870defm : BranchExtendedMnemonic<"nl", 4>; 4871defm : BranchExtendedMnemonic<"le", 36>; 4872defm : BranchExtendedMnemonic<"ng", 36>; 4873defm : BranchExtendedMnemonic<"ne", 68>; 4874defm : BranchExtendedMnemonic<"nu", 100>; 4875defm : BranchExtendedMnemonic<"ns", 100>; 4876 4877def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4878def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4879def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4880def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4881def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4882def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4883def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4884def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4885 4886def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4887def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4888def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 4889def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 4890def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 4891def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4892def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 4893def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4894 4895multiclass TrapExtendedMnemonic<string name, int to> { 4896 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 4897 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 4898 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 4899 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 4900} 4901defm : TrapExtendedMnemonic<"lt", 16>; 4902defm : TrapExtendedMnemonic<"le", 20>; 4903defm : TrapExtendedMnemonic<"eq", 4>; 4904defm : TrapExtendedMnemonic<"ge", 12>; 4905defm : TrapExtendedMnemonic<"gt", 8>; 4906defm : TrapExtendedMnemonic<"nl", 12>; 4907defm : TrapExtendedMnemonic<"ne", 24>; 4908defm : TrapExtendedMnemonic<"ng", 20>; 4909defm : TrapExtendedMnemonic<"llt", 2>; 4910defm : TrapExtendedMnemonic<"lle", 6>; 4911defm : TrapExtendedMnemonic<"lge", 5>; 4912defm : TrapExtendedMnemonic<"lgt", 1>; 4913defm : TrapExtendedMnemonic<"lnl", 5>; 4914defm : TrapExtendedMnemonic<"lng", 6>; 4915defm : TrapExtendedMnemonic<"u", 31>; 4916 4917// Atomic loads 4918def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>; 4919def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>; 4920def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>; 4921def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>; 4922def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>; 4923def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>; 4924 4925// Atomic stores 4926def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 4927def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 4928def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 4929def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 4930def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 4931def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 4932 4933let Predicates = [IsISA3_0] in { 4934 4935// Copy-Paste Facility 4936// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 4937// PASTE for naming consistency. 4938let mayLoad = 1 in 4939def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 4940 4941let mayStore = 1 in 4942def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>; 4943 4944let mayStore = 1, Defs = [CR0] in 4945def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 4946 4947def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>; 4948def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>; 4949def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB", 4950 (ins gprc:$rA, gprc:$rB)>; 4951def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB", 4952 (ins gprc:$rA, gprc:$rB)>; 4953def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>; 4954 4955// Message Synchronize 4956def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 4957 4958// Power-Saving Mode Instruction: 4959def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 4960 4961} // IsISA3_0 4962 4963// Fast 32-bit reverse bits algorithm: 4964// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 4965// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 4966// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 4967// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 4968// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 4969// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 4970// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 4971// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 4972// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 4973// Step 4.2: Insert B3 to the right position: 4974// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 4975// Step 4.3: Insert B1 to the right position: 4976// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 4977def MaskValues { 4978 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 4979 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 4980 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 4981 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 4982 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 4983 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 4984} 4985 4986def Shift1 { 4987 dag Right = (RLWINM $A, 31, 1, 31); 4988 dag Left = (RLWINM $A, 1, 0, 30); 4989} 4990 4991def Swap1 { 4992 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 4993 (AND Shift1.Left, MaskValues.Hi1)); 4994} 4995 4996def Shift2 { 4997 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 4998 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 4999} 5000 5001def Swap2 { 5002 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5003 (AND Shift2.Left, MaskValues.Hi2)); 5004} 5005 5006def Shift4 { 5007 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5008 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5009} 5010 5011def Swap4 { 5012 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5013 (AND Shift4.Left, MaskValues.Hi4)); 5014} 5015 5016def Rotate { 5017 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5018} 5019 5020def RotateInsertByte3 { 5021 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5022} 5023 5024def RotateInsertByte1 { 5025 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5026} 5027 5028def : Pat<(i32 (bitreverse i32:$A)), 5029 (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5030 5031// Fast 64-bit reverse bits algorithm: 5032// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5033// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5034// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5035// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5036// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5037// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5038// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5039// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5040// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5041// then OR them together to get the final result. 5042def MaskValues64 { 5043 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5044 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5045 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5046 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5047 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5048 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5049} 5050 5051def DWMaskValues { 5052 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5053 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5054 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5055 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5056 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5057 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5058} 5059 5060def DWSwapInByte { 5061 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5062 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5063 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5064 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5065 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5066 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5067} 5068 5069// Intra-byte swap is done, now start inter-byte swap. 5070def DWBytes4567 { 5071 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5072} 5073 5074def DWBytes7456 { 5075 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5076} 5077 5078def DWBytes7656 { 5079 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5080} 5081 5082// B7 B6 B5 B4 in the right order 5083def DWBytes7654 { 5084 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5085 dag DWord = 5086 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5087} 5088 5089def DWBytes0123 { 5090 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5091} 5092 5093def DWBytes3012 { 5094 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5095} 5096 5097def DWBytes3212 { 5098 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5099} 5100 5101// B3 B2 B1 B0 in the right order 5102def DWBytes3210 { 5103 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5104 dag DWord = 5105 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5106} 5107 5108// Now both high word and low word are reversed, next 5109// swap the high word and low word. 5110def : Pat<(i64 (bitreverse i64:$A)), 5111 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5112