1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86 87def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 88 SDTCisPtrTy<0>, SDTCisVT<1, i32> 89]>; 90 91def tocentry32 : Operand<iPTR> { 92 let MIOperandInfo = (ops i32imm:$imm); 93} 94 95def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 96 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 97]>; 98def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 99 SDTCisVec<0>, SDTCisInt<1> 100]>; 101def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 102 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 103]>; 104def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 106]>; 107 108def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 109 SDTCisVec<0>, SDTCisVec<1> 110]>; 111 112def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 113 SDTCisVec<0>, SDTCisPtrTy<1> 114]>; 115 116def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 118]>; 119 120def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 121 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 122]>; 123 124//===----------------------------------------------------------------------===// 125// PowerPC specific DAG Nodes. 126// 127 128def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 129def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 130def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 131def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 132 133def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 134def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 135def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 136def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 137def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 138def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 139def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 140def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 141 142def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 143 SDTFPUnaryOp, [SDNPHasChain]>; 144def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 145 SDTFPUnaryOp, [SDNPHasChain]>; 146def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 147 SDTFPRoundOp, [SDNPHasChain]>; 148def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 149 SDTFPRoundOp, [SDNPHasChain]>; 150 151def PPCany_fcfid : PatFrags<(ops node:$op), 152 [(PPCfcfid node:$op), 153 (PPCstrict_fcfid node:$op)]>; 154def PPCany_fcfidu : PatFrags<(ops node:$op), 155 [(PPCfcfidu node:$op), 156 (PPCstrict_fcfidu node:$op)]>; 157def PPCany_fcfids : PatFrags<(ops node:$op), 158 [(PPCfcfids node:$op), 159 (PPCstrict_fcfids node:$op)]>; 160def PPCany_fcfidus : PatFrags<(ops node:$op), 161 [(PPCfcfidus node:$op), 162 (PPCstrict_fcfidus node:$op)]>; 163 164def PPCcv_fp_to_uint_in_vsr: 165 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 166def PPCcv_fp_to_sint_in_vsr: 167 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 168def PPCstore_scal_int_from_vsr: 169 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 170 [SDNPHasChain, SDNPMayStore]>; 171def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 172 [SDNPHasChain, SDNPMayStore]>; 173def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 174 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 175def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 176 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 177def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 178 [SDNPHasChain, SDNPMayLoad]>; 179def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 180 [SDNPHasChain, SDNPMayStore]>; 181def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 182 183// Extract FPSCR (not modeled at the DAG level). 184def PPCmffs : SDNode<"PPCISD::MFFS", 185 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 186 [SDNPHasChain]>; 187 188// Perform FADD in round-to-zero mode. 189def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 190def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 191 [SDNPHasChain]>; 192 193def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 194 [(PPCfaddrtz node:$lhs, node:$rhs), 195 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 196 197def PPCfsel : SDNode<"PPCISD::FSEL", 198 // Type constraint for fsel. 199 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 200 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 201def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; 202def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; 203def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 204def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 205def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 206 [SDNPMayLoad, SDNPMemOperand]>; 207 208def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 209 210def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 211def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 212 [SDNPMayLoad]>; 213def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 214def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 215def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 216def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 217def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 218 SDTypeProfile<1, 3, [ 219 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 220 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 221def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 222def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 223def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 224def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 225def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 226 SDTypeProfile<1, 3, [ 227 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 228 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 229def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 230def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 231def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 232 233def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 234def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 235def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 236def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 237def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 238def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 239 240def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 241 242// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 243// amounts. These nodes are generated by the multi-precision shift code. 244def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 245def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 246def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 247 248def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 249 250def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 251 252def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 253 SDTFPUnaryOp, [SDNPHasChain]>; 254def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260 261def PPCany_fctidz : PatFrags<(ops node:$op), 262 [(PPCstrict_fctidz node:$op), 263 (PPCfctidz node:$op)]>; 264def PPCany_fctiwz : PatFrags<(ops node:$op), 265 [(PPCstrict_fctiwz node:$op), 266 (PPCfctiwz node:$op)]>; 267def PPCany_fctiduz : PatFrags<(ops node:$op), 268 [(PPCstrict_fctiduz node:$op), 269 (PPCfctiduz node:$op)]>; 270def PPCany_fctiwuz : PatFrags<(ops node:$op), 271 [(PPCstrict_fctiwuz node:$op), 272 (PPCfctiwuz node:$op)]>; 273 274// Move 2 i64 values into a VSX register 275def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 276 SDTypeProfile<1, 2, 277 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 278 SDTCisSameAs<1,2>]>, 279 []>; 280 281def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 282 SDTypeProfile<1, 2, 283 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 284 SDTCisVT<1,i32>]>, 285 []>; 286 287def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 288 SDTypeProfile<1, 2, 289 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 290 SDTCisPtrTy<2>]>, 291 []>; 292 293// These are target-independent nodes, but have target-specific formats. 294def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 295 [SDNPHasChain, SDNPOutGlue]>; 296def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 297 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 298 299def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 300def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 301 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 302 SDNPVariadic]>; 303def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 304 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 305 SDNPVariadic]>; 306def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 307 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 308 SDNPVariadic]>; 309def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 310 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 311def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 313 SDNPVariadic]>; 314def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 315 SDTypeProfile<0, 1, []>, 316 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 317 SDNPVariadic]>; 318 319// Call nodes for strictfp calls (that define RM). 320def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 321 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 322 SDNPVariadic]>; 323def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 324 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 325 SDNPVariadic]>; 326def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 327 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 328 SDNPVariadic]>; 329def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 330 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 331 SDNPVariadic]>; 332def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 333 SDTypeProfile<0, 1, []>, 334 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 335 SDNPVariadic]>; 336 337def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 338 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 339 340def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 341 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 342 343def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 344 SDTypeProfile<1, 1, [SDTCisInt<0>, 345 SDTCisPtrTy<1>]>, 346 [SDNPHasChain, SDNPSideEffect]>; 347def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 348 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 349 [SDNPHasChain, SDNPSideEffect]>; 350 351def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 352def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 353 [SDNPHasChain, SDNPSideEffect]>; 354 355def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 356 [SDNPHasChain, SDNPSideEffect]>; 357def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 358def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 359 [SDNPHasChain, SDNPSideEffect]>; 360 361def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 362def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 363 364def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 365 [SDNPHasChain, SDNPOptInGlue]>; 366 367// PPC-specific atomic operations. 368def PPCatomicCmpSwap_8 : 369 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def PPCatomicCmpSwap_16 : 372 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 375 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 376def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 377 [SDNPHasChain, SDNPMayStore]>; 378 379// Instructions to set/unset CR bit 6 for SVR4 vararg calls 380def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 381 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 382def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 383 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 384 385// Instructions to support dynamic alloca. 386def SDTDynOp : SDTypeProfile<1, 2, []>; 387def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 388def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 389def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 390def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 391 392// PC Relative Specific Nodes 393def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 394def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 395 SDTIntUnaryOp, []>; 396def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 397 SDTIntUnaryOp, []>; 398 399//===----------------------------------------------------------------------===// 400// PowerPC specific transformation functions and pattern fragments. 401// 402 403// A floating point immediate that is not a positive zero and can be converted 404// to a single precision floating point non-denormal immediate without loss of 405// information. 406def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 407 APFloat APFloatOfN = N->getValueAPF(); 408 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 409}]>; 410 411// Convert the floating point immediate into a 32 bit floating point immediate 412// and get a i32 with the resulting bits. 413def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 414 APFloat APFloatOfN = N->getValueAPF(); 415 convertToNonDenormSingle(APFloatOfN); 416 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 417 SDLoc(N), MVT::i32); 418}]>; 419 420// Check if the value can be converted to be single precision immediate, which 421// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 422// precision before exploiting with XXSPLTI32DX. 423def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 424 APFloat APFloatOfN = N->getValueAPF(); 425 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 426}]>; 427 428// Get the Hi bits of a 64 bit immediate. 429def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 430 APFloat APFloatOfN = N->getValueAPF(); 431 bool Unused; 432 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 433 &Unused); 434 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 435 0xFFFFFFFF00000000LL) >> 32); 436 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 437}]>; 438 439// Get the Lo bits of a 64 bit immediate. 440def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 441 APFloat APFloatOfN = N->getValueAPF(); 442 bool Unused; 443 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 444 &Unused); 445 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 446 0xFFFFFFFF); 447 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 448}]>; 449 450def imm34 : PatLeaf<(imm), [{ 451 return isInt<34>(N->getSExtValue()); 452}]>; 453 454def getImmAs64BitInt : SDNodeXForm<imm, [{ 455 return getI64Imm(N->getSExtValue(), SDLoc(N)); 456}]>; 457 458def SHL32 : SDNodeXForm<imm, [{ 459 // Transformation function: 31 - imm 460 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 461}]>; 462 463def SRL32 : SDNodeXForm<imm, [{ 464 // Transformation function: 32 - imm 465 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 466 : getI32Imm(0, SDLoc(N)); 467}]>; 468 469def LO16 : SDNodeXForm<imm, [{ 470 // Transformation function: get the low 16 bits. 471 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 472}]>; 473 474def HI16 : SDNodeXForm<imm, [{ 475 // Transformation function: shift the immediate value down into the low bits. 476 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 477}]>; 478 479def HA16 : SDNodeXForm<imm, [{ 480 // Transformation function: shift the immediate value down into the low bits. 481 long Val = N->getZExtValue(); 482 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 483}]>; 484def MB : SDNodeXForm<imm, [{ 485 // Transformation function: get the start bit of a mask 486 unsigned mb = 0, me; 487 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 488 return getI32Imm(mb, SDLoc(N)); 489}]>; 490 491def ME : SDNodeXForm<imm, [{ 492 // Transformation function: get the end bit of a mask 493 unsigned mb, me = 0; 494 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 495 return getI32Imm(me, SDLoc(N)); 496}]>; 497def maskimm32 : PatLeaf<(imm), [{ 498 // maskImm predicate - True if immediate is a run of ones. 499 unsigned mb, me; 500 if (N->getValueType(0) == MVT::i32) 501 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 502 else 503 return false; 504}]>; 505 506def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 507 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 508 // sign extended field. Used by instructions like 'addi'. 509 return (int32_t)Imm == (short)Imm; 510}]>; 511def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 512 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 513 // sign extended field. Used by instructions like 'addi'. 514 return (int64_t)Imm == (short)Imm; 515}]>; 516def immZExt16 : PatLeaf<(imm), [{ 517 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 518 // field. Used by instructions like 'ori'. 519 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 520}], LO16>; 521def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 522 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 523}]>; 524def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 525def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 526 527// imm16Shifted* - These match immediates where the low 16-bits are zero. There 528// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 529// identical in 32-bit mode, but in 64-bit mode, they return true if the 530// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 531// clear). 532def imm16ShiftedZExt : PatLeaf<(imm), [{ 533 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 534 // immediate are set. Used by instructions like 'xoris'. 535 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 536}], HI16>; 537 538def imm16ShiftedSExt : PatLeaf<(imm), [{ 539 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 540 // immediate are set. Used by instructions like 'addis'. Identical to 541 // imm16ShiftedZExt in 32-bit mode. 542 if (N->getZExtValue() & 0xFFFF) return false; 543 if (N->getValueType(0) == MVT::i32) 544 return true; 545 // For 64-bit, make sure it is sext right. 546 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 547}], HI16>; 548 549def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 550 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 551 // zero extended field. 552 return isUInt<32>(Imm); 553}]>; 554 555// This is a somewhat weaker condition than actually checking for 4-byte 556// alignment. It is simply checking that the displacement can be represented 557// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 558// instructions). 559// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 560// restricted memrix (4-aligned) constants are alignment sensitive. If these 561// offsets are hidden behind TOC entries than the values of the lower-order 562// bits cannot be checked directly. As a result, we need to also incorporate 563// an alignment check into the relevant patterns. 564 565def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 566 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 567}]>; 568def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 569 (store node:$val, node:$ptr), [{ 570 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 571}]>; 572def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 573 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 574}]>; 575def DSFormPreStore : PatFrag< 576 (ops node:$val, node:$base, node:$offset), 577 (pre_store node:$val, node:$base, node:$offset), [{ 578 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 579}]>; 580 581def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 582 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 583}]>; 584def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 585 (store node:$val, node:$ptr), [{ 586 return cast<StoreSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 587}]>; 588def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 589 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 590}]>; 591 592// This is a somewhat weaker condition than actually checking for 16-byte 593// alignment. It is simply checking that the displacement can be represented 594// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 595// instructions). 596def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 597 return isOffsetMultipleOf(N, 16); 598}]>; 599def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 600 (store node:$val, node:$ptr), [{ 601 return isOffsetMultipleOf(N, 16); 602}]>; 603def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 604 return !isOffsetMultipleOf(N, 16); 605}]>; 606def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 607 (store node:$val, node:$ptr), [{ 608 return !isOffsetMultipleOf(N, 16); 609}]>; 610 611// PatFrag for binary operation whose operands are both non-constant 612class BinOpWithoutSImm16Operand<SDNode opcode> : 613 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 614 int16_t Imm; 615 return !isIntS16Immediate(N->getOperand(0), Imm) 616 && !isIntS16Immediate(N->getOperand(1), Imm); 617}]>; 618 619def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 620def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 621 622//===----------------------------------------------------------------------===// 623// PowerPC Flag Definitions. 624 625class isPPC64 { bit PPC64 = 1; } 626class isRecordForm { bit RC = 1; } 627 628class RegConstraint<string C> { 629 string Constraints = C; 630} 631class NoEncode<string E> { 632 string DisableEncoding = E; 633} 634 635 636//===----------------------------------------------------------------------===// 637// PowerPC Operand Definitions. 638 639// In the default PowerPC assembler syntax, registers are specified simply 640// by number, so they cannot be distinguished from immediate values (without 641// looking at the opcode). This means that the default operand matching logic 642// for the asm parser does not work, and we need to specify custom matchers. 643// Since those can only be specified with RegisterOperand classes and not 644// directly on the RegisterClass, all instructions patterns used by the asm 645// parser need to use a RegisterOperand (instead of a RegisterClass) for 646// all their register operands. 647// For this purpose, we define one RegisterOperand for each RegisterClass, 648// using the same name as the class, just in lower case. 649 650def PPCRegGPRCAsmOperand : AsmOperandClass { 651 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 652} 653def gprc : RegisterOperand<GPRC> { 654 let ParserMatchClass = PPCRegGPRCAsmOperand; 655} 656def PPCRegG8RCAsmOperand : AsmOperandClass { 657 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 658} 659def g8rc : RegisterOperand<G8RC> { 660 let ParserMatchClass = PPCRegG8RCAsmOperand; 661} 662def PPCRegG8pRCAsmOperand : AsmOperandClass { 663 let Name = "RegG8pRC"; let PredicateMethod = "isEvenRegNumber"; 664} 665def g8prc : RegisterOperand<G8pRC> { 666 let ParserMatchClass = PPCRegG8pRCAsmOperand; 667} 668def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 669 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 670} 671def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 672 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 673} 674def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 675 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 676} 677def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 678 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 679} 680def PPCRegF8RCAsmOperand : AsmOperandClass { 681 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 682} 683def f8rc : RegisterOperand<F8RC> { 684 let ParserMatchClass = PPCRegF8RCAsmOperand; 685} 686def PPCRegF4RCAsmOperand : AsmOperandClass { 687 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 688} 689def f4rc : RegisterOperand<F4RC> { 690 let ParserMatchClass = PPCRegF4RCAsmOperand; 691} 692def PPCRegVRRCAsmOperand : AsmOperandClass { 693 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 694} 695def vrrc : RegisterOperand<VRRC> { 696 let ParserMatchClass = PPCRegVRRCAsmOperand; 697} 698def PPCRegVFRCAsmOperand : AsmOperandClass { 699 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 700} 701def vfrc : RegisterOperand<VFRC> { 702 let ParserMatchClass = PPCRegVFRCAsmOperand; 703} 704def PPCRegCRBITRCAsmOperand : AsmOperandClass { 705 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 706} 707def crbitrc : RegisterOperand<CRBITRC> { 708 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 709} 710def PPCRegCRRCAsmOperand : AsmOperandClass { 711 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 712} 713def crrc : RegisterOperand<CRRC> { 714 let ParserMatchClass = PPCRegCRRCAsmOperand; 715} 716def PPCRegSPERCAsmOperand : AsmOperandClass { 717 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 718} 719def sperc : RegisterOperand<SPERC> { 720 let ParserMatchClass = PPCRegSPERCAsmOperand; 721} 722def PPCRegSPE4RCAsmOperand : AsmOperandClass { 723 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 724} 725def spe4rc : RegisterOperand<GPRC> { 726 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 727} 728 729def PPCU1ImmAsmOperand : AsmOperandClass { 730 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 731 let RenderMethod = "addImmOperands"; 732} 733def u1imm : Operand<i32> { 734 let PrintMethod = "printU1ImmOperand"; 735 let ParserMatchClass = PPCU1ImmAsmOperand; 736 let OperandType = "OPERAND_IMMEDIATE"; 737} 738 739def PPCU2ImmAsmOperand : AsmOperandClass { 740 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 741 let RenderMethod = "addImmOperands"; 742} 743def u2imm : Operand<i32> { 744 let PrintMethod = "printU2ImmOperand"; 745 let ParserMatchClass = PPCU2ImmAsmOperand; 746 let OperandType = "OPERAND_IMMEDIATE"; 747} 748 749def PPCATBitsAsHintAsmOperand : AsmOperandClass { 750 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 751 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 752} 753def atimm : Operand<i32> { 754 let PrintMethod = "printATBitsAsHint"; 755 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 756 let OperandType = "OPERAND_IMMEDIATE"; 757} 758 759def PPCU3ImmAsmOperand : AsmOperandClass { 760 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 761 let RenderMethod = "addImmOperands"; 762} 763def u3imm : Operand<i32> { 764 let PrintMethod = "printU3ImmOperand"; 765 let ParserMatchClass = PPCU3ImmAsmOperand; 766 let OperandType = "OPERAND_IMMEDIATE"; 767} 768 769def PPCU4ImmAsmOperand : AsmOperandClass { 770 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 771 let RenderMethod = "addImmOperands"; 772} 773def u4imm : Operand<i32> { 774 let PrintMethod = "printU4ImmOperand"; 775 let ParserMatchClass = PPCU4ImmAsmOperand; 776 let OperandType = "OPERAND_IMMEDIATE"; 777} 778def PPCS5ImmAsmOperand : AsmOperandClass { 779 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 780 let RenderMethod = "addImmOperands"; 781} 782def s5imm : Operand<i32> { 783 let PrintMethod = "printS5ImmOperand"; 784 let ParserMatchClass = PPCS5ImmAsmOperand; 785 let DecoderMethod = "decodeSImmOperand<5>"; 786 let OperandType = "OPERAND_IMMEDIATE"; 787} 788def PPCU5ImmAsmOperand : AsmOperandClass { 789 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 790 let RenderMethod = "addImmOperands"; 791} 792def u5imm : Operand<i32> { 793 let PrintMethod = "printU5ImmOperand"; 794 let ParserMatchClass = PPCU5ImmAsmOperand; 795 let DecoderMethod = "decodeUImmOperand<5>"; 796 let OperandType = "OPERAND_IMMEDIATE"; 797} 798def PPCU6ImmAsmOperand : AsmOperandClass { 799 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 800 let RenderMethod = "addImmOperands"; 801} 802def u6imm : Operand<i32> { 803 let PrintMethod = "printU6ImmOperand"; 804 let ParserMatchClass = PPCU6ImmAsmOperand; 805 let DecoderMethod = "decodeUImmOperand<6>"; 806 let OperandType = "OPERAND_IMMEDIATE"; 807} 808def PPCU7ImmAsmOperand : AsmOperandClass { 809 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 810 let RenderMethod = "addImmOperands"; 811} 812def u7imm : Operand<i32> { 813 let PrintMethod = "printU7ImmOperand"; 814 let ParserMatchClass = PPCU7ImmAsmOperand; 815 let DecoderMethod = "decodeUImmOperand<7>"; 816 let OperandType = "OPERAND_IMMEDIATE"; 817} 818def PPCU8ImmAsmOperand : AsmOperandClass { 819 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 820 let RenderMethod = "addImmOperands"; 821} 822def u8imm : Operand<i32> { 823 let PrintMethod = "printU8ImmOperand"; 824 let ParserMatchClass = PPCU8ImmAsmOperand; 825 let DecoderMethod = "decodeUImmOperand<8>"; 826 let OperandType = "OPERAND_IMMEDIATE"; 827} 828def PPCU10ImmAsmOperand : AsmOperandClass { 829 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 830 let RenderMethod = "addImmOperands"; 831} 832def u10imm : Operand<i32> { 833 let PrintMethod = "printU10ImmOperand"; 834 let ParserMatchClass = PPCU10ImmAsmOperand; 835 let DecoderMethod = "decodeUImmOperand<10>"; 836 let OperandType = "OPERAND_IMMEDIATE"; 837} 838def PPCU12ImmAsmOperand : AsmOperandClass { 839 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 840 let RenderMethod = "addImmOperands"; 841} 842def u12imm : Operand<i32> { 843 let PrintMethod = "printU12ImmOperand"; 844 let ParserMatchClass = PPCU12ImmAsmOperand; 845 let DecoderMethod = "decodeUImmOperand<12>"; 846 let OperandType = "OPERAND_IMMEDIATE"; 847} 848def PPCS16ImmAsmOperand : AsmOperandClass { 849 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 850 let RenderMethod = "addS16ImmOperands"; 851} 852def s16imm : Operand<i32> { 853 let PrintMethod = "printS16ImmOperand"; 854 let EncoderMethod = "getImm16Encoding"; 855 let ParserMatchClass = PPCS16ImmAsmOperand; 856 let DecoderMethod = "decodeSImmOperand<16>"; 857 let OperandType = "OPERAND_IMMEDIATE"; 858} 859def PPCU16ImmAsmOperand : AsmOperandClass { 860 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 861 let RenderMethod = "addU16ImmOperands"; 862} 863def u16imm : Operand<i32> { 864 let PrintMethod = "printU16ImmOperand"; 865 let EncoderMethod = "getImm16Encoding"; 866 let ParserMatchClass = PPCU16ImmAsmOperand; 867 let DecoderMethod = "decodeUImmOperand<16>"; 868 let OperandType = "OPERAND_IMMEDIATE"; 869} 870def PPCS17ImmAsmOperand : AsmOperandClass { 871 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 872 let RenderMethod = "addS16ImmOperands"; 873} 874def s17imm : Operand<i32> { 875 // This operand type is used for addis/lis to allow the assembler parser 876 // to accept immediates in the range -65536..65535 for compatibility with 877 // the GNU assembler. The operand is treated as 16-bit otherwise. 878 let PrintMethod = "printS16ImmOperand"; 879 let EncoderMethod = "getImm16Encoding"; 880 let ParserMatchClass = PPCS17ImmAsmOperand; 881 let DecoderMethod = "decodeSImmOperand<16>"; 882 let OperandType = "OPERAND_IMMEDIATE"; 883} 884def PPCS34ImmAsmOperand : AsmOperandClass { 885 let Name = "S34Imm"; 886 let PredicateMethod = "isS34Imm"; 887 let RenderMethod = "addImmOperands"; 888} 889def s34imm : Operand<i64> { 890 let PrintMethod = "printS34ImmOperand"; 891 let EncoderMethod = "getImm34EncodingNoPCRel"; 892 let ParserMatchClass = PPCS34ImmAsmOperand; 893 let DecoderMethod = "decodeSImmOperand<34>"; 894 let OperandType = "OPERAND_IMMEDIATE"; 895} 896def s34imm_pcrel : Operand<i64> { 897 let PrintMethod = "printS34ImmOperand"; 898 let EncoderMethod = "getImm34EncodingPCRel"; 899 let ParserMatchClass = PPCS34ImmAsmOperand; 900 let DecoderMethod = "decodeSImmOperand<34>"; 901 let OperandType = "OPERAND_IMMEDIATE"; 902} 903def PPCImmZeroAsmOperand : AsmOperandClass { 904 let Name = "ImmZero"; 905 let PredicateMethod = "isImmZero"; 906 let RenderMethod = "addImmOperands"; 907} 908def immZero : Operand<i32> { 909 let PrintMethod = "printImmZeroOperand"; 910 let ParserMatchClass = PPCImmZeroAsmOperand; 911 let DecoderMethod = "decodeImmZeroOperand"; 912 let OperandType = "OPERAND_IMMEDIATE"; 913} 914 915def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 916 917def PPCDirectBrAsmOperand : AsmOperandClass { 918 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 919 let RenderMethod = "addBranchTargetOperands"; 920} 921def directbrtarget : Operand<OtherVT> { 922 let PrintMethod = "printBranchOperand"; 923 let EncoderMethod = "getDirectBrEncoding"; 924 let DecoderMethod = "decodeDirectBrTarget"; 925 let ParserMatchClass = PPCDirectBrAsmOperand; 926 let OperandType = "OPERAND_PCREL"; 927} 928def absdirectbrtarget : Operand<OtherVT> { 929 let PrintMethod = "printAbsBranchOperand"; 930 let EncoderMethod = "getAbsDirectBrEncoding"; 931 let ParserMatchClass = PPCDirectBrAsmOperand; 932} 933def PPCCondBrAsmOperand : AsmOperandClass { 934 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 935 let RenderMethod = "addBranchTargetOperands"; 936} 937def condbrtarget : Operand<OtherVT> { 938 let PrintMethod = "printBranchOperand"; 939 let EncoderMethod = "getCondBrEncoding"; 940 let DecoderMethod = "decodeCondBrTarget"; 941 let ParserMatchClass = PPCCondBrAsmOperand; 942 let OperandType = "OPERAND_PCREL"; 943} 944def abscondbrtarget : Operand<OtherVT> { 945 let PrintMethod = "printAbsBranchOperand"; 946 let EncoderMethod = "getAbsCondBrEncoding"; 947 let ParserMatchClass = PPCCondBrAsmOperand; 948} 949def calltarget : Operand<iPTR> { 950 let PrintMethod = "printBranchOperand"; 951 let EncoderMethod = "getDirectBrEncoding"; 952 let DecoderMethod = "decodeDirectBrTarget"; 953 let ParserMatchClass = PPCDirectBrAsmOperand; 954 let OperandType = "OPERAND_PCREL"; 955} 956def abscalltarget : Operand<iPTR> { 957 let PrintMethod = "printAbsBranchOperand"; 958 let EncoderMethod = "getAbsDirectBrEncoding"; 959 let ParserMatchClass = PPCDirectBrAsmOperand; 960} 961def PPCCRBitMaskOperand : AsmOperandClass { 962 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 963} 964def crbitm: Operand<i8> { 965 let PrintMethod = "printcrbitm"; 966 let EncoderMethod = "get_crbitm_encoding"; 967 let DecoderMethod = "decodeCRBitMOperand"; 968 let ParserMatchClass = PPCCRBitMaskOperand; 969} 970// Address operands 971// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 972def PPCRegGxRCNoR0Operand : AsmOperandClass { 973 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 974} 975def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 976 let ParserMatchClass = PPCRegGxRCNoR0Operand; 977} 978 979// New addressing modes with 34 bit immediates. 980def PPCDispRI34Operand : AsmOperandClass { 981 let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; 982 let RenderMethod = "addImmOperands"; 983} 984def dispRI34 : Operand<iPTR> { 985 let ParserMatchClass = PPCDispRI34Operand; 986} 987def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. 988 let PrintMethod = "printMemRegImm34"; 989 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 990 let EncoderMethod = "getMemRI34Encoding"; 991 let DecoderMethod = "decodeMemRI34Operands"; 992} 993// memri, imm is a 34-bit value for pc-relative instructions where 994// base register is set to zero. 995def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. 996 let PrintMethod = "printMemRegImm34PCRel"; 997 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 998 let EncoderMethod = "getMemRI34PCRelEncoding"; 999 let DecoderMethod = "decodeMemRI34PCRelOperands"; 1000} 1001 1002// A version of ptr_rc usable with the asm parser. 1003def PPCRegGxRCOperand : AsmOperandClass { 1004 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 1005} 1006def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 1007 let ParserMatchClass = PPCRegGxRCOperand; 1008} 1009 1010def PPCDispRIOperand : AsmOperandClass { 1011 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 1012 let RenderMethod = "addS16ImmOperands"; 1013} 1014def dispRI : Operand<iPTR> { 1015 let ParserMatchClass = PPCDispRIOperand; 1016} 1017def PPCDispRIXOperand : AsmOperandClass { 1018 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 1019 let RenderMethod = "addS16ImmOperands"; 1020} 1021def dispRIX : Operand<iPTR> { 1022 let ParserMatchClass = PPCDispRIXOperand; 1023} 1024def PPCDispRIHashOperand : AsmOperandClass { 1025 let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8"; 1026 let RenderMethod = "addImmOperands"; 1027} 1028def dispRIHash : Operand<iPTR> { 1029 let ParserMatchClass = PPCDispRIHashOperand; 1030} 1031def PPCDispRIX16Operand : AsmOperandClass { 1032 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 1033 let RenderMethod = "addS16ImmOperands"; 1034} 1035def dispRIX16 : Operand<iPTR> { 1036 let ParserMatchClass = PPCDispRIX16Operand; 1037} 1038def PPCDispSPE8Operand : AsmOperandClass { 1039 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 1040 let RenderMethod = "addImmOperands"; 1041} 1042def dispSPE8 : Operand<iPTR> { 1043 let ParserMatchClass = PPCDispSPE8Operand; 1044} 1045def PPCDispSPE4Operand : AsmOperandClass { 1046 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 1047 let RenderMethod = "addImmOperands"; 1048} 1049def dispSPE4 : Operand<iPTR> { 1050 let ParserMatchClass = PPCDispSPE4Operand; 1051} 1052def PPCDispSPE2Operand : AsmOperandClass { 1053 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 1054 let RenderMethod = "addImmOperands"; 1055} 1056def dispSPE2 : Operand<iPTR> { 1057 let ParserMatchClass = PPCDispSPE2Operand; 1058} 1059 1060def memri : Operand<iPTR> { 1061 let PrintMethod = "printMemRegImm"; 1062 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 1063 let EncoderMethod = "getMemRIEncoding"; 1064 let DecoderMethod = "decodeMemRIOperands"; 1065 let OperandType = "OPERAND_MEMORY"; 1066} 1067def memrr : Operand<iPTR> { 1068 let PrintMethod = "printMemRegReg"; 1069 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 1070 let OperandType = "OPERAND_MEMORY"; 1071} 1072def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 1073 let PrintMethod = "printMemRegImm"; 1074 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 1075 let EncoderMethod = "getMemRIXEncoding"; 1076 let DecoderMethod = "decodeMemRIXOperands"; 1077 let OperandType = "OPERAND_MEMORY"; 1078} 1079def memrihash : Operand<iPTR> { 1080 // memrihash 8-aligned for ROP Protection Instructions. 1081 let PrintMethod = "printMemRegImmHash"; 1082 let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); 1083 let EncoderMethod = "getMemRIHashEncoding"; 1084 let DecoderMethod = "decodeMemRIHashOperands"; 1085 let OperandType = "OPERAND_MEMORY"; 1086} 1087def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 1088 let PrintMethod = "printMemRegImm"; 1089 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 1090 let EncoderMethod = "getMemRIX16Encoding"; 1091 let DecoderMethod = "decodeMemRIX16Operands"; 1092 let OperandType = "OPERAND_MEMORY"; 1093} 1094def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 1095 let PrintMethod = "printMemRegImm"; 1096 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 1097 let EncoderMethod = "getSPE8DisEncoding"; 1098 let DecoderMethod = "decodeSPE8Operands"; 1099 let OperandType = "OPERAND_MEMORY"; 1100} 1101def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 1102 let PrintMethod = "printMemRegImm"; 1103 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 1104 let EncoderMethod = "getSPE4DisEncoding"; 1105 let DecoderMethod = "decodeSPE4Operands"; 1106 let OperandType = "OPERAND_MEMORY"; 1107} 1108def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 1109 let PrintMethod = "printMemRegImm"; 1110 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 1111 let EncoderMethod = "getSPE2DisEncoding"; 1112 let DecoderMethod = "decodeSPE2Operands"; 1113 let OperandType = "OPERAND_MEMORY"; 1114} 1115 1116// A single-register address. This is used with the SjLj 1117// pseudo-instructions which translates to LD/LWZ. These instructions requires 1118// G8RC_NOX0 registers. 1119def memr : Operand<iPTR> { 1120 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 1121 let OperandType = "OPERAND_MEMORY"; 1122} 1123def PPCTLSRegOperand : AsmOperandClass { 1124 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 1125 let RenderMethod = "addTLSRegOperands"; 1126} 1127def tlsreg32 : Operand<i32> { 1128 let EncoderMethod = "getTLSRegEncoding"; 1129 let ParserMatchClass = PPCTLSRegOperand; 1130} 1131def tlsgd32 : Operand<i32> {} 1132def tlscall32 : Operand<i32> { 1133 let PrintMethod = "printTLSCall"; 1134 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 1135 let EncoderMethod = "getTLSCallEncoding"; 1136} 1137 1138// PowerPC Predicate operand. 1139def pred : Operand<OtherVT> { 1140 let PrintMethod = "printPredicateOperand"; 1141 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 1142} 1143 1144// Define PowerPC specific addressing mode. 1145 1146// d-form 1147def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 1148// ds-form 1149def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 1150// dq-form 1151def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 1152// 8LS:d-form 1153def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 1154 1155// Below forms are all x-form addressing mode, use three different ones so we 1156// can make a accurate check for x-form instructions in ISEL. 1157// x-form addressing mode whose associated displacement form is D. 1158def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 1159// x-form addressing mode whose associated displacement form is DS. 1160def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 1161// x-form addressing mode whose associated displacement form is DQ. 1162def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 1163 1164def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 1165 1166// The address in a single register. This is used with the SjLj 1167// pseudo-instructions. 1168def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 1169 1170/// This is just the offset part of iaddr, used for preinc. 1171def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 1172 1173// Load and Store Instruction Selection addressing modes. 1174def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 1175def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 1176def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 1177def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 1178def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 1179def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; 1180def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; 1181 1182//===----------------------------------------------------------------------===// 1183// PowerPC Instruction Predicate Definitions. 1184def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 1185def In64BitMode : Predicate<"Subtarget->isPPC64()">; 1186def IsBookE : Predicate<"Subtarget->isBookE()">; 1187def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 1188def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 1189def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 1190def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 1191def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 1192def IsE500 : Predicate<"Subtarget->isE500()">; 1193def HasSPE : Predicate<"Subtarget->hasSPE()">; 1194def HasICBT : Predicate<"Subtarget->hasICBT()">; 1195def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 1196def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 1197def NoNaNsFPMath 1198 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 1199def NaNsFPMath 1200 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 1201def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 1202def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 1203def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 1204def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 1205def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 1206def HasFPU : Predicate<"Subtarget->hasFPU()">; 1207def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 1208def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 1209 1210// AIX assembler may not be modern enough to support some extended mne. 1211def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 1212 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 1213def IsAIX : Predicate<"Subtarget->isAIXABI()">; 1214def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 1215 1216//===----------------------------------------------------------------------===// 1217// PowerPC Multiclass Definitions. 1218 1219multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1220 string asmbase, string asmstr, InstrItinClass itin, 1221 list<dag> pattern> { 1222 let BaseName = asmbase in { 1223 def NAME : XForm_6<opcode, xo, OOL, IOL, 1224 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1225 pattern>, RecFormRel; 1226 let Defs = [CR0] in 1227 def _rec : XForm_6<opcode, xo, OOL, IOL, 1228 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1229 []>, isRecordForm, RecFormRel; 1230 } 1231} 1232 1233multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1234 string asmbase, string asmstr, InstrItinClass itin, 1235 list<dag> pattern> { 1236 let BaseName = asmbase in { 1237 let Defs = [CARRY] in 1238 def NAME : XForm_6<opcode, xo, OOL, IOL, 1239 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1240 pattern>, RecFormRel; 1241 let Defs = [CARRY, CR0] in 1242 def _rec : XForm_6<opcode, xo, OOL, IOL, 1243 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1244 []>, isRecordForm, RecFormRel; 1245 } 1246} 1247 1248multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1249 string asmbase, string asmstr, InstrItinClass itin, 1250 list<dag> pattern> { 1251 let BaseName = asmbase in { 1252 let Defs = [CARRY] in 1253 def NAME : XForm_10<opcode, xo, OOL, IOL, 1254 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1255 pattern>, RecFormRel; 1256 let Defs = [CARRY, CR0] in 1257 def _rec : XForm_10<opcode, xo, OOL, IOL, 1258 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1259 []>, isRecordForm, RecFormRel; 1260 } 1261} 1262 1263multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1264 string asmbase, string asmstr, InstrItinClass itin, 1265 list<dag> pattern> { 1266 let BaseName = asmbase in { 1267 def NAME : XForm_11<opcode, xo, OOL, IOL, 1268 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1269 pattern>, RecFormRel; 1270 let Defs = [CR0] in 1271 def _rec : XForm_11<opcode, xo, OOL, IOL, 1272 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1273 []>, isRecordForm, RecFormRel; 1274 } 1275} 1276 1277multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1278 string asmbase, string asmstr, InstrItinClass itin, 1279 list<dag> pattern> { 1280 let BaseName = asmbase in { 1281 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1282 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1283 pattern>, RecFormRel; 1284 let Defs = [CR0] in 1285 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1286 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1287 []>, isRecordForm, RecFormRel; 1288 } 1289} 1290 1291// Multiclass for instructions which have a record overflow form as well 1292// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 1293multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1294 string asmbase, string asmstr, InstrItinClass itin, 1295 list<dag> pattern> { 1296 let BaseName = asmbase in { 1297 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 1298 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1299 pattern>, RecFormRel; 1300 let Defs = [CR0] in 1301 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 1302 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1303 []>, isRecordForm, RecFormRel; 1304 } 1305 let BaseName = !strconcat(asmbase, "O") in { 1306 let Defs = [XER] in 1307 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1308 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1309 []>, RecFormRel; 1310 let Defs = [XER, CR0] in 1311 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1312 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1313 []>, isRecordForm, RecFormRel; 1314 } 1315} 1316 1317// Multiclass for instructions for which the non record form is not cracked 1318// and the record form is cracked (i.e. divw, mullw, etc.) 1319multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1320 string asmbase, string asmstr, InstrItinClass itin, 1321 list<dag> pattern> { 1322 let BaseName = asmbase in { 1323 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1324 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1325 pattern>, RecFormRel; 1326 let Defs = [CR0] in 1327 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1328 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1329 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 1330 PPC970_DGroup_Cracked; 1331 } 1332 let BaseName = !strconcat(asmbase, "O") in { 1333 let Defs = [XER] in 1334 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1335 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1336 []>, RecFormRel; 1337 let Defs = [XER, CR0] in 1338 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1339 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1340 []>, isRecordForm, RecFormRel; 1341 } 1342} 1343 1344multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1345 string asmbase, string asmstr, InstrItinClass itin, 1346 list<dag> pattern> { 1347 let BaseName = asmbase in { 1348 let Defs = [CARRY] in 1349 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1350 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1351 pattern>, RecFormRel; 1352 let Defs = [CARRY, CR0] in 1353 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1354 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1355 []>, isRecordForm, RecFormRel; 1356 } 1357 let BaseName = !strconcat(asmbase, "O") in { 1358 let Defs = [CARRY, XER] in 1359 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1360 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1361 []>, RecFormRel; 1362 let Defs = [CARRY, XER, CR0] in 1363 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1364 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1365 []>, isRecordForm, RecFormRel; 1366 } 1367} 1368 1369multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1370 string asmbase, string asmstr, InstrItinClass itin, 1371 list<dag> pattern> { 1372 let BaseName = asmbase in { 1373 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1374 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1375 pattern>, RecFormRel; 1376 let Defs = [CR0] in 1377 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1378 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1379 []>, isRecordForm, RecFormRel; 1380 } 1381 let BaseName = !strconcat(asmbase, "O") in { 1382 let Defs = [XER] in 1383 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1384 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1385 []>, RecFormRel; 1386 let Defs = [XER, CR0] in 1387 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1388 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1389 []>, isRecordForm, RecFormRel; 1390 } 1391} 1392 1393multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1394 string asmbase, string asmstr, InstrItinClass itin, 1395 list<dag> pattern> { 1396 let BaseName = asmbase in { 1397 let Defs = [CARRY] in 1398 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1399 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1400 pattern>, RecFormRel; 1401 let Defs = [CARRY, CR0] in 1402 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1403 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1404 []>, isRecordForm, RecFormRel; 1405 } 1406 let BaseName = !strconcat(asmbase, "O") in { 1407 let Defs = [CARRY, XER] in 1408 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1409 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1410 []>, RecFormRel; 1411 let Defs = [CARRY, XER, CR0] in 1412 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1413 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1414 []>, isRecordForm, RecFormRel; 1415 } 1416} 1417 1418multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 1419 string asmbase, string asmstr, InstrItinClass itin, 1420 list<dag> pattern> { 1421 let BaseName = asmbase in { 1422 def NAME : MForm_2<opcode, OOL, IOL, 1423 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1424 pattern>, RecFormRel; 1425 let Defs = [CR0] in 1426 def _rec : MForm_2<opcode, OOL, IOL, 1427 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1428 []>, isRecordForm, RecFormRel; 1429 } 1430} 1431 1432multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 1433 string asmbase, string asmstr, InstrItinClass itin, 1434 list<dag> pattern> { 1435 let BaseName = asmbase in { 1436 def NAME : MDForm_1<opcode, xo, OOL, IOL, 1437 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1438 pattern>, RecFormRel; 1439 let Defs = [CR0] in 1440 def _rec : MDForm_1<opcode, xo, OOL, IOL, 1441 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1442 []>, isRecordForm, RecFormRel; 1443 } 1444} 1445 1446multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 1447 string asmbase, string asmstr, InstrItinClass itin, 1448 list<dag> pattern> { 1449 let BaseName = asmbase in { 1450 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 1451 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1452 pattern>, RecFormRel; 1453 let Defs = [CR0] in 1454 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1455 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1456 []>, isRecordForm, RecFormRel; 1457 } 1458} 1459 1460multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1461 string asmbase, string asmstr, InstrItinClass itin, 1462 list<dag> pattern> { 1463 let BaseName = asmbase in { 1464 let Defs = [CARRY] in 1465 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1466 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1467 pattern>, RecFormRel; 1468 let Defs = [CARRY, CR0] in 1469 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1470 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1471 []>, isRecordForm, RecFormRel; 1472 } 1473} 1474 1475multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1476 string asmbase, string asmstr, InstrItinClass itin, 1477 list<dag> pattern> { 1478 let BaseName = asmbase in { 1479 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1480 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1481 pattern>, RecFormRel; 1482 let Defs = [CR0] in 1483 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1484 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1485 []>, isRecordForm, RecFormRel; 1486 } 1487} 1488 1489multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1490 string asmbase, string asmstr, InstrItinClass itin, 1491 list<dag> pattern> { 1492 let BaseName = asmbase in { 1493 def NAME : XForm_26<opcode, xo, OOL, IOL, 1494 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1495 pattern>, RecFormRel; 1496 let Defs = [CR1] in 1497 def _rec : XForm_26<opcode, xo, OOL, IOL, 1498 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1499 []>, isRecordForm, RecFormRel; 1500 } 1501} 1502 1503multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1504 string asmbase, string asmstr, InstrItinClass itin, 1505 list<dag> pattern> { 1506 let BaseName = asmbase in { 1507 def NAME : XForm_28<opcode, xo, OOL, IOL, 1508 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1509 pattern>, RecFormRel; 1510 let Defs = [CR1] in 1511 def _rec : XForm_28<opcode, xo, OOL, IOL, 1512 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1513 []>, isRecordForm, RecFormRel; 1514 } 1515} 1516 1517multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1518 string asmbase, string asmstr, InstrItinClass itin, 1519 list<dag> pattern> { 1520 let BaseName = asmbase in { 1521 def NAME : AForm_1<opcode, xo, OOL, IOL, 1522 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1523 pattern>, RecFormRel; 1524 let Defs = [CR1] in 1525 def _rec : AForm_1<opcode, xo, OOL, IOL, 1526 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1527 []>, isRecordForm, RecFormRel; 1528 } 1529} 1530 1531multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1532 string asmbase, string asmstr, InstrItinClass itin, 1533 list<dag> pattern> { 1534 let BaseName = asmbase in { 1535 def NAME : AForm_2<opcode, xo, OOL, IOL, 1536 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1537 pattern>, RecFormRel; 1538 let Defs = [CR1] in 1539 def _rec : AForm_2<opcode, xo, OOL, IOL, 1540 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1541 []>, isRecordForm, RecFormRel; 1542 } 1543} 1544 1545multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1546 string asmbase, string asmstr, InstrItinClass itin, 1547 list<dag> pattern> { 1548 let BaseName = asmbase in { 1549 def NAME : AForm_3<opcode, xo, OOL, IOL, 1550 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1551 pattern>, RecFormRel; 1552 let Defs = [CR1] in 1553 def _rec : AForm_3<opcode, xo, OOL, IOL, 1554 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1555 []>, isRecordForm, RecFormRel; 1556 } 1557} 1558 1559//===----------------------------------------------------------------------===// 1560// PowerPC Instruction Definitions. 1561 1562// Pseudo instructions: 1563 1564let hasCtrlDep = 1 in { 1565let Defs = [R1], Uses = [R1] in { 1566def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1567 "#ADJCALLSTACKDOWN $amt1 $amt2", 1568 [(callseq_start timm:$amt1, timm:$amt2)]>; 1569def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1570 "#ADJCALLSTACKUP $amt1 $amt2", 1571 [(callseq_end timm:$amt1, timm:$amt2)]>; 1572} 1573} // hasCtrlDep 1574 1575let Defs = [R1], Uses = [R1] in 1576def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1577 [(set i32:$result, 1578 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1579def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1580 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1581// Probed alloca to support stack clash protection. 1582let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1583def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1584 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1585 [(set i32:$result, 1586 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1587def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1588 gprc:$fp, gprc:$actual_negsize), 1589 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1590def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1591 gprc:$fp, gprc:$actual_negsize), 1592 (ins gprc:$negsize, memri:$fpsi), 1593 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1594 RegConstraint<"$actual_negsize = $negsize">; 1595def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1596 (ins i64imm:$stacksize), 1597 "#PROBED_STACKALLOC_32", []>; 1598} 1599 1600// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1601// instruction selection into a branch sequence. 1602let PPC970_Single = 1 in { 1603 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1604 // because either operand might become the first operand in an isel, and 1605 // that operand cannot be r0. 1606 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1607 gprc_nor0:$T, gprc_nor0:$F, 1608 i32imm:$BROPC), "#SELECT_CC_I4", 1609 []>; 1610 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1611 g8rc_nox0:$T, g8rc_nox0:$F, 1612 i32imm:$BROPC), "#SELECT_CC_I8", 1613 []>; 1614 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1615 i32imm:$BROPC), "#SELECT_CC_F4", 1616 []>; 1617 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1618 i32imm:$BROPC), "#SELECT_CC_F8", 1619 []>; 1620 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1621 i32imm:$BROPC), "#SELECT_CC_F16", 1622 []>; 1623 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1624 i32imm:$BROPC), "#SELECT_CC_VRRC", 1625 []>; 1626 1627 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1628 // register bit directly. 1629 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1630 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1631 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1632 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1633 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1634 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1635let Predicates = [HasFPU] in { 1636 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1637 f4rc:$T, f4rc:$F), "#SELECT_F4", 1638 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1639 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1640 f8rc:$T, f8rc:$F), "#SELECT_F8", 1641 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1642 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1643 vrrc:$T, vrrc:$F), "#SELECT_F16", 1644 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1645} 1646 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1647 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1648 [(set v4i32:$dst, 1649 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1650} 1651 1652// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1653// scavenge a register for it. 1654let mayStore = 1 in { 1655def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1656 "#SPILL_CR", []>; 1657def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1658 "#SPILL_CRBIT", []>; 1659} 1660 1661// RESTORE_CR - Indicate that we're restoring the CR register (previously 1662// spilled), so we'll need to scavenge a register for it. 1663let mayLoad = 1 in { 1664def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1665 "#RESTORE_CR", []>; 1666def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1667 "#RESTORE_CRBIT", []>; 1668} 1669 1670let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1671 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1672 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1673 [(retflag)]>, Requires<[In32BitMode]>; 1674 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1675 let isPredicable = 1 in 1676 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1677 []>; 1678 1679 let isCodeGenOnly = 1 in { 1680 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1681 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1682 []>; 1683 1684 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1685 "bcctr 12, $bi, 0", IIC_BrB, []>; 1686 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1687 "bcctr 4, $bi, 0", IIC_BrB, []>; 1688 } 1689 } 1690} 1691 1692// Set the float rounding mode. 1693let Uses = [RM], Defs = [RM] in { 1694def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1695 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1696 1697def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1698 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1699 1700def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1701 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1702} 1703 1704let Defs = [LR] in 1705 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1706 PPC970_Unit_BRU; 1707let Defs = [LR] in 1708 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1709 PPC970_Unit_BRU; 1710 1711let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1712 hasSideEffects = 0 in { 1713 let isBarrier = 1 in { 1714 let isPredicable = 1 in 1715 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1716 "b $dst", IIC_BrB, 1717 [(br bb:$dst)]>; 1718 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1719 "ba $dst", IIC_BrB, []>; 1720 } 1721 1722 // BCC represents an arbitrary conditional branch on a predicate. 1723 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1724 // a two-value operand where a dag node expects two operands. :( 1725 let isCodeGenOnly = 1 in { 1726 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1727 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1728 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1729 def BCC : BCC_class; 1730 1731 // The same as BCC, except that it's not a terminator. Used for introducing 1732 // control flow dependency without creating new blocks. 1733 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1734 1735 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1736 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1737 1738 let isReturn = 1, Uses = [LR, RM] in 1739 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1740 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1741 } 1742 1743 let isCodeGenOnly = 1 in { 1744 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1745 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1746 "bc 12, $bi, $dst">; 1747 1748 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1749 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1750 "bc 4, $bi, $dst">; 1751 1752 let isReturn = 1, Uses = [LR, RM] in { 1753 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1754 "bclr 12, $bi, 0", IIC_BrB, []>; 1755 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1756 "bclr 4, $bi, 0", IIC_BrB, []>; 1757 } 1758 } 1759 1760 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1761 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1762 "bdzlr", IIC_BrB, []>; 1763 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1764 "bdnzlr", IIC_BrB, []>; 1765 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1766 "bdzlr+", IIC_BrB, []>; 1767 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1768 "bdnzlr+", IIC_BrB, []>; 1769 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1770 "bdzlr-", IIC_BrB, []>; 1771 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1772 "bdnzlr-", IIC_BrB, []>; 1773 } 1774 1775 let Defs = [CTR], Uses = [CTR] in { 1776 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1777 "bdz $dst">; 1778 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1779 "bdnz $dst">; 1780 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1781 "bdza $dst">; 1782 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1783 "bdnza $dst">; 1784 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1785 "bdz+ $dst">; 1786 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1787 "bdnz+ $dst">; 1788 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1789 "bdza+ $dst">; 1790 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1791 "bdnza+ $dst">; 1792 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1793 "bdz- $dst">; 1794 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1795 "bdnz- $dst">; 1796 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1797 "bdza- $dst">; 1798 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1799 "bdnza- $dst">; 1800 } 1801} 1802 1803// The unconditional BCL used by the SjLj setjmp code. 1804let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1805 hasSideEffects = 0 in { 1806 let Defs = [LR], Uses = [RM] in { 1807 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1808 "bcl 20, 31, $dst">; 1809 } 1810} 1811 1812let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1813 // Convenient aliases for call instructions 1814 let Uses = [RM] in { 1815 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1816 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1817 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1818 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1819 1820 let isCodeGenOnly = 1 in { 1821 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1822 "bl $func", IIC_BrB, []>; 1823 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1824 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1825 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1826 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1827 1828 def BCL : BForm_4<16, 12, 0, 1, (outs), 1829 (ins crbitrc:$bi, condbrtarget:$dst), 1830 "bcl 12, $bi, $dst">; 1831 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1832 (ins crbitrc:$bi, condbrtarget:$dst), 1833 "bcl 4, $bi, $dst">; 1834 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1835 (outs), (ins calltarget:$func), 1836 "bl $func\n\tnop", IIC_BrB, []>; 1837 } 1838 } 1839 let Uses = [CTR, RM] in { 1840 let isPredicable = 1 in 1841 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1842 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1843 Requires<[In32BitMode]>; 1844 1845 let isCodeGenOnly = 1 in { 1846 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1847 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1848 []>; 1849 1850 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1851 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1852 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1853 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1854 } 1855 } 1856 let Uses = [LR, RM] in { 1857 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1858 "blrl", IIC_BrB, []>; 1859 1860 let isCodeGenOnly = 1 in { 1861 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1862 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1863 []>; 1864 1865 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1866 "bclrl 12, $bi, 0", IIC_BrB, []>; 1867 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1868 "bclrl 4, $bi, 0", IIC_BrB, []>; 1869 } 1870 } 1871 let Defs = [CTR], Uses = [CTR, RM] in { 1872 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1873 "bdzl $dst">; 1874 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1875 "bdnzl $dst">; 1876 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1877 "bdzla $dst">; 1878 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1879 "bdnzla $dst">; 1880 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1881 "bdzl+ $dst">; 1882 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1883 "bdnzl+ $dst">; 1884 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1885 "bdzla+ $dst">; 1886 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1887 "bdnzla+ $dst">; 1888 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1889 "bdzl- $dst">; 1890 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1891 "bdnzl- $dst">; 1892 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1893 "bdzla- $dst">; 1894 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1895 "bdnzla- $dst">; 1896 } 1897 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1898 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1899 "bdzlrl", IIC_BrB, []>; 1900 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1901 "bdnzlrl", IIC_BrB, []>; 1902 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1903 "bdzlrl+", IIC_BrB, []>; 1904 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1905 "bdnzlrl+", IIC_BrB, []>; 1906 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1907 "bdzlrl-", IIC_BrB, []>; 1908 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1909 "bdnzlrl-", IIC_BrB, []>; 1910 } 1911} 1912 1913let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1914 // Convenient aliases for call instructions 1915 let Uses = [RM] in { 1916 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1917 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1918 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1919 "bla $func", IIC_BrB, [(PPCcall_rm (i32 imm:$func))]>; 1920 1921 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1922 (outs), (ins calltarget:$func), 1923 "bl $func\n\tnop", IIC_BrB, []>; 1924 } 1925 let Uses = [CTR, RM] in { 1926 let isPredicable = 1 in 1927 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1928 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1929 Requires<[In32BitMode]>; 1930 } 1931} 1932 1933let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1934def TCRETURNdi :PPCEmitTimePseudo< (outs), 1935 (ins calltarget:$dst, i32imm:$offset), 1936 "#TC_RETURNd $dst $offset", 1937 []>; 1938 1939 1940let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1941def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1942 "#TC_RETURNa $func $offset", 1943 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1944 1945let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1946def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1947 "#TC_RETURNr $dst $offset", 1948 []>; 1949 1950let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1951 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1952 def BCTRL_LWZinto_toc: 1953 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1954 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1955 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1956 1957} 1958 1959let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1960 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1961 def BCTRL_LWZinto_toc_RM: 1962 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1963 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1964 [(PPCbctrl_load_toc_rm iaddr:$src)]>, Requires<[In32BitMode]>; 1965 1966} 1967 1968let isCodeGenOnly = 1, hasSideEffects = 0 in { 1969 1970let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1971 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1972def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1973 []>, Requires<[In32BitMode]>; 1974 1975let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1976 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1977def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1978 "b $dst", IIC_BrB, 1979 []>; 1980 1981let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1982 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1983def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1984 "ba $dst", IIC_BrB, 1985 []>; 1986 1987} 1988 1989// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1990// is not. 1991let hasSideEffects = 1 in { 1992 let Defs = [CTR] in 1993 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1994 "#EH_SJLJ_SETJMP32", 1995 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1996 Requires<[In32BitMode]>; 1997} 1998 1999let hasSideEffects = 1, isBarrier = 1 in { 2000 let isTerminator = 1 in 2001 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 2002 "#EH_SJLJ_LONGJMP32", 2003 [(PPCeh_sjlj_longjmp addr:$buf)]>, 2004 Requires<[In32BitMode]>; 2005} 2006 2007// This pseudo is never removed from the function, as it serves as 2008// a terminator. Size is set to 0 to prevent the builtin assembler 2009// from emitting it. 2010let isBranch = 1, isTerminator = 1, Size = 0 in { 2011 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 2012 "#EH_SjLj_Setup\t$dst", []>; 2013} 2014 2015// System call. 2016let PPC970_Unit = 7 in { 2017 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 2018 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 2019} 2020 2021// Branch history rolling buffer. 2022def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 2023 [(PPCclrbhrb)]>, 2024 PPC970_DGroup_Single; 2025// The $dmy argument used for MFBHRBE is not needed; however, including 2026// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 2027// interferes with necessary special handling (see PPCFastISel.cpp). 2028def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 2029 (ins u10imm:$imm, u10imm:$dmy), 2030 "mfbhrbe $rD, $imm", IIC_BrB, 2031 [(set i32:$rD, 2032 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 2033 PPC970_DGroup_First; 2034 2035def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 2036 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 2037 PPC970_DGroup_Single; 2038 2039def : InstAlias<"rfebb", (RFEBB 1)>; 2040 2041// DCB* instructions. 2042def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 2043 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 2044 PPC970_DGroup_Single; 2045def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 2046 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 2047 PPC970_DGroup_Single; 2048def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 2049 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 2050 PPC970_DGroup_Single; 2051def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 2052 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 2053 PPC970_DGroup_Single; 2054def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 2055 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 2056 PPC970_DGroup_Single; 2057 2058def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), 2059 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 2060 PPC970_DGroup_Single; 2061 2062let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 2063def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 2064 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 2065 PPC970_DGroup_Single; 2066def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 2067 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 2068 PPC970_DGroup_Single; 2069} // hasSideEffects = 0 2070 2071def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 2072 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 2073def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 2074 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 2075def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 2076 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 2077def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 2078 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 2079 2080def : Pat<(int_ppc_dcbt xoaddr:$dst), 2081 (DCBT 0, xoaddr:$dst)>; 2082def : Pat<(int_ppc_dcbtst xoaddr:$dst), 2083 (DCBTST 0, xoaddr:$dst)>; 2084def : Pat<(int_ppc_dcbf xoaddr:$dst), 2085 (DCBF 0, xoaddr:$dst)>; 2086def : Pat<(int_ppc_icbt xoaddr:$dst), 2087 (ICBT 0, xoaddr:$dst)>; 2088 2089def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 2090 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 2091def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 2092 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 2093def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 2094 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 2095 2096def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 2097 (DCBT i32:$TH, xoaddr:$dst)>; 2098def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 2099 (DCBTST i32:$TH, xoaddr:$dst)>; 2100 2101// Atomic operations 2102// FIXME: some of these might be used with constant operands. This will result 2103// in constant materialization instructions that may be redundant. We currently 2104// clean this up in PPCMIPeephole with calls to 2105// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 2106// in the first place. 2107let Defs = [CR0] in { 2108 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 2109 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 2110 [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; 2111 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 2112 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 2113 [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; 2114 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 2115 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 2116 [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; 2117 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 2118 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 2119 [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; 2120 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 2121 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 2122 [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; 2123 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 2124 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 2125 [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; 2126 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 2127 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 2128 [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; 2129 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 2130 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 2131 [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; 2132 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 2133 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 2134 [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; 2135 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 2136 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 2137 [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; 2138 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 2139 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 2140 [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; 2141 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 2142 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 2143 [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; 2144 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 2145 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 2146 [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; 2147 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 2148 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 2149 [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; 2150 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 2151 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 2152 [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; 2153 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 2154 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 2155 [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; 2156 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 2157 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 2158 [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; 2159 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 2160 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 2161 [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; 2162 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 2163 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 2164 [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; 2165 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 2166 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 2167 [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; 2168 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 2169 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 2170 [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; 2171 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 2172 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 2173 [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; 2174 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 2175 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 2176 [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; 2177 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 2178 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 2179 [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; 2180 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 2181 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 2182 [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; 2183 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 2184 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 2185 [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; 2186 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 2187 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 2188 [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; 2189 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 2190 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 2191 [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; 2192 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 2193 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 2194 [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; 2195 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 2196 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 2197 [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; 2198 2199 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 2200 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 2201 [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 2202 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 2203 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 2204 [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 2205 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 2206 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 2207 [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 2208 2209 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 2210 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 2211 [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; 2212 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 2213 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 2214 [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; 2215 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 2216 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 2217 [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; 2218} 2219 2220def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 2221 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 2222def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 2223 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 2224 2225// Instructions to support atomic operations 2226let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2227def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 2228 "lbarx $rD, $src", IIC_LdStLWARX, []>, 2229 Requires<[HasPartwordAtomics]>; 2230 2231def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 2232 "lharx $rD, $src", IIC_LdStLWARX, []>, 2233 Requires<[HasPartwordAtomics]>; 2234 2235def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 2236 "lwarx $rD, $src", IIC_LdStLWARX, []>; 2237 2238// Instructions to support lock versions of atomics 2239// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 2240def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 2241 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 2242 Requires<[HasPartwordAtomics]>; 2243 2244def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 2245 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 2246 Requires<[HasPartwordAtomics]>; 2247 2248def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 2249 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 2250 2251// The atomic instructions use the destination register as well as the next one 2252// or two registers in order (modulo 31). 2253let hasExtraSrcRegAllocReq = 1 in 2254def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 2255 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 2256 Requires<[IsISA3_0]>; 2257} 2258 2259let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 2260def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 2261 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 2262 isRecordForm, Requires<[HasPartwordAtomics]>; 2263 2264def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 2265 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 2266 isRecordForm, Requires<[HasPartwordAtomics]>; 2267 2268def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 2269 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 2270} 2271 2272let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2273def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 2274 "stwat $rS, $rA, $FC", IIC_LdStStore>, 2275 Requires<[IsISA3_0]>; 2276 2277let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 2278def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 2279 2280def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 2281 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 2282def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 2283 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 2284def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 2285 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 2286def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 2287 "td $to, $rA, $rB", IIC_IntTrapD, []>; 2288 2289def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 2290 "popcntb $rA, $rS", IIC_IntGeneral, 2291 [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>; 2292 2293//===----------------------------------------------------------------------===// 2294// PPC32 Load Instructions. 2295// 2296 2297// Unindexed (r+i) Loads. 2298let PPC970_Unit = 2 in { 2299def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 2300 "lbz $rD, $src", IIC_LdStLoad, 2301 [(set i32:$rD, (zextloadi8 DForm:$src))]>; 2302def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 2303 "lha $rD, $src", IIC_LdStLHA, 2304 [(set i32:$rD, (sextloadi16 DForm:$src))]>, 2305 PPC970_DGroup_Cracked; 2306def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 2307 "lhz $rD, $src", IIC_LdStLoad, 2308 [(set i32:$rD, (zextloadi16 DForm:$src))]>; 2309def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 2310 "lwz $rD, $src", IIC_LdStLoad, 2311 [(set i32:$rD, (load DForm:$src))]>; 2312 2313let Predicates = [HasFPU] in { 2314def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 2315 "lfs $rD, $src", IIC_LdStLFD, 2316 [(set f32:$rD, (load DForm:$src))]>; 2317def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 2318 "lfd $rD, $src", IIC_LdStLFD, 2319 [(set f64:$rD, (load DForm:$src))]>; 2320} 2321 2322 2323// Unindexed (r+i) Loads with Update (preinc). 2324let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2325def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2326 "lbzu $rD, $addr", IIC_LdStLoadUpd, 2327 []>, RegConstraint<"$addr.reg = $ea_result">, 2328 NoEncode<"$ea_result">; 2329 2330def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2331 "lhau $rD, $addr", IIC_LdStLHAU, 2332 []>, RegConstraint<"$addr.reg = $ea_result">, 2333 NoEncode<"$ea_result">; 2334 2335def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2336 "lhzu $rD, $addr", IIC_LdStLoadUpd, 2337 []>, RegConstraint<"$addr.reg = $ea_result">, 2338 NoEncode<"$ea_result">; 2339 2340def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2341 "lwzu $rD, $addr", IIC_LdStLoadUpd, 2342 []>, RegConstraint<"$addr.reg = $ea_result">, 2343 NoEncode<"$ea_result">; 2344 2345let Predicates = [HasFPU] in { 2346def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2347 "lfsu $rD, $addr", IIC_LdStLFDU, 2348 []>, RegConstraint<"$addr.reg = $ea_result">, 2349 NoEncode<"$ea_result">; 2350 2351def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2352 "lfdu $rD, $addr", IIC_LdStLFDU, 2353 []>, RegConstraint<"$addr.reg = $ea_result">, 2354 NoEncode<"$ea_result">; 2355} 2356 2357 2358// Indexed (r+r) Loads with Update (preinc). 2359def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2360 (ins memrr:$addr), 2361 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 2362 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2363 NoEncode<"$ea_result">; 2364 2365def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2366 (ins memrr:$addr), 2367 "lhaux $rD, $addr", IIC_LdStLHAUX, 2368 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2369 NoEncode<"$ea_result">; 2370 2371def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2372 (ins memrr:$addr), 2373 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 2374 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2375 NoEncode<"$ea_result">; 2376 2377def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2378 (ins memrr:$addr), 2379 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 2380 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2381 NoEncode<"$ea_result">; 2382 2383let Predicates = [HasFPU] in { 2384def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 2385 (ins memrr:$addr), 2386 "lfsux $rD, $addr", IIC_LdStLFDUX, 2387 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2388 NoEncode<"$ea_result">; 2389 2390def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 2391 (ins memrr:$addr), 2392 "lfdux $rD, $addr", IIC_LdStLFDUX, 2393 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2394 NoEncode<"$ea_result">; 2395} 2396} 2397} 2398 2399// Indexed (r+r) Loads. 2400// 2401let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2402def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 2403 "lbzx $rD, $src", IIC_LdStLoad, 2404 [(set i32:$rD, (zextloadi8 XForm:$src))]>; 2405def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 2406 "lhax $rD, $src", IIC_LdStLHA, 2407 [(set i32:$rD, (sextloadi16 XForm:$src))]>, 2408 PPC970_DGroup_Cracked; 2409def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 2410 "lhzx $rD, $src", IIC_LdStLoad, 2411 [(set i32:$rD, (zextloadi16 XForm:$src))]>; 2412def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 2413 "lwzx $rD, $src", IIC_LdStLoad, 2414 [(set i32:$rD, (load XForm:$src))]>; 2415def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 2416 "lhbrx $rD, $src", IIC_LdStLoad, 2417 [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>; 2418def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 2419 "lwbrx $rD, $src", IIC_LdStLoad, 2420 [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>; 2421 2422let Predicates = [HasFPU] in { 2423def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 2424 "lfsx $frD, $src", IIC_LdStLFD, 2425 [(set f32:$frD, (load XForm:$src))]>; 2426def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 2427 "lfdx $frD, $src", IIC_LdStLFD, 2428 [(set f64:$frD, (load XForm:$src))]>; 2429 2430def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 2431 "lfiwax $frD, $src", IIC_LdStLFD, 2432 [(set f64:$frD, (PPClfiwax ForceXForm:$src))]>; 2433def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 2434 "lfiwzx $frD, $src", IIC_LdStLFD, 2435 [(set f64:$frD, (PPClfiwzx ForceXForm:$src))]>; 2436} 2437} 2438 2439// Load Multiple 2440let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2441def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 2442 "lmw $rD, $src", IIC_LdStLMW, []>; 2443 2444//===----------------------------------------------------------------------===// 2445// PPC32 Store Instructions. 2446// 2447 2448// Unindexed (r+i) Stores. 2449let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2450def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 2451 "stb $rS, $dst", IIC_LdStStore, 2452 [(truncstorei8 i32:$rS, DForm:$dst)]>; 2453def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 2454 "sth $rS, $dst", IIC_LdStStore, 2455 [(truncstorei16 i32:$rS, DForm:$dst)]>; 2456def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 2457 "stw $rS, $dst", IIC_LdStStore, 2458 [(store i32:$rS, DForm:$dst)]>; 2459let Predicates = [HasFPU] in { 2460def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 2461 "stfs $rS, $dst", IIC_LdStSTFD, 2462 [(store f32:$rS, DForm:$dst)]>; 2463def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 2464 "stfd $rS, $dst", IIC_LdStSTFD, 2465 [(store f64:$rS, DForm:$dst)]>; 2466} 2467} 2468 2469// Unindexed (r+i) Stores with Update (preinc). 2470let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2471def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2472 "stbu $rS, $dst", IIC_LdStSTU, []>, 2473 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2474def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2475 "sthu $rS, $dst", IIC_LdStSTU, []>, 2476 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2477def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2478 "stwu $rS, $dst", IIC_LdStSTU, []>, 2479 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2480let Predicates = [HasFPU] in { 2481def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 2482 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 2483 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2484def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 2485 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 2486 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2487} 2488} 2489 2490// Patterns to match the pre-inc stores. We can't put the patterns on 2491// the instruction definitions directly as ISel wants the address base 2492// and offset to be separate operands, not a single complex operand. 2493def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2494 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2495def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2496 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2497def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2498 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2499def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2500 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2501def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2502 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2503 2504// Indexed (r+r) Stores. 2505let PPC970_Unit = 2 in { 2506def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 2507 "stbx $rS, $dst", IIC_LdStStore, 2508 [(truncstorei8 i32:$rS, XForm:$dst)]>, 2509 PPC970_DGroup_Cracked; 2510def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2511 "sthx $rS, $dst", IIC_LdStStore, 2512 [(truncstorei16 i32:$rS, XForm:$dst)]>, 2513 PPC970_DGroup_Cracked; 2514def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2515 "stwx $rS, $dst", IIC_LdStStore, 2516 [(store i32:$rS, XForm:$dst)]>, 2517 PPC970_DGroup_Cracked; 2518 2519def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2520 "sthbrx $rS, $dst", IIC_LdStStore, 2521 [(PPCstbrx i32:$rS, ForceXForm:$dst, i16)]>, 2522 PPC970_DGroup_Cracked; 2523def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2524 "stwbrx $rS, $dst", IIC_LdStStore, 2525 [(PPCstbrx i32:$rS, ForceXForm:$dst, i32)]>, 2526 PPC970_DGroup_Cracked; 2527 2528let Predicates = [HasFPU] in { 2529def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2530 "stfiwx $frS, $dst", IIC_LdStSTFD, 2531 [(PPCstfiwx f64:$frS, ForceXForm:$dst)]>; 2532 2533def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2534 "stfsx $frS, $dst", IIC_LdStSTFD, 2535 [(store f32:$frS, XForm:$dst)]>; 2536def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2537 "stfdx $frS, $dst", IIC_LdStSTFD, 2538 [(store f64:$frS, XForm:$dst)]>; 2539} 2540} 2541 2542// Indexed (r+r) Stores with Update (preinc). 2543let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2544def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2545 (ins gprc:$rS, memrr:$dst), 2546 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2547 RegConstraint<"$dst.ptrreg = $ea_res">, 2548 NoEncode<"$ea_res">, 2549 PPC970_DGroup_Cracked; 2550def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2551 (ins gprc:$rS, memrr:$dst), 2552 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2553 RegConstraint<"$dst.ptrreg = $ea_res">, 2554 NoEncode<"$ea_res">, 2555 PPC970_DGroup_Cracked; 2556def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2557 (ins gprc:$rS, memrr:$dst), 2558 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2559 RegConstraint<"$dst.ptrreg = $ea_res">, 2560 NoEncode<"$ea_res">, 2561 PPC970_DGroup_Cracked; 2562let Predicates = [HasFPU] in { 2563def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2564 (ins f4rc:$rS, memrr:$dst), 2565 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2566 RegConstraint<"$dst.ptrreg = $ea_res">, 2567 NoEncode<"$ea_res">, 2568 PPC970_DGroup_Cracked; 2569def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2570 (ins f8rc:$rS, memrr:$dst), 2571 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2572 RegConstraint<"$dst.ptrreg = $ea_res">, 2573 NoEncode<"$ea_res">, 2574 PPC970_DGroup_Cracked; 2575} 2576} 2577 2578// Patterns to match the pre-inc stores. We can't put the patterns on 2579// the instruction definitions directly as ISel wants the address base 2580// and offset to be separate operands, not a single complex operand. 2581def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2582 (STBUX $rS, $ptrreg, $ptroff)>; 2583def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2584 (STHUX $rS, $ptrreg, $ptroff)>; 2585def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2586 (STWUX $rS, $ptrreg, $ptroff)>; 2587let Predicates = [HasFPU] in { 2588def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2589 (STFSUX $rS, $ptrreg, $ptroff)>; 2590def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2591 (STFDUX $rS, $ptrreg, $ptroff)>; 2592} 2593 2594// Store Multiple 2595let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2596def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2597 "stmw $rS, $dst", IIC_LdStLMW, []>; 2598 2599def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2600 "sync $L", IIC_LdStSync, []>; 2601 2602let isCodeGenOnly = 1 in { 2603 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2604 "msync", IIC_LdStSync, []> { 2605 let L = 0; 2606 } 2607} 2608 2609// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2610def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2611 "eieio", IIC_LdStLoad, []>; 2612 2613def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2614 [(int_ppc_eieio)]>; 2615 2616def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2617def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2618def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2619def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2620def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2621def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2622def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2623def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2624def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2625def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2626 2627//===----------------------------------------------------------------------===// 2628// PPC32 Arithmetic Instructions. 2629// 2630 2631let PPC970_Unit = 1 in { // FXU Operations. 2632def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2633 "addi $rD, $rA, $imm", IIC_IntSimple, 2634 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2635let BaseName = "addic" in { 2636let Defs = [CARRY] in 2637def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2638 "addic $rD, $rA, $imm", IIC_IntGeneral, 2639 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2640 RecFormRel, PPC970_DGroup_Cracked; 2641let Defs = [CARRY, CR0] in 2642def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2643 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2644 []>, isRecordForm, RecFormRel; 2645} 2646def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2647 "addis $rD, $rA, $imm", IIC_IntSimple, 2648 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2649let isCodeGenOnly = 1 in 2650def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2651 "la $rD, $sym($rA)", IIC_IntGeneral, 2652 [(set i32:$rD, (add i32:$rA, 2653 (PPClo tglobaladdr:$sym, 0)))]>; 2654def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2655 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2656 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2657let Defs = [CARRY] in 2658def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2659 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2660 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2661 2662let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2663 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2664 "li $rD, $imm", IIC_IntSimple, 2665 [(set i32:$rD, imm32SExt16:$imm)]>; 2666 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2667 "lis $rD, $imm", IIC_IntSimple, 2668 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2669} 2670} 2671 2672def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2673def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2674 2675let PPC970_Unit = 1 in { // FXU Operations. 2676let Defs = [CR0] in { 2677def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2678 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2679 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2680 isRecordForm; 2681def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2682 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2683 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2684 isRecordForm; 2685} 2686def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2687 "ori $dst, $src1, $src2", IIC_IntSimple, 2688 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2689def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2690 "oris $dst, $src1, $src2", IIC_IntSimple, 2691 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2692def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2693 "xori $dst, $src1, $src2", IIC_IntSimple, 2694 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2695def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2696 "xoris $dst, $src1, $src2", IIC_IntSimple, 2697 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2698 2699def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2700 []>; 2701let isCodeGenOnly = 1 in { 2702// The POWER6 and POWER7 have special group-terminating nops. 2703def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2704 "ori 1, 1, 0", IIC_IntSimple, []>; 2705def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2706 "ori 2, 2, 0", IIC_IntSimple, []>; 2707} 2708 2709let isCompare = 1, hasSideEffects = 0 in { 2710 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2711 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2712 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2713 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2714 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2715 (ins u1imm:$L, gprc:$rA, gprc:$rB), 2716 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2717 Requires<[IsISA3_0]>; 2718} 2719} 2720 2721let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2722let isCommutable = 1 in { 2723defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2724 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2725 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2726defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2727 "and", "$rA, $rS, $rB", IIC_IntSimple, 2728 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2729} // isCommutable 2730defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2731 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2732 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2733let isCommutable = 1 in { 2734defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2735 "or", "$rA, $rS, $rB", IIC_IntSimple, 2736 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2737defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2738 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2739 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2740} // isCommutable 2741defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2742 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2743 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2744let isCommutable = 1 in { 2745defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2746 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2747 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2748defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2749 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2750 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2751} // isCommutable 2752defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2753 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2754 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2755defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2756 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2757 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2758defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2759 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2760 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2761} 2762 2763def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2764def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2765 2766def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2767def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2768 2769def : InstAlias<"nop", (ORI R0, R0, 0)>; 2770 2771let PPC970_Unit = 1 in { // FXU Operations. 2772let hasSideEffects = 0 in { 2773defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2774 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2775 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2776defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2777 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2778 [(set i32:$rA, (ctlz i32:$rS))]>; 2779defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2780 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2781 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2782defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2783 "extsb", "$rA, $rS", IIC_IntSimple, 2784 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2785defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2786 "extsh", "$rA, $rS", IIC_IntSimple, 2787 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2788 2789let isCommutable = 1 in 2790def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2791 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2792 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2793} 2794let isCompare = 1, hasSideEffects = 0 in { 2795 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2796 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2797 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2798 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2799} 2800} 2801let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2802let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2803 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2804 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2805 def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2806 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2807 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2808 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2809 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2810 def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2811 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2812 } 2813} 2814 2815def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2816 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2817def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2818 "ftsqrt $crD, $fB", IIC_FPCompare, 2819 [(set i32:$crD, (PPCftsqrt f64:$fB))]>; 2820 2821let mayRaiseFPException = 1, hasSideEffects = 0 in { 2822 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2823 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2824 "frin", "$frD, $frB", IIC_FPGeneral, 2825 [(set f64:$frD, (any_fround f64:$frB))]>; 2826 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2827 "frin", "$frD, $frB", IIC_FPGeneral, 2828 [(set f32:$frD, (any_fround f32:$frB))]>; 2829 2830 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2831 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2832 "frip", "$frD, $frB", IIC_FPGeneral, 2833 [(set f64:$frD, (any_fceil f64:$frB))]>; 2834 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2835 "frip", "$frD, $frB", IIC_FPGeneral, 2836 [(set f32:$frD, (any_fceil f32:$frB))]>; 2837 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2838 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2839 "friz", "$frD, $frB", IIC_FPGeneral, 2840 [(set f64:$frD, (any_ftrunc f64:$frB))]>; 2841 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2842 "friz", "$frD, $frB", IIC_FPGeneral, 2843 [(set f32:$frD, (any_ftrunc f32:$frB))]>; 2844 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2845 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2846 "frim", "$frD, $frB", IIC_FPGeneral, 2847 [(set f64:$frD, (any_ffloor f64:$frB))]>; 2848 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2849 "frim", "$frD, $frB", IIC_FPGeneral, 2850 [(set f32:$frD, (any_ffloor f32:$frB))]>; 2851} 2852 2853let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2854 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2855 "fctiw", "$frD, $frB", IIC_FPGeneral, 2856 []>; 2857 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2858 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2859 []>; 2860 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2861 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2862 [(set f64:$frD, (PPCany_fctiwz f64:$frB))]>; 2863 2864 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2865 "frsp", "$frD, $frB", IIC_FPGeneral, 2866 [(set f32:$frD, (any_fpround f64:$frB))]>; 2867 2868 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2869 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2870 [(set f64:$frD, (any_fsqrt f64:$frB))]>; 2871 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2872 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2873 [(set f32:$frD, (any_fsqrt f32:$frB))]>; 2874} 2875} 2876 2877def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2878 2879/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2880/// often coalesced away and we don't want the dispatch group builder to think 2881/// that they will fill slots (which could cause the load of a LSU reject to 2882/// sneak into a d-group with a store). 2883let hasSideEffects = 0, Predicates = [HasFPU] in 2884defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2885 "fmr", "$frD, $frB", IIC_FPGeneral, 2886 []>, // (set f32:$frD, f32:$frB) 2887 PPC970_Unit_Pseudo; 2888 2889let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2890// These are artificially split into two different forms, for 4/8 byte FP. 2891defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2892 "fabs", "$frD, $frB", IIC_FPGeneral, 2893 [(set f32:$frD, (fabs f32:$frB))]>; 2894let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2895defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2896 "fabs", "$frD, $frB", IIC_FPGeneral, 2897 [(set f64:$frD, (fabs f64:$frB))]>; 2898defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2899 "fnabs", "$frD, $frB", IIC_FPGeneral, 2900 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2901let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2902defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2903 "fnabs", "$frD, $frB", IIC_FPGeneral, 2904 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2905defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2906 "fneg", "$frD, $frB", IIC_FPGeneral, 2907 [(set f32:$frD, (fneg f32:$frB))]>; 2908let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2909defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2910 "fneg", "$frD, $frB", IIC_FPGeneral, 2911 [(set f64:$frD, (fneg f64:$frB))]>; 2912 2913defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2914 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2915 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2916let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2917defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2918 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2919 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2920 2921// Reciprocal estimates. 2922let mayRaiseFPException = 1 in { 2923defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2924 "fre", "$frD, $frB", IIC_FPGeneral, 2925 [(set f64:$frD, (PPCfre f64:$frB))]>; 2926defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2927 "fres", "$frD, $frB", IIC_FPGeneral, 2928 [(set f32:$frD, (PPCfre f32:$frB))]>; 2929defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2930 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2931 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2932defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2933 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2934 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2935} 2936} 2937 2938// XL-Form instructions. condition register logical ops. 2939// 2940let hasSideEffects = 0 in 2941def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2942 "mcrf $BF, $BFA", IIC_BrMCR>, 2943 PPC970_DGroup_First, PPC970_Unit_CRU; 2944 2945// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2946// condition-register logical instructions have preferred forms. Specifically, 2947// it is preferred that the bit specified by the BT field be in the same 2948// condition register as that specified by the bit BB. We might want to account 2949// for this via hinting the register allocator and anti-dep breakers, or we 2950// could constrain the register class to force this constraint and then loosen 2951// it during register allocation via convertToThreeAddress or some similar 2952// mechanism. 2953 2954let isCommutable = 1 in { 2955def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2956 (ins crbitrc:$CRA, crbitrc:$CRB), 2957 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2958 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2959 2960def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2961 (ins crbitrc:$CRA, crbitrc:$CRB), 2962 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2963 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2964 2965def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2966 (ins crbitrc:$CRA, crbitrc:$CRB), 2967 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2968 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2969 2970def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2971 (ins crbitrc:$CRA, crbitrc:$CRB), 2972 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2973 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2974 2975def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2976 (ins crbitrc:$CRA, crbitrc:$CRB), 2977 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2978 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2979 2980def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2981 (ins crbitrc:$CRA, crbitrc:$CRB), 2982 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2983 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2984} // isCommutable 2985 2986def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2987 (ins crbitrc:$CRA, crbitrc:$CRB), 2988 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2989 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2990 2991def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2992 (ins crbitrc:$CRA, crbitrc:$CRB), 2993 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2994 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2995 2996let isCodeGenOnly = 1 in { 2997let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2998def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2999 "creqv $dst, $dst, $dst", IIC_BrCR, 3000 [(set i1:$dst, 1)]>; 3001 3002def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 3003 "crxor $dst, $dst, $dst", IIC_BrCR, 3004 [(set i1:$dst, 0)]>; 3005} 3006 3007let Defs = [CR1EQ], CRD = 6 in { 3008def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 3009 "creqv 6, 6, 6", IIC_BrCR, 3010 [(PPCcr6set)]>; 3011 3012def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 3013 "crxor 6, 6, 6", IIC_BrCR, 3014 [(PPCcr6unset)]>; 3015} 3016} 3017 3018// XFX-Form instructions. Instructions that deal with SPRs. 3019// 3020 3021def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 3022 "mfspr $RT, $SPR", IIC_SprMFSPR>; 3023def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 3024 "mtspr $SPR, $RT", IIC_SprMTSPR>; 3025 3026def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 3027 "mftb $RT, $SPR", IIC_SprMFTB>; 3028 3029def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 3030 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 3031 3032def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 3033 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 3034 3035 3036// A pseudo-instruction used to implement the read of the 64-bit cycle counter 3037// on a 32-bit target. 3038let hasSideEffects = 1 in 3039def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 3040 "#ReadTB", []>; 3041 3042let Uses = [CTR] in { 3043def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 3044 "mfctr $rT", IIC_SprMFSPR>, 3045 PPC970_DGroup_First, PPC970_Unit_FXU; 3046} 3047let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 3048def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 3049 "mtctr $rS", IIC_SprMTSPR>, 3050 PPC970_DGroup_First, PPC970_Unit_FXU; 3051} 3052let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 3053let Pattern = [(int_set_loop_iterations i32:$rS)] in 3054def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 3055 "mtctr $rS", IIC_SprMTSPR>, 3056 PPC970_DGroup_First, PPC970_Unit_FXU; 3057} 3058 3059let hasSideEffects = 0 in { 3060let Defs = [LR] in { 3061def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 3062 "mtlr $rS", IIC_SprMTSPR>, 3063 PPC970_DGroup_First, PPC970_Unit_FXU; 3064} 3065let Uses = [LR] in { 3066def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 3067 "mflr $rT", IIC_SprMFSPR>, 3068 PPC970_DGroup_First, PPC970_Unit_FXU; 3069} 3070} 3071 3072let isCodeGenOnly = 1 in { 3073 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 3074 // like a GPR on the PPC970. As such, copies in and out have the same 3075 // performance characteristics as an OR instruction. 3076 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 3077 "mtspr 256, $rS", IIC_IntGeneral>, 3078 PPC970_DGroup_Single, PPC970_Unit_FXU; 3079 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 3080 "mfspr $rT, 256", IIC_IntGeneral>, 3081 PPC970_DGroup_First, PPC970_Unit_FXU; 3082 3083 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 3084 (outs VRSAVERC:$reg), (ins gprc:$rS), 3085 "mtspr 256, $rS", IIC_IntGeneral>, 3086 PPC970_DGroup_Single, PPC970_Unit_FXU; 3087 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 3088 (ins VRSAVERC:$reg), 3089 "mfspr $rT, 256", IIC_IntGeneral>, 3090 PPC970_DGroup_First, PPC970_Unit_FXU; 3091} 3092 3093// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 3094def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 3095def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 3096 3097let hasSideEffects = 0 in { 3098// mtocrf's input needs to be prepared by shifting by an amount dependent 3099// on the cr register selected. Thus, post-ra anti-dep breaking must not 3100// later change that register assignment. 3101let hasExtraDefRegAllocReq = 1 in { 3102def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 3103 "mtocrf $FXM, $ST", IIC_BrMCRX>, 3104 PPC970_DGroup_First, PPC970_Unit_CRU; 3105 3106// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 3107// is dependent on the cr fields being set. 3108def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 3109 "mtcrf $FXM, $rS", IIC_BrMCRX>, 3110 PPC970_MicroCode, PPC970_Unit_CRU; 3111} // hasExtraDefRegAllocReq = 1 3112 3113// mfocrf's input needs to be prepared by shifting by an amount dependent 3114// on the cr register selected. Thus, post-ra anti-dep breaking must not 3115// later change that register assignment. 3116let hasExtraSrcRegAllocReq = 1 in { 3117def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 3118 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 3119 PPC970_DGroup_First, PPC970_Unit_CRU; 3120 3121// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 3122// is dependent on the cr fields being copied. 3123def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 3124 "mfcr $rT", IIC_SprMFCR>, 3125 PPC970_MicroCode, PPC970_Unit_CRU; 3126} // hasExtraSrcRegAllocReq = 1 3127 3128def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 3129 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 3130} // hasSideEffects = 0 3131 3132def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 3133 3134let Predicates = [HasFPU] in { 3135// Custom inserter instruction to perform FADD in round-to-zero mode. 3136let Uses = [RM], mayRaiseFPException = 1 in { 3137 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 3138 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 3139} 3140 3141// The above pseudo gets expanded to make use of the following instructions 3142// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 3143 3144// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 3145// RM should be set. 3146let hasSideEffects = 1, Defs = [RM] in { 3147def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 3148 "mtfsb0 $FM", IIC_IntMTFSB0, 3149 [(int_ppc_mtfsb0 timm:$FM)]>, 3150 PPC970_DGroup_Single, PPC970_Unit_FPU; 3151def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 3152 "mtfsb1 $FM", IIC_IntMTFSB0, 3153 [(int_ppc_mtfsb1 timm:$FM)]>, 3154 PPC970_DGroup_Single, PPC970_Unit_FPU; 3155} 3156 3157let Defs = [RM], hasSideEffects = 1 in { 3158 let isCodeGenOnly = 1 in 3159 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 3160 "mtfsf $FM, $rT", IIC_IntMTFSB0, 3161 [(int_ppc_mtfsf timm:$FM, f64:$rT)]>, 3162 PPC970_DGroup_Single, PPC970_Unit_FPU; 3163} 3164let Uses = [RM], hasSideEffects = 1 in { 3165 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 3166 "mffs $rT", IIC_IntMFFS, 3167 [(set f64:$rT, (PPCmffs))]>, 3168 PPC970_DGroup_Single, PPC970_Unit_FPU; 3169 3170 let Defs = [CR1] in 3171 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 3172 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 3173 3174 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 3175 "mffsce $rT", IIC_IntMFFS, []>, 3176 PPC970_DGroup_Single, PPC970_Unit_FPU; 3177 3178 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 3179 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 3180 IIC_IntMFFS, []>, 3181 PPC970_DGroup_Single, PPC970_Unit_FPU; 3182 3183 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 3184 (ins u3imm:$DRM), 3185 "mffscdrni $rT, $DRM", 3186 IIC_IntMFFS, []>, 3187 PPC970_DGroup_Single, PPC970_Unit_FPU; 3188 3189 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 3190 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 3191 IIC_IntMFFS, []>, 3192 PPC970_DGroup_Single, PPC970_Unit_FPU; 3193 3194 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 3195 (ins u2imm:$RM), "mffscrni $rT, $RM", 3196 IIC_IntMFFS, []>, 3197 PPC970_DGroup_Single, PPC970_Unit_FPU; 3198 3199 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 3200 "mffsl $rT", IIC_IntMFFS, []>, 3201 PPC970_DGroup_Single, PPC970_Unit_FPU; 3202} 3203} 3204 3205let Predicates = [IsISA3_0] in { 3206def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3207 "modsw $rT, $rA, $rB", IIC_IntDivW, 3208 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 3209def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3210 "moduw $rT, $rA, $rB", IIC_IntDivW, 3211 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 3212let hasSideEffects = 1 in 3213def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), 3214 (ins gprc:$rA, gprc:$rB, u2imm:$CY), 3215 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>; 3216} 3217 3218let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 3219// XO-Form instructions. Arithmetic instructions that can set overflow bit 3220let isCommutable = 1 in 3221defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3222 "add", "$rT, $rA, $rB", IIC_IntSimple, 3223 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 3224let isCodeGenOnly = 1 in 3225def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 3226 "add $rT, $rA, $rB", IIC_IntSimple, 3227 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 3228let isCommutable = 1 in 3229defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3230 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 3231 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 3232 PPC970_DGroup_Cracked; 3233 3234defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3235 "divw", "$rT, $rA, $rB", IIC_IntDivW, 3236 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 3237defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3238 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 3239 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 3240defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3241 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 3242 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 3243 Requires<[HasExtDiv]>; 3244defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3245 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 3246 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 3247 Requires<[HasExtDiv]>; 3248let isCommutable = 1 in { 3249defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3250 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 3251 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 3252defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3253 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 3254 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 3255defm MULLW : XOForm_1rx<31, 235, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3256 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 3257 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 3258} // isCommutable 3259defm SUBF : XOForm_1rx<31, 40, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3260 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 3261 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 3262defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3263 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 3264 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 3265 PPC970_DGroup_Cracked; 3266defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 3267 "neg", "$rT, $rA", IIC_IntSimple, 3268 [(set i32:$rT, (ineg i32:$rA))]>; 3269let Uses = [CARRY] in { 3270let isCommutable = 1 in 3271defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3272 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 3273 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 3274defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 3275 "addme", "$rT, $rA", IIC_IntGeneral, 3276 [(set i32:$rT, (adde i32:$rA, -1))]>; 3277defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 3278 "addze", "$rT, $rA", IIC_IntGeneral, 3279 [(set i32:$rT, (adde i32:$rA, 0))]>; 3280defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3281 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 3282 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 3283defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 3284 "subfme", "$rT, $rA", IIC_IntGeneral, 3285 [(set i32:$rT, (sube -1, i32:$rA))]>; 3286defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 3287 "subfze", "$rT, $rA", IIC_IntGeneral, 3288 [(set i32:$rT, (sube 0, i32:$rA))]>; 3289} 3290} 3291 3292def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 3293def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3294def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 3295def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3296 3297// A-Form instructions. Most of the instructions executed in the FPU are of 3298// this type. 3299// 3300let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 3301let mayRaiseFPException = 1, Uses = [RM] in { 3302let isCommutable = 1 in { 3303 defm FMADD : AForm_1r<63, 29, 3304 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3305 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3306 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 3307 defm FMADDS : AForm_1r<59, 29, 3308 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3309 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3310 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 3311 defm FMSUB : AForm_1r<63, 28, 3312 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3313 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3314 [(set f64:$FRT, 3315 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 3316 defm FMSUBS : AForm_1r<59, 28, 3317 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3318 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3319 [(set f32:$FRT, 3320 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 3321 defm FNMADD : AForm_1r<63, 31, 3322 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3323 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3324 [(set f64:$FRT, 3325 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3326 defm FNMADDS : AForm_1r<59, 31, 3327 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3328 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3329 [(set f32:$FRT, 3330 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3331 defm FNMSUB : AForm_1r<63, 30, 3332 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3333 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3334 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3335 (fneg f64:$FRB))))]>; 3336 defm FNMSUBS : AForm_1r<59, 30, 3337 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3338 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3339 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3340 (fneg f32:$FRB))))]>; 3341} // isCommutable 3342} 3343// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3344// having 4 of these, force the comparison to always be an 8-byte double (code 3345// should use an FMRSD if the input comparison value really wants to be a float) 3346// and 4/8 byte forms for the result and operand type.. 3347let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3348defm FSELD : AForm_1r<63, 23, 3349 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3350 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3351 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3352defm FSELS : AForm_1r<63, 23, 3353 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3354 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3355 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3356let Uses = [RM], mayRaiseFPException = 1 in { 3357 let isCommutable = 1 in { 3358 defm FADD : AForm_2r<63, 21, 3359 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3360 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3361 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3362 defm FADDS : AForm_2r<59, 21, 3363 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3364 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3365 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3366 } // isCommutable 3367 defm FDIV : AForm_2r<63, 18, 3368 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3369 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3370 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3371 defm FDIVS : AForm_2r<59, 18, 3372 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3373 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3374 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3375 let isCommutable = 1 in { 3376 defm FMUL : AForm_3r<63, 25, 3377 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3378 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3379 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3380 defm FMULS : AForm_3r<59, 25, 3381 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3382 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3383 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3384 } // isCommutable 3385 defm FSUB : AForm_2r<63, 20, 3386 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3387 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3388 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3389 defm FSUBS : AForm_2r<59, 20, 3390 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3391 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3392 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3393 } 3394} 3395 3396let hasSideEffects = 0 in { 3397let PPC970_Unit = 1 in { // FXU Operations. 3398 let isSelect = 1 in 3399 def ISEL : AForm_4<31, 15, 3400 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 3401 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 3402 []>; 3403} 3404 3405let PPC970_Unit = 1 in { // FXU Operations. 3406// M-Form instructions. rotate and mask instructions. 3407// 3408let isCommutable = 1 in { 3409// RLWIMI can be commuted if the rotate amount is zero. 3410defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 3411 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 3412 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 3413 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3414 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 3415} 3416let BaseName = "rlwinm" in { 3417def RLWINM : MForm_2<21, 3418 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3419 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3420 []>, RecFormRel; 3421let Defs = [CR0] in 3422def RLWINM_rec : MForm_2<21, 3423 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3424 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3425 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3426} 3427defm RLWNM : MForm_2r<23, (outs gprc:$rA), 3428 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 3429 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 3430 []>; 3431} 3432} // hasSideEffects = 0 3433 3434//===----------------------------------------------------------------------===// 3435// PowerPC Instruction Patterns 3436// 3437 3438// Arbitrary immediate support. Implement in terms of LIS/ORI. 3439def : Pat<(i32 imm:$imm), 3440 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3441 3442// Implement the 'not' operation with the NOR instruction. 3443def i32not : OutPatFrag<(ops node:$in), 3444 (NOR $in, $in)>; 3445def : Pat<(not i32:$in), 3446 (i32not $in)>; 3447 3448// ADD an arbitrary immediate. 3449def : Pat<(add i32:$in, imm:$imm), 3450 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3451// OR an arbitrary immediate. 3452def : Pat<(or i32:$in, imm:$imm), 3453 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3454// XOR an arbitrary immediate. 3455def : Pat<(xor i32:$in, imm:$imm), 3456 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3457// SUBFIC 3458def : Pat<(sub imm32SExt16:$imm, i32:$in), 3459 (SUBFIC $in, imm:$imm)>; 3460 3461// SHL/SRL 3462def : Pat<(shl i32:$in, (i32 imm:$imm)), 3463 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3464def : Pat<(srl i32:$in, (i32 imm:$imm)), 3465 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3466 3467// ROTL 3468def : Pat<(rotl i32:$in, i32:$sh), 3469 (RLWNM $in, $sh, 0, 31)>; 3470def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3471 (RLWINM $in, imm:$imm, 0, 31)>; 3472 3473// RLWNM 3474def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3475 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3476 3477// Calls 3478def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3479 (BL tglobaladdr:$dst)>; 3480 3481def : Pat<(PPCcall (i32 texternalsym:$dst)), 3482 (BL texternalsym:$dst)>; 3483 3484def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3485 (BL_RM tglobaladdr:$dst)>; 3486 3487def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3488 (BL_RM texternalsym:$dst)>; 3489 3490// Calls for AIX only 3491def : Pat<(PPCcall (i32 mcsym:$dst)), 3492 (BL mcsym:$dst)>; 3493 3494def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3495 (BL_NOP mcsym:$dst)>; 3496 3497def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3498 (BL_NOP texternalsym:$dst)>; 3499 3500def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3501 (BL_RM mcsym:$dst)>; 3502 3503def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3504 (BL_NOP_RM mcsym:$dst)>; 3505 3506def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3507 (BL_NOP_RM texternalsym:$dst)>; 3508 3509def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3510 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3511 3512def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3513 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3514 3515def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3516 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3517 3518def : Pat<(int_ppc_readflm), (MFFS)>; 3519 3520// Hi and Lo for Darwin Global Addresses. 3521def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3522def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3523def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3524def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3525def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3526def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3527def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3528def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3529def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3530 (ADDIS $in, tglobaltlsaddr:$g)>; 3531def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3532 (ADDI $in, tglobaltlsaddr:$g)>; 3533def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3534 (ADDIS $in, tglobaladdr:$g)>; 3535def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3536 (ADDIS $in, tconstpool:$g)>; 3537def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3538 (ADDIS $in, tjumptable:$g)>; 3539def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3540 (ADDIS $in, tblockaddress:$g)>; 3541 3542// Support for thread-local storage. 3543def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3544 [(set i32:$rD, (PPCppc32GOT))]>; 3545 3546// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3547// This uses two output registers, the first as the real output, the second as a 3548// temporary register, used internally in code generation. 3549def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3550 []>, NoEncode<"$rT">; 3551 3552def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3553 "#LDgotTprelL32", 3554 [(set i32:$rD, 3555 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3556def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3557 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3558 3559def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3560 "#ADDItlsgdL32", 3561 [(set i32:$rD, 3562 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3563// LR is a true define, while the rest of the Defs are clobbers. R3 is 3564// explicitly defined when this op is created, so not mentioned here. 3565let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3566 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3567def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3568 "GETtlsADDR32", 3569 [(set i32:$rD, 3570 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3571// R3 is explicitly defined when this op is created, so not mentioned here. 3572// The rest of the Defs are the exact set of registers that will be clobbered by 3573// the call. 3574let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3575 Defs = [R0,R4,R5,R11,LR,CR0] in 3576def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3577 "GETtlsADDR32AIX", 3578 [(set i32:$rD, 3579 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3580// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3581// are true defines while the rest of the Defs are clobbers. 3582let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3583 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3584def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3585 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3586 "#ADDItlsgdLADDR32", 3587 [(set i32:$rD, 3588 (PPCaddiTlsgdLAddr i32:$reg, 3589 tglobaltlsaddr:$disp, 3590 tglobaltlsaddr:$sym))]>; 3591def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3592 "#ADDItlsldL32", 3593 [(set i32:$rD, 3594 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3595// This pseudo is expanded to two copies to put the variable offset in R4 and 3596// the region handle in R3 and GETtlsADDR32AIX. 3597def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3598 "#TLSGDAIX", 3599 [(set i32:$rD, 3600 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3601// LR is a true define, while the rest of the Defs are clobbers. R3 is 3602// explicitly defined when this op is created, so not mentioned here. 3603let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3604 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3605def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3606 "GETtlsldADDR32", 3607 [(set i32:$rD, 3608 (PPCgetTlsldAddr i32:$reg, 3609 tglobaltlsaddr:$sym))]>; 3610// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3611// are true defines while the rest of the Defs are clobbers. 3612let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3613 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3614def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3615 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3616 "#ADDItlsldLADDR32", 3617 [(set i32:$rD, 3618 (PPCaddiTlsldLAddr i32:$reg, 3619 tglobaltlsaddr:$disp, 3620 tglobaltlsaddr:$sym))]>; 3621def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3622 "#ADDIdtprelL32", 3623 [(set i32:$rD, 3624 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3625def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3626 "#ADDISdtprelHA32", 3627 [(set i32:$rD, 3628 (PPCaddisDtprelHA i32:$reg, 3629 tglobaltlsaddr:$disp))]>; 3630 3631// Support for Position-independent code 3632def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3633 "#LWZtoc", 3634 [(set i32:$rD, 3635 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3636def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3637 "#LWZtocL", 3638 [(set i32:$rD, 3639 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3640def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3641 "#ADDIStocHA", 3642 [(set i32:$rD, 3643 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3644// Local Data Transform 3645def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3646 "#ADDItoc", 3647 [(set i32:$rD, 3648 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3649 3650// Get Global (GOT) Base Register offset, from the word immediately preceding 3651// the function label. 3652def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3653 3654// Pseudo-instruction marked for deletion. When deleting the instruction would 3655// cause iterator invalidation in MIR transformation passes, this pseudo can be 3656// used instead. It will be removed unconditionally at pre-emit time (prior to 3657// branch selection). 3658def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3659 3660// Standard shifts. These are represented separately from the real shifts above 3661// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3662// amounts. 3663def : Pat<(sra i32:$rS, i32:$rB), 3664 (SRAW $rS, $rB)>; 3665def : Pat<(srl i32:$rS, i32:$rB), 3666 (SRW $rS, $rB)>; 3667def : Pat<(shl i32:$rS, i32:$rB), 3668 (SLW $rS, $rB)>; 3669 3670def : Pat<(i32 (zextloadi1 DForm:$src)), 3671 (LBZ DForm:$src)>; 3672def : Pat<(i32 (zextloadi1 XForm:$src)), 3673 (LBZX XForm:$src)>; 3674def : Pat<(i32 (extloadi1 DForm:$src)), 3675 (LBZ DForm:$src)>; 3676def : Pat<(i32 (extloadi1 XForm:$src)), 3677 (LBZX XForm:$src)>; 3678def : Pat<(i32 (extloadi8 DForm:$src)), 3679 (LBZ DForm:$src)>; 3680def : Pat<(i32 (extloadi8 XForm:$src)), 3681 (LBZX XForm:$src)>; 3682def : Pat<(i32 (extloadi16 DForm:$src)), 3683 (LHZ DForm:$src)>; 3684def : Pat<(i32 (extloadi16 XForm:$src)), 3685 (LHZX XForm:$src)>; 3686let Predicates = [HasFPU] in { 3687def : Pat<(f64 (extloadf32 DForm:$src)), 3688 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3689def : Pat<(f64 (extloadf32 XForm:$src)), 3690 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3691 3692def : Pat<(f64 (any_fpextend f32:$src)), 3693 (COPY_TO_REGCLASS $src, F8RC)>; 3694} 3695 3696// Only seq_cst fences require the heavyweight sync (SYNC 0). 3697// All others can use the lightweight sync (SYNC 1). 3698// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3699// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3700// versions of Power. 3701def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3702def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3703def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3704def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3705 3706let Predicates = [HasFPU] in { 3707// Additional fnmsub patterns for custom node 3708def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3709 (FNMSUB $A, $B, $C)>; 3710def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3711 (FNMSUBS $A, $B, $C)>; 3712def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3713 (FMSUB $A, $B, $C)>; 3714def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3715 (FMSUBS $A, $B, $C)>; 3716def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3717 (FNMADD $A, $B, $C)>; 3718def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3719 (FNMADDS $A, $B, $C)>; 3720 3721// FCOPYSIGN's operand types need not agree. 3722def : Pat<(fcopysign f64:$frB, f32:$frA), 3723 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3724def : Pat<(fcopysign f32:$frB, f64:$frA), 3725 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3726} 3727 3728// XL Compat intrinsics. 3729def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3730def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3731def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (FNMSUB $A, $B, $C)>; 3732def : Pat<(int_ppc_fnmsubs f32:$A, f32:$B, f32:$C), (FNMSUBS $A, $B, $C)>; 3733def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3734def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3735def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3736def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3737 3738include "PPCInstrAltivec.td" 3739include "PPCInstrSPE.td" 3740include "PPCInstr64Bit.td" 3741include "PPCInstrVSX.td" 3742include "PPCInstrHTM.td" 3743 3744def crnot : OutPatFrag<(ops node:$in), 3745 (CRNOR $in, $in)>; 3746def : Pat<(not i1:$in), 3747 (crnot $in)>; 3748 3749// Prefixed instructions may require access to the above defs at a later 3750// time so we include this after the def. 3751include "PPCInstrPrefix.td" 3752 3753// Patterns for arithmetic i1 operations. 3754def : Pat<(add i1:$a, i1:$b), 3755 (CRXOR $a, $b)>; 3756def : Pat<(sub i1:$a, i1:$b), 3757 (CRXOR $a, $b)>; 3758def : Pat<(mul i1:$a, i1:$b), 3759 (CRAND $a, $b)>; 3760 3761// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3762// (-1 is used to mean all bits set). 3763def : Pat<(i1 -1), (CRSET)>; 3764 3765// i1 extensions, implemented in terms of isel. 3766def : Pat<(i32 (zext i1:$in)), 3767 (SELECT_I4 $in, (LI 1), (LI 0))>; 3768def : Pat<(i32 (sext i1:$in)), 3769 (SELECT_I4 $in, (LI -1), (LI 0))>; 3770 3771def : Pat<(i64 (zext i1:$in)), 3772 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3773def : Pat<(i64 (sext i1:$in)), 3774 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3775 3776// FIXME: We should choose either a zext or a sext based on other constants 3777// already around. 3778def : Pat<(i32 (anyext i1:$in)), 3779 (SELECT_I4 $in, (LI 1), (LI 0))>; 3780def : Pat<(i64 (anyext i1:$in)), 3781 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3782 3783// match setcc on i1 variables. 3784// CRANDC is: 3785// 1 1 : F 3786// 1 0 : T 3787// 0 1 : F 3788// 0 0 : F 3789// 3790// LT is: 3791// -1 -1 : F 3792// -1 0 : T 3793// 0 -1 : F 3794// 0 0 : F 3795// 3796// ULT is: 3797// 1 1 : F 3798// 1 0 : F 3799// 0 1 : T 3800// 0 0 : F 3801def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3802 (CRANDC $s1, $s2)>; 3803def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3804 (CRANDC $s2, $s1)>; 3805// CRORC is: 3806// 1 1 : T 3807// 1 0 : T 3808// 0 1 : F 3809// 0 0 : T 3810// 3811// LE is: 3812// -1 -1 : T 3813// -1 0 : T 3814// 0 -1 : F 3815// 0 0 : T 3816// 3817// ULE is: 3818// 1 1 : T 3819// 1 0 : F 3820// 0 1 : T 3821// 0 0 : T 3822def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3823 (CRORC $s1, $s2)>; 3824def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3825 (CRORC $s2, $s1)>; 3826 3827def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3828 (CREQV $s1, $s2)>; 3829 3830// GE is: 3831// -1 -1 : T 3832// -1 0 : F 3833// 0 -1 : T 3834// 0 0 : T 3835// 3836// UGE is: 3837// 1 1 : T 3838// 1 0 : T 3839// 0 1 : F 3840// 0 0 : T 3841def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3842 (CRORC $s2, $s1)>; 3843def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3844 (CRORC $s1, $s2)>; 3845 3846// GT is: 3847// -1 -1 : F 3848// -1 0 : F 3849// 0 -1 : T 3850// 0 0 : F 3851// 3852// UGT is: 3853// 1 1 : F 3854// 1 0 : T 3855// 0 1 : F 3856// 0 0 : F 3857def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3858 (CRANDC $s2, $s1)>; 3859def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3860 (CRANDC $s1, $s2)>; 3861 3862def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3863 (CRXOR $s1, $s2)>; 3864 3865// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3866// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3867// floating-point types. 3868 3869multiclass CRNotPat<dag pattern, dag result> { 3870 def : Pat<pattern, (crnot result)>; 3871 def : Pat<(not pattern), result>; 3872 3873 // We can also fold the crnot into an extension: 3874 def : Pat<(i32 (zext pattern)), 3875 (SELECT_I4 result, (LI 0), (LI 1))>; 3876 def : Pat<(i32 (sext pattern)), 3877 (SELECT_I4 result, (LI 0), (LI -1))>; 3878 3879 // We can also fold the crnot into an extension: 3880 def : Pat<(i64 (zext pattern)), 3881 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3882 def : Pat<(i64 (sext pattern)), 3883 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3884 3885 // FIXME: We should choose either a zext or a sext based on other constants 3886 // already around. 3887 def : Pat<(i32 (anyext pattern)), 3888 (SELECT_I4 result, (LI 0), (LI 1))>; 3889 3890 def : Pat<(i64 (anyext pattern)), 3891 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3892} 3893 3894// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3895// we need to write imm:$imm in the output patterns below, not just $imm, or 3896// else the resulting matcher will not correctly add the immediate operand 3897// (making it a register operand instead). 3898 3899// extended SETCC. 3900multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3901 OutPatFrag rfrag, OutPatFrag rfrag8> { 3902 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3903 (rfrag $s1)>; 3904 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3905 (rfrag8 $s1)>; 3906 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3907 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3908 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3909 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3910 3911 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3912 (rfrag $s1)>; 3913 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3914 (rfrag8 $s1)>; 3915 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3916 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3917 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3918 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3919} 3920 3921// Note that we do all inversions below with i(32|64)not, instead of using 3922// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3923// has 2-cycle latency. 3924 3925defm : ExtSetCCPat<SETEQ, 3926 PatFrag<(ops node:$in, node:$cc), 3927 (setcc $in, 0, $cc)>, 3928 OutPatFrag<(ops node:$in), 3929 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3930 OutPatFrag<(ops node:$in), 3931 (RLDICL (CNTLZD $in), 58, 63)> >; 3932 3933defm : ExtSetCCPat<SETNE, 3934 PatFrag<(ops node:$in, node:$cc), 3935 (setcc $in, 0, $cc)>, 3936 OutPatFrag<(ops node:$in), 3937 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3938 OutPatFrag<(ops node:$in), 3939 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3940 3941defm : ExtSetCCPat<SETLT, 3942 PatFrag<(ops node:$in, node:$cc), 3943 (setcc $in, 0, $cc)>, 3944 OutPatFrag<(ops node:$in), 3945 (RLWINM $in, 1, 31, 31)>, 3946 OutPatFrag<(ops node:$in), 3947 (RLDICL $in, 1, 63)> >; 3948 3949defm : ExtSetCCPat<SETGE, 3950 PatFrag<(ops node:$in, node:$cc), 3951 (setcc $in, 0, $cc)>, 3952 OutPatFrag<(ops node:$in), 3953 (RLWINM (i32not $in), 1, 31, 31)>, 3954 OutPatFrag<(ops node:$in), 3955 (RLDICL (i64not $in), 1, 63)> >; 3956 3957defm : ExtSetCCPat<SETGT, 3958 PatFrag<(ops node:$in, node:$cc), 3959 (setcc $in, 0, $cc)>, 3960 OutPatFrag<(ops node:$in), 3961 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3962 OutPatFrag<(ops node:$in), 3963 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3964 3965defm : ExtSetCCPat<SETLE, 3966 PatFrag<(ops node:$in, node:$cc), 3967 (setcc $in, 0, $cc)>, 3968 OutPatFrag<(ops node:$in), 3969 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3970 OutPatFrag<(ops node:$in), 3971 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3972 3973defm : ExtSetCCPat<SETLT, 3974 PatFrag<(ops node:$in, node:$cc), 3975 (setcc $in, -1, $cc)>, 3976 OutPatFrag<(ops node:$in), 3977 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3978 OutPatFrag<(ops node:$in), 3979 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3980 3981defm : ExtSetCCPat<SETGE, 3982 PatFrag<(ops node:$in, node:$cc), 3983 (setcc $in, -1, $cc)>, 3984 OutPatFrag<(ops node:$in), 3985 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3986 OutPatFrag<(ops node:$in), 3987 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3988 3989defm : ExtSetCCPat<SETGT, 3990 PatFrag<(ops node:$in, node:$cc), 3991 (setcc $in, -1, $cc)>, 3992 OutPatFrag<(ops node:$in), 3993 (RLWINM (i32not $in), 1, 31, 31)>, 3994 OutPatFrag<(ops node:$in), 3995 (RLDICL (i64not $in), 1, 63)> >; 3996 3997defm : ExtSetCCPat<SETLE, 3998 PatFrag<(ops node:$in, node:$cc), 3999 (setcc $in, -1, $cc)>, 4000 OutPatFrag<(ops node:$in), 4001 (RLWINM $in, 1, 31, 31)>, 4002 OutPatFrag<(ops node:$in), 4003 (RLDICL $in, 1, 63)> >; 4004 4005// An extended SETCC with shift amount. 4006multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 4007 OutPatFrag rfrag, OutPatFrag rfrag8> { 4008 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 4009 (rfrag $s1, $sa)>; 4010 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 4011 (rfrag8 $s1, $sa)>; 4012 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 4013 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 4014 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 4015 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 4016 4017 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 4018 (rfrag $s1, $sa)>; 4019 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 4020 (rfrag8 $s1, $sa)>; 4021 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 4022 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 4023 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 4024 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 4025} 4026 4027defm : ExtSetCCShiftPat<SETNE, 4028 PatFrag<(ops node:$in, node:$sa, node:$cc), 4029 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 4030 OutPatFrag<(ops node:$in, node:$sa), 4031 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 4032 OutPatFrag<(ops node:$in, node:$sa), 4033 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 4034 4035defm : ExtSetCCShiftPat<SETEQ, 4036 PatFrag<(ops node:$in, node:$sa, node:$cc), 4037 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 4038 OutPatFrag<(ops node:$in, node:$sa), 4039 (RLWNM (i32not $in), 4040 (SUBFIC $sa, 32), 31, 31)>, 4041 OutPatFrag<(ops node:$in, node:$sa), 4042 (RLDCL (i64not $in), 4043 (SUBFIC $sa, 64), 63)> >; 4044 4045// SETCC for i32. 4046def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 4047 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 4048def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 4049 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 4050def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 4051 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 4052def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 4053 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 4054def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 4055 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 4056def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 4057 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 4058 4059// For non-equality comparisons, the default code would materialize the 4060// constant, then compare against it, like this: 4061// lis r2, 4660 4062// ori r2, r2, 22136 4063// cmpw cr0, r3, r2 4064// beq cr0,L6 4065// Since we are just comparing for equality, we can emit this instead: 4066// xoris r0,r3,0x1234 4067// cmplwi cr0,r0,0x5678 4068// beq cr0,L6 4069 4070def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 4071 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 4072 (LO16 imm:$imm)), sub_eq)>; 4073 4074def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 4075 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 4076def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 4077 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 4078def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 4079 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 4080def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 4081 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 4082def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 4083 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 4084 4085// SETCC for i64. 4086def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 4087 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 4088def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 4089 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 4090def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 4091 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 4092def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 4093 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 4094def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 4095 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 4096def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 4097 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 4098 4099// For non-equality comparisons, the default code would materialize the 4100// constant, then compare against it, like this: 4101// lis r2, 4660 4102// ori r2, r2, 22136 4103// cmpd cr0, r3, r2 4104// beq cr0,L6 4105// Since we are just comparing for equality, we can emit this instead: 4106// xoris r0,r3,0x1234 4107// cmpldi cr0,r0,0x5678 4108// beq cr0,L6 4109 4110def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 4111 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 4112 (LO16 imm:$imm)), sub_eq)>; 4113 4114def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 4115 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 4116def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 4117 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 4118def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 4119 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 4120def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 4121 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 4122def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 4123 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 4124 4125let Predicates = [IsNotISA3_1] in { 4126// Instantiations of CRNotPat for i32. 4127defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 4128 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 4129defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 4130 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 4131defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 4132 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 4133defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 4134 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 4135defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 4136 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 4137defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 4138 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 4139 4140defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 4141 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 4142 (LO16 imm:$imm)), sub_eq)>; 4143 4144defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 4145 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 4146defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 4147 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 4148defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 4149 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 4150defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 4151 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 4152defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 4153 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 4154 4155// Instantiations of CRNotPat for i64. 4156defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 4157 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 4158defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 4159 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 4160defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 4161 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 4162defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 4163 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 4164defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 4165 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 4166defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 4167 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 4168 4169defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 4170 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 4171 (LO16 imm:$imm)), sub_eq)>; 4172 4173defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 4174 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 4175defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 4176 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 4177defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 4178 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 4179defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 4180 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 4181defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 4182 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 4183} 4184 4185multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 4186 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 4187 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4188 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 4189 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4190 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 4191 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4192 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 4193 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4194 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 4195 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4196 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 4197 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4198 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 4199 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 4200 4201 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 4202 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4203 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 4204 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4205 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 4206 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4207 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 4208 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4209 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 4210 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4211 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 4212 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4213 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 4214 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 4215} 4216 4217let Predicates = [HasFPU] in { 4218// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 4219// SETCC for f32. 4220defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 4221 4222// SETCC for f64. 4223defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 4224 4225// SETCC for f128. 4226defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 4227 4228// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 4229// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 4230// then VXVC is set. 4231// SETCCS for f32. 4232defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 4233 4234// SETCCS for f64. 4235defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 4236 4237// SETCCS for f128. 4238defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 4239} 4240 4241// This must be in this file because it relies on patterns defined in this file 4242// after the inclusion of the instruction sets. 4243let Predicates = [HasSPE] in { 4244// SETCC for f32. 4245def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 4246 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4247def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 4248 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4249def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 4250 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4251def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 4252 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4253def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 4254 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4255def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 4256 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4257 4258defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 4259 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4260defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 4261 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4262defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 4263 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4264defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 4265 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4266defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 4267 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4268defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 4269 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4270 4271// SETCC for f64. 4272def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 4273 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4274def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 4275 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4276def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 4277 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4278def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 4279 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4280def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 4281 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4282def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 4283 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4284 4285defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 4286 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4287defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4288 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4289defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4290 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4291defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4292 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4293defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4294 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4295defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4296 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4297} 4298// match select on i1 variables: 4299def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4300 (CROR (CRAND $cond , $tval), 4301 (CRAND (crnot $cond), $fval))>; 4302 4303// match selectcc on i1 variables: 4304// select (lhs == rhs), tval, fval is: 4305// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4306def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4307 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4308 (CRAND (CRORC $rhs, $lhs), $fval))>; 4309def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4310 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4311 (CRAND (CRORC $lhs, $rhs), $fval))>; 4312def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4313 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4314 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4315def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4316 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4317 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4318def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4319 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4320 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4321def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4322 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4323 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4324def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4325 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4326 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4327def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4328 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4329 (CRAND (CRORC $lhs, $rhs), $fval))>; 4330def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4331 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4332 (CRAND (CRORC $rhs, $lhs), $fval))>; 4333def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4334 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4335 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4336 4337// match selectcc on i1 variables with non-i1 output. 4338def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4339 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4340def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4341 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4342def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4343 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4344def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4345 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4346def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4347 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4348def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4349 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4350def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4351 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4352def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4353 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4354def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4355 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4356def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4357 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4358 4359def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4360 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4361def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4362 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4363def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4364 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4365def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4366 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4367def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4368 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4369def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4370 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4371def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4372 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4373def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4374 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4375def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4376 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4377def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4378 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4379 4380let Predicates = [HasFPU] in { 4381def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4382 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4383def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4384 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4385def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4386 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4387def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4388 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4389def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4390 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4391def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4392 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4393def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4394 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4395def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4396 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4397def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4398 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4399def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4400 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4401 4402def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4403 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4404def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4405 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4406def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4407 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4408def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4409 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4410def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4411 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4412def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4413 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4414def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4415 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4416def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4417 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4418def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4419 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4420def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4421 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4422} 4423 4424def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4425 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4426def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4427 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4428def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4429 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4430def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4431 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4432def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4433 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4434def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4435 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4436def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4437 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4438def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4439 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4440def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4441 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4442def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4443 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4444 4445def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4446 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4447def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4448 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4449def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4450 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4451def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4452 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4453def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4454 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4455def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4456 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4457def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4458 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4459def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4460 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4461def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4462 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4463def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4464 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4465 4466def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4467 "#ANDI_rec_1_EQ_BIT", 4468 [(set i1:$dst, (trunc (not i32:$in)))]>; 4469def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4470 "#ANDI_rec_1_GT_BIT", 4471 [(set i1:$dst, (trunc i32:$in))]>; 4472 4473def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4474 "#ANDI_rec_1_EQ_BIT8", 4475 [(set i1:$dst, (trunc (not i64:$in)))]>; 4476def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4477 "#ANDI_rec_1_GT_BIT8", 4478 [(set i1:$dst, (trunc i64:$in))]>; 4479 4480def : Pat<(i1 (not (trunc i32:$in))), 4481 (ANDI_rec_1_EQ_BIT $in)>; 4482def : Pat<(i1 (not (trunc i64:$in))), 4483 (ANDI_rec_1_EQ_BIT8 $in)>; 4484 4485def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4486def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4487def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4488 4489//===----------------------------------------------------------------------===// 4490// PowerPC Instructions used for assembler/disassembler only 4491// 4492 4493// FIXME: For B=0 or B > 8, the registers following RT are used. 4494// WARNING: Do not add patterns for this instruction without fixing this. 4495def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4496 (ins gprc:$A, u5imm:$B), 4497 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4498 4499// FIXME: For B=0 or B > 8, the registers following RT are used. 4500// WARNING: Do not add patterns for this instruction without fixing this. 4501def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4502 (ins gprc:$RT, gprc:$A, u5imm:$B), 4503 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4504 4505def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4506 "isync", IIC_SprISYNC, []>; 4507 4508def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4509 "icbi $src", IIC_LdStICBI, []>; 4510 4511def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4512 "wait $L", IIC_LdStLoad, []>; 4513 4514def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4515 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4516 4517def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4518 "mtsr $SR, $RS", IIC_SprMTSR>; 4519 4520def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4521 "mfsr $RS, $SR", IIC_SprMFSR>; 4522 4523def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4524 "mtsrin $RS, $RB", IIC_SprMTSR>; 4525 4526def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4527 "mfsrin $RS, $RB", IIC_SprMFSR>; 4528 4529def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4530 "mtmsr $RS, $L", IIC_SprMTMSR>; 4531 4532def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4533 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4534 let L = 0; 4535} 4536 4537def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4538 Requires<[IsBookE]> { 4539 bits<1> E; 4540 4541 let Inst{16} = E; 4542 let Inst{21-30} = 163; 4543} 4544 4545def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4546 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4547def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4548 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4549 4550def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4551def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4552def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4553def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4554 4555def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4556 "mfmsr $RT", IIC_SprMFMSR, []>; 4557 4558def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4559 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4560 4561def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4562 "mcrfs $BF, $BFA", IIC_BrMCR>; 4563 4564// All MTFSF variants may change the rounding mode so conservatively set it 4565// as an implicit def for all of them. 4566let Predicates = [HasFPU] in { 4567let Defs = [RM], hasSideEffects = 1 in { 4568let isCodeGenOnly = 1, 4569 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4570def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4571 "mtfsfi $BF, $U", IIC_IntMFFS>; 4572def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4573 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4574let Defs = [CR1] in 4575def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4576 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4577 4578def MTFSF : XFLForm_1<63, 711, (outs), 4579 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4580 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4581let Defs = [CR1] in 4582def MTFSF_rec : XFLForm_1<63, 711, (outs), 4583 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4584 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4585} 4586 4587def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4588def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4589def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4590def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4591} 4592 4593def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4594 "slbie $RB", IIC_SprSLBIE, []>; 4595 4596def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4597 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4598 4599def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4600 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4601 4602def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4603 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4604 4605def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4606 4607let Defs = [CR0] in 4608def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4609 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4610 4611def TLBIA : XForm_0<31, 370, (outs), (ins), 4612 "tlbia", IIC_SprTLBIA, []>; 4613 4614def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4615 "tlbsync", IIC_SprTLBSYNC, []>; 4616 4617def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4618 "tlbiel $RB", IIC_SprTLBIEL, []>; 4619 4620def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4621 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4622def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4623 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4624 4625def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4626 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4627 4628def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4629 IIC_LdStLoad>, Requires<[IsBookE]>; 4630 4631def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4632 IIC_LdStLoad>, Requires<[IsBookE]>; 4633 4634def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4635 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4636 4637def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4638 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4639 4640def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4641 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4642 4643def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4644 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4645 4646def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4647 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4648 Requires<[IsPPC4xx]>; 4649def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4650 (ins gprc:$RST, gprc:$A, gprc:$B), 4651 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4652 Requires<[IsPPC4xx]>, isRecordForm; 4653 4654def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4655 4656def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4657 Requires<[IsBookE]>; 4658def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4659 Requires<[IsBookE]>; 4660 4661def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4662 Requires<[IsE500]>; 4663def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4664 Requires<[IsE500]>; 4665 4666def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4667 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4668def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4669 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4670 4671def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4672def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4673 4674def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4675 4676def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4677 (ins gprc:$A, gprc:$B), 4678 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4679def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4680 (ins gprc:$A, gprc:$B), 4681 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4682def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4683 (ins gprc:$A, gprc:$B), 4684 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4685def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4686 (ins gprc:$A, gprc:$B), 4687 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4688 4689def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4690 (ins gprc:$RST, gprc:$A, gprc:$B), 4691 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4692def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4693 (ins gprc:$RST, gprc:$A, gprc:$B), 4694 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4695def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4696 (ins gprc:$RST, gprc:$A, gprc:$B), 4697 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4698def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4699 (ins gprc:$RST, gprc:$A, gprc:$B), 4700 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4701 4702// External PID Load Store Instructions 4703 4704def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4705 "lbepx $rD, $src", IIC_LdStLoad, []>, 4706 Requires<[IsE500]>; 4707 4708def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4709 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4710 Requires<[IsE500]>; 4711 4712def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4713 "lhepx $rD, $src", IIC_LdStLoad, []>, 4714 Requires<[IsE500]>; 4715 4716def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4717 "lwepx $rD, $src", IIC_LdStLoad, []>, 4718 Requires<[IsE500]>; 4719 4720def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4721 "stbepx $rS, $dst", IIC_LdStStore, []>, 4722 Requires<[IsE500]>; 4723 4724def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4725 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4726 Requires<[IsE500]>; 4727 4728def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4729 "sthepx $rS, $dst", IIC_LdStStore, []>, 4730 Requires<[IsE500]>; 4731 4732def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4733 "stwepx $rS, $dst", IIC_LdStStore, []>, 4734 Requires<[IsE500]>; 4735 4736def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4737 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4738 4739def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4740 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4741 4742def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4743 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4744 Requires<[IsE500]>; 4745 4746def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4747 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4748 Requires<[IsE500]>; 4749 4750def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4751 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4752 4753def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4754 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4755 4756def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4757 IIC_LdStICBI, []>, Requires<[IsE500]>; 4758 4759//===----------------------------------------------------------------------===// 4760// PowerPC Assembler Instruction Aliases 4761// 4762 4763// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4764// These are aliases that require C++ handling to convert to the target 4765// instruction, while InstAliases can be handled directly by tblgen. 4766class PPCAsmPseudo<string asm, dag iops> 4767 : Instruction { 4768 let Namespace = "PPC"; 4769 bit PPC64 = 0; // Default value, override with isPPC64 4770 4771 let OutOperandList = (outs); 4772 let InOperandList = iops; 4773 let Pattern = []; 4774 let AsmString = asm; 4775 let isAsmParserOnly = 1; 4776 let isPseudo = 1; 4777 let hasNoSchedulingInfo = 1; 4778} 4779 4780def : InstAlias<"sc", (SC 0)>; 4781 4782def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4783def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4784def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4785def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4786def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4787 4788def : InstAlias<"wait", (WAIT 0)>; 4789def : InstAlias<"waitrsv", (WAIT 1)>; 4790def : InstAlias<"waitimpl", (WAIT 2)>; 4791 4792def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4793 4794def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4795def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4796 4797def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4798def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4799def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4800 4801def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4802def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4803def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4804 4805def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4806def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4807def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4808 4809def : Pat<(int_ppc_isync), (ISYNC)>; 4810def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4811 (DCBF 1, xoaddr:$dst)>; 4812def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4813 (DCBF 3, xoaddr:$dst)>; 4814 4815let Predicates = [IsISA3_1] in { 4816 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4817 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4818 4819 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4820 (DCBF 4, xoaddr:$dst)>; 4821 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4822 (DCBF 6, xoaddr:$dst)>; 4823} 4824 4825def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4826def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4827def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4828def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4829 4830def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4831def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4832def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4833 4834def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4835 4836def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4837def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4838 4839//Disable this alias on AIX for now because as does not support them. 4840let Predicates = [ModernAs] in { 4841 4842foreach BR = 0-7 in { 4843 def : InstAlias<"mfbr"#BR#" $Rx", 4844 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4845 Requires<[IsPPC4xx]>; 4846 def : InstAlias<"mtbr"#BR#" $Rx", 4847 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4848 Requires<[IsPPC4xx]>; 4849} 4850 4851def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4852def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4853def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4854def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4855 4856def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4857def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4858 4859def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4860def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4861 4862def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4863def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4864 4865def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4866def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4867 4868def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4869def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4870 4871def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4872def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4873 4874def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4875def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4876 4877def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4878def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4879 4880def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4881def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4882 4883def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4884def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4885 4886def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4887def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4888 4889def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4890def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4891 4892def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4893def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4894 4895def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4896def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4897 4898foreach SPRG = 4-7 in { 4899 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4900 Requires<[IsBookE]>; 4901 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4902 Requires<[IsBookE]>; 4903 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4904 Requires<[IsBookE]>; 4905 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4906 Requires<[IsBookE]>; 4907} 4908 4909foreach SPRG = 0-3 in { 4910 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4911 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4912 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4913 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4914} 4915 4916def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4917def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4918 4919def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4920def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4921 4922def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4923 4924def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4925def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4926 4927foreach BATR = 0-3 in { 4928 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4929 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4930 Requires<[IsPPC6xx]>; 4931 def : InstAlias<"mfdbatu $Rx, "#BATR, 4932 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4933 Requires<[IsPPC6xx]>; 4934 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4935 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4936 Requires<[IsPPC6xx]>; 4937 def : InstAlias<"mfdbatl $Rx, "#BATR, 4938 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4939 Requires<[IsPPC6xx]>; 4940 def : InstAlias<"mtibatu "#BATR#", $Rx", 4941 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4942 Requires<[IsPPC6xx]>; 4943 def : InstAlias<"mfibatu $Rx, "#BATR, 4944 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4945 Requires<[IsPPC6xx]>; 4946 def : InstAlias<"mtibatl "#BATR#", $Rx", 4947 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4948 Requires<[IsPPC6xx]>; 4949 def : InstAlias<"mfibatl $Rx, "#BATR, 4950 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4951 Requires<[IsPPC6xx]>; 4952} 4953 4954def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4955def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4956 4957def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4958def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4959 4960def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4961def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4962 4963def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4964def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4965 4966def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4967def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4968 4969def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4970def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4971 4972def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4973def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4974 4975def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4976def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4977 4978def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4979def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4980 4981def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4982def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4983 4984} 4985 4986def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4987 4988def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4989 Requires<[IsPPC4xx]>; 4990def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4991 Requires<[IsPPC4xx]>; 4992def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4993 Requires<[IsPPC4xx]>; 4994def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4995 Requires<[IsPPC4xx]>; 4996 4997def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4998 4999def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 5000 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 5001def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 5002 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 5003def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 5004 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 5005def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 5006 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 5007 5008def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 5009 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5010def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 5011 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5012def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 5013 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5014def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 5015 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5016def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 5017 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5018def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 5019 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5020def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 5021 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5022def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 5023 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 5024def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 5025 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5026def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 5027 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5028def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 5029 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5030def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 5031 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5032def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 5033 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5034def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 5035 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5036def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 5037 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5038def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 5039 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 5040def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 5041 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 5042def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 5043 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 5044 5045def : InstAlias<"isellt $rT, $rA, $rB", 5046 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 5047def : InstAlias<"iselgt $rT, $rA, $rB", 5048 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 5049def : InstAlias<"iseleq $rT, $rA, $rB", 5050 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 5051 5052def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 5053def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 5054def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 5055def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 5056def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 5057def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 5058 5059def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 5060def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 5061// The POWER variant 5062def : MnemonicAlias<"cntlz", "cntlzw">; 5063def : MnemonicAlias<"cntlz.", "cntlzw.">; 5064 5065def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 5066 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5067def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 5068 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5069def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 5070 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5071def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 5072 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5073def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 5074 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5075def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 5076 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5077def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 5078 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5079def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 5080 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5081def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 5082 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5083def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 5084 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5085def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 5086 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5087def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 5088 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5089def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 5090 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5091def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 5092 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5093def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 5094 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 5095def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 5096 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 5097def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 5098 5099def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 5100def : InstAlias<"rotldi $rA, $rS, $n", 5101 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 5102def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 5103def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 5104def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 5105def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 5106def : InstAlias<"clrldi $rA, $rS, $n", 5107 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 5108def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 5109def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 5110 5111def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 5112 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5113def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 5114 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5115def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 5116 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5117def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 5118 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5119def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 5120 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5121def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 5122 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5123 5124// These generic branch instruction forms are used for the assembler parser only. 5125// Defs and Uses are conservative, since we don't know the BO value. 5126let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 5127 let Defs = [CTR], Uses = [CTR, RM] in { 5128 def gBC : BForm_3<16, 0, 0, (outs), 5129 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 5130 "bc $bo, $bi, $dst">; 5131 def gBCA : BForm_3<16, 1, 0, (outs), 5132 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 5133 "bca $bo, $bi, $dst">; 5134 let isAsmParserOnly = 1 in { 5135 def gBCat : BForm_3_at<16, 0, 0, (outs), 5136 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5137 condbrtarget:$dst), 5138 "bc$at $bo, $bi, $dst">; 5139 def gBCAat : BForm_3_at<16, 1, 0, (outs), 5140 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5141 abscondbrtarget:$dst), 5142 "bca$at $bo, $bi, $dst">; 5143 } // isAsmParserOnly = 1 5144 } 5145 let Defs = [LR, CTR], Uses = [CTR, RM] in { 5146 def gBCL : BForm_3<16, 0, 1, (outs), 5147 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 5148 "bcl $bo, $bi, $dst">; 5149 def gBCLA : BForm_3<16, 1, 1, (outs), 5150 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 5151 "bcla $bo, $bi, $dst">; 5152 let isAsmParserOnly = 1 in { 5153 def gBCLat : BForm_3_at<16, 0, 1, (outs), 5154 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5155 condbrtarget:$dst), 5156 "bcl$at $bo, $bi, $dst">; 5157 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 5158 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5159 abscondbrtarget:$dst), 5160 "bcla$at $bo, $bi, $dst">; 5161 } // // isAsmParserOnly = 1 5162 } 5163 let Defs = [CTR], Uses = [CTR, LR, RM] in 5164 def gBCLR : XLForm_2<19, 16, 0, (outs), 5165 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5166 "bclr $bo, $bi, $bh", IIC_BrB, []>; 5167 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 5168 def gBCLRL : XLForm_2<19, 16, 1, (outs), 5169 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5170 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 5171 let Defs = [CTR], Uses = [CTR, LR, RM] in 5172 def gBCCTR : XLForm_2<19, 528, 0, (outs), 5173 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5174 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 5175 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 5176 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 5177 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5178 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 5179} 5180 5181multiclass BranchSimpleMnemonicAT<string pm, int at> { 5182 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 5183 condbrtarget:$dst)>; 5184 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 5185 condbrtarget:$dst)>; 5186 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 5187 condbrtarget:$dst)>; 5188 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 5189 condbrtarget:$dst)>; 5190} 5191defm : BranchSimpleMnemonicAT<"+", 3>; 5192defm : BranchSimpleMnemonicAT<"-", 2>; 5193 5194def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 5195def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 5196def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 5197def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 5198 5199multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 5200 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 5201 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 5202 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 5203 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 5204 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 5205 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 5206} 5207multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 5208 : BranchSimpleMnemonic1<name, pm, bo> { 5209 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 5210 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 5211} 5212defm : BranchSimpleMnemonic2<"t", "", 12>; 5213defm : BranchSimpleMnemonic2<"f", "", 4>; 5214defm : BranchSimpleMnemonic2<"t", "-", 14>; 5215defm : BranchSimpleMnemonic2<"f", "-", 6>; 5216defm : BranchSimpleMnemonic2<"t", "+", 15>; 5217defm : BranchSimpleMnemonic2<"f", "+", 7>; 5218defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 5219defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 5220defm : BranchSimpleMnemonic1<"dzt", "", 10>; 5221defm : BranchSimpleMnemonic1<"dzf", "", 2>; 5222 5223multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 5224 def : InstAlias<"b"#name#pm#" $cc, $dst", 5225 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 5226 def : InstAlias<"b"#name#pm#" $dst", 5227 (BCC bibo, CR0, condbrtarget:$dst)>; 5228 5229 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 5230 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 5231 def : InstAlias<"b"#name#"a"#pm#" $dst", 5232 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 5233 5234 def : InstAlias<"b"#name#"lr"#pm#" $cc", 5235 (BCCLR bibo, crrc:$cc)>; 5236 def : InstAlias<"b"#name#"lr"#pm, 5237 (BCCLR bibo, CR0)>; 5238 5239 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 5240 (BCCCTR bibo, crrc:$cc)>; 5241 def : InstAlias<"b"#name#"ctr"#pm, 5242 (BCCCTR bibo, CR0)>; 5243 5244 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 5245 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 5246 def : InstAlias<"b"#name#"l"#pm#" $dst", 5247 (BCCL bibo, CR0, condbrtarget:$dst)>; 5248 5249 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 5250 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 5251 def : InstAlias<"b"#name#"la"#pm#" $dst", 5252 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 5253 5254 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 5255 (BCCLRL bibo, crrc:$cc)>; 5256 def : InstAlias<"b"#name#"lrl"#pm, 5257 (BCCLRL bibo, CR0)>; 5258 5259 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 5260 (BCCCTRL bibo, crrc:$cc)>; 5261 def : InstAlias<"b"#name#"ctrl"#pm, 5262 (BCCCTRL bibo, CR0)>; 5263} 5264multiclass BranchExtendedMnemonic<string name, int bibo> { 5265 defm : BranchExtendedMnemonicPM<name, "", bibo>; 5266 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 5267 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 5268} 5269defm : BranchExtendedMnemonic<"lt", 12>; 5270defm : BranchExtendedMnemonic<"gt", 44>; 5271defm : BranchExtendedMnemonic<"eq", 76>; 5272defm : BranchExtendedMnemonic<"un", 108>; 5273defm : BranchExtendedMnemonic<"so", 108>; 5274defm : BranchExtendedMnemonic<"ge", 4>; 5275defm : BranchExtendedMnemonic<"nl", 4>; 5276defm : BranchExtendedMnemonic<"le", 36>; 5277defm : BranchExtendedMnemonic<"ng", 36>; 5278defm : BranchExtendedMnemonic<"ne", 68>; 5279defm : BranchExtendedMnemonic<"nu", 100>; 5280defm : BranchExtendedMnemonic<"ns", 100>; 5281 5282def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 5283def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 5284def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 5285def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 5286def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 5287def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 5288def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 5289def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5290 5291def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5292def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5293def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5294def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5295def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5296def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5297def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5298def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5299 5300def : InstAlias<"trap", (TW 31, R0, R0)>; 5301 5302multiclass TrapExtendedMnemonic<string name, int to> { 5303 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5304 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5305 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5306 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5307} 5308defm : TrapExtendedMnemonic<"lt", 16>; 5309defm : TrapExtendedMnemonic<"le", 20>; 5310defm : TrapExtendedMnemonic<"eq", 4>; 5311defm : TrapExtendedMnemonic<"ge", 12>; 5312defm : TrapExtendedMnemonic<"gt", 8>; 5313defm : TrapExtendedMnemonic<"nl", 12>; 5314defm : TrapExtendedMnemonic<"ne", 24>; 5315defm : TrapExtendedMnemonic<"ng", 20>; 5316defm : TrapExtendedMnemonic<"llt", 2>; 5317defm : TrapExtendedMnemonic<"lle", 6>; 5318defm : TrapExtendedMnemonic<"lge", 5>; 5319defm : TrapExtendedMnemonic<"lgt", 1>; 5320defm : TrapExtendedMnemonic<"lnl", 5>; 5321defm : TrapExtendedMnemonic<"lng", 6>; 5322defm : TrapExtendedMnemonic<"u", 31>; 5323 5324// Atomic loads 5325def : Pat<(atomic_load_8 DForm:$src), (LBZ memri:$src)>; 5326def : Pat<(atomic_load_16 DForm:$src), (LHZ memri:$src)>; 5327def : Pat<(atomic_load_32 DForm:$src), (LWZ memri:$src)>; 5328def : Pat<(atomic_load_8 XForm:$src), (LBZX memrr:$src)>; 5329def : Pat<(atomic_load_16 XForm:$src), (LHZX memrr:$src)>; 5330def : Pat<(atomic_load_32 XForm:$src), (LWZX memrr:$src)>; 5331 5332// Atomic stores 5333def : Pat<(atomic_store_8 DForm:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 5334def : Pat<(atomic_store_16 DForm:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 5335def : Pat<(atomic_store_32 DForm:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 5336def : Pat<(atomic_store_8 XForm:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 5337def : Pat<(atomic_store_16 XForm:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 5338def : Pat<(atomic_store_32 XForm:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 5339 5340let Predicates = [IsISA3_0] in { 5341 5342// Copy-Paste Facility 5343// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5344// PASTE for naming consistency. 5345let mayLoad = 1 in 5346def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5347 5348let mayStore = 1, Defs = [CR0] in 5349def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5350 5351def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5352def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5353 5354// Message Synchronize 5355def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5356 5357// Power-Saving Mode Instruction: 5358def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5359 5360def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5361 "setb $RT, $BFA", IIC_IntGeneral>; 5362} // IsISA3_0 5363 5364let Predicates = [IsISA3_0] in { 5365def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5366 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5367} 5368def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5369 (i32 (MULHW $a, $b))>; 5370def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5371 (i32 (MULHWU $a, $b))>; 5372def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5373 (i32 (CMPB $a, $b))>; 5374 5375def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5376 (LHBRX ForceXForm:$ptr)>; 5377def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5378 (LWBRX ForceXForm:$ptr)>; 5379def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5380 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5381def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5382 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5383 5384 5385// Fast 32-bit reverse bits algorithm: 5386// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5387// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5388// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5389// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5390// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5391// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5392// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5393// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5394// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5395// Step 4.2: Insert B3 to the right position: 5396// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5397// Step 4.3: Insert B1 to the right position: 5398// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5399def MaskValues { 5400 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5401 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5402 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5403 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5404 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5405 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5406} 5407 5408def Shift1 { 5409 dag Right = (RLWINM $A, 31, 1, 31); 5410 dag Left = (RLWINM $A, 1, 0, 30); 5411} 5412 5413def Swap1 { 5414 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5415 (AND Shift1.Left, MaskValues.Hi1)); 5416} 5417 5418def Shift2 { 5419 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5420 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5421} 5422 5423def Swap2 { 5424 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5425 (AND Shift2.Left, MaskValues.Hi2)); 5426} 5427 5428def Shift4 { 5429 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5430 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5431} 5432 5433def Swap4 { 5434 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5435 (AND Shift4.Left, MaskValues.Hi4)); 5436} 5437 5438def Rotate { 5439 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5440} 5441 5442def RotateInsertByte3 { 5443 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5444} 5445 5446def RotateInsertByte1 { 5447 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5448} 5449 5450// Clear the upper half of the register when in 64-bit mode 5451let Predicates = [In64BitMode] in 5452def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5453let Predicates = [In32BitMode] in 5454def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5455 5456// Fast 64-bit reverse bits algorithm: 5457// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5458// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5459// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5460// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5461// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5462// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5463// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5464// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5465// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5466// then OR them together to get the final result. 5467def MaskValues64 { 5468 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5469 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5470 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5471 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5472 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5473 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5474} 5475 5476def DWMaskValues { 5477 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5478 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5479 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5480 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5481 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5482 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5483} 5484 5485def DWSwapInByte { 5486 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5487 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5488 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5489 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5490 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5491 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5492} 5493 5494// Intra-byte swap is done, now start inter-byte swap. 5495def DWBytes4567 { 5496 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5497} 5498 5499def DWBytes7456 { 5500 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5501} 5502 5503def DWBytes7656 { 5504 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5505} 5506 5507// B7 B6 B5 B4 in the right order 5508def DWBytes7654 { 5509 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5510 dag DWord = 5511 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5512} 5513 5514def DWBytes0123 { 5515 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5516} 5517 5518def DWBytes3012 { 5519 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5520} 5521 5522def DWBytes3212 { 5523 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5524} 5525 5526// B3 B2 B1 B0 in the right order 5527def DWBytes3210 { 5528 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5529 dag DWord = 5530 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5531} 5532 5533// These instructions store a hash computed from the value of the link register 5534// and the value of the stack pointer. 5535let mayStore = 1 in { 5536def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5537 (ins gprc:$RB, memrihash:$D_RA_XD), 5538 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 5539def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5540 (ins gprc:$RB, memrihash:$D_RA_XD), 5541 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 5542} 5543 5544// These instructions check a hash computed from the value of the link register 5545// and the value of the stack pointer. The hasSideEffects flag is needed as the 5546// instruction may TRAP if the hash does not match the hash stored at the 5547// specified address. 5548let mayLoad = 1, hasSideEffects = 1 in { 5549def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5550 (ins gprc:$RB, memrihash:$D_RA_XD), 5551 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 5552def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5553 (ins gprc:$RB, memrihash:$D_RA_XD), 5554 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 5555} 5556 5557// Now both high word and low word are reversed, next 5558// swap the high word and low word. 5559def : Pat<(i64 (bitreverse i64:$A)), 5560 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5561 5562def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5563 (STWCX gprc:$A, ForceXForm:$dst)>; 5564def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5565 (STBCX gprc:$A, ForceXForm:$dst)>; 5566def : Pat<(int_ppc_trap gprc:$A), 5567 (TWI 24, $A, 0)>; 5568 5569def : Pat<(int_ppc_fcfid f64:$A), 5570 (XSCVSXDDP $A)>; 5571def : Pat<(int_ppc_fcfud f64:$A), 5572 (XSCVUXDDP $A)>; 5573def : Pat<(int_ppc_fctid f64:$A), 5574 (FCTID $A)>; 5575def : Pat<(int_ppc_fctidz f64:$A), 5576 (XSCVDPSXDS $A)>; 5577def : Pat<(int_ppc_fctiw f64:$A), 5578 (FCTIW $A)>; 5579def : Pat<(int_ppc_fctiwz f64:$A), 5580 (XSCVDPSXWS $A)>; 5581def : Pat<(int_ppc_fctudz f64:$A), 5582 (XSCVDPUXDS $A)>; 5583def : Pat<(int_ppc_fctuwz f64:$A), 5584 (XSCVDPUXWS $A)>; 5585 5586def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5587def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5588def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5589 (MFSPR $SPR)>; 5590def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5591 (MTSPR $SPR, $RT)>; 5592def : Pat<(int_ppc_mtmsr gprc:$RS), 5593 (MTMSR $RS, 0)>; 5594 5595let Predicates = [IsISA2_07] in { 5596 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5597 (STHCX gprc:$A, ForceXForm:$dst)>; 5598} 5599def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5600 (DCBTST 16, ForceXForm:$dst)>; 5601def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5602 (DCBT 16, ForceXForm:$dst)>; 5603 5604def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5605 (STFIWX f64:$XT, ForceXForm:$dst)>; 5606