xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.td (revision 6966ac055c3b7a39266fb982493330df7a097997)
1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the subset of the 32-bit PowerPC instruction set, as used
10// by the PowerPC instruction selector.
11//
12//===----------------------------------------------------------------------===//
13
14include "PPCInstrFormats.td"
15
16//===----------------------------------------------------------------------===//
17// PowerPC specific type constraints.
18//
19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
20  SDTCisVT<0, f64>, SDTCisPtrTy<1>
21]>;
22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
23  SDTCisVT<0, f64>, SDTCisPtrTy<1>
24]>;
25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [
26  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
27]>;
28def SDT_PPCstxsix : SDTypeProfile<0, 3, [
29  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
30]>;
31def SDT_PPCcv_fp_to_int  : SDTypeProfile<1, 1, [
32  SDTCisFP<0>, SDTCisFP<1>
33  ]>;
34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [
35  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
36]>;
37def SDT_PPCVexts  : SDTypeProfile<1, 2, [
38  SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
39]>;
40def SDT_PPCSExtVElems  : SDTypeProfile<1, 1, [
41  SDTCisVec<0>, SDTCisVec<1>
42]>;
43
44def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
45                                           SDTCisVT<1, i32> ]>;
46def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
47                                         SDTCisVT<1, i32> ]>;
48def SDT_PPCvperm   : SDTypeProfile<1, 3, [
49  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
50]>;
51
52def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
53  SDTCisVec<1>, SDTCisInt<2>
54]>;
55
56def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
57  SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>
58]>;
59
60def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
61  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
62]>;
63
64def SDT_PPCVecReverse: SDTypeProfile<1, 1, [ SDTCisVec<0>,
65  SDTCisVec<1>
66]>;
67
68def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>,
69  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
70]>;
71
72def SDT_PPCvcmp : SDTypeProfile<1, 3, [
73  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
74]>;
75
76def SDT_PPCcondbr : SDTypeProfile<0, 3, [
77  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
78]>;
79
80def SDT_PPClbrx : SDTypeProfile<1, 2, [
81  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
82]>;
83def SDT_PPCstbrx : SDTypeProfile<0, 3, [
84  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
85]>;
86
87def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
88  SDTCisPtrTy<0>, SDTCisVT<1, i32>
89]>;
90
91def tocentry32 : Operand<iPTR> {
92  let MIOperandInfo = (ops i32imm:$imm);
93}
94
95def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
96  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
97]>;
98def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
99  SDTCisVec<0>, SDTCisInt<1>
100]>;
101def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
102  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
103]>;
104def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
105  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
106]>;
107
108def SDT_PPCqbflt : SDTypeProfile<1, 1, [
109  SDTCisVec<0>, SDTCisVec<1>
110]>;
111
112def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
113  SDTCisVec<0>, SDTCisPtrTy<1>
114]>;
115
116def SDT_PPCextswsli : SDTypeProfile<1, 2, [  // extswsli
117  SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2>
118]>;
119
120//===----------------------------------------------------------------------===//
121// PowerPC specific DAG Nodes.
122//
123
124def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
125def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
126
127def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
128def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
129def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
130def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
131def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
132def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
133def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
134def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
135
136def PPCcv_fp_to_uint_in_vsr:
137    SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>;
138def PPCcv_fp_to_sint_in_vsr:
139    SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>;
140def PPCstore_scal_int_from_vsr:
141   SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr,
142           [SDNPHasChain, SDNPMayStore]>;
143def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
144                       [SDNPHasChain, SDNPMayStore]>;
145def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
146                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
147def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
148                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
149def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
150                       [SDNPHasChain, SDNPMayLoad]>;
151def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
152                       [SDNPHasChain, SDNPMayStore]>;
153def PPCVexts  : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;
154def PPCSExtVElems  : SDNode<"PPCISD::SExtVElems", SDT_PPCSExtVElems, []>;
155
156// Extract FPSCR (not modeled at the DAG level).
157def PPCmffs   : SDNode<"PPCISD::MFFS",
158                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
159
160// Perform FADD in round-to-zero mode.
161def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
162
163
164def PPCfsel   : SDNode<"PPCISD::FSEL",
165   // Type constraint for fsel.
166   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
167                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
168
169def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
170def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
171def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
172                         [SDNPMayLoad, SDNPMemOperand]>;
173def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
174def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
175
176def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
177
178def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
179def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
180                            [SDNPMayLoad]>;
181def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
182def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
183def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
184def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
185def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
186                               SDTypeProfile<1, 3, [
187                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
188                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
189def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
190def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
191def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
192def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
193                               SDTypeProfile<1, 3, [
194                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
195                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
196def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
197def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
198
199def PPCvperm     : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
200def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
201def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>;
202def PPCxxreverse : SDNode<"PPCISD::XXREVERSE", SDT_PPCVecReverse, []>;
203def PPCxxpermdi  : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>;
204def PPCvecshl    : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
205
206def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
207def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
208def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
209def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
210
211def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
212
213def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
214                          [SDNPHasChain, SDNPMayLoad]>;
215
216def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
217
218// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
219// amounts.  These nodes are generated by the multi-precision shift code.
220def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
221def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
222def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
223
224def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>;
225
226// Move 2 i64 values into a VSX register
227def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",
228                           SDTypeProfile<1, 2,
229                             [SDTCisFP<0>, SDTCisSameSizeAs<1,2>,
230                              SDTCisSameAs<1,2>]>,
231                           []>;
232
233def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64",
234                           SDTypeProfile<1, 2,
235                             [SDTCisVT<0, f64>, SDTCisVT<1,i32>,
236                             SDTCisVT<1,i32>]>,
237                           []>;
238
239def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE",
240                            SDTypeProfile<1, 2,
241                              [SDTCisVT<0, i32>, SDTCisVT<1, f64>,
242                              SDTCisPtrTy<2>]>,
243                              []>;
244
245// These are target-independent nodes, but have target-specific formats.
246def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
247                           [SDNPHasChain, SDNPOutGlue]>;
248def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
249                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
250
251def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
252def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
253                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
254                       SDNPVariadic]>;
255def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
256                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
257                           SDNPVariadic]>;
258def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
259                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
260def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
261                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
262                       SDNPVariadic]>;
263def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
264                               SDTypeProfile<0, 1, []>,
265                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
266                                SDNPVariadic]>;
267
268def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
269                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
270
271def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
272                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
273
274def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
275                                SDTypeProfile<1, 1, [SDTCisInt<0>,
276                                                     SDTCisPtrTy<1>]>,
277                                [SDNPHasChain, SDNPSideEffect]>;
278def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
279                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
280                                [SDNPHasChain, SDNPSideEffect]>;
281
282def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
283def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
284                           [SDNPHasChain, SDNPSideEffect]>;
285
286def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
287                           [SDNPHasChain, SDNPSideEffect]>;
288def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
289def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
290                           [SDNPHasChain, SDNPSideEffect]>;
291
292def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
293def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
294
295def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
296                           [SDNPHasChain, SDNPOptInGlue]>;
297
298// PPC-specific atomic operations.
299def PPCatomicCmpSwap_8 :
300  SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3,
301         [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
302def PPCatomicCmpSwap_16 :
303  SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3,
304         [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
305def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
306                           [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
307def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
308                           [SDNPHasChain, SDNPMayStore]>;
309
310// Instructions to set/unset CR bit 6 for SVR4 vararg calls
311def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
312                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
313def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
314                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
315
316// Instructions to support dynamic alloca.
317def SDTDynOp  : SDTypeProfile<1, 2, []>;
318def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
319def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
320def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
321
322//===----------------------------------------------------------------------===//
323// PowerPC specific transformation functions and pattern fragments.
324//
325
326def SHL32 : SDNodeXForm<imm, [{
327  // Transformation function: 31 - imm
328  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
329}]>;
330
331def SRL32 : SDNodeXForm<imm, [{
332  // Transformation function: 32 - imm
333  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
334                           : getI32Imm(0, SDLoc(N));
335}]>;
336
337def LO16 : SDNodeXForm<imm, [{
338  // Transformation function: get the low 16 bits.
339  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
340}]>;
341
342def HI16 : SDNodeXForm<imm, [{
343  // Transformation function: shift the immediate value down into the low bits.
344  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
345}]>;
346
347def HA16 : SDNodeXForm<imm, [{
348  // Transformation function: shift the immediate value down into the low bits.
349  long Val = N->getZExtValue();
350  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
351}]>;
352def MB : SDNodeXForm<imm, [{
353  // Transformation function: get the start bit of a mask
354  unsigned mb = 0, me;
355  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
356  return getI32Imm(mb, SDLoc(N));
357}]>;
358
359def ME : SDNodeXForm<imm, [{
360  // Transformation function: get the end bit of a mask
361  unsigned mb, me = 0;
362  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
363  return getI32Imm(me, SDLoc(N));
364}]>;
365def maskimm32 : PatLeaf<(imm), [{
366  // maskImm predicate - True if immediate is a run of ones.
367  unsigned mb, me;
368  if (N->getValueType(0) == MVT::i32)
369    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
370  else
371    return false;
372}]>;
373
374def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
375  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
376  // sign extended field.  Used by instructions like 'addi'.
377  return (int32_t)Imm == (short)Imm;
378}]>;
379def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
380  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
381  // sign extended field.  Used by instructions like 'addi'.
382  return (int64_t)Imm == (short)Imm;
383}]>;
384def immZExt16  : PatLeaf<(imm), [{
385  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
386  // field.  Used by instructions like 'ori'.
387  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
388}], LO16>;
389def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
390def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
391
392// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
393// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
394// identical in 32-bit mode, but in 64-bit mode, they return true if the
395// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
396// clear).
397def imm16ShiftedZExt : PatLeaf<(imm), [{
398  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
399  // immediate are set.  Used by instructions like 'xoris'.
400  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
401}], HI16>;
402
403def imm16ShiftedSExt : PatLeaf<(imm), [{
404  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
405  // immediate are set.  Used by instructions like 'addis'.  Identical to
406  // imm16ShiftedZExt in 32-bit mode.
407  if (N->getZExtValue() & 0xFFFF) return false;
408  if (N->getValueType(0) == MVT::i32)
409    return true;
410  // For 64-bit, make sure it is sext right.
411  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
412}], HI16>;
413
414def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
415  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
416  // zero extended field.
417  return isUInt<32>(Imm);
418}]>;
419
420// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
421// restricted memrix (4-aligned) constants are alignment sensitive. If these
422// offsets are hidden behind TOC entries than the values of the lower-order
423// bits cannot be checked directly. As a result, we need to also incorporate
424// an alignment check into the relevant patterns.
425
426def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
427  return cast<LoadSDNode>(N)->getAlignment() >= 4;
428}]>;
429def aligned4store : PatFrag<(ops node:$val, node:$ptr),
430                            (store node:$val, node:$ptr), [{
431  return cast<StoreSDNode>(N)->getAlignment() >= 4;
432}]>;
433def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
434  return cast<LoadSDNode>(N)->getAlignment() >= 4;
435}]>;
436def aligned4pre_store : PatFrag<
437                          (ops node:$val, node:$base, node:$offset),
438                          (pre_store node:$val, node:$base, node:$offset), [{
439  return cast<StoreSDNode>(N)->getAlignment() >= 4;
440}]>;
441
442def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
443  return cast<LoadSDNode>(N)->getAlignment() < 4;
444}]>;
445def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
446                              (store node:$val, node:$ptr), [{
447  return cast<StoreSDNode>(N)->getAlignment() < 4;
448}]>;
449def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
450  return cast<LoadSDNode>(N)->getAlignment() < 4;
451}]>;
452
453// This is a somewhat weaker condition than actually checking for 16-byte
454// alignment. It is simply checking that the displacement can be represented
455// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form
456// instructions).
457def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
458  return isOffsetMultipleOf(N, 16);
459}]>;
460def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),
461                               (store node:$val, node:$ptr), [{
462  return isOffsetMultipleOf(N, 16);
463}]>;
464def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
465  return !isOffsetMultipleOf(N, 16);
466}]>;
467def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),
468                                  (store node:$val, node:$ptr), [{
469  return !isOffsetMultipleOf(N, 16);
470}]>;
471
472// PatFrag for binary operation whose operands are both non-constant
473class BinOpWithoutSImm16Operand<SDNode opcode> :
474  PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{
475    int16_t Imm;
476    return !isIntS16Immediate(N->getOperand(0), Imm)
477             && !isIntS16Immediate(N->getOperand(1), Imm);
478}]>;
479
480def add_without_simm16 : BinOpWithoutSImm16Operand<add>;
481def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>;
482
483//===----------------------------------------------------------------------===//
484// PowerPC Flag Definitions.
485
486class isPPC64 { bit PPC64 = 1; }
487class isDOT   { bit RC = 1; }
488
489class RegConstraint<string C> {
490  string Constraints = C;
491}
492class NoEncode<string E> {
493  string DisableEncoding = E;
494}
495
496
497//===----------------------------------------------------------------------===//
498// PowerPC Operand Definitions.
499
500// In the default PowerPC assembler syntax, registers are specified simply
501// by number, so they cannot be distinguished from immediate values (without
502// looking at the opcode).  This means that the default operand matching logic
503// for the asm parser does not work, and we need to specify custom matchers.
504// Since those can only be specified with RegisterOperand classes and not
505// directly on the RegisterClass, all instructions patterns used by the asm
506// parser need to use a RegisterOperand (instead of a RegisterClass) for
507// all their register operands.
508// For this purpose, we define one RegisterOperand for each RegisterClass,
509// using the same name as the class, just in lower case.
510
511def PPCRegGPRCAsmOperand : AsmOperandClass {
512  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
513}
514def gprc : RegisterOperand<GPRC> {
515  let ParserMatchClass = PPCRegGPRCAsmOperand;
516}
517def PPCRegG8RCAsmOperand : AsmOperandClass {
518  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
519}
520def g8rc : RegisterOperand<G8RC> {
521  let ParserMatchClass = PPCRegG8RCAsmOperand;
522}
523def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
524  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
525}
526def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
527  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
528}
529def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
530  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
531}
532def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
533  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
534}
535def PPCRegF8RCAsmOperand : AsmOperandClass {
536  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
537}
538def f8rc : RegisterOperand<F8RC> {
539  let ParserMatchClass = PPCRegF8RCAsmOperand;
540}
541def PPCRegF4RCAsmOperand : AsmOperandClass {
542  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
543}
544def f4rc : RegisterOperand<F4RC> {
545  let ParserMatchClass = PPCRegF4RCAsmOperand;
546}
547def PPCRegVRRCAsmOperand : AsmOperandClass {
548  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
549}
550def vrrc : RegisterOperand<VRRC> {
551  let ParserMatchClass = PPCRegVRRCAsmOperand;
552}
553def PPCRegVFRCAsmOperand : AsmOperandClass {
554  let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";
555}
556def vfrc : RegisterOperand<VFRC> {
557  let ParserMatchClass = PPCRegVFRCAsmOperand;
558}
559def PPCRegCRBITRCAsmOperand : AsmOperandClass {
560  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
561}
562def crbitrc : RegisterOperand<CRBITRC> {
563  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
564}
565def PPCRegCRRCAsmOperand : AsmOperandClass {
566  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
567}
568def crrc : RegisterOperand<CRRC> {
569  let ParserMatchClass = PPCRegCRRCAsmOperand;
570}
571def PPCRegSPERCAsmOperand : AsmOperandClass {
572  let Name = "RegSPERC"; let PredicateMethod = "isRegNumber";
573}
574def sperc : RegisterOperand<SPERC> {
575  let ParserMatchClass = PPCRegSPERCAsmOperand;
576}
577def PPCRegSPE4RCAsmOperand : AsmOperandClass {
578  let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber";
579}
580def spe4rc : RegisterOperand<SPE4RC> {
581  let ParserMatchClass = PPCRegSPE4RCAsmOperand;
582}
583
584def PPCU1ImmAsmOperand : AsmOperandClass {
585  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
586  let RenderMethod = "addImmOperands";
587}
588def u1imm   : Operand<i32> {
589  let PrintMethod = "printU1ImmOperand";
590  let ParserMatchClass = PPCU1ImmAsmOperand;
591}
592
593def PPCU2ImmAsmOperand : AsmOperandClass {
594  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
595  let RenderMethod = "addImmOperands";
596}
597def u2imm   : Operand<i32> {
598  let PrintMethod = "printU2ImmOperand";
599  let ParserMatchClass = PPCU2ImmAsmOperand;
600}
601
602def PPCATBitsAsHintAsmOperand : AsmOperandClass {
603  let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
604  let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
605}
606def atimm   : Operand<i32> {
607  let PrintMethod = "printATBitsAsHint";
608  let ParserMatchClass = PPCATBitsAsHintAsmOperand;
609}
610
611def PPCU3ImmAsmOperand : AsmOperandClass {
612  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
613  let RenderMethod = "addImmOperands";
614}
615def u3imm   : Operand<i32> {
616  let PrintMethod = "printU3ImmOperand";
617  let ParserMatchClass = PPCU3ImmAsmOperand;
618}
619
620def PPCU4ImmAsmOperand : AsmOperandClass {
621  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
622  let RenderMethod = "addImmOperands";
623}
624def u4imm   : Operand<i32> {
625  let PrintMethod = "printU4ImmOperand";
626  let ParserMatchClass = PPCU4ImmAsmOperand;
627}
628def PPCS5ImmAsmOperand : AsmOperandClass {
629  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
630  let RenderMethod = "addImmOperands";
631}
632def s5imm   : Operand<i32> {
633  let PrintMethod = "printS5ImmOperand";
634  let ParserMatchClass = PPCS5ImmAsmOperand;
635  let DecoderMethod = "decodeSImmOperand<5>";
636}
637def PPCU5ImmAsmOperand : AsmOperandClass {
638  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
639  let RenderMethod = "addImmOperands";
640}
641def u5imm   : Operand<i32> {
642  let PrintMethod = "printU5ImmOperand";
643  let ParserMatchClass = PPCU5ImmAsmOperand;
644  let DecoderMethod = "decodeUImmOperand<5>";
645}
646def PPCU6ImmAsmOperand : AsmOperandClass {
647  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
648  let RenderMethod = "addImmOperands";
649}
650def u6imm   : Operand<i32> {
651  let PrintMethod = "printU6ImmOperand";
652  let ParserMatchClass = PPCU6ImmAsmOperand;
653  let DecoderMethod = "decodeUImmOperand<6>";
654}
655def PPCU7ImmAsmOperand : AsmOperandClass {
656  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
657  let RenderMethod = "addImmOperands";
658}
659def u7imm   : Operand<i32> {
660  let PrintMethod = "printU7ImmOperand";
661  let ParserMatchClass = PPCU7ImmAsmOperand;
662  let DecoderMethod = "decodeUImmOperand<7>";
663}
664def PPCU8ImmAsmOperand : AsmOperandClass {
665  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
666  let RenderMethod = "addImmOperands";
667}
668def u8imm   : Operand<i32> {
669  let PrintMethod = "printU8ImmOperand";
670  let ParserMatchClass = PPCU8ImmAsmOperand;
671  let DecoderMethod = "decodeUImmOperand<8>";
672}
673def PPCU10ImmAsmOperand : AsmOperandClass {
674  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
675  let RenderMethod = "addImmOperands";
676}
677def u10imm  : Operand<i32> {
678  let PrintMethod = "printU10ImmOperand";
679  let ParserMatchClass = PPCU10ImmAsmOperand;
680  let DecoderMethod = "decodeUImmOperand<10>";
681}
682def PPCU12ImmAsmOperand : AsmOperandClass {
683  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
684  let RenderMethod = "addImmOperands";
685}
686def u12imm  : Operand<i32> {
687  let PrintMethod = "printU12ImmOperand";
688  let ParserMatchClass = PPCU12ImmAsmOperand;
689  let DecoderMethod = "decodeUImmOperand<12>";
690}
691def PPCS16ImmAsmOperand : AsmOperandClass {
692  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
693  let RenderMethod = "addS16ImmOperands";
694}
695def s16imm  : Operand<i32> {
696  let PrintMethod = "printS16ImmOperand";
697  let EncoderMethod = "getImm16Encoding";
698  let ParserMatchClass = PPCS16ImmAsmOperand;
699  let DecoderMethod = "decodeSImmOperand<16>";
700}
701def PPCU16ImmAsmOperand : AsmOperandClass {
702  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
703  let RenderMethod = "addU16ImmOperands";
704}
705def u16imm  : Operand<i32> {
706  let PrintMethod = "printU16ImmOperand";
707  let EncoderMethod = "getImm16Encoding";
708  let ParserMatchClass = PPCU16ImmAsmOperand;
709  let DecoderMethod = "decodeUImmOperand<16>";
710}
711def PPCS17ImmAsmOperand : AsmOperandClass {
712  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
713  let RenderMethod = "addS16ImmOperands";
714}
715def s17imm  : Operand<i32> {
716  // This operand type is used for addis/lis to allow the assembler parser
717  // to accept immediates in the range -65536..65535 for compatibility with
718  // the GNU assembler.  The operand is treated as 16-bit otherwise.
719  let PrintMethod = "printS16ImmOperand";
720  let EncoderMethod = "getImm16Encoding";
721  let ParserMatchClass = PPCS17ImmAsmOperand;
722  let DecoderMethod = "decodeSImmOperand<16>";
723}
724
725def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
726
727def PPCDirectBrAsmOperand : AsmOperandClass {
728  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
729  let RenderMethod = "addBranchTargetOperands";
730}
731def directbrtarget : Operand<OtherVT> {
732  let PrintMethod = "printBranchOperand";
733  let EncoderMethod = "getDirectBrEncoding";
734  let ParserMatchClass = PPCDirectBrAsmOperand;
735}
736def absdirectbrtarget : Operand<OtherVT> {
737  let PrintMethod = "printAbsBranchOperand";
738  let EncoderMethod = "getAbsDirectBrEncoding";
739  let ParserMatchClass = PPCDirectBrAsmOperand;
740}
741def PPCCondBrAsmOperand : AsmOperandClass {
742  let Name = "CondBr"; let PredicateMethod = "isCondBr";
743  let RenderMethod = "addBranchTargetOperands";
744}
745def condbrtarget : Operand<OtherVT> {
746  let PrintMethod = "printBranchOperand";
747  let EncoderMethod = "getCondBrEncoding";
748  let ParserMatchClass = PPCCondBrAsmOperand;
749}
750def abscondbrtarget : Operand<OtherVT> {
751  let PrintMethod = "printAbsBranchOperand";
752  let EncoderMethod = "getAbsCondBrEncoding";
753  let ParserMatchClass = PPCCondBrAsmOperand;
754}
755def calltarget : Operand<iPTR> {
756  let PrintMethod = "printBranchOperand";
757  let EncoderMethod = "getDirectBrEncoding";
758  let DecoderMethod = "DecodePCRel24BranchTarget";
759  let ParserMatchClass = PPCDirectBrAsmOperand;
760  let OperandType = "OPERAND_PCREL";
761}
762def abscalltarget : Operand<iPTR> {
763  let PrintMethod = "printAbsBranchOperand";
764  let EncoderMethod = "getAbsDirectBrEncoding";
765  let ParserMatchClass = PPCDirectBrAsmOperand;
766}
767def PPCCRBitMaskOperand : AsmOperandClass {
768 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
769}
770def crbitm: Operand<i8> {
771  let PrintMethod = "printcrbitm";
772  let EncoderMethod = "get_crbitm_encoding";
773  let DecoderMethod = "decodeCRBitMOperand";
774  let ParserMatchClass = PPCCRBitMaskOperand;
775}
776// Address operands
777// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
778def PPCRegGxRCNoR0Operand : AsmOperandClass {
779  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
780}
781def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
782  let ParserMatchClass = PPCRegGxRCNoR0Operand;
783}
784// A version of ptr_rc usable with the asm parser.
785def PPCRegGxRCOperand : AsmOperandClass {
786  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
787}
788def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
789  let ParserMatchClass = PPCRegGxRCOperand;
790}
791
792def PPCDispRIOperand : AsmOperandClass {
793 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
794 let RenderMethod = "addS16ImmOperands";
795}
796def dispRI : Operand<iPTR> {
797  let ParserMatchClass = PPCDispRIOperand;
798}
799def PPCDispRIXOperand : AsmOperandClass {
800 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
801 let RenderMethod = "addImmOperands";
802}
803def dispRIX : Operand<iPTR> {
804  let ParserMatchClass = PPCDispRIXOperand;
805}
806def PPCDispRIX16Operand : AsmOperandClass {
807 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
808 let RenderMethod = "addImmOperands";
809}
810def dispRIX16 : Operand<iPTR> {
811  let ParserMatchClass = PPCDispRIX16Operand;
812}
813def PPCDispSPE8Operand : AsmOperandClass {
814 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
815 let RenderMethod = "addImmOperands";
816}
817def dispSPE8 : Operand<iPTR> {
818  let ParserMatchClass = PPCDispSPE8Operand;
819}
820def PPCDispSPE4Operand : AsmOperandClass {
821 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
822 let RenderMethod = "addImmOperands";
823}
824def dispSPE4 : Operand<iPTR> {
825  let ParserMatchClass = PPCDispSPE4Operand;
826}
827def PPCDispSPE2Operand : AsmOperandClass {
828 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
829 let RenderMethod = "addImmOperands";
830}
831def dispSPE2 : Operand<iPTR> {
832  let ParserMatchClass = PPCDispSPE2Operand;
833}
834
835def memri : Operand<iPTR> {
836  let PrintMethod = "printMemRegImm";
837  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
838  let EncoderMethod = "getMemRIEncoding";
839  let DecoderMethod = "decodeMemRIOperands";
840}
841def memrr : Operand<iPTR> {
842  let PrintMethod = "printMemRegReg";
843  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
844}
845def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
846  let PrintMethod = "printMemRegImm";
847  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
848  let EncoderMethod = "getMemRIXEncoding";
849  let DecoderMethod = "decodeMemRIXOperands";
850}
851def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
852  let PrintMethod = "printMemRegImm";
853  let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
854  let EncoderMethod = "getMemRIX16Encoding";
855  let DecoderMethod = "decodeMemRIX16Operands";
856}
857def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
858  let PrintMethod = "printMemRegImm";
859  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
860  let EncoderMethod = "getSPE8DisEncoding";
861  let DecoderMethod = "decodeSPE8Operands";
862}
863def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
864  let PrintMethod = "printMemRegImm";
865  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
866  let EncoderMethod = "getSPE4DisEncoding";
867  let DecoderMethod = "decodeSPE4Operands";
868}
869def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
870  let PrintMethod = "printMemRegImm";
871  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
872  let EncoderMethod = "getSPE2DisEncoding";
873  let DecoderMethod = "decodeSPE2Operands";
874}
875
876// A single-register address. This is used with the SjLj
877// pseudo-instructions which tranlates to LD/LWZ.  These instructions requires
878// G8RC_NOX0 registers.
879def memr : Operand<iPTR> {
880  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
881}
882def PPCTLSRegOperand : AsmOperandClass {
883  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
884  let RenderMethod = "addTLSRegOperands";
885}
886def tlsreg32 : Operand<i32> {
887  let EncoderMethod = "getTLSRegEncoding";
888  let ParserMatchClass = PPCTLSRegOperand;
889}
890def tlsgd32 : Operand<i32> {}
891def tlscall32 : Operand<i32> {
892  let PrintMethod = "printTLSCall";
893  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
894  let EncoderMethod = "getTLSCallEncoding";
895}
896
897// PowerPC Predicate operand.
898def pred : Operand<OtherVT> {
899  let PrintMethod = "printPredicateOperand";
900  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
901}
902
903// Define PowerPC specific addressing mode.
904
905// d-form
906def iaddr    : ComplexPattern<iPTR, 2, "SelectAddrImm",     [], []>;  // "stb"
907// ds-form
908def iaddrX4  : ComplexPattern<iPTR, 2, "SelectAddrImmX4",   [], []>;  // "std"
909// dq-form
910def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16",  [], []>;  // "stxv"
911
912// Below forms are all x-form addressing mode, use three different ones so we
913// can make a accurate check for x-form instructions in ISEL.
914// x-form addressing mode whose associated diplacement form is D.
915def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",     [], []>;    // "stbx"
916// x-form addressing mode whose associated diplacement form is DS.
917def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4",    [], []>;  // "stdx"
918// x-form addressing mode whose associated diplacement form is DQ.
919def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16",   [], []>; // "stxvx"
920
921def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
922
923// The address in a single register. This is used with the SjLj
924// pseudo-instructions.
925def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
926
927/// This is just the offset part of iaddr, used for preinc.
928def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
929
930//===----------------------------------------------------------------------===//
931// PowerPC Instruction Predicate Definitions.
932def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
933def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
934def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
935def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
936def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
937def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
938def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
939def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
940def IsE500  : Predicate<"PPCSubTarget->isE500()">;
941def HasSPE  : Predicate<"PPCSubTarget->hasSPE()">;
942def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
943def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
944def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
945def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
946def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
947def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
948def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
949def HasFPU : Predicate<"PPCSubTarget->hasFPU()">;
950
951//===----------------------------------------------------------------------===//
952// PowerPC Multiclass Definitions.
953
954multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
955                    string asmbase, string asmstr, InstrItinClass itin,
956                    list<dag> pattern> {
957  let BaseName = asmbase in {
958    def NAME : XForm_6<opcode, xo, OOL, IOL,
959                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
960                       pattern>, RecFormRel;
961    let Defs = [CR0] in
962    def o    : XForm_6<opcode, xo, OOL, IOL,
963                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
964                       []>, isDOT, RecFormRel;
965  }
966}
967
968multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
969                     string asmbase, string asmstr, InstrItinClass itin,
970                     list<dag> pattern> {
971  let BaseName = asmbase in {
972    let Defs = [CARRY] in
973    def NAME : XForm_6<opcode, xo, OOL, IOL,
974                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
975                       pattern>, RecFormRel;
976    let Defs = [CARRY, CR0] in
977    def o    : XForm_6<opcode, xo, OOL, IOL,
978                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
979                       []>, isDOT, RecFormRel;
980  }
981}
982
983multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
984                      string asmbase, string asmstr, InstrItinClass itin,
985                      list<dag> pattern> {
986  let BaseName = asmbase in {
987    let Defs = [CARRY] in
988    def NAME : XForm_10<opcode, xo, OOL, IOL,
989                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
990                       pattern>, RecFormRel;
991    let Defs = [CARRY, CR0] in
992    def o    : XForm_10<opcode, xo, OOL, IOL,
993                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
994                       []>, isDOT, RecFormRel;
995  }
996}
997
998multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
999                    string asmbase, string asmstr, InstrItinClass itin,
1000                    list<dag> pattern> {
1001  let BaseName = asmbase in {
1002    def NAME : XForm_11<opcode, xo, OOL, IOL,
1003                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1004                       pattern>, RecFormRel;
1005    let Defs = [CR0] in
1006    def o    : XForm_11<opcode, xo, OOL, IOL,
1007                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1008                       []>, isDOT, RecFormRel;
1009  }
1010}
1011
1012multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1013                    string asmbase, string asmstr, InstrItinClass itin,
1014                    list<dag> pattern> {
1015  let BaseName = asmbase in {
1016    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
1017                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1018                       pattern>, RecFormRel;
1019    let Defs = [CR0] in
1020    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
1021                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1022                       []>, isDOT, RecFormRel;
1023  }
1024}
1025
1026// Multiclass for instructions which have a record overflow form as well
1027// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.)
1028multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1029                      string asmbase, string asmstr, InstrItinClass itin,
1030                      list<dag> pattern> {
1031  let BaseName = asmbase in {
1032    def NAME : XOForm_1<opcode, xo, 0, OOL, IOL,
1033                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1034                        pattern>, RecFormRel;
1035    let Defs = [CR0] in
1036    def o    : XOForm_1<opcode, xo, 0, OOL, IOL,
1037                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1038                        []>, isDOT, RecFormRel;
1039  }
1040  let BaseName = !strconcat(asmbase, "O") in {
1041    let Defs = [XER] in
1042    def O    : XOForm_1<opcode, xo, 1, OOL, IOL,
1043                        !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1044                        []>, RecFormRel;
1045    let Defs = [XER, CR0] in
1046    def Oo    : XOForm_1<opcode, xo, 1, OOL, IOL,
1047                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1048                         []>, isDOT, RecFormRel;
1049  }
1050}
1051
1052// Multiclass for instructions for which the non record form is not cracked
1053// and the record form is cracked (i.e. divw, mullw, etc.)
1054multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1055                      string asmbase, string asmstr, InstrItinClass itin,
1056                      list<dag> pattern> {
1057  let BaseName = asmbase in {
1058    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
1059                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1060                       pattern>, RecFormRel;
1061    let Defs = [CR0] in
1062    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
1063                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1064                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
1065                       PPC970_DGroup_Cracked;
1066  }
1067  let BaseName = !strconcat(asmbase, "O") in {
1068    let Defs = [XER] in
1069    def O    : XOForm_1<opcode, xo, 1, OOL, IOL,
1070                        !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1071                        []>, RecFormRel;
1072    let Defs = [XER, CR0] in
1073    def Oo   : XOForm_1<opcode, xo, 1, OOL, IOL,
1074                        !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1075                        []>, isDOT, RecFormRel;
1076  }
1077}
1078
1079multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1080                      string asmbase, string asmstr, InstrItinClass itin,
1081                      list<dag> pattern> {
1082  let BaseName = asmbase in {
1083    let Defs = [CARRY] in
1084    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
1085                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1086                       pattern>, RecFormRel;
1087    let Defs = [CARRY, CR0] in
1088    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
1089                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1090                       []>, isDOT, RecFormRel;
1091  }
1092  let BaseName = !strconcat(asmbase, "O") in {
1093    let Defs = [CARRY, XER] in
1094    def O    : XOForm_1<opcode, xo, 1, OOL, IOL,
1095                        !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1096                        []>, RecFormRel;
1097    let Defs = [CARRY, XER, CR0] in
1098    def Oo   : XOForm_1<opcode, xo, 1, OOL, IOL,
1099                        !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1100                        []>, isDOT, RecFormRel;
1101  }
1102}
1103
1104multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1105                    string asmbase, string asmstr, InstrItinClass itin,
1106                    list<dag> pattern> {
1107  let BaseName = asmbase in {
1108    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
1109                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1110                       pattern>, RecFormRel;
1111    let Defs = [CR0] in
1112    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
1113                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1114                       []>, isDOT, RecFormRel;
1115  }
1116  let BaseName = !strconcat(asmbase, "O") in {
1117    let Defs = [XER] in
1118    def O    : XOForm_3<opcode, xo, 1, OOL, IOL,
1119                        !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1120                        []>, RecFormRel;
1121    let Defs = [XER, CR0] in
1122    def Oo   : XOForm_3<opcode, xo, 1, OOL, IOL,
1123                        !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1124                        []>, isDOT, RecFormRel;
1125  }
1126}
1127
1128multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
1129                      string asmbase, string asmstr, InstrItinClass itin,
1130                      list<dag> pattern> {
1131  let BaseName = asmbase in {
1132    let Defs = [CARRY] in
1133    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
1134                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1135                       pattern>, RecFormRel;
1136    let Defs = [CARRY, CR0] in
1137    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
1138                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1139                       []>, isDOT, RecFormRel;
1140  }
1141  let BaseName = !strconcat(asmbase, "O") in {
1142    let Defs = [CARRY, XER] in
1143    def O    : XOForm_3<opcode, xo, 1, OOL, IOL,
1144                        !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
1145                        []>, RecFormRel;
1146    let Defs = [CARRY, XER, CR0] in
1147    def Oo   : XOForm_3<opcode, xo, 1, OOL, IOL,
1148                        !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
1149                        []>, isDOT, RecFormRel;
1150  }
1151}
1152
1153multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
1154                    string asmbase, string asmstr, InstrItinClass itin,
1155                    list<dag> pattern> {
1156  let BaseName = asmbase in {
1157    def NAME : MForm_2<opcode, OOL, IOL,
1158                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1159                       pattern>, RecFormRel;
1160    let Defs = [CR0] in
1161    def o    : MForm_2<opcode, OOL, IOL,
1162                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1163                       []>, isDOT, RecFormRel;
1164  }
1165}
1166
1167multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
1168                    string asmbase, string asmstr, InstrItinClass itin,
1169                    list<dag> pattern> {
1170  let BaseName = asmbase in {
1171    def NAME : MDForm_1<opcode, xo, OOL, IOL,
1172                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1173                       pattern>, RecFormRel;
1174    let Defs = [CR0] in
1175    def o    : MDForm_1<opcode, xo, OOL, IOL,
1176                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1177                       []>, isDOT, RecFormRel;
1178  }
1179}
1180
1181multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
1182                     string asmbase, string asmstr, InstrItinClass itin,
1183                     list<dag> pattern> {
1184  let BaseName = asmbase in {
1185    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
1186                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1187                        pattern>, RecFormRel;
1188    let Defs = [CR0] in
1189    def o    : MDSForm_1<opcode, xo, OOL, IOL,
1190                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1191                        []>, isDOT, RecFormRel;
1192  }
1193}
1194
1195multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1196                      string asmbase, string asmstr, InstrItinClass itin,
1197                      list<dag> pattern> {
1198  let BaseName = asmbase in {
1199    let Defs = [CARRY] in
1200    def NAME : XSForm_1<opcode, xo, OOL, IOL,
1201                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1202                       pattern>, RecFormRel;
1203    let Defs = [CARRY, CR0] in
1204    def o    : XSForm_1<opcode, xo, OOL, IOL,
1205                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1206                       []>, isDOT, RecFormRel;
1207  }
1208}
1209
1210multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1211                    string asmbase, string asmstr, InstrItinClass itin,
1212                    list<dag> pattern> {
1213  let BaseName = asmbase in {
1214    def NAME : XSForm_1<opcode, xo, OOL, IOL,
1215                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1216                       pattern>, RecFormRel;
1217    let Defs = [CR0] in
1218    def o    : XSForm_1<opcode, xo, OOL, IOL,
1219                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1220                       []>, isDOT, RecFormRel;
1221  }
1222}
1223
1224multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1225                    string asmbase, string asmstr, InstrItinClass itin,
1226                    list<dag> pattern> {
1227  let BaseName = asmbase in {
1228    def NAME : XForm_26<opcode, xo, OOL, IOL,
1229                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1230                       pattern>, RecFormRel;
1231    let Defs = [CR1] in
1232    def o    : XForm_26<opcode, xo, OOL, IOL,
1233                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1234                       []>, isDOT, RecFormRel;
1235  }
1236}
1237
1238multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1239                    string asmbase, string asmstr, InstrItinClass itin,
1240                    list<dag> pattern> {
1241  let BaseName = asmbase in {
1242    def NAME : XForm_28<opcode, xo, OOL, IOL,
1243                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1244                       pattern>, RecFormRel;
1245    let Defs = [CR1] in
1246    def o    : XForm_28<opcode, xo, OOL, IOL,
1247                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1248                       []>, isDOT, RecFormRel;
1249  }
1250}
1251
1252multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1253                    string asmbase, string asmstr, InstrItinClass itin,
1254                    list<dag> pattern> {
1255  let BaseName = asmbase in {
1256    def NAME : AForm_1<opcode, xo, OOL, IOL,
1257                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1258                       pattern>, RecFormRel;
1259    let Defs = [CR1] in
1260    def o    : AForm_1<opcode, xo, OOL, IOL,
1261                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1262                       []>, isDOT, RecFormRel;
1263  }
1264}
1265
1266multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1267                    string asmbase, string asmstr, InstrItinClass itin,
1268                    list<dag> pattern> {
1269  let BaseName = asmbase in {
1270    def NAME : AForm_2<opcode, xo, OOL, IOL,
1271                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1272                       pattern>, RecFormRel;
1273    let Defs = [CR1] in
1274    def o    : AForm_2<opcode, xo, OOL, IOL,
1275                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1276                       []>, isDOT, RecFormRel;
1277  }
1278}
1279
1280multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1281                    string asmbase, string asmstr, InstrItinClass itin,
1282                    list<dag> pattern> {
1283  let BaseName = asmbase in {
1284    def NAME : AForm_3<opcode, xo, OOL, IOL,
1285                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1286                       pattern>, RecFormRel;
1287    let Defs = [CR1] in
1288    def o    : AForm_3<opcode, xo, OOL, IOL,
1289                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1290                       []>, isDOT, RecFormRel;
1291  }
1292}
1293
1294//===----------------------------------------------------------------------===//
1295// PowerPC Instruction Definitions.
1296
1297// Pseudo instructions:
1298
1299let hasCtrlDep = 1 in {
1300let Defs = [R1], Uses = [R1] in {
1301def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1302                              "#ADJCALLSTACKDOWN $amt1 $amt2",
1303                              [(callseq_start timm:$amt1, timm:$amt2)]>;
1304def ADJCALLSTACKUP   : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1305                              "#ADJCALLSTACKUP $amt1 $amt2",
1306                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1307}
1308
1309def UPDATE_VRSAVE    : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$rS),
1310                              "UPDATE_VRSAVE $rD, $rS", []>;
1311}
1312
1313let Defs = [R1], Uses = [R1] in
1314def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1315                       [(set i32:$result,
1316                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1317def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1318                       [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1319
1320// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1321// instruction selection into a branch sequence.
1322let PPC970_Single = 1 in {
1323  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1324  // because either operand might become the first operand in an isel, and
1325  // that operand cannot be r0.
1326  def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond,
1327                              gprc_nor0:$T, gprc_nor0:$F,
1328                              i32imm:$BROPC), "#SELECT_CC_I4",
1329                              []>;
1330  def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond,
1331                              g8rc_nox0:$T, g8rc_nox0:$F,
1332                              i32imm:$BROPC), "#SELECT_CC_I8",
1333                              []>;
1334  def SELECT_CC_F4  : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1335                              i32imm:$BROPC), "#SELECT_CC_F4",
1336                              []>;
1337  def SELECT_CC_F8  : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1338                              i32imm:$BROPC), "#SELECT_CC_F8",
1339                              []>;
1340  def SELECT_CC_F16  : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1341                              i32imm:$BROPC), "#SELECT_CC_F16",
1342                              []>;
1343  def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1344                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1345                              []>;
1346
1347  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1348  // register bit directly.
1349  def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1350                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1351                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1352  def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1353                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1354                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1355let Predicates = [HasFPU] in {
1356  def SELECT_F4  : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1357                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1358                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1359  def SELECT_F8  : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1360                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1361                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1362  def SELECT_F16  : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1363                          vrrc:$T, vrrc:$F), "#SELECT_F16",
1364                          [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;
1365}
1366  def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1367                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1368                          [(set v4i32:$dst,
1369                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1370}
1371
1372// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1373// scavenge a register for it.
1374let mayStore = 1 in {
1375def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F),
1376                     "#SPILL_CR", []>;
1377def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F),
1378                         "#SPILL_CRBIT", []>;
1379}
1380
1381// RESTORE_CR - Indicate that we're restoring the CR register (previously
1382// spilled), so we'll need to scavenge a register for it.
1383let mayLoad = 1 in {
1384def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F),
1385                     "#RESTORE_CR", []>;
1386def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),
1387                           "#RESTORE_CRBIT", []>;
1388}
1389
1390let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1391  let isReturn = 1, Uses = [LR, RM] in
1392    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1393                           [(retflag)]>, Requires<[In32BitMode]>;
1394  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1395    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1396                            []>;
1397
1398    let isCodeGenOnly = 1 in {
1399      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1400                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1401                               []>;
1402
1403      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1404                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1405      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1406                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1407    }
1408  }
1409}
1410
1411// Set the float rounding mode.
1412let Uses = [RM], Defs = [RM] in {
1413def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),
1414                    "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>;
1415
1416def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in),
1417                    "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>;
1418}
1419
1420let Defs = [LR] in
1421  def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
1422                   PPC970_Unit_BRU;
1423let Defs = [LR] in
1424  def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1425                    PPC970_Unit_BRU;
1426
1427let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1428  let isBarrier = 1 in {
1429  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1430                  "b $dst", IIC_BrB,
1431                  [(br bb:$dst)]>;
1432  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1433                  "ba $dst", IIC_BrB, []>;
1434  }
1435
1436  // BCC represents an arbitrary conditional branch on a predicate.
1437  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1438  // a two-value operand where a dag node expects two operands. :(
1439  let isCodeGenOnly = 1 in {
1440    class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1441                            "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1442                            /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1443    def BCC : BCC_class;
1444
1445    // The same as BCC, except that it's not a terminator. Used for introducing
1446    // control flow dependency without creating new blocks.
1447    let isTerminator = 0 in def CTRL_DEP : BCC_class;
1448
1449    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1450                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1451
1452    let isReturn = 1, Uses = [LR, RM] in
1453    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1454                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1455  }
1456
1457  let isCodeGenOnly = 1 in {
1458    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1459    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1460             "bc 12, $bi, $dst">;
1461
1462    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1463    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1464             "bc 4, $bi, $dst">;
1465
1466    let isReturn = 1, Uses = [LR, RM] in
1467    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1468                             "bclr 12, $bi, 0", IIC_BrB, []>;
1469    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1470                             "bclr 4, $bi, 0", IIC_BrB, []>;
1471  }
1472
1473  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1474   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1475                             "bdzlr", IIC_BrB, []>;
1476   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1477                             "bdnzlr", IIC_BrB, []>;
1478   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1479                             "bdzlr+", IIC_BrB, []>;
1480   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1481                             "bdnzlr+", IIC_BrB, []>;
1482   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1483                             "bdzlr-", IIC_BrB, []>;
1484   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1485                             "bdnzlr-", IIC_BrB, []>;
1486  }
1487
1488  let Defs = [CTR], Uses = [CTR] in {
1489    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1490                       "bdz $dst">;
1491    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1492                       "bdnz $dst">;
1493    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1494                        "bdza $dst">;
1495    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1496                        "bdnza $dst">;
1497    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1498                       "bdz+ $dst">;
1499    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1500                       "bdnz+ $dst">;
1501    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1502                        "bdza+ $dst">;
1503    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1504                        "bdnza+ $dst">;
1505    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1506                       "bdz- $dst">;
1507    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1508                       "bdnz- $dst">;
1509    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1510                        "bdza- $dst">;
1511    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1512                        "bdnza- $dst">;
1513  }
1514}
1515
1516// The unconditional BCL used by the SjLj setjmp code.
1517let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1518  let Defs = [LR], Uses = [RM] in {
1519    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1520                            "bcl 20, 31, $dst">;
1521  }
1522}
1523
1524let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1525  // Convenient aliases for call instructions
1526  let Uses = [RM] in {
1527    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1528                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1529    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1530                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1531
1532    let isCodeGenOnly = 1 in {
1533      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1534                          "bl $func", IIC_BrB, []>;
1535      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1536                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1537      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1538                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1539
1540      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1541                         (ins crbitrc:$bi, condbrtarget:$dst),
1542                         "bcl 12, $bi, $dst">;
1543      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1544                         (ins crbitrc:$bi, condbrtarget:$dst),
1545                         "bcl 4, $bi, $dst">;
1546      def BL_NOP  : IForm_and_DForm_4_zero<18, 0, 1, 24,
1547                                           (outs), (ins calltarget:$func),
1548                                           "bl $func\n\tnop", IIC_BrB, []>;
1549    }
1550  }
1551  let Uses = [CTR, RM] in {
1552    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1553                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1554                Requires<[In32BitMode]>;
1555
1556    let isCodeGenOnly = 1 in {
1557      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1558                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1559                                []>;
1560
1561      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1562                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1563      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1564                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1565    }
1566  }
1567  let Uses = [LR, RM] in {
1568    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1569                            "blrl", IIC_BrB, []>;
1570
1571    let isCodeGenOnly = 1 in {
1572      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1573                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1574                              []>;
1575
1576      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1577                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1578      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1579                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1580    }
1581  }
1582  let Defs = [CTR], Uses = [CTR, RM] in {
1583    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1584                        "bdzl $dst">;
1585    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1586                        "bdnzl $dst">;
1587    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1588                         "bdzla $dst">;
1589    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1590                         "bdnzla $dst">;
1591    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1592                        "bdzl+ $dst">;
1593    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1594                        "bdnzl+ $dst">;
1595    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1596                         "bdzla+ $dst">;
1597    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1598                         "bdnzla+ $dst">;
1599    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1600                        "bdzl- $dst">;
1601    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1602                        "bdnzl- $dst">;
1603    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1604                         "bdzla- $dst">;
1605    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1606                         "bdnzla- $dst">;
1607  }
1608  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1609    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1610                               "bdzlrl", IIC_BrB, []>;
1611    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1612                               "bdnzlrl", IIC_BrB, []>;
1613    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1614                               "bdzlrl+", IIC_BrB, []>;
1615    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1616                               "bdnzlrl+", IIC_BrB, []>;
1617    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1618                               "bdzlrl-", IIC_BrB, []>;
1619    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1620                               "bdnzlrl-", IIC_BrB, []>;
1621  }
1622}
1623
1624let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1625def TCRETURNdi :PPCEmitTimePseudo< (outs),
1626                        (ins calltarget:$dst, i32imm:$offset),
1627                 "#TC_RETURNd $dst $offset",
1628                 []>;
1629
1630
1631let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1632def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1633                 "#TC_RETURNa $func $offset",
1634                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1635
1636let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1637def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1638                 "#TC_RETURNr $dst $offset",
1639                 []>;
1640
1641
1642let isCodeGenOnly = 1 in {
1643
1644let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1645    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1646def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1647                            []>, Requires<[In32BitMode]>;
1648
1649let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1650    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1651def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1652                  "b $dst", IIC_BrB,
1653                  []>;
1654
1655let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1656    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1657def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1658                  "ba $dst", IIC_BrB,
1659                  []>;
1660
1661}
1662
1663// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp
1664// is not.
1665let hasSideEffects = 1 in {
1666  let Defs = [CTR] in
1667  def EH_SjLj_SetJmp32  : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
1668                            "#EH_SJLJ_SETJMP32",
1669                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1670                          Requires<[In32BitMode]>;
1671}
1672
1673let hasSideEffects = 1, isBarrier = 1 in {
1674  let isTerminator = 1 in
1675  def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
1676                            "#EH_SJLJ_LONGJMP32",
1677                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1678                          Requires<[In32BitMode]>;
1679}
1680
1681// This pseudo is never removed from the function, as it serves as
1682// a terminator.  Size is set to 0 to prevent the builtin assembler
1683// from emitting it.
1684let isBranch = 1, isTerminator = 1, Size = 0 in {
1685  def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst),
1686                        "#EH_SjLj_Setup\t$dst", []>;
1687}
1688
1689// System call.
1690let PPC970_Unit = 7 in {
1691  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1692                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1693}
1694
1695// Branch history rolling buffer.
1696def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1697                      [(PPCclrbhrb)]>,
1698                      PPC970_DGroup_Single;
1699// The $dmy argument used for MFBHRBE is not needed; however, including
1700// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1701// interferes with necessary special handling (see PPCFastISel.cpp).
1702def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1703                         (ins u10imm:$imm, u10imm:$dmy),
1704                         "mfbhrbe $rD, $imm", IIC_BrB,
1705                         [(set i32:$rD,
1706                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1707                         PPC970_DGroup_First;
1708
1709def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1710                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1711                     PPC970_DGroup_Single;
1712
1713// DCB* instructions.
1714def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1715                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1716                      PPC970_DGroup_Single;
1717def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1718                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1719                      PPC970_DGroup_Single;
1720def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1721                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1722                      PPC970_DGroup_Single;
1723def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1724                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1725                      PPC970_DGroup_Single;
1726def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1727                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1728                      PPC970_DGroup_Single;
1729
1730def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
1731                      "dcbf $dst, $TH", IIC_LdStDCBF, []>,
1732                      PPC970_DGroup_Single;
1733
1734let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1735def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1736                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1737                      PPC970_DGroup_Single;
1738def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1739                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1740                      PPC970_DGroup_Single;
1741} // hasSideEffects = 0
1742
1743def ICBLC  : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
1744                       "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
1745def ICBLQ  : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
1746                       "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1747def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1748                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1749def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
1750                       "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1751
1752def : Pat<(int_ppc_dcbt xoaddr:$dst),
1753          (DCBT 0, xoaddr:$dst)>;
1754def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1755          (DCBTST 0, xoaddr:$dst)>;
1756def : Pat<(int_ppc_dcbf xoaddr:$dst),
1757          (DCBF 0, xoaddr:$dst)>;
1758
1759def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1760          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1761def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1762          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1763def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1764          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1765
1766// Atomic operations
1767// FIXME: some of these might be used with constant operands. This will result
1768// in constant materialization instructions that may be redundant. We currently
1769// clean this up in PPCMIPeephole with calls to
1770// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
1771// in the first place.
1772let Defs = [CR0] in {
1773  def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo<
1774    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1775    [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1776  def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo<
1777    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1778    [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1779  def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo<
1780    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1781    [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1782  def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo<
1783    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1784    [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1785  def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo<
1786    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1787    [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1788  def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo<
1789    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1790    [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1791  def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo<
1792    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
1793    [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
1794  def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo<
1795    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
1796    [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
1797  def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo<
1798    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
1799    [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
1800  def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo<
1801    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
1802    [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
1803  def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo<
1804    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1805    [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1806  def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo<
1807    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1808    [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1809  def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo<
1810    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1811    [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1812  def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo<
1813    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1814    [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1815  def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo<
1816    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1817    [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1818  def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo<
1819    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1820    [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1821  def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo<
1822    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
1823    [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
1824  def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo<
1825    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
1826    [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
1827  def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo<
1828    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
1829    [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
1830  def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo<
1831    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
1832    [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
1833  def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo<
1834    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1835    [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1836  def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo<
1837    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1838    [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1839  def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo<
1840    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1841    [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1842  def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo<
1843    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1844    [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1845  def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo<
1846    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1847    [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1848  def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo<
1849    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1850    [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1851  def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo<
1852    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
1853    [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
1854  def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo<
1855    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
1856    [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
1857  def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo<
1858    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
1859    [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
1860  def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo<
1861    (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
1862    [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
1863
1864  def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo<
1865    (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1866    [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1867  def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo<
1868    (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1869    [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1870  def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo<
1871    (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1872    [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1873
1874  def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo<
1875    (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1876    [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1877  def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo<
1878    (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1879    [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1880  def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo<
1881    (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1882    [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1883}
1884
1885def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new),
1886        (ATOMIC_CMP_SWAP_I8 xoaddr:$ptr, i32:$old, i32:$new)>;
1887def : Pat<(PPCatomicCmpSwap_16 xoaddr:$ptr, i32:$old, i32:$new),
1888        (ATOMIC_CMP_SWAP_I16 xoaddr:$ptr, i32:$old, i32:$new)>;
1889
1890// Instructions to support atomic operations
1891let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
1892def LBARX : XForm_1_memOp<31,  52, (outs gprc:$rD), (ins memrr:$src),
1893                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1894                    Requires<[HasPartwordAtomics]>;
1895
1896def LHARX : XForm_1_memOp<31,  116, (outs gprc:$rD), (ins memrr:$src),
1897                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1898                    Requires<[HasPartwordAtomics]>;
1899
1900def LWARX : XForm_1_memOp<31,  20, (outs gprc:$rD), (ins memrr:$src),
1901                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1902
1903// Instructions to support lock versions of atomics
1904// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1905def LBARXL : XForm_1_memOp<31,  52, (outs gprc:$rD), (ins memrr:$src),
1906                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1907                     Requires<[HasPartwordAtomics]>;
1908
1909def LHARXL : XForm_1_memOp<31,  116, (outs gprc:$rD), (ins memrr:$src),
1910                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1911                     Requires<[HasPartwordAtomics]>;
1912
1913def LWARXL : XForm_1_memOp<31,  20, (outs gprc:$rD), (ins memrr:$src),
1914                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1915
1916// The atomic instructions use the destination register as well as the next one
1917// or two registers in order (modulo 31).
1918let hasExtraSrcRegAllocReq = 1 in
1919def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1920                         "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1921           Requires<[IsISA3_0]>;
1922}
1923
1924let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
1925def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1926                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1927                    isDOT, Requires<[HasPartwordAtomics]>;
1928
1929def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1930                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1931                    isDOT, Requires<[HasPartwordAtomics]>;
1932
1933def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1934                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1935}
1936
1937let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
1938def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1939                          "stwat $rS, $rA, $FC", IIC_LdStStore>,
1940            Requires<[IsISA3_0]>;
1941
1942let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1943def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1944
1945def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1946                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1947def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1948                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1949def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1950                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1951def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1952                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1953
1954//===----------------------------------------------------------------------===//
1955// PPC32 Load Instructions.
1956//
1957
1958// Unindexed (r+i) Loads.
1959let PPC970_Unit = 2 in {
1960def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1961                  "lbz $rD, $src", IIC_LdStLoad,
1962                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1963def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1964                  "lha $rD, $src", IIC_LdStLHA,
1965                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1966                  PPC970_DGroup_Cracked;
1967def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1968                  "lhz $rD, $src", IIC_LdStLoad,
1969                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1970def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1971                  "lwz $rD, $src", IIC_LdStLoad,
1972                  [(set i32:$rD, (load iaddr:$src))]>;
1973
1974let Predicates = [HasFPU] in {
1975def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1976                  "lfs $rD, $src", IIC_LdStLFD,
1977                  [(set f32:$rD, (load iaddr:$src))]>;
1978def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1979                  "lfd $rD, $src", IIC_LdStLFD,
1980                  [(set f64:$rD, (load iaddr:$src))]>;
1981}
1982
1983
1984// Unindexed (r+i) Loads with Update (preinc).
1985let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
1986def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1987                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1988                   []>, RegConstraint<"$addr.reg = $ea_result">,
1989                   NoEncode<"$ea_result">;
1990
1991def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1992                   "lhau $rD, $addr", IIC_LdStLHAU,
1993                   []>, RegConstraint<"$addr.reg = $ea_result">,
1994                   NoEncode<"$ea_result">;
1995
1996def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1997                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1998                   []>, RegConstraint<"$addr.reg = $ea_result">,
1999                   NoEncode<"$ea_result">;
2000
2001def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
2002                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
2003                   []>, RegConstraint<"$addr.reg = $ea_result">,
2004                   NoEncode<"$ea_result">;
2005
2006let Predicates = [HasFPU] in {
2007def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
2008                  "lfsu $rD, $addr", IIC_LdStLFDU,
2009                  []>, RegConstraint<"$addr.reg = $ea_result">,
2010                   NoEncode<"$ea_result">;
2011
2012def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
2013                  "lfdu $rD, $addr", IIC_LdStLFDU,
2014                  []>, RegConstraint<"$addr.reg = $ea_result">,
2015                   NoEncode<"$ea_result">;
2016}
2017
2018
2019// Indexed (r+r) Loads with Update (preinc).
2020def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
2021                   (ins memrr:$addr),
2022                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
2023                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
2024                   NoEncode<"$ea_result">;
2025
2026def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
2027                   (ins memrr:$addr),
2028                   "lhaux $rD, $addr", IIC_LdStLHAUX,
2029                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
2030                   NoEncode<"$ea_result">;
2031
2032def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
2033                   (ins memrr:$addr),
2034                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
2035                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
2036                   NoEncode<"$ea_result">;
2037
2038def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
2039                   (ins memrr:$addr),
2040                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
2041                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
2042                   NoEncode<"$ea_result">;
2043
2044let Predicates = [HasFPU] in {
2045def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
2046                   (ins memrr:$addr),
2047                   "lfsux $rD, $addr", IIC_LdStLFDUX,
2048                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
2049                   NoEncode<"$ea_result">;
2050
2051def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
2052                   (ins memrr:$addr),
2053                   "lfdux $rD, $addr", IIC_LdStLFDUX,
2054                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
2055                   NoEncode<"$ea_result">;
2056}
2057}
2058}
2059
2060// Indexed (r+r) Loads.
2061//
2062let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
2063def LBZX : XForm_1_memOp<31,  87, (outs gprc:$rD), (ins memrr:$src),
2064                   "lbzx $rD, $src", IIC_LdStLoad,
2065                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
2066def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src),
2067                   "lhax $rD, $src", IIC_LdStLHA,
2068                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
2069                   PPC970_DGroup_Cracked;
2070def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src),
2071                   "lhzx $rD, $src", IIC_LdStLoad,
2072                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
2073def LWZX : XForm_1_memOp<31,  23, (outs gprc:$rD), (ins memrr:$src),
2074                   "lwzx $rD, $src", IIC_LdStLoad,
2075                   [(set i32:$rD, (load xaddr:$src))]>;
2076def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src),
2077                   "lhbrx $rD, $src", IIC_LdStLoad,
2078                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
2079def LWBRX : XForm_1_memOp<31,  534, (outs gprc:$rD), (ins memrr:$src),
2080                   "lwbrx $rD, $src", IIC_LdStLoad,
2081                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
2082
2083let Predicates = [HasFPU] in {
2084def LFSX   : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src),
2085                      "lfsx $frD, $src", IIC_LdStLFD,
2086                      [(set f32:$frD, (load xaddr:$src))]>;
2087def LFDX   : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src),
2088                      "lfdx $frD, $src", IIC_LdStLFD,
2089                      [(set f64:$frD, (load xaddr:$src))]>;
2090
2091def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src),
2092                      "lfiwax $frD, $src", IIC_LdStLFD,
2093                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
2094def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src),
2095                      "lfiwzx $frD, $src", IIC_LdStLFD,
2096                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
2097}
2098}
2099
2100// Load Multiple
2101def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
2102                  "lmw $rD, $src", IIC_LdStLMW, []>;
2103
2104//===----------------------------------------------------------------------===//
2105// PPC32 Store Instructions.
2106//
2107
2108// Unindexed (r+i) Stores.
2109let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
2110def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst),
2111                   "stb $rS, $dst", IIC_LdStStore,
2112                   [(truncstorei8 i32:$rS, iaddr:$dst)]>;
2113def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst),
2114                   "sth $rS, $dst", IIC_LdStStore,
2115                   [(truncstorei16 i32:$rS, iaddr:$dst)]>;
2116def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst),
2117                   "stw $rS, $dst", IIC_LdStStore,
2118                   [(store i32:$rS, iaddr:$dst)]>;
2119let Predicates = [HasFPU] in {
2120def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
2121                   "stfs $rS, $dst", IIC_LdStSTFD,
2122                   [(store f32:$rS, iaddr:$dst)]>;
2123def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
2124                   "stfd $rS, $dst", IIC_LdStSTFD,
2125                   [(store f64:$rS, iaddr:$dst)]>;
2126}
2127}
2128
2129// Unindexed (r+i) Stores with Update (preinc).
2130let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
2131def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
2132                    "stbu $rS, $dst", IIC_LdStSTU, []>,
2133                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
2134def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
2135                    "sthu $rS, $dst", IIC_LdStSTU, []>,
2136                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
2137def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
2138                    "stwu $rS, $dst", IIC_LdStSTU, []>,
2139                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
2140let Predicates = [HasFPU] in {
2141def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
2142                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
2143                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
2144def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
2145                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
2146                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
2147}
2148}
2149
2150// Patterns to match the pre-inc stores.  We can't put the patterns on
2151// the instruction definitions directly as ISel wants the address base
2152// and offset to be separate operands, not a single complex operand.
2153def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
2154          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
2155def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
2156          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
2157def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
2158          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
2159def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
2160          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
2161def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
2162          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
2163
2164// Indexed (r+r) Stores.
2165let PPC970_Unit = 2 in {
2166def STBX  : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
2167                   "stbx $rS, $dst", IIC_LdStStore,
2168                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
2169                   PPC970_DGroup_Cracked;
2170def STHX  : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
2171                   "sthx $rS, $dst", IIC_LdStStore,
2172                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
2173                   PPC970_DGroup_Cracked;
2174def STWX  : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
2175                   "stwx $rS, $dst", IIC_LdStStore,
2176                   [(store i32:$rS, xaddr:$dst)]>,
2177                   PPC970_DGroup_Cracked;
2178
2179def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
2180                   "sthbrx $rS, $dst", IIC_LdStStore,
2181                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
2182                   PPC970_DGroup_Cracked;
2183def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
2184                   "stwbrx $rS, $dst", IIC_LdStStore,
2185                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
2186                   PPC970_DGroup_Cracked;
2187
2188let Predicates = [HasFPU] in {
2189def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
2190                     "stfiwx $frS, $dst", IIC_LdStSTFD,
2191                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
2192
2193def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
2194                     "stfsx $frS, $dst", IIC_LdStSTFD,
2195                     [(store f32:$frS, xaddr:$dst)]>;
2196def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
2197                     "stfdx $frS, $dst", IIC_LdStSTFD,
2198                     [(store f64:$frS, xaddr:$dst)]>;
2199}
2200}
2201
2202// Indexed (r+r) Stores with Update (preinc).
2203let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
2204def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
2205                          (ins gprc:$rS, memrr:$dst),
2206                          "stbux $rS, $dst", IIC_LdStSTUX, []>,
2207                          RegConstraint<"$dst.ptrreg = $ea_res">,
2208                          NoEncode<"$ea_res">,
2209                          PPC970_DGroup_Cracked;
2210def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
2211                          (ins gprc:$rS, memrr:$dst),
2212                          "sthux $rS, $dst", IIC_LdStSTUX, []>,
2213                          RegConstraint<"$dst.ptrreg = $ea_res">,
2214                          NoEncode<"$ea_res">,
2215                          PPC970_DGroup_Cracked;
2216def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
2217                          (ins gprc:$rS, memrr:$dst),
2218                          "stwux $rS, $dst", IIC_LdStSTUX, []>,
2219                          RegConstraint<"$dst.ptrreg = $ea_res">,
2220                          NoEncode<"$ea_res">,
2221                          PPC970_DGroup_Cracked;
2222let Predicates = [HasFPU] in {
2223def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res),
2224                          (ins f4rc:$rS, memrr:$dst),
2225                          "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
2226                          RegConstraint<"$dst.ptrreg = $ea_res">,
2227                          NoEncode<"$ea_res">,
2228                          PPC970_DGroup_Cracked;
2229def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res),
2230                          (ins f8rc:$rS, memrr:$dst),
2231                          "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
2232                          RegConstraint<"$dst.ptrreg = $ea_res">,
2233                          NoEncode<"$ea_res">,
2234                          PPC970_DGroup_Cracked;
2235}
2236}
2237
2238// Patterns to match the pre-inc stores.  We can't put the patterns on
2239// the instruction definitions directly as ISel wants the address base
2240// and offset to be separate operands, not a single complex operand.
2241def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2242          (STBUX $rS, $ptrreg, $ptroff)>;
2243def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2244          (STHUX $rS, $ptrreg, $ptroff)>;
2245def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2246          (STWUX $rS, $ptrreg, $ptroff)>;
2247let Predicates = [HasFPU] in {
2248def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2249          (STFSUX $rS, $ptrreg, $ptroff)>;
2250def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2251          (STFDUX $rS, $ptrreg, $ptroff)>;
2252}
2253
2254// Store Multiple
2255def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
2256                   "stmw $rS, $dst", IIC_LdStLMW, []>;
2257
2258def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
2259                        "sync $L", IIC_LdStSync, []>;
2260
2261let isCodeGenOnly = 1 in {
2262  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
2263                           "msync", IIC_LdStSync, []> {
2264    let L = 0;
2265  }
2266}
2267
2268def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
2269def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
2270def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2271def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2272
2273//===----------------------------------------------------------------------===//
2274// PPC32 Arithmetic Instructions.
2275//
2276
2277let PPC970_Unit = 1 in {  // FXU Operations.
2278def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
2279                     "addi $rD, $rA, $imm", IIC_IntSimple,
2280                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
2281let BaseName = "addic" in {
2282let Defs = [CARRY] in
2283def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2284                     "addic $rD, $rA, $imm", IIC_IntGeneral,
2285                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
2286                     RecFormRel, PPC970_DGroup_Cracked;
2287let Defs = [CARRY, CR0] in
2288def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2289                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
2290                     []>, isDOT, RecFormRel;
2291}
2292def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
2293                     "addis $rD, $rA, $imm", IIC_IntSimple,
2294                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
2295let isCodeGenOnly = 1 in
2296def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
2297                     "la $rD, $sym($rA)", IIC_IntGeneral,
2298                     [(set i32:$rD, (add i32:$rA,
2299                                          (PPClo tglobaladdr:$sym, 0)))]>;
2300def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2301                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
2302                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
2303let Defs = [CARRY] in
2304def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2305                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
2306                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2307
2308let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
2309  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
2310                       "li $rD, $imm", IIC_IntSimple,
2311                       [(set i32:$rD, imm32SExt16:$imm)]>;
2312  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
2313                       "lis $rD, $imm", IIC_IntSimple,
2314                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
2315}
2316}
2317
2318let PPC970_Unit = 1 in {  // FXU Operations.
2319let Defs = [CR0] in {
2320def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2321                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
2322                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
2323                    isDOT;
2324def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2325                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
2326                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
2327                    isDOT;
2328}
2329def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2330                    "ori $dst, $src1, $src2", IIC_IntSimple,
2331                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
2332def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2333                    "oris $dst, $src1, $src2", IIC_IntSimple,
2334                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
2335def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2336                    "xori $dst, $src1, $src2", IIC_IntSimple,
2337                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
2338def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2339                    "xoris $dst, $src1, $src2", IIC_IntSimple,
2340                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
2341
2342def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
2343                         []>;
2344let isCodeGenOnly = 1 in {
2345// The POWER6 and POWER7 have special group-terminating nops.
2346def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
2347                                        "ori 1, 1, 0", IIC_IntSimple, []>;
2348def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
2349                                        "ori 2, 2, 0", IIC_IntSimple, []>;
2350}
2351
2352let isCompare = 1, hasSideEffects = 0 in {
2353  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
2354                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
2355  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
2356                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
2357  def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
2358                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
2359                                "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
2360               Requires<[IsISA3_0]>;
2361}
2362}
2363
2364let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2365let isCommutable = 1 in {
2366defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2367                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
2368                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
2369defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2370                     "and", "$rA, $rS, $rB", IIC_IntSimple,
2371                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
2372} // isCommutable
2373defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2374                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
2375                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
2376let isCommutable = 1 in {
2377defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2378                     "or", "$rA, $rS, $rB", IIC_IntSimple,
2379                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
2380defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2381                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
2382                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
2383} // isCommutable
2384defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2385                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
2386                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
2387let isCommutable = 1 in {
2388defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2389                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
2390                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
2391defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2392                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
2393                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
2394} // isCommutable
2395defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2396                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
2397                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
2398defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2399                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
2400                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
2401defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2402                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
2403                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
2404}
2405
2406let PPC970_Unit = 1 in {  // FXU Operations.
2407let hasSideEffects = 0 in {
2408defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
2409                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
2410                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2411defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
2412                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
2413                        [(set i32:$rA, (ctlz i32:$rS))]>;
2414defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
2415                        "cnttzw", "$rA, $rS", IIC_IntGeneral,
2416                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
2417defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2418                        "extsb", "$rA, $rS", IIC_IntSimple,
2419                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2420defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2421                        "extsh", "$rA, $rS", IIC_IntSimple,
2422                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2423
2424let isCommutable = 1 in
2425def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2426                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2427                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2428}
2429let isCompare = 1, hasSideEffects = 0 in {
2430  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2431                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2432  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2433                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2434}
2435}
2436let PPC970_Unit = 3, Predicates = [HasFPU] in {  // FPU Operations.
2437//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2438//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2439let isCompare = 1, hasSideEffects = 0 in {
2440  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2441                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2442  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2443  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2444                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2445}
2446
2447def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2448                      "ftdiv $crD, $fA, $fB", IIC_FPCompare>;
2449def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
2450                      "ftsqrt $crD, $fB", IIC_FPCompare>;
2451
2452let Uses = [RM] in {
2453  let hasSideEffects = 0 in {
2454  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2455                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2456                          []>;
2457  defm FCTIWU  : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
2458                          "fctiwu", "$frD, $frB", IIC_FPGeneral,
2459                          []>;
2460  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2461                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2462                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2463
2464  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2465                          "frsp", "$frD, $frB", IIC_FPGeneral,
2466                          [(set f32:$frD, (fpround f64:$frB))]>;
2467
2468  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2469  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2470                          "frin", "$frD, $frB", IIC_FPGeneral,
2471                          [(set f64:$frD, (fround f64:$frB))]>;
2472  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2473                          "frin", "$frD, $frB", IIC_FPGeneral,
2474                          [(set f32:$frD, (fround f32:$frB))]>;
2475  }
2476
2477  let hasSideEffects = 0 in {
2478  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2479  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2480                          "frip", "$frD, $frB", IIC_FPGeneral,
2481                          [(set f64:$frD, (fceil f64:$frB))]>;
2482  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2483                          "frip", "$frD, $frB", IIC_FPGeneral,
2484                          [(set f32:$frD, (fceil f32:$frB))]>;
2485  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2486  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2487                          "friz", "$frD, $frB", IIC_FPGeneral,
2488                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2489  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2490                          "friz", "$frD, $frB", IIC_FPGeneral,
2491                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2492  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2493  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2494                          "frim", "$frD, $frB", IIC_FPGeneral,
2495                          [(set f64:$frD, (ffloor f64:$frB))]>;
2496  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2497                          "frim", "$frD, $frB", IIC_FPGeneral,
2498                          [(set f32:$frD, (ffloor f32:$frB))]>;
2499
2500  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2501                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2502                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2503  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2504                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2505                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2506  }
2507  }
2508}
2509
2510/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2511/// often coalesced away and we don't want the dispatch group builder to think
2512/// that they will fill slots (which could cause the load of a LSU reject to
2513/// sneak into a d-group with a store).
2514let hasSideEffects = 0, Predicates = [HasFPU] in
2515defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2516                       "fmr", "$frD, $frB", IIC_FPGeneral,
2517                       []>,  // (set f32:$frD, f32:$frB)
2518                       PPC970_Unit_Pseudo;
2519
2520let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in {  // FPU Operations.
2521// These are artificially split into two different forms, for 4/8 byte FP.
2522defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2523                        "fabs", "$frD, $frB", IIC_FPGeneral,
2524                        [(set f32:$frD, (fabs f32:$frB))]>;
2525let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2526defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2527                        "fabs", "$frD, $frB", IIC_FPGeneral,
2528                        [(set f64:$frD, (fabs f64:$frB))]>;
2529defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2530                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2531                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2532let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2533defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2534                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2535                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2536defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2537                        "fneg", "$frD, $frB", IIC_FPGeneral,
2538                        [(set f32:$frD, (fneg f32:$frB))]>;
2539let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2540defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2541                        "fneg", "$frD, $frB", IIC_FPGeneral,
2542                        [(set f64:$frD, (fneg f64:$frB))]>;
2543
2544defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2545                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2546                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2547let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2548defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2549                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2550                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2551
2552// Reciprocal estimates.
2553defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2554                          "fre", "$frD, $frB", IIC_FPGeneral,
2555                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2556defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2557                          "fres", "$frD, $frB", IIC_FPGeneral,
2558                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2559defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2560                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2561                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2562defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2563                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2564                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2565}
2566
2567// XL-Form instructions.  condition register logical ops.
2568//
2569let hasSideEffects = 0 in
2570def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2571                      "mcrf $BF, $BFA", IIC_BrMCR>,
2572             PPC970_DGroup_First, PPC970_Unit_CRU;
2573
2574// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2575// condition-register logical instructions have preferred forms. Specifically,
2576// it is preferred that the bit specified by the BT field be in the same
2577// condition register as that specified by the bit BB. We might want to account
2578// for this via hinting the register allocator and anti-dep breakers, or we
2579// could constrain the register class to force this constraint and then loosen
2580// it during register allocation via convertToThreeAddress or some similar
2581// mechanism.
2582
2583let isCommutable = 1 in {
2584def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2585                               (ins crbitrc:$CRA, crbitrc:$CRB),
2586                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2587                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2588
2589def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2590                               (ins crbitrc:$CRA, crbitrc:$CRB),
2591                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2592                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2593
2594def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2595                               (ins crbitrc:$CRA, crbitrc:$CRB),
2596                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2597                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2598
2599def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2600                               (ins crbitrc:$CRA, crbitrc:$CRB),
2601                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2602                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2603
2604def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2605                              (ins crbitrc:$CRA, crbitrc:$CRB),
2606                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2607                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2608
2609def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2610                               (ins crbitrc:$CRA, crbitrc:$CRB),
2611                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2612                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2613} // isCommutable
2614
2615def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2616                               (ins crbitrc:$CRA, crbitrc:$CRB),
2617                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2618                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2619
2620def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2621                               (ins crbitrc:$CRA, crbitrc:$CRB),
2622                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2623                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2624
2625let isCodeGenOnly = 1 in {
2626let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2627def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2628              "creqv $dst, $dst, $dst", IIC_BrCR,
2629              [(set i1:$dst, 1)]>;
2630
2631def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2632              "crxor $dst, $dst, $dst", IIC_BrCR,
2633              [(set i1:$dst, 0)]>;
2634}
2635
2636let Defs = [CR1EQ], CRD = 6 in {
2637def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2638              "creqv 6, 6, 6", IIC_BrCR,
2639              [(PPCcr6set)]>;
2640
2641def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2642              "crxor 6, 6, 6", IIC_BrCR,
2643              [(PPCcr6unset)]>;
2644}
2645}
2646
2647// XFX-Form instructions.  Instructions that deal with SPRs.
2648//
2649
2650def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2651                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2652def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2653                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2654
2655def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2656                     "mftb $RT, $SPR", IIC_SprMFTB>;
2657
2658def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
2659                     "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2660
2661def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
2662                     "mtpmr $SPR, $RT", IIC_SprMTPMR>;
2663
2664
2665// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2666// on a 32-bit target.
2667let hasSideEffects = 1 in
2668def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins),
2669                    "#ReadTB", []>;
2670
2671let Uses = [CTR] in {
2672def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2673                          "mfctr $rT", IIC_SprMFSPR>,
2674            PPC970_DGroup_First, PPC970_Unit_FXU;
2675}
2676let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2677def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2678                          "mtctr $rS", IIC_SprMTSPR>,
2679            PPC970_DGroup_First, PPC970_Unit_FXU;
2680}
2681let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2682let Pattern = [(int_set_loop_iterations i32:$rS)] in
2683def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2684                              "mtctr $rS", IIC_SprMTSPR>,
2685                PPC970_DGroup_First, PPC970_Unit_FXU;
2686}
2687
2688let Defs = [LR] in {
2689def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2690                          "mtlr $rS", IIC_SprMTSPR>,
2691            PPC970_DGroup_First, PPC970_Unit_FXU;
2692}
2693let Uses = [LR] in {
2694def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2695                          "mflr $rT", IIC_SprMFSPR>,
2696            PPC970_DGroup_First, PPC970_Unit_FXU;
2697}
2698
2699let isCodeGenOnly = 1 in {
2700  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2701  // like a GPR on the PPC970.  As such, copies in and out have the same
2702  // performance characteristics as an OR instruction.
2703  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2704                               "mtspr 256, $rS", IIC_IntGeneral>,
2705                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2706  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2707                               "mfspr $rT, 256", IIC_IntGeneral>,
2708                 PPC970_DGroup_First, PPC970_Unit_FXU;
2709
2710  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2711                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2712                                "mtspr 256, $rS", IIC_IntGeneral>,
2713                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2714  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2715                                (ins VRSAVERC:$reg),
2716                                "mfspr $rT, 256", IIC_IntGeneral>,
2717                  PPC970_DGroup_First, PPC970_Unit_FXU;
2718}
2719
2720// Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
2721def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
2722def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
2723
2724// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2725// so we'll need to scavenge a register for it.
2726let mayStore = 1 in
2727def SPILL_VRSAVE : PPCEmitTimePseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2728                     "#SPILL_VRSAVE", []>;
2729
2730// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2731// spilled), so we'll need to scavenge a register for it.
2732let mayLoad = 1 in
2733def RESTORE_VRSAVE : PPCEmitTimePseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2734                     "#RESTORE_VRSAVE", []>;
2735
2736let hasSideEffects = 0 in {
2737// mtocrf's input needs to be prepared by shifting by an amount dependent
2738// on the cr register selected. Thus, post-ra anti-dep breaking must not
2739// later change that register assignment.
2740let hasExtraDefRegAllocReq = 1 in {
2741def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2742                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2743            PPC970_DGroup_First, PPC970_Unit_CRU;
2744
2745// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2746// is dependent on the cr fields being set.
2747def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2748                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2749            PPC970_MicroCode, PPC970_Unit_CRU;
2750} // hasExtraDefRegAllocReq = 1
2751
2752// mfocrf's input needs to be prepared by shifting by an amount dependent
2753// on the cr register selected. Thus, post-ra anti-dep breaking must not
2754// later change that register assignment.
2755let hasExtraSrcRegAllocReq = 1 in {
2756def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2757                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2758            PPC970_DGroup_First, PPC970_Unit_CRU;
2759
2760// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2761// is dependent on the cr fields being copied.
2762def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2763                     "mfcr $rT", IIC_SprMFCR>,
2764                     PPC970_MicroCode, PPC970_Unit_CRU;
2765} // hasExtraSrcRegAllocReq = 1
2766
2767def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2768                   "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
2769} // hasSideEffects = 0
2770
2771let Predicates = [HasFPU] in {
2772// Custom inserter instruction to perform FADD in round-to-zero mode.
2773let Uses = [RM] in {
2774  def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2775                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2776}
2777
2778// The above pseudo gets expanded to make use of the following instructions
2779// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2780let Uses = [RM], Defs = [RM] in {
2781  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2782                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2783               PPC970_DGroup_Single, PPC970_Unit_FPU;
2784  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2785                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2786               PPC970_DGroup_Single, PPC970_Unit_FPU;
2787  let isCodeGenOnly = 1 in
2788  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2789                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2790                PPC970_DGroup_Single, PPC970_Unit_FPU;
2791}
2792let Uses = [RM] in {
2793  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2794                         "mffs $rT", IIC_IntMFFS,
2795                         [(set f64:$rT, (PPCmffs))]>,
2796               PPC970_DGroup_Single, PPC970_Unit_FPU;
2797
2798  let Defs = [CR1] in
2799  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2800                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2801
2802  def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
2803                                  "mffsce $rT", IIC_IntMFFS, []>,
2804               PPC970_DGroup_Single, PPC970_Unit_FPU;
2805
2806  def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT),
2807                                         (ins f8rc:$FRB), "mffscdrn $rT, $FRB",
2808                                         IIC_IntMFFS, []>,
2809                 PPC970_DGroup_Single, PPC970_Unit_FPU;
2810
2811  def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT),
2812                                          (ins u3imm:$DRM),
2813                                          "mffscdrni $rT, $DRM",
2814                                          IIC_IntMFFS, []>,
2815                  PPC970_DGroup_Single, PPC970_Unit_FPU;
2816
2817  def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT),
2818                                        (ins f8rc:$FRB), "mffscrn $rT, $FRB",
2819                                        IIC_IntMFFS, []>,
2820                PPC970_DGroup_Single, PPC970_Unit_FPU;
2821
2822  def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT),
2823                                       (ins u2imm:$RM), "mffscrni $rT, $RM",
2824                                       IIC_IntMFFS, []>,
2825                 PPC970_DGroup_Single, PPC970_Unit_FPU;
2826
2827  def MFFSL  : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins),
2828                                  "mffsl $rT", IIC_IntMFFS, []>,
2829               PPC970_DGroup_Single, PPC970_Unit_FPU;
2830}
2831}
2832
2833let Predicates = [IsISA3_0] in {
2834def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2835                        "modsw $rT, $rA, $rB", IIC_IntDivW,
2836                        [(set i32:$rT, (srem i32:$rA, i32:$rB))]>;
2837def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2838                        "moduw $rT, $rA, $rB", IIC_IntDivW,
2839                        [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
2840}
2841
2842let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2843// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2844let isCommutable = 1 in
2845defm ADD4  : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2846                        "add", "$rT, $rA, $rB", IIC_IntSimple,
2847                        [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2848let isCodeGenOnly = 1 in
2849def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2850                       "add $rT, $rA, $rB", IIC_IntSimple,
2851                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2852let isCommutable = 1 in
2853defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2854                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2855                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2856                        PPC970_DGroup_Cracked;
2857
2858defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2859                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2860                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2861defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2862                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2863                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2864defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2865                         "divwe", "$rT, $rA, $rB", IIC_IntDivW,
2866                         [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2867                         Requires<[HasExtDiv]>;
2868defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2869                          "divweu", "$rT, $rA, $rB", IIC_IntDivW,
2870                          [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2871                          Requires<[HasExtDiv]>;
2872let isCommutable = 1 in {
2873defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2874                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2875                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2876defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2877                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2878                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2879defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2880                        "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2881                        [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2882} // isCommutable
2883defm SUBF  : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2884                        "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2885                        [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2886defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2887                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2888                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2889                        PPC970_DGroup_Cracked;
2890defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2891                        "neg", "$rT, $rA", IIC_IntSimple,
2892                        [(set i32:$rT, (ineg i32:$rA))]>;
2893let Uses = [CARRY] in {
2894let isCommutable = 1 in
2895defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2896                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2897                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2898defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2899                         "addme", "$rT, $rA", IIC_IntGeneral,
2900                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2901defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2902                         "addze", "$rT, $rA", IIC_IntGeneral,
2903                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2904defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2905                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2906                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2907defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2908                         "subfme", "$rT, $rA", IIC_IntGeneral,
2909                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2910defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2911                         "subfze", "$rT, $rA", IIC_IntGeneral,
2912                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2913}
2914}
2915
2916// A-Form instructions.  Most of the instructions executed in the FPU are of
2917// this type.
2918//
2919let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in {  // FPU Operations.
2920let Uses = [RM] in {
2921let isCommutable = 1 in {
2922  defm FMADD : AForm_1r<63, 29,
2923                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2924                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2925                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2926  defm FMADDS : AForm_1r<59, 29,
2927                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2928                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2929                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2930  defm FMSUB : AForm_1r<63, 28,
2931                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2932                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2933                      [(set f64:$FRT,
2934                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2935  defm FMSUBS : AForm_1r<59, 28,
2936                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2937                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2938                      [(set f32:$FRT,
2939                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2940  defm FNMADD : AForm_1r<63, 31,
2941                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2942                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2943                      [(set f64:$FRT,
2944                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2945  defm FNMADDS : AForm_1r<59, 31,
2946                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2947                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2948                      [(set f32:$FRT,
2949                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2950  defm FNMSUB : AForm_1r<63, 30,
2951                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2952                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2953                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2954                                                 (fneg f64:$FRB))))]>;
2955  defm FNMSUBS : AForm_1r<59, 30,
2956                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2957                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2958                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2959                                                 (fneg f32:$FRB))))]>;
2960} // isCommutable
2961}
2962// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2963// having 4 of these, force the comparison to always be an 8-byte double (code
2964// should use an FMRSD if the input comparison value really wants to be a float)
2965// and 4/8 byte forms for the result and operand type..
2966let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2967defm FSELD : AForm_1r<63, 23,
2968                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2969                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2970                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2971defm FSELS : AForm_1r<63, 23,
2972                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2973                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2974                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2975let Uses = [RM] in {
2976  let isCommutable = 1 in {
2977  defm FADD  : AForm_2r<63, 21,
2978                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2979                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2980                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2981  defm FADDS : AForm_2r<59, 21,
2982                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2983                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2984                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2985  } // isCommutable
2986  defm FDIV  : AForm_2r<63, 18,
2987                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2988                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2989                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2990  defm FDIVS : AForm_2r<59, 18,
2991                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2992                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2993                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2994  let isCommutable = 1 in {
2995  defm FMUL  : AForm_3r<63, 25,
2996                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2997                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2998                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2999  defm FMULS : AForm_3r<59, 25,
3000                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
3001                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
3002                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
3003  } // isCommutable
3004  defm FSUB  : AForm_2r<63, 20,
3005                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
3006                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
3007                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
3008  defm FSUBS : AForm_2r<59, 20,
3009                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
3010                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
3011                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
3012  }
3013}
3014
3015let hasSideEffects = 0 in {
3016let PPC970_Unit = 1 in {  // FXU Operations.
3017  let isSelect = 1 in
3018  def ISEL  : AForm_4<31, 15,
3019                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
3020                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
3021                     []>;
3022}
3023
3024let PPC970_Unit = 1 in {  // FXU Operations.
3025// M-Form instructions.  rotate and mask instructions.
3026//
3027let isCommutable = 1 in {
3028// RLWIMI can be commuted if the rotate amount is zero.
3029defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
3030                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
3031                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
3032                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
3033                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
3034}
3035let BaseName = "rlwinm" in {
3036def RLWINM : MForm_2<21,
3037                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
3038                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
3039                     []>, RecFormRel;
3040let Defs = [CR0] in
3041def RLWINMo : MForm_2<21,
3042                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
3043                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
3044                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
3045}
3046defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
3047                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
3048                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
3049                       []>;
3050}
3051} // hasSideEffects = 0
3052
3053//===----------------------------------------------------------------------===//
3054// PowerPC Instruction Patterns
3055//
3056
3057// Arbitrary immediate support.  Implement in terms of LIS/ORI.
3058def : Pat<(i32 imm:$imm),
3059          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
3060
3061// Implement the 'not' operation with the NOR instruction.
3062def i32not : OutPatFrag<(ops node:$in),
3063                        (NOR $in, $in)>;
3064def        : Pat<(not i32:$in),
3065                 (i32not $in)>;
3066
3067// ADD an arbitrary immediate.
3068def : Pat<(add i32:$in, imm:$imm),
3069          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
3070// OR an arbitrary immediate.
3071def : Pat<(or i32:$in, imm:$imm),
3072          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
3073// XOR an arbitrary immediate.
3074def : Pat<(xor i32:$in, imm:$imm),
3075          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
3076// SUBFIC
3077def : Pat<(sub imm32SExt16:$imm, i32:$in),
3078          (SUBFIC $in, imm:$imm)>;
3079
3080// SHL/SRL
3081def : Pat<(shl i32:$in, (i32 imm:$imm)),
3082          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
3083def : Pat<(srl i32:$in, (i32 imm:$imm)),
3084          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
3085
3086// ROTL
3087def : Pat<(rotl i32:$in, i32:$sh),
3088          (RLWNM $in, $sh, 0, 31)>;
3089def : Pat<(rotl i32:$in, (i32 imm:$imm)),
3090          (RLWINM $in, imm:$imm, 0, 31)>;
3091
3092// RLWNM
3093def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
3094          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
3095
3096// Calls
3097def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
3098          (BL tglobaladdr:$dst)>;
3099
3100def : Pat<(PPCcall (i32 texternalsym:$dst)),
3101          (BL texternalsym:$dst)>;
3102
3103// Calls for AIX only
3104def : Pat<(PPCcall (i32 mcsym:$dst)),
3105          (BL mcsym:$dst)>;
3106def : Pat<(PPCcall_nop (i32 mcsym:$dst)),
3107          (BL_NOP mcsym:$dst)>;
3108
3109def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
3110          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
3111
3112def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
3113          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
3114
3115def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
3116          (TCRETURNri CTRRC:$dst, imm:$imm)>;
3117
3118
3119
3120// Hi and Lo for Darwin Global Addresses.
3121def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
3122def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
3123def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
3124def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
3125def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
3126def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
3127def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
3128def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
3129def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
3130          (ADDIS $in, tglobaltlsaddr:$g)>;
3131def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
3132          (ADDI $in, tglobaltlsaddr:$g)>;
3133def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
3134          (ADDIS $in, tglobaladdr:$g)>;
3135def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
3136          (ADDIS $in, tconstpool:$g)>;
3137def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
3138          (ADDIS $in, tjumptable:$g)>;
3139def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
3140          (ADDIS $in, tblockaddress:$g)>;
3141
3142// Support for thread-local storage.
3143def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
3144                [(set i32:$rD, (PPCppc32GOT))]>;
3145
3146// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
3147// This uses two output registers, the first as the real output, the second as a
3148// temporary register, used internally in code generation.
3149def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
3150                []>, NoEncode<"$rT">;
3151
3152def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
3153                           "#LDgotTprelL32",
3154                           [(set i32:$rD,
3155                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
3156def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
3157          (ADD4TLS $in, tglobaltlsaddr:$g)>;
3158
3159def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
3160                         "#ADDItlsgdL32",
3161                         [(set i32:$rD,
3162                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
3163// LR is a true define, while the rest of the Defs are clobbers.  R3 is
3164// explicitly defined when this op is created, so not mentioned here.
3165let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3166    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
3167def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
3168                          "GETtlsADDR32",
3169                          [(set i32:$rD,
3170                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
3171// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
3172// are true defines while the rest of the Defs are clobbers.
3173let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3174    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
3175def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD),
3176                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
3177                              "#ADDItlsgdLADDR32",
3178                              [(set i32:$rD,
3179                                (PPCaddiTlsgdLAddr i32:$reg,
3180                                                   tglobaltlsaddr:$disp,
3181                                                   tglobaltlsaddr:$sym))]>;
3182def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
3183                          "#ADDItlsldL32",
3184                          [(set i32:$rD,
3185                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
3186// LR is a true define, while the rest of the Defs are clobbers.  R3 is
3187// explicitly defined when this op is created, so not mentioned here.
3188let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3189    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
3190def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
3191                            "GETtlsldADDR32",
3192                            [(set i32:$rD,
3193                              (PPCgetTlsldAddr i32:$reg,
3194                                               tglobaltlsaddr:$sym))]>;
3195// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
3196// are true defines while the rest of the Defs are clobbers.
3197let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
3198    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
3199def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD),
3200                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
3201                              "#ADDItlsldLADDR32",
3202                              [(set i32:$rD,
3203                                (PPCaddiTlsldLAddr i32:$reg,
3204                                                   tglobaltlsaddr:$disp,
3205                                                   tglobaltlsaddr:$sym))]>;
3206def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
3207                           "#ADDIdtprelL32",
3208                           [(set i32:$rD,
3209                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
3210def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
3211                            "#ADDISdtprelHA32",
3212                            [(set i32:$rD,
3213                              (PPCaddisDtprelHA i32:$reg,
3214                                                tglobaltlsaddr:$disp))]>;
3215
3216// Support for Position-independent code
3217def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
3218                   "#LWZtoc",
3219                   [(set i32:$rD,
3220                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
3221// Get Global (GOT) Base Register offset, from the word immediately preceding
3222// the function label.
3223def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
3224
3225
3226// Standard shifts.  These are represented separately from the real shifts above
3227// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
3228// amounts.
3229def : Pat<(sra i32:$rS, i32:$rB),
3230          (SRAW $rS, $rB)>;
3231def : Pat<(srl i32:$rS, i32:$rB),
3232          (SRW $rS, $rB)>;
3233def : Pat<(shl i32:$rS, i32:$rB),
3234          (SLW $rS, $rB)>;
3235
3236def : Pat<(zextloadi1 iaddr:$src),
3237          (LBZ iaddr:$src)>;
3238def : Pat<(zextloadi1 xaddr:$src),
3239          (LBZX xaddr:$src)>;
3240def : Pat<(extloadi1 iaddr:$src),
3241          (LBZ iaddr:$src)>;
3242def : Pat<(extloadi1 xaddr:$src),
3243          (LBZX xaddr:$src)>;
3244def : Pat<(extloadi8 iaddr:$src),
3245          (LBZ iaddr:$src)>;
3246def : Pat<(extloadi8 xaddr:$src),
3247          (LBZX xaddr:$src)>;
3248def : Pat<(extloadi16 iaddr:$src),
3249          (LHZ iaddr:$src)>;
3250def : Pat<(extloadi16 xaddr:$src),
3251          (LHZX xaddr:$src)>;
3252let Predicates = [HasFPU] in {
3253def : Pat<(f64 (extloadf32 iaddr:$src)),
3254          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
3255def : Pat<(f64 (extloadf32 xaddr:$src)),
3256          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
3257
3258def : Pat<(f64 (fpextend f32:$src)),
3259          (COPY_TO_REGCLASS $src, F8RC)>;
3260}
3261
3262// Only seq_cst fences require the heavyweight sync (SYNC 0).
3263// All others can use the lightweight sync (SYNC 1).
3264// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
3265// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
3266// versions of Power.
3267def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
3268def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
3269def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
3270def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
3271
3272let Predicates = [HasFPU] in {
3273// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
3274def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
3275          (FNMSUB $A, $C, $B)>;
3276def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
3277          (FNMSUB $A, $C, $B)>;
3278def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
3279          (FNMSUBS $A, $C, $B)>;
3280def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
3281          (FNMSUBS $A, $C, $B)>;
3282
3283// FCOPYSIGN's operand types need not agree.
3284def : Pat<(fcopysign f64:$frB, f32:$frA),
3285          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
3286def : Pat<(fcopysign f32:$frB, f64:$frA),
3287          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
3288}
3289
3290include "PPCInstrAltivec.td"
3291include "PPCInstrSPE.td"
3292include "PPCInstr64Bit.td"
3293include "PPCInstrVSX.td"
3294include "PPCInstrQPX.td"
3295include "PPCInstrHTM.td"
3296
3297def crnot : OutPatFrag<(ops node:$in),
3298                       (CRNOR $in, $in)>;
3299def       : Pat<(not i1:$in),
3300                (crnot $in)>;
3301
3302// Patterns for arithmetic i1 operations.
3303def : Pat<(add i1:$a, i1:$b),
3304          (CRXOR $a, $b)>;
3305def : Pat<(sub i1:$a, i1:$b),
3306          (CRXOR $a, $b)>;
3307def : Pat<(mul i1:$a, i1:$b),
3308          (CRAND $a, $b)>;
3309
3310// We're sometimes asked to materialize i1 -1, which is just 1 in this case
3311// (-1 is used to mean all bits set).
3312def : Pat<(i1 -1), (CRSET)>;
3313
3314// i1 extensions, implemented in terms of isel.
3315def : Pat<(i32 (zext i1:$in)),
3316          (SELECT_I4 $in, (LI 1), (LI 0))>;
3317def : Pat<(i32 (sext i1:$in)),
3318          (SELECT_I4 $in, (LI -1), (LI 0))>;
3319
3320def : Pat<(i64 (zext i1:$in)),
3321          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3322def : Pat<(i64 (sext i1:$in)),
3323          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
3324
3325// FIXME: We should choose either a zext or a sext based on other constants
3326// already around.
3327def : Pat<(i32 (anyext i1:$in)),
3328          (SELECT_I4 $in, (LI 1), (LI 0))>;
3329def : Pat<(i64 (anyext i1:$in)),
3330          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3331
3332// match setcc on i1 variables.
3333// CRANDC is:
3334//   1 1 : F
3335//   1 0 : T
3336//   0 1 : F
3337//   0 0 : F
3338//
3339// LT is:
3340//  -1 -1  : F
3341//  -1  0  : T
3342//   0 -1  : F
3343//   0  0  : F
3344//
3345// ULT is:
3346//   1 1 : F
3347//   1 0 : F
3348//   0 1 : T
3349//   0 0 : F
3350def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3351          (CRANDC $s1, $s2)>;
3352def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3353          (CRANDC $s2, $s1)>;
3354// CRORC is:
3355//   1 1 : T
3356//   1 0 : T
3357//   0 1 : F
3358//   0 0 : T
3359//
3360// LE is:
3361//  -1 -1 : T
3362//  -1  0 : T
3363//   0 -1 : F
3364//   0  0 : T
3365//
3366// ULE is:
3367//   1 1 : T
3368//   1 0 : F
3369//   0 1 : T
3370//   0 0 : T
3371def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3372          (CRORC $s1, $s2)>;
3373def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3374          (CRORC $s2, $s1)>;
3375
3376def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3377          (CREQV $s1, $s2)>;
3378
3379// GE is:
3380//  -1 -1 : T
3381//  -1  0 : F
3382//   0 -1 : T
3383//   0  0 : T
3384//
3385// UGE is:
3386//   1 1 : T
3387//   1 0 : T
3388//   0 1 : F
3389//   0 0 : T
3390def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3391          (CRORC $s2, $s1)>;
3392def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3393          (CRORC $s1, $s2)>;
3394
3395// GT is:
3396//  -1 -1 : F
3397//  -1  0 : F
3398//   0 -1 : T
3399//   0  0 : F
3400//
3401// UGT is:
3402//  1 1 : F
3403//  1 0 : T
3404//  0 1 : F
3405//  0 0 : F
3406def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3407          (CRANDC $s2, $s1)>;
3408def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3409          (CRANDC $s1, $s2)>;
3410
3411def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3412          (CRXOR $s1, $s2)>;
3413
3414// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
3415// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3416// floating-point types.
3417
3418multiclass CRNotPat<dag pattern, dag result> {
3419  def : Pat<pattern, (crnot result)>;
3420  def : Pat<(not pattern), result>;
3421
3422  // We can also fold the crnot into an extension:
3423  def : Pat<(i32 (zext pattern)),
3424            (SELECT_I4 result, (LI 0), (LI 1))>;
3425  def : Pat<(i32 (sext pattern)),
3426            (SELECT_I4 result, (LI 0), (LI -1))>;
3427
3428  // We can also fold the crnot into an extension:
3429  def : Pat<(i64 (zext pattern)),
3430            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3431  def : Pat<(i64 (sext pattern)),
3432            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
3433
3434  // FIXME: We should choose either a zext or a sext based on other constants
3435  // already around.
3436  def : Pat<(i32 (anyext pattern)),
3437            (SELECT_I4 result, (LI 0), (LI 1))>;
3438
3439  def : Pat<(i64 (anyext pattern)),
3440            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3441}
3442
3443// FIXME: Because of what seems like a bug in TableGen's type-inference code,
3444// we need to write imm:$imm in the output patterns below, not just $imm, or
3445// else the resulting matcher will not correctly add the immediate operand
3446// (making it a register operand instead).
3447
3448// extended SETCC.
3449multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
3450                       OutPatFrag rfrag, OutPatFrag rfrag8> {
3451  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
3452            (rfrag $s1)>;
3453  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
3454            (rfrag8 $s1)>;
3455  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
3456            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3457  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
3458            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3459
3460  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
3461            (rfrag $s1)>;
3462  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
3463            (rfrag8 $s1)>;
3464  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
3465            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3466  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
3467            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3468}
3469
3470// Note that we do all inversions below with i(32|64)not, instead of using
3471// (xori x, 1) because on the A2 nor has single-cycle latency while xori
3472// has 2-cycle latency.
3473
3474defm : ExtSetCCPat<SETEQ,
3475                   PatFrag<(ops node:$in, node:$cc),
3476                           (setcc $in, 0, $cc)>,
3477                   OutPatFrag<(ops node:$in),
3478                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
3479                   OutPatFrag<(ops node:$in),
3480                              (RLDICL (CNTLZD $in), 58, 63)> >;
3481
3482defm : ExtSetCCPat<SETNE,
3483                   PatFrag<(ops node:$in, node:$cc),
3484                           (setcc $in, 0, $cc)>,
3485                   OutPatFrag<(ops node:$in),
3486                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3487                   OutPatFrag<(ops node:$in),
3488                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3489
3490defm : ExtSetCCPat<SETLT,
3491                   PatFrag<(ops node:$in, node:$cc),
3492                           (setcc $in, 0, $cc)>,
3493                   OutPatFrag<(ops node:$in),
3494                              (RLWINM $in, 1, 31, 31)>,
3495                   OutPatFrag<(ops node:$in),
3496                              (RLDICL $in, 1, 63)> >;
3497
3498defm : ExtSetCCPat<SETGE,
3499                   PatFrag<(ops node:$in, node:$cc),
3500                           (setcc $in, 0, $cc)>,
3501                   OutPatFrag<(ops node:$in),
3502                              (RLWINM (i32not $in), 1, 31, 31)>,
3503                   OutPatFrag<(ops node:$in),
3504                              (RLDICL (i64not $in), 1, 63)> >;
3505
3506defm : ExtSetCCPat<SETGT,
3507                   PatFrag<(ops node:$in, node:$cc),
3508                           (setcc $in, 0, $cc)>,
3509                   OutPatFrag<(ops node:$in),
3510                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3511                   OutPatFrag<(ops node:$in),
3512                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3513
3514defm : ExtSetCCPat<SETLE,
3515                   PatFrag<(ops node:$in, node:$cc),
3516                           (setcc $in, 0, $cc)>,
3517                   OutPatFrag<(ops node:$in),
3518                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3519                   OutPatFrag<(ops node:$in),
3520                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3521
3522defm : ExtSetCCPat<SETLT,
3523                   PatFrag<(ops node:$in, node:$cc),
3524                           (setcc $in, -1, $cc)>,
3525                   OutPatFrag<(ops node:$in),
3526                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3527                   OutPatFrag<(ops node:$in),
3528                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3529
3530defm : ExtSetCCPat<SETGE,
3531                   PatFrag<(ops node:$in, node:$cc),
3532                           (setcc $in, -1, $cc)>,
3533                   OutPatFrag<(ops node:$in),
3534                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3535                   OutPatFrag<(ops node:$in),
3536                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3537
3538defm : ExtSetCCPat<SETGT,
3539                   PatFrag<(ops node:$in, node:$cc),
3540                           (setcc $in, -1, $cc)>,
3541                   OutPatFrag<(ops node:$in),
3542                              (RLWINM (i32not $in), 1, 31, 31)>,
3543                   OutPatFrag<(ops node:$in),
3544                              (RLDICL (i64not $in), 1, 63)> >;
3545
3546defm : ExtSetCCPat<SETLE,
3547                   PatFrag<(ops node:$in, node:$cc),
3548                           (setcc $in, -1, $cc)>,
3549                   OutPatFrag<(ops node:$in),
3550                              (RLWINM $in, 1, 31, 31)>,
3551                   OutPatFrag<(ops node:$in),
3552                              (RLDICL $in, 1, 63)> >;
3553
3554// An extended SETCC with shift amount.
3555multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
3556                            OutPatFrag rfrag, OutPatFrag rfrag8> {
3557  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3558            (rfrag $s1, $sa)>;
3559  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3560            (rfrag8 $s1, $sa)>;
3561  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3562            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3563  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3564            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3565
3566  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3567            (rfrag $s1, $sa)>;
3568  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3569            (rfrag8 $s1, $sa)>;
3570  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3571            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3572  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3573            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3574}
3575
3576defm : ExtSetCCShiftPat<SETNE,
3577                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3578                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3579                        OutPatFrag<(ops node:$in, node:$sa),
3580                                   (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
3581                        OutPatFrag<(ops node:$in, node:$sa),
3582                                   (RLDCL $in, (SUBFIC $sa, 64), 63)> >;
3583
3584defm : ExtSetCCShiftPat<SETEQ,
3585                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3586                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3587                        OutPatFrag<(ops node:$in, node:$sa),
3588                                   (RLWNM (i32not $in),
3589                                          (SUBFIC $sa, 32), 31, 31)>,
3590                        OutPatFrag<(ops node:$in, node:$sa),
3591                                   (RLDCL (i64not $in),
3592                                          (SUBFIC $sa, 64), 63)> >;
3593
3594// SETCC for i32.
3595def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3596          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3597def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3598          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3599def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3600          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3601def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3602          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3603def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3604          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3605def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3606          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3607
3608// For non-equality comparisons, the default code would materialize the
3609// constant, then compare against it, like this:
3610//   lis r2, 4660
3611//   ori r2, r2, 22136
3612//   cmpw cr0, r3, r2
3613//   beq cr0,L6
3614// Since we are just comparing for equality, we can emit this instead:
3615//   xoris r0,r3,0x1234
3616//   cmplwi cr0,r0,0x5678
3617//   beq cr0,L6
3618
3619def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3620          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3621                                  (LO16 imm:$imm)), sub_eq)>;
3622
3623defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3624                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3625defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3626                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3627defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3628                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3629defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3630                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3631defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3632                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3633defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3634                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3635
3636defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3637                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3638                                        (LO16 imm:$imm)), sub_eq)>;
3639
3640def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3641          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3642def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3643          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3644def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3645          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3646def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3647          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3648def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3649          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3650
3651defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3652                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3653defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3654                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3655defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3656                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3657defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3658                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3659defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3660                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3661
3662// SETCC for i64.
3663def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3664          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3665def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3666          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3667def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3668          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3669def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3670          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3671def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3672          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3673def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3674          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3675
3676// For non-equality comparisons, the default code would materialize the
3677// constant, then compare against it, like this:
3678//   lis r2, 4660
3679//   ori r2, r2, 22136
3680//   cmpd cr0, r3, r2
3681//   beq cr0,L6
3682// Since we are just comparing for equality, we can emit this instead:
3683//   xoris r0,r3,0x1234
3684//   cmpldi cr0,r0,0x5678
3685//   beq cr0,L6
3686
3687def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3688          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3689                                  (LO16 imm:$imm)), sub_eq)>;
3690
3691defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3692                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3693defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3694                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3695defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3696                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3697defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3698                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3699defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3700                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3701defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3702                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3703
3704defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3705                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3706                                        (LO16 imm:$imm)), sub_eq)>;
3707
3708def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3709          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3710def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3711          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3712def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3713          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3714def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3715          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3716def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3717          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3718
3719defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3720                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3721defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3722                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3723defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3724                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3725defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3726                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3727defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3728                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3729
3730// SETCC for f32.
3731let Predicates = [HasFPU] in {
3732def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3733          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3734def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3735          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3736def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3737          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3738def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3739          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3740def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3741          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3742def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3743          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3744def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3745          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3746
3747defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3748                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3749defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3750                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3751defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3752                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3753defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3754                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3755defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3756                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3757defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3758                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3759defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3760                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3761
3762// SETCC for f64.
3763def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3764          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3765def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3766          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3767def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3768          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3769def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3770          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3771def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3772          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3773def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3774          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3775def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3776          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3777
3778defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3779                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3780defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3781                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3782defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3783                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3784defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3785                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3786defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3787                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3788defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3789                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3790defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3791                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3792
3793// SETCC for f128.
3794def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOLT)),
3795          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3796def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETLT)),
3797          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3798def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOGT)),
3799          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3800def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETGT)),
3801          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3802def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOEQ)),
3803          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3804def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETEQ)),
3805          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3806def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETUO)),
3807          (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
3808
3809defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)),
3810                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3811defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)),
3812                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>;
3813defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)),
3814                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3815defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)),
3816                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>;
3817defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)),
3818                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3819defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)),
3820                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>;
3821defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)),
3822                (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>;
3823
3824}
3825
3826// This must be in this file because it relies on patterns defined in this file
3827// after the inclusion of the instruction sets.
3828let Predicates = [HasSPE] in {
3829// SETCC for f32.
3830def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3831          (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
3832def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3833          (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
3834def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3835          (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
3836def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3837          (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
3838def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3839          (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
3840def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3841          (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
3842
3843defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3844                (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
3845defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3846                (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>;
3847defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3848                (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
3849defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3850                (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>;
3851defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3852                (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
3853defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3854                (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>;
3855
3856// SETCC for f64.
3857def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3858          (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
3859def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3860          (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
3861def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3862          (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
3863def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3864          (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
3865def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3866          (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
3867def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3868          (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
3869
3870defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3871                (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
3872defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3873                (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>;
3874defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3875                (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
3876defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3877                (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>;
3878defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3879                (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
3880defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3881                (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>;
3882}
3883// match select on i1 variables:
3884def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3885          (CROR (CRAND        $cond , $tval),
3886                (CRAND (crnot $cond), $fval))>;
3887
3888// match selectcc on i1 variables:
3889//   select (lhs == rhs), tval, fval is:
3890//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3891def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3892           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3893                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3894def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3895           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3896                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3897def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3898           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3899                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3900def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3901           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3902                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3903def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3904           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3905                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3906def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3907           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3908                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3909def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3910           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3911                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3912def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3913           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3914                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3915def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3916           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3917                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3918def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3919           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3920                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3921
3922// match selectcc on i1 variables with non-i1 output.
3923def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3924          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3925def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3926          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3927def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3928          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3929def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3930          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3931def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3932          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3933def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3934          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3935def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3936          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3937def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3938          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3939def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3940          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3941def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3942          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3943
3944def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3945          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3946def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3947          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3948def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3949          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3950def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3951          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3952def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3953          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3954def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3955          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3956def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3957          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3958def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3959          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3960def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3961          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3962def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3963          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3964
3965let Predicates = [HasFPU] in {
3966def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3967          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3968def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3969          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3970def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3971          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3972def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3973          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3974def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3975          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3976def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3977          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3978def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3979          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3980def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3981          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3982def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3983          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3984def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3985          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3986
3987def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3988          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3989def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3990          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3991def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3992          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3993def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3994          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3995def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3996          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3997def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3998          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3999def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
4000          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
4001def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
4002          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
4003def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
4004          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
4005def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
4006          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
4007}
4008
4009def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)),
4010          (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
4011def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)),
4012          (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
4013def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)),
4014          (SELECT_F16 (CRORC  $lhs, $rhs), $tval, $fval)>;
4015def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)),
4016          (SELECT_F16 (CRORC  $rhs, $lhs), $tval, $fval)>;
4017def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)),
4018          (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>;
4019def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)),
4020         (SELECT_F16 (CRORC  $rhs, $lhs), $tval, $fval)>;
4021def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)),
4022          (SELECT_F16 (CRORC  $lhs, $rhs), $tval, $fval)>;
4023def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)),
4024          (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>;
4025def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)),
4026          (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>;
4027def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)),
4028          (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>;
4029
4030def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
4031          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
4032def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
4033          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
4034def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
4035          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
4036def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
4037          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
4038def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
4039          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
4040def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
4041          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
4042def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
4043          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
4044def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
4045          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
4046def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
4047          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
4048def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
4049          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
4050
4051def ANDIo_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
4052                             "#ANDIo_1_EQ_BIT",
4053                             [(set i1:$dst, (trunc (not i32:$in)))]>;
4054def ANDIo_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
4055                             "#ANDIo_1_GT_BIT",
4056                             [(set i1:$dst, (trunc i32:$in))]>;
4057
4058def ANDIo_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
4059                              "#ANDIo_1_EQ_BIT8",
4060                              [(set i1:$dst, (trunc (not i64:$in)))]>;
4061def ANDIo_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
4062                              "#ANDIo_1_GT_BIT8",
4063                              [(set i1:$dst, (trunc i64:$in))]>;
4064
4065def : Pat<(i1 (not (trunc i32:$in))),
4066           (ANDIo_1_EQ_BIT $in)>;
4067def : Pat<(i1 (not (trunc i64:$in))),
4068           (ANDIo_1_EQ_BIT8 $in)>;
4069
4070//===----------------------------------------------------------------------===//
4071// PowerPC Instructions used for assembler/disassembler only
4072//
4073
4074// FIXME: For B=0 or B > 8, the registers following RT are used.
4075// WARNING: Do not add patterns for this instruction without fixing this.
4076def LSWI  : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT),
4077                                  (ins gprc:$A, u5imm:$B),
4078                                  "lswi $RT, $A, $B", IIC_LdStLoad, []>;
4079
4080// FIXME: For B=0 or B > 8, the registers following RT are used.
4081// WARNING: Do not add patterns for this instruction without fixing this.
4082def STSWI : XForm_base_r3xo_memOp<31, 725, (outs),
4083                                  (ins gprc:$RT, gprc:$A, u5imm:$B),
4084                                  "stswi $RT, $A, $B", IIC_LdStLoad, []>;
4085
4086def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
4087                         "isync", IIC_SprISYNC, []>;
4088
4089def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
4090                    "icbi $src", IIC_LdStICBI, []>;
4091
4092// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
4093def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
4094                           "eieio", IIC_LdStLoad, []>;
4095
4096def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
4097                         "wait $L", IIC_LdStLoad, []>;
4098
4099def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
4100                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
4101
4102def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
4103            "mtsr $SR, $RS", IIC_SprMTSR>;
4104
4105def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
4106            "mfsr $RS, $SR", IIC_SprMFSR>;
4107
4108def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
4109            "mtsrin $RS, $RB", IIC_SprMTSR>;
4110
4111def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
4112            "mfsrin $RS, $RB", IIC_SprMFSR>;
4113
4114def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
4115                    "mtmsr $RS, $L", IIC_SprMTMSR>;
4116
4117def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
4118                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
4119  let L = 0;
4120}
4121
4122def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
4123              Requires<[IsBookE]> {
4124  bits<1> E;
4125
4126  let Inst{16} = E;
4127  let Inst{21-30} = 163;
4128}
4129
4130def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
4131               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
4132def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
4133               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
4134
4135def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
4136def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
4137def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
4138def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
4139
4140def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
4141                  "mfmsr $RT", IIC_SprMFMSR, []>;
4142
4143def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
4144                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
4145
4146def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
4147                     "mcrfs $BF, $BFA", IIC_BrMCR>;
4148
4149def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
4150                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
4151
4152def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
4153                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
4154
4155def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
4156def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
4157
4158let Predicates = [HasFPU] in {
4159def MTFSF : XFLForm_1<63, 711, (outs),
4160                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
4161                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
4162def MTFSFo : XFLForm_1<63, 711, (outs),
4163                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
4164                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
4165
4166def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
4167def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
4168}
4169
4170def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
4171                        "slbie $RB", IIC_SprSLBIE, []>;
4172
4173def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
4174                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
4175
4176def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
4177                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
4178
4179def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
4180                       "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
4181
4182def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
4183
4184let Defs = [CR0] in
4185def SLBFEEo : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB),
4186                         "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isDOT;
4187
4188def TLBIA : XForm_0<31, 370, (outs), (ins),
4189                        "tlbia", IIC_SprTLBIA, []>;
4190
4191def TLBSYNC : XForm_0<31, 566, (outs), (ins),
4192                        "tlbsync", IIC_SprTLBSYNC, []>;
4193
4194def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
4195                          "tlbiel $RB", IIC_SprTLBIEL, []>;
4196
4197def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
4198                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
4199def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
4200                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
4201
4202def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
4203                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
4204
4205def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
4206                IIC_LdStLoad>, Requires<[IsBookE]>;
4207
4208def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
4209                IIC_LdStLoad>, Requires<[IsBookE]>;
4210
4211def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
4212                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
4213
4214def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
4215                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
4216
4217def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
4218               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
4219
4220def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
4221               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
4222
4223def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
4224                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
4225                             Requires<[IsPPC4xx]>;
4226def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
4227                              (ins gprc:$RST, gprc:$A, gprc:$B),
4228                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
4229                              Requires<[IsPPC4xx]>, isDOT;
4230
4231def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
4232
4233def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
4234                  Requires<[IsBookE]>;
4235def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
4236                   Requires<[IsBookE]>;
4237
4238def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
4239                   Requires<[IsE500]>;
4240def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
4241                    Requires<[IsE500]>;
4242
4243def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
4244                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
4245def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
4246                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
4247
4248def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
4249def NAP   : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
4250
4251def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
4252
4253def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST),
4254                                  (ins gprc:$A, gprc:$B),
4255                                  "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
4256def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST),
4257                                  (ins gprc:$A, gprc:$B),
4258                                  "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
4259def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST),
4260                                  (ins gprc:$A, gprc:$B),
4261                                  "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
4262def LDCIX :  XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST),
4263                                  (ins gprc:$A, gprc:$B),
4264                                  "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
4265
4266def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs),
4267                                  (ins gprc:$RST, gprc:$A, gprc:$B),
4268                                  "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
4269def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs),
4270                                  (ins gprc:$RST, gprc:$A, gprc:$B),
4271                                  "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
4272def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs),
4273                                  (ins gprc:$RST, gprc:$A, gprc:$B),
4274                                  "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
4275def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs),
4276                                  (ins gprc:$RST, gprc:$A, gprc:$B),
4277                                  "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
4278
4279// External PID Load Store Instructions
4280
4281def LBEPX   : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src),
4282                      "lbepx $rD, $src", IIC_LdStLoad, []>,
4283                      Requires<[IsE500]>;
4284
4285def LFDEPX  : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src),
4286                      "lfdepx $frD, $src", IIC_LdStLFD, []>,
4287                      Requires<[IsE500]>;
4288
4289def LHEPX   : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src),
4290                      "lhepx $rD, $src", IIC_LdStLoad, []>,
4291                      Requires<[IsE500]>;
4292
4293def LWEPX   : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src),
4294                      "lwepx $rD, $src", IIC_LdStLoad, []>,
4295                      Requires<[IsE500]>;
4296
4297def STBEPX  : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst),
4298                      "stbepx $rS, $dst", IIC_LdStStore, []>,
4299                      Requires<[IsE500]>;
4300
4301def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst),
4302                      "stfdepx $frS, $dst", IIC_LdStSTFD, []>,
4303                      Requires<[IsE500]>;
4304
4305def STHEPX  : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst),
4306                      "sthepx $rS, $dst", IIC_LdStStore, []>,
4307                      Requires<[IsE500]>;
4308
4309def STWEPX  : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst),
4310                      "stwepx $rS, $dst", IIC_LdStStore, []>,
4311                      Requires<[IsE500]>;
4312
4313def DCBFEP  : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst",
4314                      IIC_LdStDCBF, []>, Requires<[IsE500]>;
4315
4316def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst",
4317                      IIC_LdStDCBF, []>, Requires<[IsE500]>;
4318
4319def DCBTEP  : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH),
4320                      "dcbtep $TH, $dst", IIC_LdStDCBF, []>,
4321                      Requires<[IsE500]>;
4322
4323def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH),
4324                      "dcbtstep $TH, $dst", IIC_LdStDCBF, []>,
4325                      Requires<[IsE500]>;
4326
4327def DCBZEP  : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst",
4328                      IIC_LdStDCBF, []>, Requires<[IsE500]>;
4329
4330def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst",
4331                      IIC_LdStDCBF, []>, Requires<[IsE500]>;
4332
4333def ICBIEP  : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src",
4334                      IIC_LdStICBI, []>, Requires<[IsE500]>;
4335
4336//===----------------------------------------------------------------------===//
4337// PowerPC Assembler Instruction Aliases
4338//
4339
4340// Pseudo-instructions for alternate assembly syntax (never used by codegen).
4341// These are aliases that require C++ handling to convert to the target
4342// instruction, while InstAliases can be handled directly by tblgen.
4343class PPCAsmPseudo<string asm, dag iops>
4344  : Instruction {
4345  let Namespace = "PPC";
4346  bit PPC64 = 0;  // Default value, override with isPPC64
4347
4348  let OutOperandList = (outs);
4349  let InOperandList = iops;
4350  let Pattern = [];
4351  let AsmString = asm;
4352  let isAsmParserOnly = 1;
4353  let isPseudo = 1;
4354  let hasNoSchedulingInfo = 1;
4355}
4356
4357def : InstAlias<"sc", (SC 0)>;
4358
4359def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
4360def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
4361def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
4362def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
4363
4364def : InstAlias<"wait", (WAIT 0)>;
4365def : InstAlias<"waitrsv", (WAIT 1)>;
4366def : InstAlias<"waitimpl", (WAIT 2)>;
4367
4368def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
4369
4370def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
4371def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
4372
4373def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
4374def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
4375def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
4376
4377def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
4378def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
4379def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
4380
4381def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
4382def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
4383def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
4384
4385def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
4386def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
4387def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
4388def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
4389
4390def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
4391def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
4392
4393def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
4394def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
4395
4396def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
4397def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
4398
4399def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
4400def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
4401
4402def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
4403def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
4404
4405def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
4406def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
4407
4408def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
4409def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
4410
4411def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
4412def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
4413
4414def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
4415def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
4416
4417def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4418def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
4419
4420def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4421def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
4422
4423def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
4424def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
4425
4426def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
4427def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
4428
4429def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
4430def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
4431
4432def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
4433def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
4434def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
4435
4436def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
4437def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
4438
4439def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
4440def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4441def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
4442def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4443
4444def : InstAlias<"xnop", (XORI R0, R0, 0)>;
4445
4446def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4447def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4448
4449def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4450def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4451
4452def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
4453
4454foreach BATR = 0-3 in {
4455    def : InstAlias<"mtdbatu "#BATR#", $Rx",
4456                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
4457                    Requires<[IsPPC6xx]>;
4458    def : InstAlias<"mfdbatu $Rx, "#BATR,
4459                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
4460                    Requires<[IsPPC6xx]>;
4461    def : InstAlias<"mtdbatl "#BATR#", $Rx",
4462                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
4463                    Requires<[IsPPC6xx]>;
4464    def : InstAlias<"mfdbatl $Rx, "#BATR,
4465                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
4466                    Requires<[IsPPC6xx]>;
4467    def : InstAlias<"mtibatu "#BATR#", $Rx",
4468                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
4469                    Requires<[IsPPC6xx]>;
4470    def : InstAlias<"mfibatu $Rx, "#BATR,
4471                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
4472                    Requires<[IsPPC6xx]>;
4473    def : InstAlias<"mtibatl "#BATR#", $Rx",
4474                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
4475                    Requires<[IsPPC6xx]>;
4476    def : InstAlias<"mfibatl $Rx, "#BATR,
4477                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
4478                    Requires<[IsPPC6xx]>;
4479}
4480
4481foreach BR = 0-7 in {
4482    def : InstAlias<"mfbr"#BR#" $Rx",
4483                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
4484                    Requires<[IsPPC4xx]>;
4485    def : InstAlias<"mtbr"#BR#" $Rx",
4486                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
4487                    Requires<[IsPPC4xx]>;
4488}
4489
4490def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4491def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
4492
4493def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4494def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
4495
4496def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4497def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
4498
4499def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4500def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
4501
4502def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
4503def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
4504
4505def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4506def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
4507
4508def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
4509
4510def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
4511                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4512def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
4513                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4514def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
4515                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4516def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
4517                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4518
4519def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4520def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4521def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4522def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4523
4524def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
4525def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
4526
4527def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
4528def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
4529
4530foreach SPRG = 0-3 in {
4531  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
4532  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
4533  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4534  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4535}
4536foreach SPRG = 4-7 in {
4537  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
4538                  Requires<[IsBookE]>;
4539  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
4540                  Requires<[IsBookE]>;
4541  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4542                  Requires<[IsBookE]>;
4543  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4544                  Requires<[IsBookE]>;
4545}
4546
4547def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
4548
4549def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
4550def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
4551
4552def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
4553
4554def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
4555def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
4556
4557def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
4558def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
4559def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
4560def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
4561
4562def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
4563
4564def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
4565                Requires<[IsPPC4xx]>;
4566def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
4567                Requires<[IsPPC4xx]>;
4568def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
4569                Requires<[IsPPC4xx]>;
4570def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
4571                Requires<[IsPPC4xx]>;
4572
4573def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
4574                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4575def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
4576                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4577def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
4578                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4579def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
4580                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4581def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
4582                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4583def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
4584                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4585def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
4586                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4587def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
4588                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4589def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
4590                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4591def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
4592                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4593def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
4594                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4595def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
4596                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4597def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
4598                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4599def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
4600                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4601def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
4602                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4603def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
4604                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4605def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
4606                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4607def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
4608                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4609
4610def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4611def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4612def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4613def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4614def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4615def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4616
4617def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
4618def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
4619// The POWER variant
4620def : MnemonicAlias<"cntlz",  "cntlzw">;
4621def : MnemonicAlias<"cntlz.", "cntlzw.">;
4622
4623def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
4624                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4625def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
4626                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4627def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
4628                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4629def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
4630                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4631def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
4632                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4633def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
4634                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4635def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
4636                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4637def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
4638                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4639def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
4640                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4641def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
4642                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4643def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
4644                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4645def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
4646                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4647def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
4648                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4649def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
4650                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4651def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
4652                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4653def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
4654                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4655def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
4656
4657def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4658def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4659def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4660def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4661def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4662def : InstAlias<"clrldi $rA, $rS, $n",
4663                (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;
4664def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4665def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;
4666
4667def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
4668                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4669def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
4670                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4671def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
4672                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4673def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
4674                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4675def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
4676                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4677def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
4678                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4679
4680// These generic branch instruction forms are used for the assembler parser only.
4681// Defs and Uses are conservative, since we don't know the BO value.
4682let PPC970_Unit = 7, isBranch = 1 in {
4683  let Defs = [CTR], Uses = [CTR, RM] in {
4684    def gBC : BForm_3<16, 0, 0, (outs),
4685                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4686                      "bc $bo, $bi, $dst">;
4687    def gBCA : BForm_3<16, 1, 0, (outs),
4688                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4689                       "bca $bo, $bi, $dst">;
4690    let isAsmParserOnly = 1 in {
4691      def gBCat : BForm_3_at<16, 0, 0, (outs),
4692                             (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4693                                  condbrtarget:$dst),
4694                                  "bc$at $bo, $bi, $dst">;
4695      def gBCAat : BForm_3_at<16, 1, 0, (outs),
4696                              (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4697                                   abscondbrtarget:$dst),
4698                                   "bca$at $bo, $bi, $dst">;
4699    } // isAsmParserOnly = 1
4700  }
4701  let Defs = [LR, CTR], Uses = [CTR, RM] in {
4702    def gBCL : BForm_3<16, 0, 1, (outs),
4703                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4704                       "bcl $bo, $bi, $dst">;
4705    def gBCLA : BForm_3<16, 1, 1, (outs),
4706                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4707                        "bcla $bo, $bi, $dst">;
4708    let isAsmParserOnly = 1 in {
4709      def gBCLat : BForm_3_at<16, 0, 1, (outs),
4710                         (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4711                              condbrtarget:$dst),
4712                              "bcl$at $bo, $bi, $dst">;
4713      def gBCLAat : BForm_3_at<16, 1, 1, (outs),
4714                          (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4715                               abscondbrtarget:$dst),
4716                               "bcla$at $bo, $bi, $dst">;
4717    } // // isAsmParserOnly = 1
4718  }
4719  let Defs = [CTR], Uses = [CTR, LR, RM] in
4720    def gBCLR : XLForm_2<19, 16, 0, (outs),
4721                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4722                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
4723  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4724    def gBCLRL : XLForm_2<19, 16, 1, (outs),
4725                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4726                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
4727  let Defs = [CTR], Uses = [CTR, LR, RM] in
4728    def gBCCTR : XLForm_2<19, 528, 0, (outs),
4729                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4730                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
4731  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4732    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
4733                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4734                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
4735}
4736
4737multiclass BranchSimpleMnemonicAT<string pm, int at> {
4738  def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,
4739                                                    condbrtarget:$dst)>;
4740  def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,
4741                                                      condbrtarget:$dst)>;
4742  def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,
4743                                                      condbrtarget:$dst)>;
4744  def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi,
4745                                                        condbrtarget:$dst)>;
4746}
4747defm : BranchSimpleMnemonicAT<"+", 3>;
4748defm : BranchSimpleMnemonicAT<"-", 2>;
4749
4750def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
4751def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4752def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4753def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4754
4755multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4756  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4757  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4758  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4759  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4760  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4761  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4762}
4763multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4764  : BranchSimpleMnemonic1<name, pm, bo> {
4765  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4766  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4767}
4768defm : BranchSimpleMnemonic2<"t", "", 12>;
4769defm : BranchSimpleMnemonic2<"f", "", 4>;
4770defm : BranchSimpleMnemonic2<"t", "-", 14>;
4771defm : BranchSimpleMnemonic2<"f", "-", 6>;
4772defm : BranchSimpleMnemonic2<"t", "+", 15>;
4773defm : BranchSimpleMnemonic2<"f", "+", 7>;
4774defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4775defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4776defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4777defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4778
4779multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4780  def : InstAlias<"b"#name#pm#" $cc, $dst",
4781                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4782  def : InstAlias<"b"#name#pm#" $dst",
4783                  (BCC bibo, CR0, condbrtarget:$dst)>;
4784
4785  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4786                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4787  def : InstAlias<"b"#name#"a"#pm#" $dst",
4788                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4789
4790  def : InstAlias<"b"#name#"lr"#pm#" $cc",
4791                  (BCCLR bibo, crrc:$cc)>;
4792  def : InstAlias<"b"#name#"lr"#pm,
4793                  (BCCLR bibo, CR0)>;
4794
4795  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4796                  (BCCCTR bibo, crrc:$cc)>;
4797  def : InstAlias<"b"#name#"ctr"#pm,
4798                  (BCCCTR bibo, CR0)>;
4799
4800  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4801                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4802  def : InstAlias<"b"#name#"l"#pm#" $dst",
4803                  (BCCL bibo, CR0, condbrtarget:$dst)>;
4804
4805  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4806                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4807  def : InstAlias<"b"#name#"la"#pm#" $dst",
4808                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4809
4810  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4811                  (BCCLRL bibo, crrc:$cc)>;
4812  def : InstAlias<"b"#name#"lrl"#pm,
4813                  (BCCLRL bibo, CR0)>;
4814
4815  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4816                  (BCCCTRL bibo, crrc:$cc)>;
4817  def : InstAlias<"b"#name#"ctrl"#pm,
4818                  (BCCCTRL bibo, CR0)>;
4819}
4820multiclass BranchExtendedMnemonic<string name, int bibo> {
4821  defm : BranchExtendedMnemonicPM<name, "", bibo>;
4822  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4823  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4824}
4825defm : BranchExtendedMnemonic<"lt", 12>;
4826defm : BranchExtendedMnemonic<"gt", 44>;
4827defm : BranchExtendedMnemonic<"eq", 76>;
4828defm : BranchExtendedMnemonic<"un", 108>;
4829defm : BranchExtendedMnemonic<"so", 108>;
4830defm : BranchExtendedMnemonic<"ge", 4>;
4831defm : BranchExtendedMnemonic<"nl", 4>;
4832defm : BranchExtendedMnemonic<"le", 36>;
4833defm : BranchExtendedMnemonic<"ng", 36>;
4834defm : BranchExtendedMnemonic<"ne", 68>;
4835defm : BranchExtendedMnemonic<"nu", 100>;
4836defm : BranchExtendedMnemonic<"ns", 100>;
4837
4838def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4839def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4840def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4841def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4842def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4843def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4844def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4845def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4846
4847def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4848def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4849def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4850def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4851def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4852def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4853def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4854def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4855
4856multiclass TrapExtendedMnemonic<string name, int to> {
4857  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4858  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4859  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4860  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4861}
4862defm : TrapExtendedMnemonic<"lt", 16>;
4863defm : TrapExtendedMnemonic<"le", 20>;
4864defm : TrapExtendedMnemonic<"eq", 4>;
4865defm : TrapExtendedMnemonic<"ge", 12>;
4866defm : TrapExtendedMnemonic<"gt", 8>;
4867defm : TrapExtendedMnemonic<"nl", 12>;
4868defm : TrapExtendedMnemonic<"ne", 24>;
4869defm : TrapExtendedMnemonic<"ng", 20>;
4870defm : TrapExtendedMnemonic<"llt", 2>;
4871defm : TrapExtendedMnemonic<"lle", 6>;
4872defm : TrapExtendedMnemonic<"lge", 5>;
4873defm : TrapExtendedMnemonic<"lgt", 1>;
4874defm : TrapExtendedMnemonic<"lnl", 5>;
4875defm : TrapExtendedMnemonic<"lng", 6>;
4876defm : TrapExtendedMnemonic<"u", 31>;
4877
4878// Atomic loads
4879def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
4880def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
4881def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
4882def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
4883def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4884def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4885
4886// Atomic stores
4887def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4888def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4889def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4890def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4891def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4892def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4893
4894let Predicates = [IsISA3_0] in {
4895
4896// Copy-Paste Facility
4897// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
4898// PASTE for naming consistency.
4899let mayLoad = 1 in
4900def CP_COPY   : X_L1_RA5_RB5<31, 774, "copy"  , gprc, IIC_LdStCOPY, []>;
4901
4902let mayStore = 1 in
4903def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
4904
4905let mayStore = 1, Defs = [CR0] in
4906def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
4907
4908def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
4909def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
4910def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
4911                                  (ins gprc:$rA, gprc:$rB)>;
4912def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
4913                                  (ins gprc:$rA, gprc:$rB)>;
4914def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
4915
4916// Message Synchronize
4917def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
4918
4919// Power-Saving Mode Instruction:
4920def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
4921
4922} // IsISA3_0
4923
4924// Fast 32-bit reverse bits algorithm:
4925// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
4926// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);
4927// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):
4928// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC);
4929// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):
4930// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0);
4931// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]):
4932// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes):
4933// n' = (n rotl 24);  After which n' = [B4, B1, B2, B3]
4934// Step 4.2: Insert B3 to the right position:
4935// n' = rlwimi n', n, 8, 8, 15;  After which n' = [B4, B3, B2, B3]
4936// Step 4.3: Insert B1 to the right position:
4937// n' = rlwimi n', n, 8, 24, 31;  After which n' = [B4, B3, B2, B1]
4938def MaskValues {
4939  dag Lo1 = (ORI (LIS 0x5555), 0x5555);
4940  dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
4941  dag Lo2 = (ORI (LIS 0x3333), 0x3333);
4942  dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
4943  dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
4944  dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0);
4945}
4946
4947def Shift1 {
4948  dag Right = (RLWINM $A, 31, 1, 31);
4949  dag Left = (RLWINM $A, 1, 0, 30);
4950}
4951
4952def Swap1 {
4953  dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
4954   (AND Shift1.Left, MaskValues.Hi1));
4955}
4956
4957def Shift2 {
4958  dag Right = (RLWINM Swap1.Bit, 30, 2, 31);
4959  dag Left = (RLWINM Swap1.Bit, 2, 0, 29);
4960}
4961
4962def Swap2 {
4963  dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
4964                 (AND Shift2.Left, MaskValues.Hi2));
4965}
4966
4967def Shift4 {
4968  dag Right = (RLWINM Swap2.Bits, 28, 4, 31);
4969  dag Left = (RLWINM Swap2.Bits, 4, 0, 27);
4970}
4971
4972def Swap4 {
4973  dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4),
4974                 (AND Shift4.Left, MaskValues.Hi4));
4975}
4976
4977def Rotate {
4978  dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31);
4979}
4980
4981def RotateInsertByte3 {
4982  dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15);
4983}
4984
4985def RotateInsertByte1 {
4986  dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31);
4987}
4988
4989def : Pat<(i32 (bitreverse i32:$A)),
4990  (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
4991
4992// Fast 64-bit reverse bits algorithm:
4993// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
4994// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA);
4995// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):
4996// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC);
4997// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):
4998// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0);
4999// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]):
5000// Apply the same byte reverse algorithm mentioned above for the fast 32-bit
5001// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And
5002// then OR them together to get the final result.
5003def MaskValues64 {
5004  dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32));
5005  dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));
5006  dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32));
5007  dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32));
5008  dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32));
5009  dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32));
5010}
5011
5012def DWMaskValues {
5013  dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555);
5014  dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);
5015  dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333);
5016  dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC);
5017  dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F);
5018  dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0);
5019}
5020
5021def DWSwapInByte {
5022  dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1),
5023                   (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));
5024  dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2),
5025                   (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2));
5026  dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4),
5027                   (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4));
5028}
5029
5030// Intra-byte swap is done, now start inter-byte swap.
5031def DWBytes4567 {
5032  dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32));
5033}
5034
5035def DWBytes7456 {
5036  dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31);
5037}
5038
5039def DWBytes7656 {
5040  dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15);
5041}
5042
5043// B7 B6 B5 B4 in the right order
5044def DWBytes7654 {
5045  dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31);
5046  dag DWord =
5047    (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32));
5048}
5049
5050def DWBytes0123 {
5051  dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32));
5052}
5053
5054def DWBytes3012 {
5055  dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31);
5056}
5057
5058def DWBytes3212 {
5059  dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15);
5060}
5061
5062// B3 B2 B1 B0 in the right order
5063def DWBytes3210 {
5064  dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31);
5065  dag DWord =
5066    (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32));
5067}
5068
5069// Now both high word and low word are reversed, next
5070// swap the high word and low word.
5071def : Pat<(i64 (bitreverse i64:$A)),
5072  (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
5073