1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPClbrx : SDTypeProfile<1, 2, [ 78 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 79]>; 80def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83 84def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 85 SDTCisPtrTy<0>, SDTCisVT<1, i32> 86]>; 87 88def tocentry32 : Operand<iPTR> { 89 let MIOperandInfo = (ops i32imm:$imm); 90} 91 92def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 93 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 94]>; 95def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 96 SDTCisVec<0>, SDTCisInt<1> 97]>; 98def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 99 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 100]>; 101def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 102 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 103]>; 104 105def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 106 SDTCisVec<0>, SDTCisVec<1> 107]>; 108 109def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 110 SDTCisVec<0>, SDTCisPtrTy<1> 111]>; 112 113def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 115]>; 116 117def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 118 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 119]>; 120 121//===----------------------------------------------------------------------===// 122// PowerPC specific DAG Nodes. 123// 124 125def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 126def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 127 128def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 129def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 130def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 131def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 132def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 133def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 134def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 135def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 136 137def PPCcv_fp_to_uint_in_vsr: 138 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 139def PPCcv_fp_to_sint_in_vsr: 140 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 141def PPCstore_scal_int_from_vsr: 142 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 143 [SDNPHasChain, SDNPMayStore]>; 144def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 145 [SDNPHasChain, SDNPMayStore]>; 146def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 147 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 148def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 149 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 150def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 151 [SDNPHasChain, SDNPMayLoad]>; 152def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 153 [SDNPHasChain, SDNPMayStore]>; 154def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 155 156// Extract FPSCR (not modeled at the DAG level). 157def PPCmffs : SDNode<"PPCISD::MFFS", 158 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 159 [SDNPHasChain]>; 160 161// Perform FADD in round-to-zero mode. 162def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 163 164 165def PPCfsel : SDNode<"PPCISD::FSEL", 166 // Type constraint for fsel. 167 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 168 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 169def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; 170def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; 171def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 172def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 173def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 174 [SDNPMayLoad, SDNPMemOperand]>; 175 176def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 177 178def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 179def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 180 [SDNPMayLoad]>; 181def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 182def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 183def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 184def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 185def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 186 SDTypeProfile<1, 3, [ 187 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 188 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 189def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 190def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 191def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 192def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 193 SDTypeProfile<1, 3, [ 194 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 195 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 196def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 197def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 198 199def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 200def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 201def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 202def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 203def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 204def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 205 206def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>; 207def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>; 208def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>; 209def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>; 210 211def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>; 212 213def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb, 214 [SDNPHasChain, SDNPMayLoad]>; 215 216def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 217 218// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 219// amounts. These nodes are generated by the multi-precision shift code. 220def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 221def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 222def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 223 224def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 225 226def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 227 228// Move 2 i64 values into a VSX register 229def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 230 SDTypeProfile<1, 2, 231 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 232 SDTCisSameAs<1,2>]>, 233 []>; 234 235def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 236 SDTypeProfile<1, 2, 237 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 238 SDTCisVT<1,i32>]>, 239 []>; 240 241def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 242 SDTypeProfile<1, 2, 243 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 244 SDTCisPtrTy<2>]>, 245 []>; 246 247// These are target-independent nodes, but have target-specific formats. 248def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 249 [SDNPHasChain, SDNPOutGlue]>; 250def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 252 253def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 254def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 255 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 256 SDNPVariadic]>; 257def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 258 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 259 SDNPVariadic]>; 260def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 261 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 262 SDNPVariadic]>; 263def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 264 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 265def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 266 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 267 SDNPVariadic]>; 268def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 269 SDTypeProfile<0, 1, []>, 270 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 271 SDNPVariadic]>; 272 273def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 274 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 275 276def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 277 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 278 279def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 280 SDTypeProfile<1, 1, [SDTCisInt<0>, 281 SDTCisPtrTy<1>]>, 282 [SDNPHasChain, SDNPSideEffect]>; 283def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 284 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 285 [SDNPHasChain, SDNPSideEffect]>; 286 287def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 288def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 289 [SDNPHasChain, SDNPSideEffect]>; 290 291def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 292 [SDNPHasChain, SDNPSideEffect]>; 293def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 294def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 295 [SDNPHasChain, SDNPSideEffect]>; 296 297def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 298def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 299 300def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 301 [SDNPHasChain, SDNPOptInGlue]>; 302 303// PPC-specific atomic operations. 304def PPCatomicCmpSwap_8 : 305 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 306 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 307def PPCatomicCmpSwap_16 : 308 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 309 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 310def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 311 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 312def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 313 [SDNPHasChain, SDNPMayStore]>; 314 315// Instructions to set/unset CR bit 6 for SVR4 vararg calls 316def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 317 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 318def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 319 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 320 321// Instructions to support dynamic alloca. 322def SDTDynOp : SDTypeProfile<1, 2, []>; 323def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 324def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 325def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 326def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 327 328// PC Relative Specific Nodes 329def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 330 331//===----------------------------------------------------------------------===// 332// PowerPC specific transformation functions and pattern fragments. 333// 334 335// A floating point immediate that is not a positive zero and can be converted 336// to a single precision floating point non-denormal immediate without loss of 337// information. 338def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 339 APFloat APFloatOfN = N->getValueAPF(); 340 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 341}]>; 342 343// Convert the floating point immediate into a 32 bit floating point immediate 344// and get a i32 with the resulting bits. 345def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 346 APFloat APFloatOfN = N->getValueAPF(); 347 convertToNonDenormSingle(APFloatOfN); 348 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 349 SDLoc(N), MVT::i32); 350}]>; 351 352def SHL32 : SDNodeXForm<imm, [{ 353 // Transformation function: 31 - imm 354 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 355}]>; 356 357def SRL32 : SDNodeXForm<imm, [{ 358 // Transformation function: 32 - imm 359 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 360 : getI32Imm(0, SDLoc(N)); 361}]>; 362 363def LO16 : SDNodeXForm<imm, [{ 364 // Transformation function: get the low 16 bits. 365 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 366}]>; 367 368def HI16 : SDNodeXForm<imm, [{ 369 // Transformation function: shift the immediate value down into the low bits. 370 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 371}]>; 372 373def HA16 : SDNodeXForm<imm, [{ 374 // Transformation function: shift the immediate value down into the low bits. 375 long Val = N->getZExtValue(); 376 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 377}]>; 378def MB : SDNodeXForm<imm, [{ 379 // Transformation function: get the start bit of a mask 380 unsigned mb = 0, me; 381 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 382 return getI32Imm(mb, SDLoc(N)); 383}]>; 384 385def ME : SDNodeXForm<imm, [{ 386 // Transformation function: get the end bit of a mask 387 unsigned mb, me = 0; 388 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 389 return getI32Imm(me, SDLoc(N)); 390}]>; 391def maskimm32 : PatLeaf<(imm), [{ 392 // maskImm predicate - True if immediate is a run of ones. 393 unsigned mb, me; 394 if (N->getValueType(0) == MVT::i32) 395 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 396 else 397 return false; 398}]>; 399 400def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 401 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 402 // sign extended field. Used by instructions like 'addi'. 403 return (int32_t)Imm == (short)Imm; 404}]>; 405def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 406 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 407 // sign extended field. Used by instructions like 'addi'. 408 return (int64_t)Imm == (short)Imm; 409}]>; 410def immZExt16 : PatLeaf<(imm), [{ 411 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 412 // field. Used by instructions like 'ori'. 413 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 414}], LO16>; 415def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 416 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 417}]>; 418def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 419def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 420 421// imm16Shifted* - These match immediates where the low 16-bits are zero. There 422// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 423// identical in 32-bit mode, but in 64-bit mode, they return true if the 424// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 425// clear). 426def imm16ShiftedZExt : PatLeaf<(imm), [{ 427 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 428 // immediate are set. Used by instructions like 'xoris'. 429 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 430}], HI16>; 431 432def imm16ShiftedSExt : PatLeaf<(imm), [{ 433 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 434 // immediate are set. Used by instructions like 'addis'. Identical to 435 // imm16ShiftedZExt in 32-bit mode. 436 if (N->getZExtValue() & 0xFFFF) return false; 437 if (N->getValueType(0) == MVT::i32) 438 return true; 439 // For 64-bit, make sure it is sext right. 440 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 441}], HI16>; 442 443def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 444 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 445 // zero extended field. 446 return isUInt<32>(Imm); 447}]>; 448 449// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 450// restricted memrix (4-aligned) constants are alignment sensitive. If these 451// offsets are hidden behind TOC entries than the values of the lower-order 452// bits cannot be checked directly. As a result, we need to also incorporate 453// an alignment check into the relevant patterns. 454 455def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 456 return cast<LoadSDNode>(N)->getAlignment() >= 4; 457}]>; 458def aligned4store : PatFrag<(ops node:$val, node:$ptr), 459 (store node:$val, node:$ptr), [{ 460 return cast<StoreSDNode>(N)->getAlignment() >= 4; 461}]>; 462def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 463 return cast<LoadSDNode>(N)->getAlignment() >= 4; 464}]>; 465def aligned4pre_store : PatFrag< 466 (ops node:$val, node:$base, node:$offset), 467 (pre_store node:$val, node:$base, node:$offset), [{ 468 return cast<StoreSDNode>(N)->getAlignment() >= 4; 469}]>; 470 471def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 472 return cast<LoadSDNode>(N)->getAlignment() < 4; 473}]>; 474def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 475 (store node:$val, node:$ptr), [{ 476 return cast<StoreSDNode>(N)->getAlignment() < 4; 477}]>; 478def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 479 return cast<LoadSDNode>(N)->getAlignment() < 4; 480}]>; 481 482// This is a somewhat weaker condition than actually checking for 16-byte 483// alignment. It is simply checking that the displacement can be represented 484// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 485// instructions). 486def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 487 return isOffsetMultipleOf(N, 16); 488}]>; 489def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 490 (store node:$val, node:$ptr), [{ 491 return isOffsetMultipleOf(N, 16); 492}]>; 493def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 494 return !isOffsetMultipleOf(N, 16); 495}]>; 496def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 497 (store node:$val, node:$ptr), [{ 498 return !isOffsetMultipleOf(N, 16); 499}]>; 500 501// PatFrag for binary operation whose operands are both non-constant 502class BinOpWithoutSImm16Operand<SDNode opcode> : 503 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 504 int16_t Imm; 505 return !isIntS16Immediate(N->getOperand(0), Imm) 506 && !isIntS16Immediate(N->getOperand(1), Imm); 507}]>; 508 509def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 510def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 511 512//===----------------------------------------------------------------------===// 513// PowerPC Flag Definitions. 514 515class isPPC64 { bit PPC64 = 1; } 516class isRecordForm { bit RC = 1; } 517 518class RegConstraint<string C> { 519 string Constraints = C; 520} 521class NoEncode<string E> { 522 string DisableEncoding = E; 523} 524 525 526//===----------------------------------------------------------------------===// 527// PowerPC Operand Definitions. 528 529// In the default PowerPC assembler syntax, registers are specified simply 530// by number, so they cannot be distinguished from immediate values (without 531// looking at the opcode). This means that the default operand matching logic 532// for the asm parser does not work, and we need to specify custom matchers. 533// Since those can only be specified with RegisterOperand classes and not 534// directly on the RegisterClass, all instructions patterns used by the asm 535// parser need to use a RegisterOperand (instead of a RegisterClass) for 536// all their register operands. 537// For this purpose, we define one RegisterOperand for each RegisterClass, 538// using the same name as the class, just in lower case. 539 540def PPCRegGPRCAsmOperand : AsmOperandClass { 541 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 542} 543def gprc : RegisterOperand<GPRC> { 544 let ParserMatchClass = PPCRegGPRCAsmOperand; 545} 546def PPCRegG8RCAsmOperand : AsmOperandClass { 547 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 548} 549def g8rc : RegisterOperand<G8RC> { 550 let ParserMatchClass = PPCRegG8RCAsmOperand; 551} 552def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 553 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 554} 555def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 556 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 557} 558def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 559 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 560} 561def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 562 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 563} 564def PPCRegF8RCAsmOperand : AsmOperandClass { 565 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 566} 567def f8rc : RegisterOperand<F8RC> { 568 let ParserMatchClass = PPCRegF8RCAsmOperand; 569} 570def PPCRegF4RCAsmOperand : AsmOperandClass { 571 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 572} 573def f4rc : RegisterOperand<F4RC> { 574 let ParserMatchClass = PPCRegF4RCAsmOperand; 575} 576def PPCRegVRRCAsmOperand : AsmOperandClass { 577 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 578} 579def vrrc : RegisterOperand<VRRC> { 580 let ParserMatchClass = PPCRegVRRCAsmOperand; 581} 582def PPCRegVFRCAsmOperand : AsmOperandClass { 583 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 584} 585def vfrc : RegisterOperand<VFRC> { 586 let ParserMatchClass = PPCRegVFRCAsmOperand; 587} 588def PPCRegCRBITRCAsmOperand : AsmOperandClass { 589 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 590} 591def crbitrc : RegisterOperand<CRBITRC> { 592 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 593} 594def PPCRegCRRCAsmOperand : AsmOperandClass { 595 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 596} 597def crrc : RegisterOperand<CRRC> { 598 let ParserMatchClass = PPCRegCRRCAsmOperand; 599} 600def PPCRegSPERCAsmOperand : AsmOperandClass { 601 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 602} 603def sperc : RegisterOperand<SPERC> { 604 let ParserMatchClass = PPCRegSPERCAsmOperand; 605} 606def PPCRegSPE4RCAsmOperand : AsmOperandClass { 607 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 608} 609def spe4rc : RegisterOperand<GPRC> { 610 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 611} 612 613def PPCU1ImmAsmOperand : AsmOperandClass { 614 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 615 let RenderMethod = "addImmOperands"; 616} 617def u1imm : Operand<i32> { 618 let PrintMethod = "printU1ImmOperand"; 619 let ParserMatchClass = PPCU1ImmAsmOperand; 620} 621 622def PPCU2ImmAsmOperand : AsmOperandClass { 623 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 624 let RenderMethod = "addImmOperands"; 625} 626def u2imm : Operand<i32> { 627 let PrintMethod = "printU2ImmOperand"; 628 let ParserMatchClass = PPCU2ImmAsmOperand; 629} 630 631def PPCATBitsAsHintAsmOperand : AsmOperandClass { 632 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 633 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 634} 635def atimm : Operand<i32> { 636 let PrintMethod = "printATBitsAsHint"; 637 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 638} 639 640def PPCU3ImmAsmOperand : AsmOperandClass { 641 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 642 let RenderMethod = "addImmOperands"; 643} 644def u3imm : Operand<i32> { 645 let PrintMethod = "printU3ImmOperand"; 646 let ParserMatchClass = PPCU3ImmAsmOperand; 647} 648 649def PPCU4ImmAsmOperand : AsmOperandClass { 650 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 651 let RenderMethod = "addImmOperands"; 652} 653def u4imm : Operand<i32> { 654 let PrintMethod = "printU4ImmOperand"; 655 let ParserMatchClass = PPCU4ImmAsmOperand; 656} 657def PPCS5ImmAsmOperand : AsmOperandClass { 658 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 659 let RenderMethod = "addImmOperands"; 660} 661def s5imm : Operand<i32> { 662 let PrintMethod = "printS5ImmOperand"; 663 let ParserMatchClass = PPCS5ImmAsmOperand; 664 let DecoderMethod = "decodeSImmOperand<5>"; 665} 666def PPCU5ImmAsmOperand : AsmOperandClass { 667 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 668 let RenderMethod = "addImmOperands"; 669} 670def u5imm : Operand<i32> { 671 let PrintMethod = "printU5ImmOperand"; 672 let ParserMatchClass = PPCU5ImmAsmOperand; 673 let DecoderMethod = "decodeUImmOperand<5>"; 674} 675def PPCU6ImmAsmOperand : AsmOperandClass { 676 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 677 let RenderMethod = "addImmOperands"; 678} 679def u6imm : Operand<i32> { 680 let PrintMethod = "printU6ImmOperand"; 681 let ParserMatchClass = PPCU6ImmAsmOperand; 682 let DecoderMethod = "decodeUImmOperand<6>"; 683} 684def PPCU7ImmAsmOperand : AsmOperandClass { 685 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 686 let RenderMethod = "addImmOperands"; 687} 688def u7imm : Operand<i32> { 689 let PrintMethod = "printU7ImmOperand"; 690 let ParserMatchClass = PPCU7ImmAsmOperand; 691 let DecoderMethod = "decodeUImmOperand<7>"; 692} 693def PPCU8ImmAsmOperand : AsmOperandClass { 694 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 695 let RenderMethod = "addImmOperands"; 696} 697def u8imm : Operand<i32> { 698 let PrintMethod = "printU8ImmOperand"; 699 let ParserMatchClass = PPCU8ImmAsmOperand; 700 let DecoderMethod = "decodeUImmOperand<8>"; 701} 702def PPCU10ImmAsmOperand : AsmOperandClass { 703 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 704 let RenderMethod = "addImmOperands"; 705} 706def u10imm : Operand<i32> { 707 let PrintMethod = "printU10ImmOperand"; 708 let ParserMatchClass = PPCU10ImmAsmOperand; 709 let DecoderMethod = "decodeUImmOperand<10>"; 710} 711def PPCU12ImmAsmOperand : AsmOperandClass { 712 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 713 let RenderMethod = "addImmOperands"; 714} 715def u12imm : Operand<i32> { 716 let PrintMethod = "printU12ImmOperand"; 717 let ParserMatchClass = PPCU12ImmAsmOperand; 718 let DecoderMethod = "decodeUImmOperand<12>"; 719} 720def PPCS16ImmAsmOperand : AsmOperandClass { 721 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 722 let RenderMethod = "addS16ImmOperands"; 723} 724def s16imm : Operand<i32> { 725 let PrintMethod = "printS16ImmOperand"; 726 let EncoderMethod = "getImm16Encoding"; 727 let ParserMatchClass = PPCS16ImmAsmOperand; 728 let DecoderMethod = "decodeSImmOperand<16>"; 729} 730def PPCU16ImmAsmOperand : AsmOperandClass { 731 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 732 let RenderMethod = "addU16ImmOperands"; 733} 734def u16imm : Operand<i32> { 735 let PrintMethod = "printU16ImmOperand"; 736 let EncoderMethod = "getImm16Encoding"; 737 let ParserMatchClass = PPCU16ImmAsmOperand; 738 let DecoderMethod = "decodeUImmOperand<16>"; 739} 740def PPCS17ImmAsmOperand : AsmOperandClass { 741 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 742 let RenderMethod = "addS16ImmOperands"; 743} 744def s17imm : Operand<i32> { 745 // This operand type is used for addis/lis to allow the assembler parser 746 // to accept immediates in the range -65536..65535 for compatibility with 747 // the GNU assembler. The operand is treated as 16-bit otherwise. 748 let PrintMethod = "printS16ImmOperand"; 749 let EncoderMethod = "getImm16Encoding"; 750 let ParserMatchClass = PPCS17ImmAsmOperand; 751 let DecoderMethod = "decodeSImmOperand<16>"; 752} 753def PPCS34ImmAsmOperand : AsmOperandClass { 754 let Name = "S34Imm"; 755 let PredicateMethod = "isS34Imm"; 756 let RenderMethod = "addImmOperands"; 757} 758def s34imm : Operand<i64> { 759 let PrintMethod = "printS34ImmOperand"; 760 let EncoderMethod = "getImm34Encoding"; 761 let ParserMatchClass = PPCS34ImmAsmOperand; 762 let DecoderMethod = "decodeSImmOperand<34>"; 763} 764def PPCImmZeroAsmOperand : AsmOperandClass { 765 let Name = "ImmZero"; 766 let PredicateMethod = "isImmZero"; 767 let RenderMethod = "addImmOperands"; 768} 769def immZero : Operand<i32> { 770 let PrintMethod = "printImmZeroOperand"; 771 let ParserMatchClass = PPCImmZeroAsmOperand; 772 let DecoderMethod = "decodeImmZeroOperand"; 773} 774 775def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 776 777def PPCDirectBrAsmOperand : AsmOperandClass { 778 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 779 let RenderMethod = "addBranchTargetOperands"; 780} 781def directbrtarget : Operand<OtherVT> { 782 let PrintMethod = "printBranchOperand"; 783 let EncoderMethod = "getDirectBrEncoding"; 784 let DecoderMethod = "decodeDirectBrTarget"; 785 let ParserMatchClass = PPCDirectBrAsmOperand; 786 let OperandType = "OPERAND_PCREL"; 787} 788def absdirectbrtarget : Operand<OtherVT> { 789 let PrintMethod = "printAbsBranchOperand"; 790 let EncoderMethod = "getAbsDirectBrEncoding"; 791 let ParserMatchClass = PPCDirectBrAsmOperand; 792} 793def PPCCondBrAsmOperand : AsmOperandClass { 794 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 795 let RenderMethod = "addBranchTargetOperands"; 796} 797def condbrtarget : Operand<OtherVT> { 798 let PrintMethod = "printBranchOperand"; 799 let EncoderMethod = "getCondBrEncoding"; 800 let DecoderMethod = "decodeCondBrTarget"; 801 let ParserMatchClass = PPCCondBrAsmOperand; 802 let OperandType = "OPERAND_PCREL"; 803} 804def abscondbrtarget : Operand<OtherVT> { 805 let PrintMethod = "printAbsBranchOperand"; 806 let EncoderMethod = "getAbsCondBrEncoding"; 807 let ParserMatchClass = PPCCondBrAsmOperand; 808} 809def calltarget : Operand<iPTR> { 810 let PrintMethod = "printBranchOperand"; 811 let EncoderMethod = "getDirectBrEncoding"; 812 let DecoderMethod = "decodeDirectBrTarget"; 813 let ParserMatchClass = PPCDirectBrAsmOperand; 814 let OperandType = "OPERAND_PCREL"; 815} 816def abscalltarget : Operand<iPTR> { 817 let PrintMethod = "printAbsBranchOperand"; 818 let EncoderMethod = "getAbsDirectBrEncoding"; 819 let ParserMatchClass = PPCDirectBrAsmOperand; 820} 821def PPCCRBitMaskOperand : AsmOperandClass { 822 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 823} 824def crbitm: Operand<i8> { 825 let PrintMethod = "printcrbitm"; 826 let EncoderMethod = "get_crbitm_encoding"; 827 let DecoderMethod = "decodeCRBitMOperand"; 828 let ParserMatchClass = PPCCRBitMaskOperand; 829} 830// Address operands 831// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 832def PPCRegGxRCNoR0Operand : AsmOperandClass { 833 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 834} 835def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 836 let ParserMatchClass = PPCRegGxRCNoR0Operand; 837} 838 839// New addressing modes with 34 bit immediates. 840def PPCDispRI34Operand : AsmOperandClass { 841 let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; 842 let RenderMethod = "addImmOperands"; 843} 844def dispRI34 : Operand<iPTR> { 845 let ParserMatchClass = PPCDispRI34Operand; 846} 847def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. 848 let PrintMethod = "printMemRegImm34"; 849 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 850 let EncoderMethod = "getMemRI34Encoding"; 851 let DecoderMethod = "decodeMemRI34Operands"; 852} 853// memri, imm is a 34-bit value for pc-relative instructions where 854// base register is set to zero. 855def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. 856 let PrintMethod = "printMemRegImm34PCRel"; 857 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 858 let EncoderMethod = "getMemRI34PCRelEncoding"; 859 let DecoderMethod = "decodeMemRI34PCRelOperands"; 860} 861 862// A version of ptr_rc usable with the asm parser. 863def PPCRegGxRCOperand : AsmOperandClass { 864 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 865} 866def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 867 let ParserMatchClass = PPCRegGxRCOperand; 868} 869 870def PPCDispRIOperand : AsmOperandClass { 871 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 872 let RenderMethod = "addS16ImmOperands"; 873} 874def dispRI : Operand<iPTR> { 875 let ParserMatchClass = PPCDispRIOperand; 876} 877def PPCDispRIXOperand : AsmOperandClass { 878 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 879 let RenderMethod = "addImmOperands"; 880} 881def dispRIX : Operand<iPTR> { 882 let ParserMatchClass = PPCDispRIXOperand; 883} 884def PPCDispRIX16Operand : AsmOperandClass { 885 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 886 let RenderMethod = "addImmOperands"; 887} 888def dispRIX16 : Operand<iPTR> { 889 let ParserMatchClass = PPCDispRIX16Operand; 890} 891def PPCDispSPE8Operand : AsmOperandClass { 892 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 893 let RenderMethod = "addImmOperands"; 894} 895def dispSPE8 : Operand<iPTR> { 896 let ParserMatchClass = PPCDispSPE8Operand; 897} 898def PPCDispSPE4Operand : AsmOperandClass { 899 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 900 let RenderMethod = "addImmOperands"; 901} 902def dispSPE4 : Operand<iPTR> { 903 let ParserMatchClass = PPCDispSPE4Operand; 904} 905def PPCDispSPE2Operand : AsmOperandClass { 906 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 907 let RenderMethod = "addImmOperands"; 908} 909def dispSPE2 : Operand<iPTR> { 910 let ParserMatchClass = PPCDispSPE2Operand; 911} 912 913def memri : Operand<iPTR> { 914 let PrintMethod = "printMemRegImm"; 915 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 916 let EncoderMethod = "getMemRIEncoding"; 917 let DecoderMethod = "decodeMemRIOperands"; 918} 919def memrr : Operand<iPTR> { 920 let PrintMethod = "printMemRegReg"; 921 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 922} 923def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 924 let PrintMethod = "printMemRegImm"; 925 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 926 let EncoderMethod = "getMemRIXEncoding"; 927 let DecoderMethod = "decodeMemRIXOperands"; 928} 929def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 930 let PrintMethod = "printMemRegImm"; 931 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 932 let EncoderMethod = "getMemRIX16Encoding"; 933 let DecoderMethod = "decodeMemRIX16Operands"; 934} 935def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 936 let PrintMethod = "printMemRegImm"; 937 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 938 let EncoderMethod = "getSPE8DisEncoding"; 939 let DecoderMethod = "decodeSPE8Operands"; 940} 941def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 942 let PrintMethod = "printMemRegImm"; 943 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 944 let EncoderMethod = "getSPE4DisEncoding"; 945 let DecoderMethod = "decodeSPE4Operands"; 946} 947def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 948 let PrintMethod = "printMemRegImm"; 949 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 950 let EncoderMethod = "getSPE2DisEncoding"; 951 let DecoderMethod = "decodeSPE2Operands"; 952} 953 954// A single-register address. This is used with the SjLj 955// pseudo-instructions which translates to LD/LWZ. These instructions requires 956// G8RC_NOX0 registers. 957def memr : Operand<iPTR> { 958 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 959} 960def PPCTLSRegOperand : AsmOperandClass { 961 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 962 let RenderMethod = "addTLSRegOperands"; 963} 964def tlsreg32 : Operand<i32> { 965 let EncoderMethod = "getTLSRegEncoding"; 966 let ParserMatchClass = PPCTLSRegOperand; 967} 968def tlsgd32 : Operand<i32> {} 969def tlscall32 : Operand<i32> { 970 let PrintMethod = "printTLSCall"; 971 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 972 let EncoderMethod = "getTLSCallEncoding"; 973} 974 975// PowerPC Predicate operand. 976def pred : Operand<OtherVT> { 977 let PrintMethod = "printPredicateOperand"; 978 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 979} 980 981// Define PowerPC specific addressing mode. 982 983// d-form 984def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 985// ds-form 986def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 987// dq-form 988def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 989 990// Below forms are all x-form addressing mode, use three different ones so we 991// can make a accurate check for x-form instructions in ISEL. 992// x-form addressing mode whose associated displacement form is D. 993def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 994// x-form addressing mode whose associated displacement form is DS. 995def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 996// x-form addressing mode whose associated displacement form is DQ. 997def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 998 999def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 1000 1001// The address in a single register. This is used with the SjLj 1002// pseudo-instructions. 1003def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 1004 1005/// This is just the offset part of iaddr, used for preinc. 1006def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 1007 1008// PC Relative Address 1009def pcreladdr : ComplexPattern<iPTR, 1, "SelectAddrPCRel", [], []>; 1010 1011//===----------------------------------------------------------------------===// 1012// PowerPC Instruction Predicate Definitions. 1013def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 1014def In64BitMode : Predicate<"Subtarget->isPPC64()">; 1015def IsBookE : Predicate<"Subtarget->isBookE()">; 1016def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 1017def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 1018def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 1019def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 1020def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 1021def IsE500 : Predicate<"Subtarget->isE500()">; 1022def HasSPE : Predicate<"Subtarget->hasSPE()">; 1023def HasICBT : Predicate<"Subtarget->hasICBT()">; 1024def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 1025def NoNaNsFPMath 1026 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 1027def NaNsFPMath 1028 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 1029def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 1030def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 1031def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 1032def HasFPU : Predicate<"Subtarget->hasFPU()">; 1033def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 1034 1035//===----------------------------------------------------------------------===// 1036// PowerPC Multiclass Definitions. 1037 1038multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1039 string asmbase, string asmstr, InstrItinClass itin, 1040 list<dag> pattern> { 1041 let BaseName = asmbase in { 1042 def NAME : XForm_6<opcode, xo, OOL, IOL, 1043 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1044 pattern>, RecFormRel; 1045 let Defs = [CR0] in 1046 def _rec : XForm_6<opcode, xo, OOL, IOL, 1047 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1048 []>, isRecordForm, RecFormRel; 1049 } 1050} 1051 1052multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1053 string asmbase, string asmstr, InstrItinClass itin, 1054 list<dag> pattern> { 1055 let BaseName = asmbase in { 1056 let Defs = [CARRY] in 1057 def NAME : XForm_6<opcode, xo, OOL, IOL, 1058 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1059 pattern>, RecFormRel; 1060 let Defs = [CARRY, CR0] in 1061 def _rec : XForm_6<opcode, xo, OOL, IOL, 1062 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1063 []>, isRecordForm, RecFormRel; 1064 } 1065} 1066 1067multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1068 string asmbase, string asmstr, InstrItinClass itin, 1069 list<dag> pattern> { 1070 let BaseName = asmbase in { 1071 let Defs = [CARRY] in 1072 def NAME : XForm_10<opcode, xo, OOL, IOL, 1073 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1074 pattern>, RecFormRel; 1075 let Defs = [CARRY, CR0] in 1076 def _rec : XForm_10<opcode, xo, OOL, IOL, 1077 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1078 []>, isRecordForm, RecFormRel; 1079 } 1080} 1081 1082multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1083 string asmbase, string asmstr, InstrItinClass itin, 1084 list<dag> pattern> { 1085 let BaseName = asmbase in { 1086 def NAME : XForm_11<opcode, xo, OOL, IOL, 1087 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1088 pattern>, RecFormRel; 1089 let Defs = [CR0] in 1090 def _rec : XForm_11<opcode, xo, OOL, IOL, 1091 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1092 []>, isRecordForm, RecFormRel; 1093 } 1094} 1095 1096multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1097 string asmbase, string asmstr, InstrItinClass itin, 1098 list<dag> pattern> { 1099 let BaseName = asmbase in { 1100 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1101 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1102 pattern>, RecFormRel; 1103 let Defs = [CR0] in 1104 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1105 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1106 []>, isRecordForm, RecFormRel; 1107 } 1108} 1109 1110// Multiclass for instructions which have a record overflow form as well 1111// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 1112multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1113 string asmbase, string asmstr, InstrItinClass itin, 1114 list<dag> pattern> { 1115 let BaseName = asmbase in { 1116 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 1117 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1118 pattern>, RecFormRel; 1119 let Defs = [CR0] in 1120 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 1121 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1122 []>, isRecordForm, RecFormRel; 1123 } 1124 let BaseName = !strconcat(asmbase, "O") in { 1125 let Defs = [XER] in 1126 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1127 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1128 []>, RecFormRel; 1129 let Defs = [XER, CR0] in 1130 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1131 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1132 []>, isRecordForm, RecFormRel; 1133 } 1134} 1135 1136// Multiclass for instructions for which the non record form is not cracked 1137// and the record form is cracked (i.e. divw, mullw, etc.) 1138multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1139 string asmbase, string asmstr, InstrItinClass itin, 1140 list<dag> pattern> { 1141 let BaseName = asmbase in { 1142 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1143 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1144 pattern>, RecFormRel; 1145 let Defs = [CR0] in 1146 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1147 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1148 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 1149 PPC970_DGroup_Cracked; 1150 } 1151 let BaseName = !strconcat(asmbase, "O") in { 1152 let Defs = [XER] in 1153 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1154 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1155 []>, RecFormRel; 1156 let Defs = [XER, CR0] in 1157 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1158 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1159 []>, isRecordForm, RecFormRel; 1160 } 1161} 1162 1163multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1164 string asmbase, string asmstr, InstrItinClass itin, 1165 list<dag> pattern> { 1166 let BaseName = asmbase in { 1167 let Defs = [CARRY] in 1168 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1169 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1170 pattern>, RecFormRel; 1171 let Defs = [CARRY, CR0] in 1172 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1173 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1174 []>, isRecordForm, RecFormRel; 1175 } 1176 let BaseName = !strconcat(asmbase, "O") in { 1177 let Defs = [CARRY, XER] in 1178 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1179 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1180 []>, RecFormRel; 1181 let Defs = [CARRY, XER, CR0] in 1182 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1183 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1184 []>, isRecordForm, RecFormRel; 1185 } 1186} 1187 1188multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1189 string asmbase, string asmstr, InstrItinClass itin, 1190 list<dag> pattern> { 1191 let BaseName = asmbase in { 1192 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1193 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1194 pattern>, RecFormRel; 1195 let Defs = [CR0] in 1196 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1197 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1198 []>, isRecordForm, RecFormRel; 1199 } 1200 let BaseName = !strconcat(asmbase, "O") in { 1201 let Defs = [XER] in 1202 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1203 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1204 []>, RecFormRel; 1205 let Defs = [XER, CR0] in 1206 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1207 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1208 []>, isRecordForm, RecFormRel; 1209 } 1210} 1211 1212multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1213 string asmbase, string asmstr, InstrItinClass itin, 1214 list<dag> pattern> { 1215 let BaseName = asmbase in { 1216 let Defs = [CARRY] in 1217 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1218 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1219 pattern>, RecFormRel; 1220 let Defs = [CARRY, CR0] in 1221 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1222 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1223 []>, isRecordForm, RecFormRel; 1224 } 1225 let BaseName = !strconcat(asmbase, "O") in { 1226 let Defs = [CARRY, XER] in 1227 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1228 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1229 []>, RecFormRel; 1230 let Defs = [CARRY, XER, CR0] in 1231 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1232 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1233 []>, isRecordForm, RecFormRel; 1234 } 1235} 1236 1237multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 1238 string asmbase, string asmstr, InstrItinClass itin, 1239 list<dag> pattern> { 1240 let BaseName = asmbase in { 1241 def NAME : MForm_2<opcode, OOL, IOL, 1242 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1243 pattern>, RecFormRel; 1244 let Defs = [CR0] in 1245 def _rec : MForm_2<opcode, OOL, IOL, 1246 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1247 []>, isRecordForm, RecFormRel; 1248 } 1249} 1250 1251multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 1252 string asmbase, string asmstr, InstrItinClass itin, 1253 list<dag> pattern> { 1254 let BaseName = asmbase in { 1255 def NAME : MDForm_1<opcode, xo, OOL, IOL, 1256 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1257 pattern>, RecFormRel; 1258 let Defs = [CR0] in 1259 def _rec : MDForm_1<opcode, xo, OOL, IOL, 1260 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1261 []>, isRecordForm, RecFormRel; 1262 } 1263} 1264 1265multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 1266 string asmbase, string asmstr, InstrItinClass itin, 1267 list<dag> pattern> { 1268 let BaseName = asmbase in { 1269 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 1270 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1271 pattern>, RecFormRel; 1272 let Defs = [CR0] in 1273 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1274 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1275 []>, isRecordForm, RecFormRel; 1276 } 1277} 1278 1279multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1280 string asmbase, string asmstr, InstrItinClass itin, 1281 list<dag> pattern> { 1282 let BaseName = asmbase in { 1283 let Defs = [CARRY] in 1284 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1285 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1286 pattern>, RecFormRel; 1287 let Defs = [CARRY, CR0] in 1288 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1289 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1290 []>, isRecordForm, RecFormRel; 1291 } 1292} 1293 1294multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1295 string asmbase, string asmstr, InstrItinClass itin, 1296 list<dag> pattern> { 1297 let BaseName = asmbase in { 1298 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1299 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1300 pattern>, RecFormRel; 1301 let Defs = [CR0] in 1302 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1303 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1304 []>, isRecordForm, RecFormRel; 1305 } 1306} 1307 1308multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1309 string asmbase, string asmstr, InstrItinClass itin, 1310 list<dag> pattern> { 1311 let BaseName = asmbase in { 1312 def NAME : XForm_26<opcode, xo, OOL, IOL, 1313 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1314 pattern>, RecFormRel; 1315 let Defs = [CR1] in 1316 def _rec : XForm_26<opcode, xo, OOL, IOL, 1317 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1318 []>, isRecordForm, RecFormRel; 1319 } 1320} 1321 1322multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1323 string asmbase, string asmstr, InstrItinClass itin, 1324 list<dag> pattern> { 1325 let BaseName = asmbase in { 1326 def NAME : XForm_28<opcode, xo, OOL, IOL, 1327 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1328 pattern>, RecFormRel; 1329 let Defs = [CR1] in 1330 def _rec : XForm_28<opcode, xo, OOL, IOL, 1331 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1332 []>, isRecordForm, RecFormRel; 1333 } 1334} 1335 1336multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1337 string asmbase, string asmstr, InstrItinClass itin, 1338 list<dag> pattern> { 1339 let BaseName = asmbase in { 1340 def NAME : AForm_1<opcode, xo, OOL, IOL, 1341 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1342 pattern>, RecFormRel; 1343 let Defs = [CR1] in 1344 def _rec : AForm_1<opcode, xo, OOL, IOL, 1345 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1346 []>, isRecordForm, RecFormRel; 1347 } 1348} 1349 1350multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1351 string asmbase, string asmstr, InstrItinClass itin, 1352 list<dag> pattern> { 1353 let BaseName = asmbase in { 1354 def NAME : AForm_2<opcode, xo, OOL, IOL, 1355 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1356 pattern>, RecFormRel; 1357 let Defs = [CR1] in 1358 def _rec : AForm_2<opcode, xo, OOL, IOL, 1359 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1360 []>, isRecordForm, RecFormRel; 1361 } 1362} 1363 1364multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1365 string asmbase, string asmstr, InstrItinClass itin, 1366 list<dag> pattern> { 1367 let BaseName = asmbase in { 1368 def NAME : AForm_3<opcode, xo, OOL, IOL, 1369 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1370 pattern>, RecFormRel; 1371 let Defs = [CR1] in 1372 def _rec : AForm_3<opcode, xo, OOL, IOL, 1373 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1374 []>, isRecordForm, RecFormRel; 1375 } 1376} 1377 1378//===----------------------------------------------------------------------===// 1379// PowerPC Instruction Definitions. 1380 1381// Pseudo instructions: 1382 1383let hasCtrlDep = 1 in { 1384let Defs = [R1], Uses = [R1] in { 1385def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1386 "#ADJCALLSTACKDOWN $amt1 $amt2", 1387 [(callseq_start timm:$amt1, timm:$amt2)]>; 1388def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1389 "#ADJCALLSTACKUP $amt1 $amt2", 1390 [(callseq_end timm:$amt1, timm:$amt2)]>; 1391} 1392 1393def UPDATE_VRSAVE : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$rS), 1394 "UPDATE_VRSAVE $rD, $rS", []>; 1395} 1396 1397let Defs = [R1], Uses = [R1] in 1398def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1399 [(set i32:$result, 1400 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1401def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1402 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1403// Probed alloca to support stack clash protection. 1404let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1405def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1406 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1407 [(set i32:$result, 1408 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1409def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs gprc:$fp, 1410 gprc:$sp), 1411 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1412def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1413 (ins i64imm:$stacksize), 1414 "#PROBED_STACKALLOC_32", []>; 1415} 1416 1417// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1418// instruction selection into a branch sequence. 1419let PPC970_Single = 1 in { 1420 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1421 // because either operand might become the first operand in an isel, and 1422 // that operand cannot be r0. 1423 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1424 gprc_nor0:$T, gprc_nor0:$F, 1425 i32imm:$BROPC), "#SELECT_CC_I4", 1426 []>; 1427 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1428 g8rc_nox0:$T, g8rc_nox0:$F, 1429 i32imm:$BROPC), "#SELECT_CC_I8", 1430 []>; 1431 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1432 i32imm:$BROPC), "#SELECT_CC_F4", 1433 []>; 1434 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1435 i32imm:$BROPC), "#SELECT_CC_F8", 1436 []>; 1437 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1438 i32imm:$BROPC), "#SELECT_CC_F16", 1439 []>; 1440 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1441 i32imm:$BROPC), "#SELECT_CC_VRRC", 1442 []>; 1443 1444 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1445 // register bit directly. 1446 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1447 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1448 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1449 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1450 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1451 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1452let Predicates = [HasFPU] in { 1453 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1454 f4rc:$T, f4rc:$F), "#SELECT_F4", 1455 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1456 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1457 f8rc:$T, f8rc:$F), "#SELECT_F8", 1458 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1459 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1460 vrrc:$T, vrrc:$F), "#SELECT_F16", 1461 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1462} 1463 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1464 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1465 [(set v4i32:$dst, 1466 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1467} 1468 1469// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1470// scavenge a register for it. 1471let mayStore = 1 in { 1472def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1473 "#SPILL_CR", []>; 1474def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1475 "#SPILL_CRBIT", []>; 1476} 1477 1478// RESTORE_CR - Indicate that we're restoring the CR register (previously 1479// spilled), so we'll need to scavenge a register for it. 1480let mayLoad = 1 in { 1481def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1482 "#RESTORE_CR", []>; 1483def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1484 "#RESTORE_CRBIT", []>; 1485} 1486 1487let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 1488 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1489 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1490 [(retflag)]>, Requires<[In32BitMode]>; 1491 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1492 let isPredicable = 1 in 1493 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1494 []>; 1495 1496 let isCodeGenOnly = 1 in { 1497 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1498 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1499 []>; 1500 1501 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1502 "bcctr 12, $bi, 0", IIC_BrB, []>; 1503 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1504 "bcctr 4, $bi, 0", IIC_BrB, []>; 1505 } 1506 } 1507} 1508 1509// Set the float rounding mode. 1510let Uses = [RM], Defs = [RM] in { 1511def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1512 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1513 1514def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1515 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1516} 1517 1518let Defs = [LR] in 1519 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1520 PPC970_Unit_BRU; 1521let Defs = [LR] in 1522 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1523 PPC970_Unit_BRU; 1524 1525let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 1526 let isBarrier = 1 in { 1527 let isPredicable = 1 in 1528 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1529 "b $dst", IIC_BrB, 1530 [(br bb:$dst)]>; 1531 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1532 "ba $dst", IIC_BrB, []>; 1533 } 1534 1535 // BCC represents an arbitrary conditional branch on a predicate. 1536 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1537 // a two-value operand where a dag node expects two operands. :( 1538 let isCodeGenOnly = 1 in { 1539 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1540 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1541 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1542 def BCC : BCC_class; 1543 1544 // The same as BCC, except that it's not a terminator. Used for introducing 1545 // control flow dependency without creating new blocks. 1546 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1547 1548 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1549 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1550 1551 let isReturn = 1, Uses = [LR, RM] in 1552 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1553 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1554 } 1555 1556 let isCodeGenOnly = 1 in { 1557 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1558 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1559 "bc 12, $bi, $dst">; 1560 1561 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1562 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1563 "bc 4, $bi, $dst">; 1564 1565 let isReturn = 1, Uses = [LR, RM] in 1566 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1567 "bclr 12, $bi, 0", IIC_BrB, []>; 1568 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1569 "bclr 4, $bi, 0", IIC_BrB, []>; 1570 } 1571 1572 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1573 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1574 "bdzlr", IIC_BrB, []>; 1575 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1576 "bdnzlr", IIC_BrB, []>; 1577 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1578 "bdzlr+", IIC_BrB, []>; 1579 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1580 "bdnzlr+", IIC_BrB, []>; 1581 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1582 "bdzlr-", IIC_BrB, []>; 1583 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1584 "bdnzlr-", IIC_BrB, []>; 1585 } 1586 1587 let Defs = [CTR], Uses = [CTR] in { 1588 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1589 "bdz $dst">; 1590 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1591 "bdnz $dst">; 1592 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1593 "bdza $dst">; 1594 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1595 "bdnza $dst">; 1596 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1597 "bdz+ $dst">; 1598 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1599 "bdnz+ $dst">; 1600 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1601 "bdza+ $dst">; 1602 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1603 "bdnza+ $dst">; 1604 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1605 "bdz- $dst">; 1606 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1607 "bdnz- $dst">; 1608 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1609 "bdza- $dst">; 1610 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1611 "bdnza- $dst">; 1612 } 1613} 1614 1615// The unconditional BCL used by the SjLj setjmp code. 1616let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1617 let Defs = [LR], Uses = [RM] in { 1618 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1619 "bcl 20, 31, $dst">; 1620 } 1621} 1622 1623let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1624 // Convenient aliases for call instructions 1625 let Uses = [RM] in { 1626 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1627 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1628 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1629 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1630 1631 let isCodeGenOnly = 1 in { 1632 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1633 "bl $func", IIC_BrB, []>; 1634 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1635 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1636 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1637 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1638 1639 def BCL : BForm_4<16, 12, 0, 1, (outs), 1640 (ins crbitrc:$bi, condbrtarget:$dst), 1641 "bcl 12, $bi, $dst">; 1642 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1643 (ins crbitrc:$bi, condbrtarget:$dst), 1644 "bcl 4, $bi, $dst">; 1645 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1646 (outs), (ins calltarget:$func), 1647 "bl $func\n\tnop", IIC_BrB, []>; 1648 } 1649 } 1650 let Uses = [CTR, RM] in { 1651 let isPredicable = 1 in 1652 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1653 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1654 Requires<[In32BitMode]>; 1655 1656 let isCodeGenOnly = 1 in { 1657 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1658 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1659 []>; 1660 1661 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1662 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1663 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1664 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1665 } 1666 } 1667 let Uses = [LR, RM] in { 1668 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1669 "blrl", IIC_BrB, []>; 1670 1671 let isCodeGenOnly = 1 in { 1672 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1673 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1674 []>; 1675 1676 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1677 "bclrl 12, $bi, 0", IIC_BrB, []>; 1678 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1679 "bclrl 4, $bi, 0", IIC_BrB, []>; 1680 } 1681 } 1682 let Defs = [CTR], Uses = [CTR, RM] in { 1683 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1684 "bdzl $dst">; 1685 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1686 "bdnzl $dst">; 1687 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1688 "bdzla $dst">; 1689 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1690 "bdnzla $dst">; 1691 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1692 "bdzl+ $dst">; 1693 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1694 "bdnzl+ $dst">; 1695 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1696 "bdzla+ $dst">; 1697 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1698 "bdnzla+ $dst">; 1699 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1700 "bdzl- $dst">; 1701 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1702 "bdnzl- $dst">; 1703 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1704 "bdzla- $dst">; 1705 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1706 "bdnzla- $dst">; 1707 } 1708 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1709 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1710 "bdzlrl", IIC_BrB, []>; 1711 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1712 "bdnzlrl", IIC_BrB, []>; 1713 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1714 "bdzlrl+", IIC_BrB, []>; 1715 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1716 "bdnzlrl+", IIC_BrB, []>; 1717 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1718 "bdzlrl-", IIC_BrB, []>; 1719 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1720 "bdnzlrl-", IIC_BrB, []>; 1721 } 1722} 1723 1724let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1725def TCRETURNdi :PPCEmitTimePseudo< (outs), 1726 (ins calltarget:$dst, i32imm:$offset), 1727 "#TC_RETURNd $dst $offset", 1728 []>; 1729 1730 1731let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1732def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1733 "#TC_RETURNa $func $offset", 1734 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1735 1736let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1737def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1738 "#TC_RETURNr $dst $offset", 1739 []>; 1740 1741let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1742 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1743 def BCTRL_LWZinto_toc: 1744 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1745 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1746 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1747 1748} 1749 1750 1751let isCodeGenOnly = 1 in { 1752 1753let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1754 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1755def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1756 []>, Requires<[In32BitMode]>; 1757 1758let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1759 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1760def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1761 "b $dst", IIC_BrB, 1762 []>; 1763 1764let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1765 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1766def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1767 "ba $dst", IIC_BrB, 1768 []>; 1769 1770} 1771 1772// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1773// is not. 1774let hasSideEffects = 1 in { 1775 let Defs = [CTR] in 1776 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1777 "#EH_SJLJ_SETJMP32", 1778 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1779 Requires<[In32BitMode]>; 1780} 1781 1782let hasSideEffects = 1, isBarrier = 1 in { 1783 let isTerminator = 1 in 1784 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1785 "#EH_SJLJ_LONGJMP32", 1786 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1787 Requires<[In32BitMode]>; 1788} 1789 1790// This pseudo is never removed from the function, as it serves as 1791// a terminator. Size is set to 0 to prevent the builtin assembler 1792// from emitting it. 1793let isBranch = 1, isTerminator = 1, Size = 0 in { 1794 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1795 "#EH_SjLj_Setup\t$dst", []>; 1796} 1797 1798// System call. 1799let PPC970_Unit = 7 in { 1800 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1801 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1802} 1803 1804// Branch history rolling buffer. 1805def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1806 [(PPCclrbhrb)]>, 1807 PPC970_DGroup_Single; 1808// The $dmy argument used for MFBHRBE is not needed; however, including 1809// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1810// interferes with necessary special handling (see PPCFastISel.cpp). 1811def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1812 (ins u10imm:$imm, u10imm:$dmy), 1813 "mfbhrbe $rD, $imm", IIC_BrB, 1814 [(set i32:$rD, 1815 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1816 PPC970_DGroup_First; 1817 1818def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1819 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1820 PPC970_DGroup_Single; 1821 1822def : InstAlias<"rfebb", (RFEBB 1)>; 1823 1824// DCB* instructions. 1825def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1826 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1827 PPC970_DGroup_Single; 1828def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1829 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1830 PPC970_DGroup_Single; 1831def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1832 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1833 PPC970_DGroup_Single; 1834def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1835 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1836 PPC970_DGroup_Single; 1837def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1838 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1839 PPC970_DGroup_Single; 1840 1841def DCBF : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst), 1842 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 1843 PPC970_DGroup_Single; 1844 1845let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1846def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1847 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1848 PPC970_DGroup_Single; 1849def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1850 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1851 PPC970_DGroup_Single; 1852} // hasSideEffects = 0 1853 1854def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 1855 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 1856def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 1857 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1858def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1859 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1860def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 1861 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1862 1863def : Pat<(int_ppc_dcbt xoaddr:$dst), 1864 (DCBT 0, xoaddr:$dst)>; 1865def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1866 (DCBTST 0, xoaddr:$dst)>; 1867def : Pat<(int_ppc_dcbf xoaddr:$dst), 1868 (DCBF 0, xoaddr:$dst)>; 1869 1870def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1871 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1872def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1873 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1874def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1875 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1876 1877def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1878 (DCBT i32:$TH, xoaddr:$dst)>; 1879def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1880 (DCBTST i32:$TH, xoaddr:$dst)>; 1881 1882// Atomic operations 1883// FIXME: some of these might be used with constant operands. This will result 1884// in constant materialization instructions that may be redundant. We currently 1885// clean this up in PPCMIPeephole with calls to 1886// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1887// in the first place. 1888let Defs = [CR0] in { 1889 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1890 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1891 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1892 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1893 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1894 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1895 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1896 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1897 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1898 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1899 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1900 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1901 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1902 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1903 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1904 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1905 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1906 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1907 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1908 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1909 [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>; 1910 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1911 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1912 [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>; 1913 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1914 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1915 [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>; 1916 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1917 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1918 [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>; 1919 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1920 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1921 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1922 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1923 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1924 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1925 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1926 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1927 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1928 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1929 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1930 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1931 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1932 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1933 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1934 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1935 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1936 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1937 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1938 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1939 [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>; 1940 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1941 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1942 [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>; 1943 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1944 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1945 [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>; 1946 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1947 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1948 [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>; 1949 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1950 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1951 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1952 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1953 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1954 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1955 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1956 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1957 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1958 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1959 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1960 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1961 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1962 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1963 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1964 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1965 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1966 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1967 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1968 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1969 [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>; 1970 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1971 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1972 [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>; 1973 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1974 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1975 [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>; 1976 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1977 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1978 [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>; 1979 1980 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1981 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1982 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1983 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1984 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1985 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1986 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1987 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1988 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1989 1990 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1991 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1992 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1993 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1994 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1995 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1996 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1997 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1998 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1999} 2000 2001def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new), 2002 (ATOMIC_CMP_SWAP_I8 xoaddr:$ptr, i32:$old, i32:$new)>; 2003def : Pat<(PPCatomicCmpSwap_16 xoaddr:$ptr, i32:$old, i32:$new), 2004 (ATOMIC_CMP_SWAP_I16 xoaddr:$ptr, i32:$old, i32:$new)>; 2005 2006// Instructions to support atomic operations 2007let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2008def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 2009 "lbarx $rD, $src", IIC_LdStLWARX, []>, 2010 Requires<[HasPartwordAtomics]>; 2011 2012def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 2013 "lharx $rD, $src", IIC_LdStLWARX, []>, 2014 Requires<[HasPartwordAtomics]>; 2015 2016def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 2017 "lwarx $rD, $src", IIC_LdStLWARX, []>; 2018 2019// Instructions to support lock versions of atomics 2020// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 2021def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 2022 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 2023 Requires<[HasPartwordAtomics]>; 2024 2025def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 2026 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 2027 Requires<[HasPartwordAtomics]>; 2028 2029def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 2030 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 2031 2032// The atomic instructions use the destination register as well as the next one 2033// or two registers in order (modulo 31). 2034let hasExtraSrcRegAllocReq = 1 in 2035def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 2036 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 2037 Requires<[IsISA3_0]>; 2038} 2039 2040let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 2041def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 2042 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 2043 isRecordForm, Requires<[HasPartwordAtomics]>; 2044 2045def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 2046 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 2047 isRecordForm, Requires<[HasPartwordAtomics]>; 2048 2049def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 2050 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 2051} 2052 2053let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2054def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 2055 "stwat $rS, $rA, $FC", IIC_LdStStore>, 2056 Requires<[IsISA3_0]>; 2057 2058let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 2059def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 2060 2061def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 2062 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 2063def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 2064 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 2065def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 2066 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 2067def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 2068 "td $to, $rA, $rB", IIC_IntTrapD, []>; 2069 2070//===----------------------------------------------------------------------===// 2071// PPC32 Load Instructions. 2072// 2073 2074// Unindexed (r+i) Loads. 2075let PPC970_Unit = 2 in { 2076def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 2077 "lbz $rD, $src", IIC_LdStLoad, 2078 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 2079def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 2080 "lha $rD, $src", IIC_LdStLHA, 2081 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 2082 PPC970_DGroup_Cracked; 2083def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 2084 "lhz $rD, $src", IIC_LdStLoad, 2085 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 2086def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 2087 "lwz $rD, $src", IIC_LdStLoad, 2088 [(set i32:$rD, (load iaddr:$src))]>; 2089 2090let Predicates = [HasFPU] in { 2091def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 2092 "lfs $rD, $src", IIC_LdStLFD, 2093 [(set f32:$rD, (load iaddr:$src))]>; 2094def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 2095 "lfd $rD, $src", IIC_LdStLFD, 2096 [(set f64:$rD, (load iaddr:$src))]>; 2097} 2098 2099 2100// Unindexed (r+i) Loads with Update (preinc). 2101let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2102def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2103 "lbzu $rD, $addr", IIC_LdStLoadUpd, 2104 []>, RegConstraint<"$addr.reg = $ea_result">, 2105 NoEncode<"$ea_result">; 2106 2107def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2108 "lhau $rD, $addr", IIC_LdStLHAU, 2109 []>, RegConstraint<"$addr.reg = $ea_result">, 2110 NoEncode<"$ea_result">; 2111 2112def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2113 "lhzu $rD, $addr", IIC_LdStLoadUpd, 2114 []>, RegConstraint<"$addr.reg = $ea_result">, 2115 NoEncode<"$ea_result">; 2116 2117def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2118 "lwzu $rD, $addr", IIC_LdStLoadUpd, 2119 []>, RegConstraint<"$addr.reg = $ea_result">, 2120 NoEncode<"$ea_result">; 2121 2122let Predicates = [HasFPU] in { 2123def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2124 "lfsu $rD, $addr", IIC_LdStLFDU, 2125 []>, RegConstraint<"$addr.reg = $ea_result">, 2126 NoEncode<"$ea_result">; 2127 2128def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2129 "lfdu $rD, $addr", IIC_LdStLFDU, 2130 []>, RegConstraint<"$addr.reg = $ea_result">, 2131 NoEncode<"$ea_result">; 2132} 2133 2134 2135// Indexed (r+r) Loads with Update (preinc). 2136def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2137 (ins memrr:$addr), 2138 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 2139 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2140 NoEncode<"$ea_result">; 2141 2142def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2143 (ins memrr:$addr), 2144 "lhaux $rD, $addr", IIC_LdStLHAUX, 2145 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2146 NoEncode<"$ea_result">; 2147 2148def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2149 (ins memrr:$addr), 2150 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 2151 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2152 NoEncode<"$ea_result">; 2153 2154def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2155 (ins memrr:$addr), 2156 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 2157 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2158 NoEncode<"$ea_result">; 2159 2160let Predicates = [HasFPU] in { 2161def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 2162 (ins memrr:$addr), 2163 "lfsux $rD, $addr", IIC_LdStLFDUX, 2164 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2165 NoEncode<"$ea_result">; 2166 2167def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 2168 (ins memrr:$addr), 2169 "lfdux $rD, $addr", IIC_LdStLFDUX, 2170 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2171 NoEncode<"$ea_result">; 2172} 2173} 2174} 2175 2176// Indexed (r+r) Loads. 2177// 2178let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2179def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 2180 "lbzx $rD, $src", IIC_LdStLoad, 2181 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 2182def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 2183 "lhax $rD, $src", IIC_LdStLHA, 2184 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 2185 PPC970_DGroup_Cracked; 2186def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 2187 "lhzx $rD, $src", IIC_LdStLoad, 2188 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 2189def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 2190 "lwzx $rD, $src", IIC_LdStLoad, 2191 [(set i32:$rD, (load xaddr:$src))]>; 2192def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 2193 "lhbrx $rD, $src", IIC_LdStLoad, 2194 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 2195def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 2196 "lwbrx $rD, $src", IIC_LdStLoad, 2197 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 2198 2199let Predicates = [HasFPU] in { 2200def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 2201 "lfsx $frD, $src", IIC_LdStLFD, 2202 [(set f32:$frD, (load xaddr:$src))]>; 2203def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 2204 "lfdx $frD, $src", IIC_LdStLFD, 2205 [(set f64:$frD, (load xaddr:$src))]>; 2206 2207def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 2208 "lfiwax $frD, $src", IIC_LdStLFD, 2209 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 2210def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 2211 "lfiwzx $frD, $src", IIC_LdStLFD, 2212 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 2213} 2214} 2215 2216// Load Multiple 2217let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2218def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 2219 "lmw $rD, $src", IIC_LdStLMW, []>; 2220 2221//===----------------------------------------------------------------------===// 2222// PPC32 Store Instructions. 2223// 2224 2225// Unindexed (r+i) Stores. 2226let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2227def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 2228 "stb $rS, $dst", IIC_LdStStore, 2229 [(truncstorei8 i32:$rS, iaddr:$dst)]>; 2230def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 2231 "sth $rS, $dst", IIC_LdStStore, 2232 [(truncstorei16 i32:$rS, iaddr:$dst)]>; 2233def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 2234 "stw $rS, $dst", IIC_LdStStore, 2235 [(store i32:$rS, iaddr:$dst)]>; 2236let Predicates = [HasFPU] in { 2237def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 2238 "stfs $rS, $dst", IIC_LdStSTFD, 2239 [(store f32:$rS, iaddr:$dst)]>; 2240def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 2241 "stfd $rS, $dst", IIC_LdStSTFD, 2242 [(store f64:$rS, iaddr:$dst)]>; 2243} 2244} 2245 2246// Unindexed (r+i) Stores with Update (preinc). 2247let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2248def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2249 "stbu $rS, $dst", IIC_LdStSTU, []>, 2250 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2251def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2252 "sthu $rS, $dst", IIC_LdStSTU, []>, 2253 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2254def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2255 "stwu $rS, $dst", IIC_LdStSTU, []>, 2256 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2257let Predicates = [HasFPU] in { 2258def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 2259 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 2260 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2261def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 2262 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 2263 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2264} 2265} 2266 2267// Patterns to match the pre-inc stores. We can't put the patterns on 2268// the instruction definitions directly as ISel wants the address base 2269// and offset to be separate operands, not a single complex operand. 2270def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2271 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2272def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2273 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2274def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2275 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2276def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2277 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2278def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2279 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2280 2281// Indexed (r+r) Stores. 2282let PPC970_Unit = 2 in { 2283def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 2284 "stbx $rS, $dst", IIC_LdStStore, 2285 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 2286 PPC970_DGroup_Cracked; 2287def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2288 "sthx $rS, $dst", IIC_LdStStore, 2289 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 2290 PPC970_DGroup_Cracked; 2291def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2292 "stwx $rS, $dst", IIC_LdStStore, 2293 [(store i32:$rS, xaddr:$dst)]>, 2294 PPC970_DGroup_Cracked; 2295 2296def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2297 "sthbrx $rS, $dst", IIC_LdStStore, 2298 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 2299 PPC970_DGroup_Cracked; 2300def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2301 "stwbrx $rS, $dst", IIC_LdStStore, 2302 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 2303 PPC970_DGroup_Cracked; 2304 2305let Predicates = [HasFPU] in { 2306def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2307 "stfiwx $frS, $dst", IIC_LdStSTFD, 2308 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 2309 2310def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2311 "stfsx $frS, $dst", IIC_LdStSTFD, 2312 [(store f32:$frS, xaddr:$dst)]>; 2313def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2314 "stfdx $frS, $dst", IIC_LdStSTFD, 2315 [(store f64:$frS, xaddr:$dst)]>; 2316} 2317} 2318 2319// Indexed (r+r) Stores with Update (preinc). 2320let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2321def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2322 (ins gprc:$rS, memrr:$dst), 2323 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2324 RegConstraint<"$dst.ptrreg = $ea_res">, 2325 NoEncode<"$ea_res">, 2326 PPC970_DGroup_Cracked; 2327def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2328 (ins gprc:$rS, memrr:$dst), 2329 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2330 RegConstraint<"$dst.ptrreg = $ea_res">, 2331 NoEncode<"$ea_res">, 2332 PPC970_DGroup_Cracked; 2333def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2334 (ins gprc:$rS, memrr:$dst), 2335 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2336 RegConstraint<"$dst.ptrreg = $ea_res">, 2337 NoEncode<"$ea_res">, 2338 PPC970_DGroup_Cracked; 2339let Predicates = [HasFPU] in { 2340def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2341 (ins f4rc:$rS, memrr:$dst), 2342 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2343 RegConstraint<"$dst.ptrreg = $ea_res">, 2344 NoEncode<"$ea_res">, 2345 PPC970_DGroup_Cracked; 2346def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2347 (ins f8rc:$rS, memrr:$dst), 2348 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2349 RegConstraint<"$dst.ptrreg = $ea_res">, 2350 NoEncode<"$ea_res">, 2351 PPC970_DGroup_Cracked; 2352} 2353} 2354 2355// Patterns to match the pre-inc stores. We can't put the patterns on 2356// the instruction definitions directly as ISel wants the address base 2357// and offset to be separate operands, not a single complex operand. 2358def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2359 (STBUX $rS, $ptrreg, $ptroff)>; 2360def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2361 (STHUX $rS, $ptrreg, $ptroff)>; 2362def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2363 (STWUX $rS, $ptrreg, $ptroff)>; 2364let Predicates = [HasFPU] in { 2365def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2366 (STFSUX $rS, $ptrreg, $ptroff)>; 2367def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2368 (STFDUX $rS, $ptrreg, $ptroff)>; 2369} 2370 2371// Store Multiple 2372let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2373def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2374 "stmw $rS, $dst", IIC_LdStLMW, []>; 2375 2376def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 2377 "sync $L", IIC_LdStSync, []>; 2378 2379let isCodeGenOnly = 1 in { 2380 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2381 "msync", IIC_LdStSync, []> { 2382 let L = 0; 2383 } 2384} 2385 2386// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2387def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2388 "eieio", IIC_LdStLoad, []>; 2389 2390def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2391def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2392def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2393def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2394def : Pat<(int_ppc_eieio), (EnforceIEIO)>; 2395 2396//===----------------------------------------------------------------------===// 2397// PPC32 Arithmetic Instructions. 2398// 2399 2400let PPC970_Unit = 1 in { // FXU Operations. 2401def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2402 "addi $rD, $rA, $imm", IIC_IntSimple, 2403 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2404let BaseName = "addic" in { 2405let Defs = [CARRY] in 2406def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2407 "addic $rD, $rA, $imm", IIC_IntGeneral, 2408 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2409 RecFormRel, PPC970_DGroup_Cracked; 2410let Defs = [CARRY, CR0] in 2411def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2412 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2413 []>, isRecordForm, RecFormRel; 2414} 2415def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2416 "addis $rD, $rA, $imm", IIC_IntSimple, 2417 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2418let isCodeGenOnly = 1 in 2419def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2420 "la $rD, $sym($rA)", IIC_IntGeneral, 2421 [(set i32:$rD, (add i32:$rA, 2422 (PPClo tglobaladdr:$sym, 0)))]>; 2423def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2424 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2425 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2426let Defs = [CARRY] in 2427def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2428 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2429 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2430 2431let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2432 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2433 "li $rD, $imm", IIC_IntSimple, 2434 [(set i32:$rD, imm32SExt16:$imm)]>; 2435 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2436 "lis $rD, $imm", IIC_IntSimple, 2437 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2438} 2439} 2440 2441def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2442def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2443 2444let PPC970_Unit = 1 in { // FXU Operations. 2445let Defs = [CR0] in { 2446def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2447 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2448 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2449 isRecordForm; 2450def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2451 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2452 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2453 isRecordForm; 2454} 2455def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2456 "ori $dst, $src1, $src2", IIC_IntSimple, 2457 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2458def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2459 "oris $dst, $src1, $src2", IIC_IntSimple, 2460 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2461def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2462 "xori $dst, $src1, $src2", IIC_IntSimple, 2463 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2464def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2465 "xoris $dst, $src1, $src2", IIC_IntSimple, 2466 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2467 2468def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2469 []>; 2470let isCodeGenOnly = 1 in { 2471// The POWER6 and POWER7 have special group-terminating nops. 2472def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2473 "ori 1, 1, 0", IIC_IntSimple, []>; 2474def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2475 "ori 2, 2, 0", IIC_IntSimple, []>; 2476} 2477 2478let isCompare = 1, hasSideEffects = 0 in { 2479 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2480 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2481 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2482 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2483 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 2484 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 2485 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2486 Requires<[IsISA3_0]>; 2487} 2488} 2489 2490let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2491let isCommutable = 1 in { 2492defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2493 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2494 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2495defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2496 "and", "$rA, $rS, $rB", IIC_IntSimple, 2497 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2498} // isCommutable 2499defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2500 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2501 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2502let isCommutable = 1 in { 2503defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2504 "or", "$rA, $rS, $rB", IIC_IntSimple, 2505 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2506defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2507 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2508 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2509} // isCommutable 2510defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2511 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2512 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2513let isCommutable = 1 in { 2514defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2515 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2516 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2517defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2518 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2519 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2520} // isCommutable 2521defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2522 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2523 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2524defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2525 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2526 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2527defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2528 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2529 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2530} 2531 2532def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2533def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2534 2535def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2536def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2537 2538def : InstAlias<"nop", (ORI R0, R0, 0)>; 2539 2540let PPC970_Unit = 1 in { // FXU Operations. 2541let hasSideEffects = 0 in { 2542defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2543 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2544 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2545defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2546 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2547 [(set i32:$rA, (ctlz i32:$rS))]>; 2548defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2549 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2550 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2551defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2552 "extsb", "$rA, $rS", IIC_IntSimple, 2553 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2554defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2555 "extsh", "$rA, $rS", IIC_IntSimple, 2556 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2557 2558let isCommutable = 1 in 2559def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2560 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2561 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2562} 2563let isCompare = 1, hasSideEffects = 0 in { 2564 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2565 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2566 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2567 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2568} 2569} 2570let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2571//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 2572// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2573let isCompare = 1, hasSideEffects = 0 in { 2574 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2575 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2576 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2577 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2578 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2579} 2580 2581def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2582 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2583def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2584 "ftsqrt $crD, $fB", IIC_FPCompare>; 2585 2586let Uses = [RM], mayRaiseFPException = 1 in { 2587 let hasSideEffects = 0 in { 2588 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2589 "fctiw", "$frD, $frB", IIC_FPGeneral, 2590 []>; 2591 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2592 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2593 []>; 2594 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2595 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2596 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 2597 2598 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2599 "frsp", "$frD, $frB", IIC_FPGeneral, 2600 [(set f32:$frD, (any_fpround f64:$frB))]>; 2601 2602 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2603 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2604 "frin", "$frD, $frB", IIC_FPGeneral, 2605 [(set f64:$frD, (any_fround f64:$frB))]>; 2606 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2607 "frin", "$frD, $frB", IIC_FPGeneral, 2608 [(set f32:$frD, (any_fround f32:$frB))]>; 2609 } 2610 2611 let hasSideEffects = 0 in { 2612 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2613 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2614 "frip", "$frD, $frB", IIC_FPGeneral, 2615 [(set f64:$frD, (any_fceil f64:$frB))]>; 2616 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2617 "frip", "$frD, $frB", IIC_FPGeneral, 2618 [(set f32:$frD, (any_fceil f32:$frB))]>; 2619 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2620 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2621 "friz", "$frD, $frB", IIC_FPGeneral, 2622 [(set f64:$frD, (any_ftrunc f64:$frB))]>; 2623 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2624 "friz", "$frD, $frB", IIC_FPGeneral, 2625 [(set f32:$frD, (any_ftrunc f32:$frB))]>; 2626 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2627 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2628 "frim", "$frD, $frB", IIC_FPGeneral, 2629 [(set f64:$frD, (any_ffloor f64:$frB))]>; 2630 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2631 "frim", "$frD, $frB", IIC_FPGeneral, 2632 [(set f32:$frD, (any_ffloor f32:$frB))]>; 2633 2634 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2635 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2636 [(set f64:$frD, (any_fsqrt f64:$frB))]>; 2637 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2638 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2639 [(set f32:$frD, (any_fsqrt f32:$frB))]>; 2640 } 2641 } 2642} 2643 2644/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2645/// often coalesced away and we don't want the dispatch group builder to think 2646/// that they will fill slots (which could cause the load of a LSU reject to 2647/// sneak into a d-group with a store). 2648let hasSideEffects = 0, Predicates = [HasFPU] in 2649defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2650 "fmr", "$frD, $frB", IIC_FPGeneral, 2651 []>, // (set f32:$frD, f32:$frB) 2652 PPC970_Unit_Pseudo; 2653 2654let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2655// These are artificially split into two different forms, for 4/8 byte FP. 2656defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2657 "fabs", "$frD, $frB", IIC_FPGeneral, 2658 [(set f32:$frD, (fabs f32:$frB))]>; 2659let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2660defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2661 "fabs", "$frD, $frB", IIC_FPGeneral, 2662 [(set f64:$frD, (fabs f64:$frB))]>; 2663defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2664 "fnabs", "$frD, $frB", IIC_FPGeneral, 2665 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2666let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2667defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2668 "fnabs", "$frD, $frB", IIC_FPGeneral, 2669 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2670defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2671 "fneg", "$frD, $frB", IIC_FPGeneral, 2672 [(set f32:$frD, (fneg f32:$frB))]>; 2673let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2674defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2675 "fneg", "$frD, $frB", IIC_FPGeneral, 2676 [(set f64:$frD, (fneg f64:$frB))]>; 2677 2678defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2679 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2680 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2681let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2682defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2683 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2684 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2685 2686// Reciprocal estimates. 2687defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2688 "fre", "$frD, $frB", IIC_FPGeneral, 2689 [(set f64:$frD, (PPCfre f64:$frB))]>; 2690defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2691 "fres", "$frD, $frB", IIC_FPGeneral, 2692 [(set f32:$frD, (PPCfre f32:$frB))]>; 2693defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2694 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2695 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2696defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2697 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2698 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2699} 2700 2701// XL-Form instructions. condition register logical ops. 2702// 2703let hasSideEffects = 0 in 2704def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2705 "mcrf $BF, $BFA", IIC_BrMCR>, 2706 PPC970_DGroup_First, PPC970_Unit_CRU; 2707 2708// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2709// condition-register logical instructions have preferred forms. Specifically, 2710// it is preferred that the bit specified by the BT field be in the same 2711// condition register as that specified by the bit BB. We might want to account 2712// for this via hinting the register allocator and anti-dep breakers, or we 2713// could constrain the register class to force this constraint and then loosen 2714// it during register allocation via convertToThreeAddress or some similar 2715// mechanism. 2716 2717let isCommutable = 1 in { 2718def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2719 (ins crbitrc:$CRA, crbitrc:$CRB), 2720 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2721 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2722 2723def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2724 (ins crbitrc:$CRA, crbitrc:$CRB), 2725 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2726 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2727 2728def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2729 (ins crbitrc:$CRA, crbitrc:$CRB), 2730 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2731 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2732 2733def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2734 (ins crbitrc:$CRA, crbitrc:$CRB), 2735 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2736 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2737 2738def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2739 (ins crbitrc:$CRA, crbitrc:$CRB), 2740 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2741 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2742 2743def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2744 (ins crbitrc:$CRA, crbitrc:$CRB), 2745 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2746 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2747} // isCommutable 2748 2749def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2750 (ins crbitrc:$CRA, crbitrc:$CRB), 2751 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2752 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2753 2754def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2755 (ins crbitrc:$CRA, crbitrc:$CRB), 2756 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2757 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2758 2759let isCodeGenOnly = 1 in { 2760let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2761def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2762 "creqv $dst, $dst, $dst", IIC_BrCR, 2763 [(set i1:$dst, 1)]>; 2764 2765def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2766 "crxor $dst, $dst, $dst", IIC_BrCR, 2767 [(set i1:$dst, 0)]>; 2768} 2769 2770let Defs = [CR1EQ], CRD = 6 in { 2771def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2772 "creqv 6, 6, 6", IIC_BrCR, 2773 [(PPCcr6set)]>; 2774 2775def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2776 "crxor 6, 6, 6", IIC_BrCR, 2777 [(PPCcr6unset)]>; 2778} 2779} 2780 2781// XFX-Form instructions. Instructions that deal with SPRs. 2782// 2783 2784def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2785 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2786def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2787 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2788 2789def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2790 "mftb $RT, $SPR", IIC_SprMFTB>; 2791 2792def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2793 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2794 2795def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2796 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 2797 2798 2799// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2800// on a 32-bit target. 2801let hasSideEffects = 1 in 2802def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2803 "#ReadTB", []>; 2804 2805let Uses = [CTR] in { 2806def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2807 "mfctr $rT", IIC_SprMFSPR>, 2808 PPC970_DGroup_First, PPC970_Unit_FXU; 2809} 2810let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2811def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2812 "mtctr $rS", IIC_SprMTSPR>, 2813 PPC970_DGroup_First, PPC970_Unit_FXU; 2814} 2815let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2816let Pattern = [(int_set_loop_iterations i32:$rS)] in 2817def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2818 "mtctr $rS", IIC_SprMTSPR>, 2819 PPC970_DGroup_First, PPC970_Unit_FXU; 2820} 2821 2822let hasSideEffects = 0 in { 2823let Defs = [LR] in { 2824def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2825 "mtlr $rS", IIC_SprMTSPR>, 2826 PPC970_DGroup_First, PPC970_Unit_FXU; 2827} 2828let Uses = [LR] in { 2829def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2830 "mflr $rT", IIC_SprMFSPR>, 2831 PPC970_DGroup_First, PPC970_Unit_FXU; 2832} 2833} 2834 2835let isCodeGenOnly = 1 in { 2836 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2837 // like a GPR on the PPC970. As such, copies in and out have the same 2838 // performance characteristics as an OR instruction. 2839 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2840 "mtspr 256, $rS", IIC_IntGeneral>, 2841 PPC970_DGroup_Single, PPC970_Unit_FXU; 2842 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2843 "mfspr $rT, 256", IIC_IntGeneral>, 2844 PPC970_DGroup_First, PPC970_Unit_FXU; 2845 2846 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2847 (outs VRSAVERC:$reg), (ins gprc:$rS), 2848 "mtspr 256, $rS", IIC_IntGeneral>, 2849 PPC970_DGroup_Single, PPC970_Unit_FXU; 2850 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2851 (ins VRSAVERC:$reg), 2852 "mfspr $rT, 256", IIC_IntGeneral>, 2853 PPC970_DGroup_First, PPC970_Unit_FXU; 2854} 2855 2856// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2857def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2858def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2859 2860// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2861// so we'll need to scavenge a register for it. 2862let mayStore = 1 in 2863def SPILL_VRSAVE : PPCEmitTimePseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2864 "#SPILL_VRSAVE", []>; 2865 2866// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2867// spilled), so we'll need to scavenge a register for it. 2868let mayLoad = 1 in 2869def RESTORE_VRSAVE : PPCEmitTimePseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2870 "#RESTORE_VRSAVE", []>; 2871 2872let hasSideEffects = 0 in { 2873// mtocrf's input needs to be prepared by shifting by an amount dependent 2874// on the cr register selected. Thus, post-ra anti-dep breaking must not 2875// later change that register assignment. 2876let hasExtraDefRegAllocReq = 1 in { 2877def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2878 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2879 PPC970_DGroup_First, PPC970_Unit_CRU; 2880 2881// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2882// is dependent on the cr fields being set. 2883def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2884 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2885 PPC970_MicroCode, PPC970_Unit_CRU; 2886} // hasExtraDefRegAllocReq = 1 2887 2888// mfocrf's input needs to be prepared by shifting by an amount dependent 2889// on the cr register selected. Thus, post-ra anti-dep breaking must not 2890// later change that register assignment. 2891let hasExtraSrcRegAllocReq = 1 in { 2892def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2893 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2894 PPC970_DGroup_First, PPC970_Unit_CRU; 2895 2896// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2897// is dependent on the cr fields being copied. 2898def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2899 "mfcr $rT", IIC_SprMFCR>, 2900 PPC970_MicroCode, PPC970_Unit_CRU; 2901} // hasExtraSrcRegAllocReq = 1 2902 2903def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2904 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2905} // hasSideEffects = 0 2906 2907def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2908 2909let Predicates = [HasFPU] in { 2910// Custom inserter instruction to perform FADD in round-to-zero mode. 2911let Uses = [RM] in { 2912 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2913 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2914} 2915 2916// The above pseudo gets expanded to make use of the following instructions 2917// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2918let Uses = [RM], Defs = [RM] in { 2919 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2920 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2921 PPC970_DGroup_Single, PPC970_Unit_FPU; 2922 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2923 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2924 PPC970_DGroup_Single, PPC970_Unit_FPU; 2925 let isCodeGenOnly = 1 in 2926 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2927 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2928 PPC970_DGroup_Single, PPC970_Unit_FPU; 2929} 2930let Uses = [RM] in { 2931 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2932 "mffs $rT", IIC_IntMFFS, 2933 [(set f64:$rT, (PPCmffs))]>, 2934 PPC970_DGroup_Single, PPC970_Unit_FPU; 2935 2936 let Defs = [CR1] in 2937 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2938 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 2939 2940 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 2941 "mffsce $rT", IIC_IntMFFS, []>, 2942 PPC970_DGroup_Single, PPC970_Unit_FPU; 2943 2944 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 2945 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 2946 IIC_IntMFFS, []>, 2947 PPC970_DGroup_Single, PPC970_Unit_FPU; 2948 2949 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 2950 (ins u3imm:$DRM), 2951 "mffscdrni $rT, $DRM", 2952 IIC_IntMFFS, []>, 2953 PPC970_DGroup_Single, PPC970_Unit_FPU; 2954 2955 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 2956 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 2957 IIC_IntMFFS, []>, 2958 PPC970_DGroup_Single, PPC970_Unit_FPU; 2959 2960 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 2961 (ins u2imm:$RM), "mffscrni $rT, $RM", 2962 IIC_IntMFFS, []>, 2963 PPC970_DGroup_Single, PPC970_Unit_FPU; 2964 2965 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 2966 "mffsl $rT", IIC_IntMFFS, []>, 2967 PPC970_DGroup_Single, PPC970_Unit_FPU; 2968} 2969} 2970 2971let Predicates = [IsISA3_0] in { 2972def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2973 "modsw $rT, $rA, $rB", IIC_IntDivW, 2974 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 2975def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2976 "moduw $rT, $rA, $rB", IIC_IntDivW, 2977 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 2978} 2979 2980let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2981// XO-Form instructions. Arithmetic instructions that can set overflow bit 2982let isCommutable = 1 in 2983defm ADD4 : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2984 "add", "$rT, $rA, $rB", IIC_IntSimple, 2985 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2986let isCodeGenOnly = 1 in 2987def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2988 "add $rT, $rA, $rB", IIC_IntSimple, 2989 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2990let isCommutable = 1 in 2991defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2992 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2993 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2994 PPC970_DGroup_Cracked; 2995 2996defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2997 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2998 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2999defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3000 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 3001 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 3002defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3003 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 3004 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 3005 Requires<[HasExtDiv]>; 3006defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3007 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 3008 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 3009 Requires<[HasExtDiv]>; 3010let isCommutable = 1 in { 3011defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3012 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 3013 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 3014defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3015 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 3016 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 3017defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3018 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 3019 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 3020} // isCommutable 3021defm SUBF : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3022 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 3023 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 3024defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3025 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 3026 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 3027 PPC970_DGroup_Cracked; 3028defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 3029 "neg", "$rT, $rA", IIC_IntSimple, 3030 [(set i32:$rT, (ineg i32:$rA))]>; 3031let Uses = [CARRY] in { 3032let isCommutable = 1 in 3033defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3034 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 3035 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 3036defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 3037 "addme", "$rT, $rA", IIC_IntGeneral, 3038 [(set i32:$rT, (adde i32:$rA, -1))]>; 3039defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 3040 "addze", "$rT, $rA", IIC_IntGeneral, 3041 [(set i32:$rT, (adde i32:$rA, 0))]>; 3042defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3043 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 3044 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 3045defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 3046 "subfme", "$rT, $rA", IIC_IntGeneral, 3047 [(set i32:$rT, (sube -1, i32:$rA))]>; 3048defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 3049 "subfze", "$rT, $rA", IIC_IntGeneral, 3050 [(set i32:$rT, (sube 0, i32:$rA))]>; 3051} 3052} 3053 3054def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 3055def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3056def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 3057def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3058 3059// A-Form instructions. Most of the instructions executed in the FPU are of 3060// this type. 3061// 3062let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 3063let Uses = [RM] in { 3064let isCommutable = 1 in { 3065 defm FMADD : AForm_1r<63, 29, 3066 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3067 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3068 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 3069 defm FMADDS : AForm_1r<59, 29, 3070 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3071 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3072 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 3073 defm FMSUB : AForm_1r<63, 28, 3074 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3075 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3076 [(set f64:$FRT, 3077 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 3078 defm FMSUBS : AForm_1r<59, 28, 3079 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3080 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3081 [(set f32:$FRT, 3082 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 3083 defm FNMADD : AForm_1r<63, 31, 3084 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3085 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3086 [(set f64:$FRT, 3087 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3088 defm FNMADDS : AForm_1r<59, 31, 3089 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3090 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3091 [(set f32:$FRT, 3092 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3093 defm FNMSUB : AForm_1r<63, 30, 3094 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3095 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3096 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3097 (fneg f64:$FRB))))]>; 3098 defm FNMSUBS : AForm_1r<59, 30, 3099 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3100 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3101 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3102 (fneg f32:$FRB))))]>; 3103} // isCommutable 3104} 3105// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3106// having 4 of these, force the comparison to always be an 8-byte double (code 3107// should use an FMRSD if the input comparison value really wants to be a float) 3108// and 4/8 byte forms for the result and operand type.. 3109let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3110defm FSELD : AForm_1r<63, 23, 3111 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3112 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3113 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3114defm FSELS : AForm_1r<63, 23, 3115 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3116 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3117 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3118let Uses = [RM], mayRaiseFPException = 1 in { 3119 let isCommutable = 1 in { 3120 defm FADD : AForm_2r<63, 21, 3121 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3122 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3123 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3124 defm FADDS : AForm_2r<59, 21, 3125 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3126 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3127 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3128 } // isCommutable 3129 defm FDIV : AForm_2r<63, 18, 3130 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3131 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3132 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3133 defm FDIVS : AForm_2r<59, 18, 3134 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3135 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3136 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3137 let isCommutable = 1 in { 3138 defm FMUL : AForm_3r<63, 25, 3139 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3140 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3141 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3142 defm FMULS : AForm_3r<59, 25, 3143 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3144 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3145 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3146 } // isCommutable 3147 defm FSUB : AForm_2r<63, 20, 3148 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3149 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3150 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3151 defm FSUBS : AForm_2r<59, 20, 3152 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3153 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3154 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3155 } 3156} 3157 3158let hasSideEffects = 0 in { 3159let PPC970_Unit = 1 in { // FXU Operations. 3160 let isSelect = 1 in 3161 def ISEL : AForm_4<31, 15, 3162 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 3163 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 3164 []>; 3165} 3166 3167let PPC970_Unit = 1 in { // FXU Operations. 3168// M-Form instructions. rotate and mask instructions. 3169// 3170let isCommutable = 1 in { 3171// RLWIMI can be commuted if the rotate amount is zero. 3172defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 3173 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 3174 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 3175 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3176 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 3177} 3178let BaseName = "rlwinm" in { 3179def RLWINM : MForm_2<21, 3180 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3181 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3182 []>, RecFormRel; 3183let Defs = [CR0] in 3184def RLWINM_rec : MForm_2<21, 3185 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3186 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3187 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3188} 3189defm RLWNM : MForm_2r<23, (outs gprc:$rA), 3190 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 3191 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 3192 []>; 3193} 3194} // hasSideEffects = 0 3195 3196//===----------------------------------------------------------------------===// 3197// PowerPC Instruction Patterns 3198// 3199 3200// Arbitrary immediate support. Implement in terms of LIS/ORI. 3201def : Pat<(i32 imm:$imm), 3202 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3203 3204// Implement the 'not' operation with the NOR instruction. 3205def i32not : OutPatFrag<(ops node:$in), 3206 (NOR $in, $in)>; 3207def : Pat<(not i32:$in), 3208 (i32not $in)>; 3209 3210// ADD an arbitrary immediate. 3211def : Pat<(add i32:$in, imm:$imm), 3212 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3213// OR an arbitrary immediate. 3214def : Pat<(or i32:$in, imm:$imm), 3215 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3216// XOR an arbitrary immediate. 3217def : Pat<(xor i32:$in, imm:$imm), 3218 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3219// SUBFIC 3220def : Pat<(sub imm32SExt16:$imm, i32:$in), 3221 (SUBFIC $in, imm:$imm)>; 3222 3223// SHL/SRL 3224def : Pat<(shl i32:$in, (i32 imm:$imm)), 3225 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3226def : Pat<(srl i32:$in, (i32 imm:$imm)), 3227 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3228 3229// ROTL 3230def : Pat<(rotl i32:$in, i32:$sh), 3231 (RLWNM $in, $sh, 0, 31)>; 3232def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3233 (RLWINM $in, imm:$imm, 0, 31)>; 3234 3235// RLWNM 3236def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3237 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3238 3239// Calls 3240def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3241 (BL tglobaladdr:$dst)>; 3242 3243def : Pat<(PPCcall (i32 texternalsym:$dst)), 3244 (BL texternalsym:$dst)>; 3245 3246// Calls for AIX only 3247def : Pat<(PPCcall (i32 mcsym:$dst)), 3248 (BL mcsym:$dst)>; 3249def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3250 (BL_NOP mcsym:$dst)>; 3251 3252def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3253 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3254 3255def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3256 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3257 3258def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3259 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3260 3261 3262 3263// Hi and Lo for Darwin Global Addresses. 3264def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3265def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3266def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3267def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3268def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3269def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3270def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3271def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3272def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3273 (ADDIS $in, tglobaltlsaddr:$g)>; 3274def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3275 (ADDI $in, tglobaltlsaddr:$g)>; 3276def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3277 (ADDIS $in, tglobaladdr:$g)>; 3278def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3279 (ADDIS $in, tconstpool:$g)>; 3280def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3281 (ADDIS $in, tjumptable:$g)>; 3282def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3283 (ADDIS $in, tblockaddress:$g)>; 3284 3285// Support for thread-local storage. 3286def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3287 [(set i32:$rD, (PPCppc32GOT))]>; 3288 3289// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3290// This uses two output registers, the first as the real output, the second as a 3291// temporary register, used internally in code generation. 3292def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3293 []>, NoEncode<"$rT">; 3294 3295def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3296 "#LDgotTprelL32", 3297 [(set i32:$rD, 3298 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3299def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3300 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3301 3302def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3303 "#ADDItlsgdL32", 3304 [(set i32:$rD, 3305 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3306// LR is a true define, while the rest of the Defs are clobbers. R3 is 3307// explicitly defined when this op is created, so not mentioned here. 3308let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3309 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3310def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3311 "GETtlsADDR32", 3312 [(set i32:$rD, 3313 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3314// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3315// are true defines while the rest of the Defs are clobbers. 3316let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3317 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3318def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3319 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3320 "#ADDItlsgdLADDR32", 3321 [(set i32:$rD, 3322 (PPCaddiTlsgdLAddr i32:$reg, 3323 tglobaltlsaddr:$disp, 3324 tglobaltlsaddr:$sym))]>; 3325def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3326 "#ADDItlsldL32", 3327 [(set i32:$rD, 3328 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3329// LR is a true define, while the rest of the Defs are clobbers. R3 is 3330// explicitly defined when this op is created, so not mentioned here. 3331let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3332 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3333def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3334 "GETtlsldADDR32", 3335 [(set i32:$rD, 3336 (PPCgetTlsldAddr i32:$reg, 3337 tglobaltlsaddr:$sym))]>; 3338// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3339// are true defines while the rest of the Defs are clobbers. 3340let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3341 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3342def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3343 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3344 "#ADDItlsldLADDR32", 3345 [(set i32:$rD, 3346 (PPCaddiTlsldLAddr i32:$reg, 3347 tglobaltlsaddr:$disp, 3348 tglobaltlsaddr:$sym))]>; 3349def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3350 "#ADDIdtprelL32", 3351 [(set i32:$rD, 3352 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3353def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3354 "#ADDISdtprelHA32", 3355 [(set i32:$rD, 3356 (PPCaddisDtprelHA i32:$reg, 3357 tglobaltlsaddr:$disp))]>; 3358 3359// Support for Position-independent code 3360def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3361 "#LWZtoc", 3362 [(set i32:$rD, 3363 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3364def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3365 "#LWZtocL", 3366 [(set i32:$rD, 3367 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3368def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3369 "#ADDIStocHA", 3370 [(set i32:$rD, 3371 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3372 3373// Get Global (GOT) Base Register offset, from the word immediately preceding 3374// the function label. 3375def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3376 3377// Pseudo-instruction marked for deletion. When deleting the instruction would 3378// cause iterator invalidation in MIR transformation passes, this pseudo can be 3379// used instead. It will be removed unconditionally at pre-emit time (prior to 3380// branch selection). 3381def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3382 3383// Standard shifts. These are represented separately from the real shifts above 3384// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3385// amounts. 3386def : Pat<(sra i32:$rS, i32:$rB), 3387 (SRAW $rS, $rB)>; 3388def : Pat<(srl i32:$rS, i32:$rB), 3389 (SRW $rS, $rB)>; 3390def : Pat<(shl i32:$rS, i32:$rB), 3391 (SLW $rS, $rB)>; 3392 3393def : Pat<(i32 (zextloadi1 iaddr:$src)), 3394 (LBZ iaddr:$src)>; 3395def : Pat<(i32 (zextloadi1 xaddr:$src)), 3396 (LBZX xaddr:$src)>; 3397def : Pat<(i32 (extloadi1 iaddr:$src)), 3398 (LBZ iaddr:$src)>; 3399def : Pat<(i32 (extloadi1 xaddr:$src)), 3400 (LBZX xaddr:$src)>; 3401def : Pat<(i32 (extloadi8 iaddr:$src)), 3402 (LBZ iaddr:$src)>; 3403def : Pat<(i32 (extloadi8 xaddr:$src)), 3404 (LBZX xaddr:$src)>; 3405def : Pat<(i32 (extloadi16 iaddr:$src)), 3406 (LHZ iaddr:$src)>; 3407def : Pat<(i32 (extloadi16 xaddr:$src)), 3408 (LHZX xaddr:$src)>; 3409let Predicates = [HasFPU] in { 3410def : Pat<(f64 (extloadf32 iaddr:$src)), 3411 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 3412def : Pat<(f64 (extloadf32 xaddr:$src)), 3413 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 3414 3415def : Pat<(f64 (fpextend f32:$src)), 3416 (COPY_TO_REGCLASS $src, F8RC)>; 3417} 3418 3419// Only seq_cst fences require the heavyweight sync (SYNC 0). 3420// All others can use the lightweight sync (SYNC 1). 3421// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3422// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3423// versions of Power. 3424def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3425def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3426def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3427def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3428 3429let Predicates = [HasFPU] in { 3430// Additional fnmsub patterns for custom node 3431def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3432 (FNMSUB $A, $B, $C)>; 3433def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3434 (FNMSUBS $A, $B, $C)>; 3435def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3436 (FMSUB $A, $B, $C)>; 3437def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3438 (FMSUBS $A, $B, $C)>; 3439def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3440 (FNMADD $A, $B, $C)>; 3441def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3442 (FNMADDS $A, $B, $C)>; 3443 3444// FCOPYSIGN's operand types need not agree. 3445def : Pat<(fcopysign f64:$frB, f32:$frA), 3446 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3447def : Pat<(fcopysign f32:$frB, f64:$frA), 3448 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3449} 3450 3451include "PPCInstrAltivec.td" 3452include "PPCInstrSPE.td" 3453include "PPCInstr64Bit.td" 3454include "PPCInstrVSX.td" 3455include "PPCInstrQPX.td" 3456include "PPCInstrHTM.td" 3457 3458def crnot : OutPatFrag<(ops node:$in), 3459 (CRNOR $in, $in)>; 3460def : Pat<(not i1:$in), 3461 (crnot $in)>; 3462 3463// Prefixed instructions may require access to the above defs at a later 3464// time so we include this after the def. 3465include "PPCInstrPrefix.td" 3466 3467// Patterns for arithmetic i1 operations. 3468def : Pat<(add i1:$a, i1:$b), 3469 (CRXOR $a, $b)>; 3470def : Pat<(sub i1:$a, i1:$b), 3471 (CRXOR $a, $b)>; 3472def : Pat<(mul i1:$a, i1:$b), 3473 (CRAND $a, $b)>; 3474 3475// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3476// (-1 is used to mean all bits set). 3477def : Pat<(i1 -1), (CRSET)>; 3478 3479// i1 extensions, implemented in terms of isel. 3480def : Pat<(i32 (zext i1:$in)), 3481 (SELECT_I4 $in, (LI 1), (LI 0))>; 3482def : Pat<(i32 (sext i1:$in)), 3483 (SELECT_I4 $in, (LI -1), (LI 0))>; 3484 3485def : Pat<(i64 (zext i1:$in)), 3486 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3487def : Pat<(i64 (sext i1:$in)), 3488 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3489 3490// FIXME: We should choose either a zext or a sext based on other constants 3491// already around. 3492def : Pat<(i32 (anyext i1:$in)), 3493 (SELECT_I4 $in, (LI 1), (LI 0))>; 3494def : Pat<(i64 (anyext i1:$in)), 3495 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3496 3497// match setcc on i1 variables. 3498// CRANDC is: 3499// 1 1 : F 3500// 1 0 : T 3501// 0 1 : F 3502// 0 0 : F 3503// 3504// LT is: 3505// -1 -1 : F 3506// -1 0 : T 3507// 0 -1 : F 3508// 0 0 : F 3509// 3510// ULT is: 3511// 1 1 : F 3512// 1 0 : F 3513// 0 1 : T 3514// 0 0 : F 3515def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3516 (CRANDC $s1, $s2)>; 3517def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3518 (CRANDC $s2, $s1)>; 3519// CRORC is: 3520// 1 1 : T 3521// 1 0 : T 3522// 0 1 : F 3523// 0 0 : T 3524// 3525// LE is: 3526// -1 -1 : T 3527// -1 0 : T 3528// 0 -1 : F 3529// 0 0 : T 3530// 3531// ULE is: 3532// 1 1 : T 3533// 1 0 : F 3534// 0 1 : T 3535// 0 0 : T 3536def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3537 (CRORC $s1, $s2)>; 3538def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3539 (CRORC $s2, $s1)>; 3540 3541def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3542 (CREQV $s1, $s2)>; 3543 3544// GE is: 3545// -1 -1 : T 3546// -1 0 : F 3547// 0 -1 : T 3548// 0 0 : T 3549// 3550// UGE is: 3551// 1 1 : T 3552// 1 0 : T 3553// 0 1 : F 3554// 0 0 : T 3555def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3556 (CRORC $s2, $s1)>; 3557def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3558 (CRORC $s1, $s2)>; 3559 3560// GT is: 3561// -1 -1 : F 3562// -1 0 : F 3563// 0 -1 : T 3564// 0 0 : F 3565// 3566// UGT is: 3567// 1 1 : F 3568// 1 0 : T 3569// 0 1 : F 3570// 0 0 : F 3571def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3572 (CRANDC $s2, $s1)>; 3573def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3574 (CRANDC $s1, $s2)>; 3575 3576def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3577 (CRXOR $s1, $s2)>; 3578 3579// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3580// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3581// floating-point types. 3582 3583multiclass CRNotPat<dag pattern, dag result> { 3584 def : Pat<pattern, (crnot result)>; 3585 def : Pat<(not pattern), result>; 3586 3587 // We can also fold the crnot into an extension: 3588 def : Pat<(i32 (zext pattern)), 3589 (SELECT_I4 result, (LI 0), (LI 1))>; 3590 def : Pat<(i32 (sext pattern)), 3591 (SELECT_I4 result, (LI 0), (LI -1))>; 3592 3593 // We can also fold the crnot into an extension: 3594 def : Pat<(i64 (zext pattern)), 3595 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3596 def : Pat<(i64 (sext pattern)), 3597 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3598 3599 // FIXME: We should choose either a zext or a sext based on other constants 3600 // already around. 3601 def : Pat<(i32 (anyext pattern)), 3602 (SELECT_I4 result, (LI 0), (LI 1))>; 3603 3604 def : Pat<(i64 (anyext pattern)), 3605 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3606} 3607 3608// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3609// we need to write imm:$imm in the output patterns below, not just $imm, or 3610// else the resulting matcher will not correctly add the immediate operand 3611// (making it a register operand instead). 3612 3613// extended SETCC. 3614multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3615 OutPatFrag rfrag, OutPatFrag rfrag8> { 3616 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3617 (rfrag $s1)>; 3618 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3619 (rfrag8 $s1)>; 3620 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3621 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3622 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3623 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3624 3625 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3626 (rfrag $s1)>; 3627 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3628 (rfrag8 $s1)>; 3629 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3630 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3631 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3632 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3633} 3634 3635// Note that we do all inversions below with i(32|64)not, instead of using 3636// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3637// has 2-cycle latency. 3638 3639defm : ExtSetCCPat<SETEQ, 3640 PatFrag<(ops node:$in, node:$cc), 3641 (setcc $in, 0, $cc)>, 3642 OutPatFrag<(ops node:$in), 3643 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3644 OutPatFrag<(ops node:$in), 3645 (RLDICL (CNTLZD $in), 58, 63)> >; 3646 3647defm : ExtSetCCPat<SETNE, 3648 PatFrag<(ops node:$in, node:$cc), 3649 (setcc $in, 0, $cc)>, 3650 OutPatFrag<(ops node:$in), 3651 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3652 OutPatFrag<(ops node:$in), 3653 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3654 3655defm : ExtSetCCPat<SETLT, 3656 PatFrag<(ops node:$in, node:$cc), 3657 (setcc $in, 0, $cc)>, 3658 OutPatFrag<(ops node:$in), 3659 (RLWINM $in, 1, 31, 31)>, 3660 OutPatFrag<(ops node:$in), 3661 (RLDICL $in, 1, 63)> >; 3662 3663defm : ExtSetCCPat<SETGE, 3664 PatFrag<(ops node:$in, node:$cc), 3665 (setcc $in, 0, $cc)>, 3666 OutPatFrag<(ops node:$in), 3667 (RLWINM (i32not $in), 1, 31, 31)>, 3668 OutPatFrag<(ops node:$in), 3669 (RLDICL (i64not $in), 1, 63)> >; 3670 3671defm : ExtSetCCPat<SETGT, 3672 PatFrag<(ops node:$in, node:$cc), 3673 (setcc $in, 0, $cc)>, 3674 OutPatFrag<(ops node:$in), 3675 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3676 OutPatFrag<(ops node:$in), 3677 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3678 3679defm : ExtSetCCPat<SETLE, 3680 PatFrag<(ops node:$in, node:$cc), 3681 (setcc $in, 0, $cc)>, 3682 OutPatFrag<(ops node:$in), 3683 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3684 OutPatFrag<(ops node:$in), 3685 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3686 3687defm : ExtSetCCPat<SETLT, 3688 PatFrag<(ops node:$in, node:$cc), 3689 (setcc $in, -1, $cc)>, 3690 OutPatFrag<(ops node:$in), 3691 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3692 OutPatFrag<(ops node:$in), 3693 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3694 3695defm : ExtSetCCPat<SETGE, 3696 PatFrag<(ops node:$in, node:$cc), 3697 (setcc $in, -1, $cc)>, 3698 OutPatFrag<(ops node:$in), 3699 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3700 OutPatFrag<(ops node:$in), 3701 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3702 3703defm : ExtSetCCPat<SETGT, 3704 PatFrag<(ops node:$in, node:$cc), 3705 (setcc $in, -1, $cc)>, 3706 OutPatFrag<(ops node:$in), 3707 (RLWINM (i32not $in), 1, 31, 31)>, 3708 OutPatFrag<(ops node:$in), 3709 (RLDICL (i64not $in), 1, 63)> >; 3710 3711defm : ExtSetCCPat<SETLE, 3712 PatFrag<(ops node:$in, node:$cc), 3713 (setcc $in, -1, $cc)>, 3714 OutPatFrag<(ops node:$in), 3715 (RLWINM $in, 1, 31, 31)>, 3716 OutPatFrag<(ops node:$in), 3717 (RLDICL $in, 1, 63)> >; 3718 3719// An extended SETCC with shift amount. 3720multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3721 OutPatFrag rfrag, OutPatFrag rfrag8> { 3722 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3723 (rfrag $s1, $sa)>; 3724 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3725 (rfrag8 $s1, $sa)>; 3726 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3727 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3728 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3729 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3730 3731 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3732 (rfrag $s1, $sa)>; 3733 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3734 (rfrag8 $s1, $sa)>; 3735 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3736 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3737 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3738 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3739} 3740 3741defm : ExtSetCCShiftPat<SETNE, 3742 PatFrag<(ops node:$in, node:$sa, node:$cc), 3743 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3744 OutPatFrag<(ops node:$in, node:$sa), 3745 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3746 OutPatFrag<(ops node:$in, node:$sa), 3747 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3748 3749defm : ExtSetCCShiftPat<SETEQ, 3750 PatFrag<(ops node:$in, node:$sa, node:$cc), 3751 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3752 OutPatFrag<(ops node:$in, node:$sa), 3753 (RLWNM (i32not $in), 3754 (SUBFIC $sa, 32), 31, 31)>, 3755 OutPatFrag<(ops node:$in, node:$sa), 3756 (RLDCL (i64not $in), 3757 (SUBFIC $sa, 64), 63)> >; 3758 3759// SETCC for i32. 3760def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3761 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3762def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3763 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3764def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3765 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3766def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3767 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3768def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3769 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3770def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3771 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3772 3773// For non-equality comparisons, the default code would materialize the 3774// constant, then compare against it, like this: 3775// lis r2, 4660 3776// ori r2, r2, 22136 3777// cmpw cr0, r3, r2 3778// beq cr0,L6 3779// Since we are just comparing for equality, we can emit this instead: 3780// xoris r0,r3,0x1234 3781// cmplwi cr0,r0,0x5678 3782// beq cr0,L6 3783 3784def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3785 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3786 (LO16 imm:$imm)), sub_eq)>; 3787 3788def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3789 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3790def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3791 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3792def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3793 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3794def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3795 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3796def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3797 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3798 3799// SETCC for i64. 3800def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3801 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3802def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3803 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3804def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3805 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3806def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3807 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3808def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3809 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3810def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3811 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3812 3813// For non-equality comparisons, the default code would materialize the 3814// constant, then compare against it, like this: 3815// lis r2, 4660 3816// ori r2, r2, 22136 3817// cmpd cr0, r3, r2 3818// beq cr0,L6 3819// Since we are just comparing for equality, we can emit this instead: 3820// xoris r0,r3,0x1234 3821// cmpldi cr0,r0,0x5678 3822// beq cr0,L6 3823 3824def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3825 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3826 (LO16 imm:$imm)), sub_eq)>; 3827 3828def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3829 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3830def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3831 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3832def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3833 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3834def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3835 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3836def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3837 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3838 3839// Instantiations of CRNotPat for i32. 3840defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3841 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3842defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3843 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3844defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3845 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3846defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3847 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3848defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3849 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3850defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3851 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3852 3853defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3854 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3855 (LO16 imm:$imm)), sub_eq)>; 3856 3857defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3858 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3859defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3860 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3861defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3862 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3863defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3864 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3865defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3866 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3867 3868// Instantiations of CRNotPat for i64. 3869defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3870 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3871defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3872 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3873defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3874 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3875defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3876 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3877defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3878 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3879defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3880 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3881 3882defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3883 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3884 (LO16 imm:$imm)), sub_eq)>; 3885 3886defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3887 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3888defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3889 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3890defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3891 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3892defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3893 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3894defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3895 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3896 3897let Predicates = [HasFPU] in { 3898// Instantiations of CRNotPat for f32. 3899defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3900 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3901defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3902 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3903defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3904 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3905defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3906 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3907defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3908 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3909defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3910 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3911defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 3912 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3913 3914// Instantiations of CRNotPat for f64. 3915defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3916 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3917defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3918 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3919defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3920 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3921defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3922 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3923defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3924 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3925defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3926 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3927defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 3928 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3929 3930// Instantiations of CRNotPat for f128. 3931defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)), 3932 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3933defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)), 3934 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3935defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)), 3936 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3937defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)), 3938 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3939defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)), 3940 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3941defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)), 3942 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3943defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)), 3944 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; 3945} 3946 3947// SETCC for f32. 3948let Predicates = [HasFPU] in { 3949def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3950 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3951def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3952 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3953def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3954 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3955def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3956 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3957def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3958 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3959def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3960 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3961def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 3962 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3963 3964// SETCC for f64. 3965def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3966 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3967def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3968 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3969def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3970 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3971def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3972 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3973def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3974 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3975def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3976 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3977def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 3978 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3979 3980// SETCC for f128. 3981def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOLT)), 3982 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3983def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETLT)), 3984 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3985def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOGT)), 3986 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3987def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETGT)), 3988 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3989def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOEQ)), 3990 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3991def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETEQ)), 3992 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3993def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETUO)), 3994 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; 3995 3996} 3997 3998// This must be in this file because it relies on patterns defined in this file 3999// after the inclusion of the instruction sets. 4000let Predicates = [HasSPE] in { 4001// SETCC for f32. 4002def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 4003 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4004def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 4005 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4006def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 4007 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4008def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 4009 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4010def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 4011 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4012def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 4013 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4014 4015defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 4016 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4017defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 4018 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4019defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 4020 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4021defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 4022 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4023defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 4024 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4025defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 4026 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4027 4028// SETCC for f64. 4029def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 4030 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4031def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 4032 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4033def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 4034 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4035def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 4036 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4037def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 4038 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4039def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 4040 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4041 4042defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 4043 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4044defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 4045 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4046defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 4047 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4048defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 4049 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4050defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 4051 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4052defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 4053 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4054} 4055// match select on i1 variables: 4056def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4057 (CROR (CRAND $cond , $tval), 4058 (CRAND (crnot $cond), $fval))>; 4059 4060// match selectcc on i1 variables: 4061// select (lhs == rhs), tval, fval is: 4062// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4063def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4064 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4065 (CRAND (CRORC $rhs, $lhs), $fval))>; 4066def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4067 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4068 (CRAND (CRORC $lhs, $rhs), $fval))>; 4069def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4070 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4071 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4072def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4073 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4074 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4075def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4076 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4077 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4078def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4079 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4080 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4081def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4082 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4083 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4084def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4085 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4086 (CRAND (CRORC $lhs, $rhs), $fval))>; 4087def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4088 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4089 (CRAND (CRORC $rhs, $lhs), $fval))>; 4090def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4091 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4092 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4093 4094// match selectcc on i1 variables with non-i1 output. 4095def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4096 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4097def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4098 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4099def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4100 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4101def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4102 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4103def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4104 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4105def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4106 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4107def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4108 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4109def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4110 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4111def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4112 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4113def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4114 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4115 4116def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4117 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4118def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4119 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4120def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4121 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4122def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4123 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4124def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4125 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4126def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4127 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4128def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4129 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4130def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4131 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4132def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4133 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4134def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4135 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4136 4137let Predicates = [HasFPU] in { 4138def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4139 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4140def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4141 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4142def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4143 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4144def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4145 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4146def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4147 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4148def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4149 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4150def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4151 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4152def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4153 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4154def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4155 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4156def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4157 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4158 4159def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4160 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4161def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4162 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4163def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4164 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4165def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4166 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4167def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4168 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4169def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4170 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4171def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4172 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4173def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4174 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4175def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4176 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4177def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4178 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4179} 4180 4181def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4182 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4183def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4184 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4185def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4186 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4187def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4188 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4189def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4190 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4191def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4192 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4193def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4194 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4195def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4196 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4197def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4198 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4199def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4200 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4201 4202def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4203 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4204def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4205 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4206def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4207 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4208def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4209 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4210def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4211 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4212def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4213 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4214def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4215 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4216def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4217 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4218def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4219 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4220def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4221 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4222 4223def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4224 "#ANDI_rec_1_EQ_BIT", 4225 [(set i1:$dst, (trunc (not i32:$in)))]>; 4226def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4227 "#ANDI_rec_1_GT_BIT", 4228 [(set i1:$dst, (trunc i32:$in))]>; 4229 4230def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4231 "#ANDI_rec_1_EQ_BIT8", 4232 [(set i1:$dst, (trunc (not i64:$in)))]>; 4233def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4234 "#ANDI_rec_1_GT_BIT8", 4235 [(set i1:$dst, (trunc i64:$in))]>; 4236 4237def : Pat<(i1 (not (trunc i32:$in))), 4238 (ANDI_rec_1_EQ_BIT $in)>; 4239def : Pat<(i1 (not (trunc i64:$in))), 4240 (ANDI_rec_1_EQ_BIT8 $in)>; 4241 4242//===----------------------------------------------------------------------===// 4243// PowerPC Instructions used for assembler/disassembler only 4244// 4245 4246// FIXME: For B=0 or B > 8, the registers following RT are used. 4247// WARNING: Do not add patterns for this instruction without fixing this. 4248def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4249 (ins gprc:$A, u5imm:$B), 4250 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4251 4252// FIXME: For B=0 or B > 8, the registers following RT are used. 4253// WARNING: Do not add patterns for this instruction without fixing this. 4254def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4255 (ins gprc:$RT, gprc:$A, u5imm:$B), 4256 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4257 4258def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4259 "isync", IIC_SprISYNC, []>; 4260 4261def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4262 "icbi $src", IIC_LdStICBI, []>; 4263 4264def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L), 4265 "wait $L", IIC_LdStLoad, []>; 4266 4267def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4268 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4269 4270def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4271 "mtsr $SR, $RS", IIC_SprMTSR>; 4272 4273def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4274 "mfsr $RS, $SR", IIC_SprMFSR>; 4275 4276def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4277 "mtsrin $RS, $RB", IIC_SprMTSR>; 4278 4279def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4280 "mfsrin $RS, $RB", IIC_SprMFSR>; 4281 4282def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 4283 "mtmsr $RS, $L", IIC_SprMTMSR>; 4284 4285def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4286 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4287 let L = 0; 4288} 4289 4290def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4291 Requires<[IsBookE]> { 4292 bits<1> E; 4293 4294 let Inst{16} = E; 4295 let Inst{21-30} = 163; 4296} 4297 4298def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4299 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4300def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4301 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4302 4303def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4304def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4305def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4306def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4307 4308def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4309 "mfmsr $RT", IIC_SprMFMSR, []>; 4310 4311def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 4312 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4313 4314def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4315 "mcrfs $BF, $BFA", IIC_BrMCR>; 4316 4317def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 4318 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4319 4320def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 4321 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4322 4323def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>; 4324def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>; 4325 4326let Predicates = [HasFPU] in { 4327def MTFSF : XFLForm_1<63, 711, (outs), 4328 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 4329 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4330def MTFSF_rec : XFLForm_1<63, 711, (outs), 4331 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 4332 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4333 4334def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4335def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4336} 4337 4338def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4339 "slbie $RB", IIC_SprSLBIE, []>; 4340 4341def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4342 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4343 4344def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4345 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4346 4347def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4348 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4349 4350def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4351 4352let Defs = [CR0] in 4353def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4354 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4355 4356def TLBIA : XForm_0<31, 370, (outs), (ins), 4357 "tlbia", IIC_SprTLBIA, []>; 4358 4359def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4360 "tlbsync", IIC_SprTLBSYNC, []>; 4361 4362def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4363 "tlbiel $RB", IIC_SprTLBIEL, []>; 4364 4365def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4366 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4367def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4368 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4369 4370def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4371 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4372 4373def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4374 IIC_LdStLoad>, Requires<[IsBookE]>; 4375 4376def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4377 IIC_LdStLoad>, Requires<[IsBookE]>; 4378 4379def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4380 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4381 4382def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4383 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4384 4385def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4386 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4387 4388def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4389 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4390 4391def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4392 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4393 Requires<[IsPPC4xx]>; 4394def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4395 (ins gprc:$RST, gprc:$A, gprc:$B), 4396 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4397 Requires<[IsPPC4xx]>, isRecordForm; 4398 4399def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4400 4401def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4402 Requires<[IsBookE]>; 4403def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4404 Requires<[IsBookE]>; 4405 4406def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4407 Requires<[IsE500]>; 4408def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4409 Requires<[IsE500]>; 4410 4411def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4412 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4413def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4414 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4415 4416def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4417def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4418 4419def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4420 4421def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4422 (ins gprc:$A, gprc:$B), 4423 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4424def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4425 (ins gprc:$A, gprc:$B), 4426 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4427def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4428 (ins gprc:$A, gprc:$B), 4429 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4430def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4431 (ins gprc:$A, gprc:$B), 4432 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4433 4434def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4435 (ins gprc:$RST, gprc:$A, gprc:$B), 4436 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4437def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4438 (ins gprc:$RST, gprc:$A, gprc:$B), 4439 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4440def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4441 (ins gprc:$RST, gprc:$A, gprc:$B), 4442 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4443def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4444 (ins gprc:$RST, gprc:$A, gprc:$B), 4445 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4446 4447// External PID Load Store Instructions 4448 4449def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4450 "lbepx $rD, $src", IIC_LdStLoad, []>, 4451 Requires<[IsE500]>; 4452 4453def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4454 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4455 Requires<[IsE500]>; 4456 4457def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4458 "lhepx $rD, $src", IIC_LdStLoad, []>, 4459 Requires<[IsE500]>; 4460 4461def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4462 "lwepx $rD, $src", IIC_LdStLoad, []>, 4463 Requires<[IsE500]>; 4464 4465def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4466 "stbepx $rS, $dst", IIC_LdStStore, []>, 4467 Requires<[IsE500]>; 4468 4469def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4470 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4471 Requires<[IsE500]>; 4472 4473def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4474 "sthepx $rS, $dst", IIC_LdStStore, []>, 4475 Requires<[IsE500]>; 4476 4477def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4478 "stwepx $rS, $dst", IIC_LdStStore, []>, 4479 Requires<[IsE500]>; 4480 4481def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4482 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4483 4484def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4485 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4486 4487def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4488 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4489 Requires<[IsE500]>; 4490 4491def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4492 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4493 Requires<[IsE500]>; 4494 4495def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4496 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4497 4498def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4499 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4500 4501def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4502 IIC_LdStICBI, []>, Requires<[IsE500]>; 4503 4504//===----------------------------------------------------------------------===// 4505// PowerPC Assembler Instruction Aliases 4506// 4507 4508// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4509// These are aliases that require C++ handling to convert to the target 4510// instruction, while InstAliases can be handled directly by tblgen. 4511class PPCAsmPseudo<string asm, dag iops> 4512 : Instruction { 4513 let Namespace = "PPC"; 4514 bit PPC64 = 0; // Default value, override with isPPC64 4515 4516 let OutOperandList = (outs); 4517 let InOperandList = iops; 4518 let Pattern = []; 4519 let AsmString = asm; 4520 let isAsmParserOnly = 1; 4521 let isPseudo = 1; 4522 let hasNoSchedulingInfo = 1; 4523} 4524 4525def : InstAlias<"sc", (SC 0)>; 4526 4527def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4528def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4529def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4530def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4531 4532def : InstAlias<"wait", (WAIT 0)>; 4533def : InstAlias<"waitrsv", (WAIT 1)>; 4534def : InstAlias<"waitimpl", (WAIT 2)>; 4535 4536def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4537 4538def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4539def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4540 4541def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4542def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4543def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4544 4545def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4546def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4547def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4548 4549def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4550def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4551def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4552 4553def : Pat<(int_ppc_isync), (ISYNC)>; 4554def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4555 (DCBF 1, xoaddr:$dst)>; 4556def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4557 (DCBF 3, xoaddr:$dst)>; 4558 4559def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4560def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4561def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4562def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4563 4564def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4565def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4566def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4567 4568def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4569 4570foreach BR = 0-7 in { 4571 def : InstAlias<"mfbr"#BR#" $Rx", 4572 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4573 Requires<[IsPPC4xx]>; 4574 def : InstAlias<"mtbr"#BR#" $Rx", 4575 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4576 Requires<[IsPPC4xx]>; 4577} 4578 4579def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4580def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4581 4582def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4583def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4584 4585def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4586def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4587 4588def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4589def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4590 4591def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4592def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4593 4594def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4595def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4596 4597def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4598def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4599 4600def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4601def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4602 4603def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4604def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4605 4606def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4607def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4608 4609def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4610def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4611 4612def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4613def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4614 4615def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4616def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4617 4618def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4619def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4620 4621def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4622def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4623 4624def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4625def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4626 4627def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4628def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4629 4630foreach SPRG = 4-7 in { 4631 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4632 Requires<[IsBookE]>; 4633 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4634 Requires<[IsBookE]>; 4635 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4636 Requires<[IsBookE]>; 4637 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4638 Requires<[IsBookE]>; 4639} 4640 4641foreach SPRG = 0-3 in { 4642 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4643 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4644 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4645 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4646} 4647 4648def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4649def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4650 4651def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4652def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4653 4654def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4655 4656def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4657def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4658 4659foreach BATR = 0-3 in { 4660 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4661 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4662 Requires<[IsPPC6xx]>; 4663 def : InstAlias<"mfdbatu $Rx, "#BATR, 4664 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4665 Requires<[IsPPC6xx]>; 4666 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4667 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4668 Requires<[IsPPC6xx]>; 4669 def : InstAlias<"mfdbatl $Rx, "#BATR, 4670 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4671 Requires<[IsPPC6xx]>; 4672 def : InstAlias<"mtibatu "#BATR#", $Rx", 4673 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4674 Requires<[IsPPC6xx]>; 4675 def : InstAlias<"mfibatu $Rx, "#BATR, 4676 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4677 Requires<[IsPPC6xx]>; 4678 def : InstAlias<"mtibatl "#BATR#", $Rx", 4679 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4680 Requires<[IsPPC6xx]>; 4681 def : InstAlias<"mfibatl $Rx, "#BATR, 4682 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4683 Requires<[IsPPC6xx]>; 4684} 4685 4686def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4687def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4688 4689def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4690def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4691 4692def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4693def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4694 4695def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4696def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4697 4698def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4699def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4700 4701def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4702def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4703 4704def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4705def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4706 4707def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4708def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4709 4710def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4711def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4712 4713def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4714def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4715 4716 4717def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4718 4719def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4720 Requires<[IsPPC4xx]>; 4721def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4722 Requires<[IsPPC4xx]>; 4723def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4724 Requires<[IsPPC4xx]>; 4725def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4726 Requires<[IsPPC4xx]>; 4727 4728def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4729 4730def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4731 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4732def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4733 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4734def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4735 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4736def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4737 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4738 4739def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4740 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4741def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4742 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4743def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4744 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4745def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4746 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4747def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4748 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4749def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4750 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4751def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4752 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4753def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4754 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4755def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4756 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4757def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4758 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4759def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4760 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4761def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4762 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4763def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4764 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4765def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4766 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4767def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4768 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4769def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4770 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4771def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4772 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4773def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4774 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4775 4776def : InstAlias<"isellt $rT, $rA, $rB", 4777 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4778def : InstAlias<"iselgt $rT, $rA, $rB", 4779 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4780def : InstAlias<"iseleq $rT, $rA, $rB", 4781 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4782 4783def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4784def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4785def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4786def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4787def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4788def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4789 4790def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4791def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4792// The POWER variant 4793def : MnemonicAlias<"cntlz", "cntlzw">; 4794def : MnemonicAlias<"cntlz.", "cntlzw.">; 4795 4796def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4797 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4798def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4799 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4800def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4801 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4802def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4803 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4804def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4805 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4806def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4807 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4808def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4809 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4810def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4811 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4812def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4813 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4814def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4815 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4816def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4817 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4818def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4819 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4820def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4821 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4822def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4823 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4824def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4825 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4826def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4827 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4828def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4829 4830def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4831def : InstAlias<"rotldi $rA, $rS, $n", 4832 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4833def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4834def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4835def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4836def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4837def : InstAlias<"clrldi $rA, $rS, $n", 4838 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4839def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4840def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4841 4842def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4843 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4844def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4845 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4846def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4847 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4848def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4849 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4850def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4851 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4852def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4853 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4854 4855// These generic branch instruction forms are used for the assembler parser only. 4856// Defs and Uses are conservative, since we don't know the BO value. 4857let PPC970_Unit = 7, isBranch = 1 in { 4858 let Defs = [CTR], Uses = [CTR, RM] in { 4859 def gBC : BForm_3<16, 0, 0, (outs), 4860 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4861 "bc $bo, $bi, $dst">; 4862 def gBCA : BForm_3<16, 1, 0, (outs), 4863 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4864 "bca $bo, $bi, $dst">; 4865 let isAsmParserOnly = 1 in { 4866 def gBCat : BForm_3_at<16, 0, 0, (outs), 4867 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4868 condbrtarget:$dst), 4869 "bc$at $bo, $bi, $dst">; 4870 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4871 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4872 abscondbrtarget:$dst), 4873 "bca$at $bo, $bi, $dst">; 4874 } // isAsmParserOnly = 1 4875 } 4876 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4877 def gBCL : BForm_3<16, 0, 1, (outs), 4878 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4879 "bcl $bo, $bi, $dst">; 4880 def gBCLA : BForm_3<16, 1, 1, (outs), 4881 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4882 "bcla $bo, $bi, $dst">; 4883 let isAsmParserOnly = 1 in { 4884 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4885 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4886 condbrtarget:$dst), 4887 "bcl$at $bo, $bi, $dst">; 4888 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4889 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4890 abscondbrtarget:$dst), 4891 "bcla$at $bo, $bi, $dst">; 4892 } // // isAsmParserOnly = 1 4893 } 4894 let Defs = [CTR], Uses = [CTR, LR, RM] in 4895 def gBCLR : XLForm_2<19, 16, 0, (outs), 4896 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4897 "bclr $bo, $bi, $bh", IIC_BrB, []>; 4898 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4899 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4900 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4901 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 4902 let Defs = [CTR], Uses = [CTR, LR, RM] in 4903 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4904 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4905 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 4906 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4907 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4908 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4909 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 4910} 4911 4912multiclass BranchSimpleMnemonicAT<string pm, int at> { 4913 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4914 condbrtarget:$dst)>; 4915 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4916 condbrtarget:$dst)>; 4917 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4918 condbrtarget:$dst)>; 4919 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4920 condbrtarget:$dst)>; 4921} 4922defm : BranchSimpleMnemonicAT<"+", 3>; 4923defm : BranchSimpleMnemonicAT<"-", 2>; 4924 4925def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4926def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4927def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4928def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4929 4930multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4931 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4932 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4933 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4934 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4935 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4936 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4937} 4938multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4939 : BranchSimpleMnemonic1<name, pm, bo> { 4940 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4941 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4942} 4943defm : BranchSimpleMnemonic2<"t", "", 12>; 4944defm : BranchSimpleMnemonic2<"f", "", 4>; 4945defm : BranchSimpleMnemonic2<"t", "-", 14>; 4946defm : BranchSimpleMnemonic2<"f", "-", 6>; 4947defm : BranchSimpleMnemonic2<"t", "+", 15>; 4948defm : BranchSimpleMnemonic2<"f", "+", 7>; 4949defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4950defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4951defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4952defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4953 4954multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4955 def : InstAlias<"b"#name#pm#" $cc, $dst", 4956 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4957 def : InstAlias<"b"#name#pm#" $dst", 4958 (BCC bibo, CR0, condbrtarget:$dst)>; 4959 4960 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4961 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4962 def : InstAlias<"b"#name#"a"#pm#" $dst", 4963 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4964 4965 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4966 (BCCLR bibo, crrc:$cc)>; 4967 def : InstAlias<"b"#name#"lr"#pm, 4968 (BCCLR bibo, CR0)>; 4969 4970 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4971 (BCCCTR bibo, crrc:$cc)>; 4972 def : InstAlias<"b"#name#"ctr"#pm, 4973 (BCCCTR bibo, CR0)>; 4974 4975 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4976 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4977 def : InstAlias<"b"#name#"l"#pm#" $dst", 4978 (BCCL bibo, CR0, condbrtarget:$dst)>; 4979 4980 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4981 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4982 def : InstAlias<"b"#name#"la"#pm#" $dst", 4983 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4984 4985 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4986 (BCCLRL bibo, crrc:$cc)>; 4987 def : InstAlias<"b"#name#"lrl"#pm, 4988 (BCCLRL bibo, CR0)>; 4989 4990 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4991 (BCCCTRL bibo, crrc:$cc)>; 4992 def : InstAlias<"b"#name#"ctrl"#pm, 4993 (BCCCTRL bibo, CR0)>; 4994} 4995multiclass BranchExtendedMnemonic<string name, int bibo> { 4996 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4997 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4998 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4999} 5000defm : BranchExtendedMnemonic<"lt", 12>; 5001defm : BranchExtendedMnemonic<"gt", 44>; 5002defm : BranchExtendedMnemonic<"eq", 76>; 5003defm : BranchExtendedMnemonic<"un", 108>; 5004defm : BranchExtendedMnemonic<"so", 108>; 5005defm : BranchExtendedMnemonic<"ge", 4>; 5006defm : BranchExtendedMnemonic<"nl", 4>; 5007defm : BranchExtendedMnemonic<"le", 36>; 5008defm : BranchExtendedMnemonic<"ng", 36>; 5009defm : BranchExtendedMnemonic<"ne", 68>; 5010defm : BranchExtendedMnemonic<"nu", 100>; 5011defm : BranchExtendedMnemonic<"ns", 100>; 5012 5013def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 5014def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 5015def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 5016def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 5017def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 5018def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 5019def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 5020def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5021 5022def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5023def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5024def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5025def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5026def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5027def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5028def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5029def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5030 5031def : InstAlias<"trap", (TW 31, R0, R0)>; 5032 5033multiclass TrapExtendedMnemonic<string name, int to> { 5034 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5035 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5036 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5037 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5038} 5039defm : TrapExtendedMnemonic<"lt", 16>; 5040defm : TrapExtendedMnemonic<"le", 20>; 5041defm : TrapExtendedMnemonic<"eq", 4>; 5042defm : TrapExtendedMnemonic<"ge", 12>; 5043defm : TrapExtendedMnemonic<"gt", 8>; 5044defm : TrapExtendedMnemonic<"nl", 12>; 5045defm : TrapExtendedMnemonic<"ne", 24>; 5046defm : TrapExtendedMnemonic<"ng", 20>; 5047defm : TrapExtendedMnemonic<"llt", 2>; 5048defm : TrapExtendedMnemonic<"lle", 6>; 5049defm : TrapExtendedMnemonic<"lge", 5>; 5050defm : TrapExtendedMnemonic<"lgt", 1>; 5051defm : TrapExtendedMnemonic<"lnl", 5>; 5052defm : TrapExtendedMnemonic<"lng", 6>; 5053defm : TrapExtendedMnemonic<"u", 31>; 5054 5055// Atomic loads 5056def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>; 5057def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>; 5058def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>; 5059def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>; 5060def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>; 5061def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>; 5062 5063// Atomic stores 5064def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 5065def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 5066def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 5067def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 5068def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 5069def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 5070 5071let Predicates = [IsISA3_0] in { 5072 5073// Copy-Paste Facility 5074// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5075// PASTE for naming consistency. 5076let mayLoad = 1 in 5077def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5078 5079let mayStore = 1 in 5080def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>; 5081 5082let mayStore = 1, Defs = [CR0] in 5083def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5084 5085def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>; 5086def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>; 5087def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB", 5088 (ins gprc:$rA, gprc:$rB)>; 5089def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB", 5090 (ins gprc:$rA, gprc:$rB)>; 5091def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>; 5092 5093// Message Synchronize 5094def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5095 5096// Power-Saving Mode Instruction: 5097def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5098 5099} // IsISA3_0 5100 5101// Fast 32-bit reverse bits algorithm: 5102// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5103// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5104// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5105// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5106// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5107// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5108// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5109// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5110// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5111// Step 4.2: Insert B3 to the right position: 5112// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5113// Step 4.3: Insert B1 to the right position: 5114// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5115def MaskValues { 5116 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5117 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5118 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5119 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5120 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5121 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5122} 5123 5124def Shift1 { 5125 dag Right = (RLWINM $A, 31, 1, 31); 5126 dag Left = (RLWINM $A, 1, 0, 30); 5127} 5128 5129def Swap1 { 5130 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5131 (AND Shift1.Left, MaskValues.Hi1)); 5132} 5133 5134def Shift2 { 5135 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5136 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5137} 5138 5139def Swap2 { 5140 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5141 (AND Shift2.Left, MaskValues.Hi2)); 5142} 5143 5144def Shift4 { 5145 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5146 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5147} 5148 5149def Swap4 { 5150 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5151 (AND Shift4.Left, MaskValues.Hi4)); 5152} 5153 5154def Rotate { 5155 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5156} 5157 5158def RotateInsertByte3 { 5159 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5160} 5161 5162def RotateInsertByte1 { 5163 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5164} 5165 5166// Clear the upper half of the register when in 64-bit mode 5167let Predicates = [In64BitMode] in 5168def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5169let Predicates = [In32BitMode] in 5170def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5171 5172// Fast 64-bit reverse bits algorithm: 5173// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5174// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5175// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5176// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5177// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5178// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5179// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5180// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5181// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5182// then OR them together to get the final result. 5183def MaskValues64 { 5184 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5185 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5186 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5187 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5188 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5189 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5190} 5191 5192def DWMaskValues { 5193 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5194 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5195 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5196 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5197 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5198 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5199} 5200 5201def DWSwapInByte { 5202 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5203 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5204 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5205 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5206 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5207 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5208} 5209 5210// Intra-byte swap is done, now start inter-byte swap. 5211def DWBytes4567 { 5212 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5213} 5214 5215def DWBytes7456 { 5216 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5217} 5218 5219def DWBytes7656 { 5220 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5221} 5222 5223// B7 B6 B5 B4 in the right order 5224def DWBytes7654 { 5225 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5226 dag DWord = 5227 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5228} 5229 5230def DWBytes0123 { 5231 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5232} 5233 5234def DWBytes3012 { 5235 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5236} 5237 5238def DWBytes3212 { 5239 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5240} 5241 5242// B3 B2 B1 B0 in the right order 5243def DWBytes3210 { 5244 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5245 dag DWord = 5246 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5247} 5248 5249// Now both high word and low word are reversed, next 5250// swap the high word and low word. 5251def : Pat<(i64 (bitreverse i64:$A)), 5252 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5253