1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86def SDT_StoreCond : SDTypeProfile<0, 3, [ 87 SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2> 88]>; 89 90def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 91 SDTCisPtrTy<0>, SDTCisVT<1, i32> 92]>; 93 94def tocentry32 : Operand<iPTR> { 95 let MIOperandInfo = (ops i32imm:$imm); 96} 97 98def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 99 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 100]>; 101def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 102 SDTCisVec<0>, SDTCisInt<1> 103]>; 104def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 106]>; 107def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 108 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 109]>; 110 111def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 112 SDTCisVec<0>, SDTCisVec<1> 113]>; 114 115def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 116 SDTCisVec<0>, SDTCisPtrTy<1> 117]>; 118 119def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 120 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 121]>; 122 123def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 125]>; 126 127//===----------------------------------------------------------------------===// 128// PowerPC specific DAG Nodes. 129// 130 131def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 132def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 133def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 134def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 135 136def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 137def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 138def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 139def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 140def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 141def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 142def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 143def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 144 145def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 146 SDTFPUnaryOp, [SDNPHasChain]>; 147def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 148 SDTFPUnaryOp, [SDNPHasChain]>; 149def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 150 SDTFPRoundOp, [SDNPHasChain]>; 151def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 152 SDTFPRoundOp, [SDNPHasChain]>; 153 154def PPCany_fcfid : PatFrags<(ops node:$op), 155 [(PPCfcfid node:$op), 156 (PPCstrict_fcfid node:$op)]>; 157def PPCany_fcfidu : PatFrags<(ops node:$op), 158 [(PPCfcfidu node:$op), 159 (PPCstrict_fcfidu node:$op)]>; 160def PPCany_fcfids : PatFrags<(ops node:$op), 161 [(PPCfcfids node:$op), 162 (PPCstrict_fcfids node:$op)]>; 163def PPCany_fcfidus : PatFrags<(ops node:$op), 164 [(PPCfcfidus node:$op), 165 (PPCstrict_fcfidus node:$op)]>; 166 167def PPCstore_scal_int_from_vsr: 168 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 169 [SDNPHasChain, SDNPMayStore]>; 170def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 171 [SDNPHasChain, SDNPMayStore]>; 172def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 173 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 174def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 175 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 176def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 177 [SDNPHasChain, SDNPMayLoad]>; 178def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 179 [SDNPHasChain, SDNPMayStore]>; 180def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 181 182// Extract FPSCR (not modeled at the DAG level). 183def PPCmffs : SDNode<"PPCISD::MFFS", 184 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 185 [SDNPHasChain]>; 186 187// Perform FADD in round-to-zero mode. 188def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 189def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 190 [SDNPHasChain]>; 191 192def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 193 [(PPCfaddrtz node:$lhs, node:$rhs), 194 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 195 196def PPCfsel : SDNode<"PPCISD::FSEL", 197 // Type constraint for fsel. 198 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 199 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 200def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 201def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 202def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 203def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 204def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 205 [SDNPMayLoad, SDNPMemOperand]>; 206 207def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 208 209def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 210def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 211 [SDNPMayLoad]>; 212def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 213def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 214def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 215def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 216def PPCgetTlsMod : SDNode<"PPCISD::GET_TLS_MOD_AIX", SDTIntUnaryOp>; 217def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>; 218def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 219 SDTypeProfile<1, 3, [ 220 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 221 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 222def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 223def PPCTlsldAIX : SDNode<"PPCISD::TLSLD_AIX", SDTIntUnaryOp>; 224def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 225def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 226def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 227def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 228 SDTypeProfile<1, 3, [ 229 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 230 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 231def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 232def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 233def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 234 235def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 236def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 237def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 238def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 239def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 240def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 241 242def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 243 244// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 245// amounts. These nodes are generated by the multi-precision shift code. 246def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 247def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 248def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 249 250def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 251 252def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 253 254def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 261 SDTFPUnaryOp, [SDNPHasChain]>; 262 263def PPCany_fctidz : PatFrags<(ops node:$op), 264 [(PPCstrict_fctidz node:$op), 265 (PPCfctidz node:$op)]>; 266def PPCany_fctiwz : PatFrags<(ops node:$op), 267 [(PPCstrict_fctiwz node:$op), 268 (PPCfctiwz node:$op)]>; 269def PPCany_fctiduz : PatFrags<(ops node:$op), 270 [(PPCstrict_fctiduz node:$op), 271 (PPCfctiduz node:$op)]>; 272def PPCany_fctiwuz : PatFrags<(ops node:$op), 273 [(PPCstrict_fctiwuz node:$op), 274 (PPCfctiwuz node:$op)]>; 275 276// Move 2 i64 values into a VSX register 277def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 278 SDTypeProfile<1, 2, 279 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 280 SDTCisSameAs<1,2>]>, 281 []>; 282 283def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 284 SDTypeProfile<1, 2, 285 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 286 SDTCisVT<1,i32>]>, 287 []>; 288 289def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 290 SDTypeProfile<1, 2, 291 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 292 SDTCisPtrTy<2>]>, 293 []>; 294 295// These are target-independent nodes, but have target-specific formats. 296def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 297 [SDNPHasChain, SDNPOutGlue]>; 298def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 299 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 300 301def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 302def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 303 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 304 SDNPVariadic]>; 305def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 306 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 307 SDNPVariadic]>; 308def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 309 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 310 SDNPVariadic]>; 311def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 313def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 314 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 315 SDNPVariadic]>; 316def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 317 SDTypeProfile<0, 1, []>, 318 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 319 SDNPVariadic]>; 320 321// Call nodes for strictfp calls (that define RM). 322def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 323 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 324 SDNPVariadic]>; 325def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 326 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 327 SDNPVariadic]>; 328def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 329 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 330 SDNPVariadic]>; 331def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 332 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 333 SDNPVariadic]>; 334def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 335 SDTypeProfile<0, 1, []>, 336 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 337 SDNPVariadic]>; 338 339def PPCretglue : SDNode<"PPCISD::RET_GLUE", SDTNone, 340 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 341 342def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 343 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 344 345def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 346 SDTypeProfile<1, 1, [SDTCisInt<0>, 347 SDTCisPtrTy<1>]>, 348 [SDNPHasChain, SDNPSideEffect]>; 349def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 350 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 351 [SDNPHasChain, SDNPSideEffect]>; 352 353def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 354def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 355 [SDNPHasChain, SDNPSideEffect]>; 356 357def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 358 [SDNPHasChain, SDNPSideEffect]>; 359def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 360def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 361 [SDNPHasChain, SDNPSideEffect]>; 362 363def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 364def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 365 366def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 367 [SDNPHasChain, SDNPOptInGlue]>; 368 369// PPC-specific atomic operations. 370def PPCatomicCmpSwap_8 : 371 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 372 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 373def PPCatomicCmpSwap_16 : 374 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 376def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 377 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 378def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 379 [SDNPHasChain, SDNPMayStore]>; 380def PPCStoreCond : SDNode<"PPCISD::STORE_COND", SDT_StoreCond, 381 [SDNPHasChain, SDNPMayStore, 382 SDNPMemOperand, SDNPOutGlue]>; 383 384// Instructions to set/unset CR bit 6 for SVR4 vararg calls 385def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 386 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 387def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 388 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 389 390// Instructions to support dynamic alloca. 391def SDTDynOp : SDTypeProfile<1, 2, []>; 392def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 393def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 394def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 395def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 396 397// PC Relative Specific Nodes 398def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 399def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 400 SDTIntUnaryOp, []>; 401def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 402 SDTIntUnaryOp, []>; 403 404//===----------------------------------------------------------------------===// 405// PowerPC specific transformation functions and pattern fragments. 406// 407 408// A floating point immediate that is not a positive zero and can be converted 409// to a single precision floating point non-denormal immediate without loss of 410// information. 411def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 412 APFloat APFloatOfN = N->getValueAPF(); 413 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 414}]>; 415 416// A floating point immediate that is exactly an integer (for example 3.0, -5.0) 417// and can be represented in 5 bits (range of [-16, 15]). 418def nzFPImmExactInti5 : PatLeaf<(fpimm), [{ 419 APFloat FloatValue = N->getValueAPF(); 420 bool IsExact; 421 APSInt IntResult(16, false); 422 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 423 return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero(); 424}]>; 425 426def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{ 427 APFloat FloatValue = N->getValueAPF(); 428 bool IsExact; 429 APSInt IntResult(32, false); 430 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 431 return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32); 432}]>; 433 434// Convert the floating point immediate into a 32 bit floating point immediate 435// and get a i32 with the resulting bits. 436def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 437 APFloat APFloatOfN = N->getValueAPF(); 438 convertToNonDenormSingle(APFloatOfN); 439 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 440 SDLoc(N), MVT::i32); 441}]>; 442 443// Check if the value can be converted to be single precision immediate, which 444// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 445// precision before exploiting with XXSPLTI32DX. 446def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 447 APFloat APFloatOfN = N->getValueAPF(); 448 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 449}]>; 450 451// Get the Hi bits of a 64 bit immediate. 452def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 453 APFloat APFloatOfN = N->getValueAPF(); 454 bool Unused; 455 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 456 &Unused); 457 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 458 0xFFFFFFFF00000000LL) >> 32); 459 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 460}]>; 461 462// Get the Lo bits of a 64 bit immediate. 463def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 464 APFloat APFloatOfN = N->getValueAPF(); 465 bool Unused; 466 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 467 &Unused); 468 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 469 0xFFFFFFFF); 470 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 471}]>; 472 473def imm34 : PatLeaf<(imm), [{ 474 return isInt<34>(N->getSExtValue()); 475}]>; 476 477def getImmAs64BitInt : SDNodeXForm<imm, [{ 478 return getI64Imm(N->getSExtValue(), SDLoc(N)); 479}]>; 480 481def SHL32 : SDNodeXForm<imm, [{ 482 // Transformation function: 31 - imm 483 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 484}]>; 485 486def SRL32 : SDNodeXForm<imm, [{ 487 // Transformation function: 32 - imm 488 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 489 : getI32Imm(0, SDLoc(N)); 490}]>; 491 492def LO16 : SDNodeXForm<imm, [{ 493 // Transformation function: get the low 16 bits. 494 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 495}]>; 496 497def HI16 : SDNodeXForm<imm, [{ 498 // Transformation function: shift the immediate value down into the low bits. 499 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 500}]>; 501 502def HA16 : SDNodeXForm<imm, [{ 503 // Transformation function: shift the immediate value down into the low bits. 504 int64_t Val = N->getZExtValue(); 505 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 506}]>; 507def MB : SDNodeXForm<imm, [{ 508 // Transformation function: get the start bit of a mask 509 unsigned mb = 0, me; 510 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 511 return getI32Imm(mb, SDLoc(N)); 512}]>; 513 514def ME : SDNodeXForm<imm, [{ 515 // Transformation function: get the end bit of a mask 516 unsigned mb, me = 0; 517 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 518 return getI32Imm(me, SDLoc(N)); 519}]>; 520def maskimm32 : PatLeaf<(imm), [{ 521 // maskImm predicate - True if immediate is a run of ones. 522 unsigned mb, me; 523 if (N->getValueType(0) == MVT::i32) 524 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 525 else 526 return false; 527}]>; 528 529def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 530 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 531 // sign extended field. Used by instructions like 'addi'. 532 return (int32_t)Imm == (short)Imm; 533}]>; 534def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 535 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 536 // sign extended field. Used by instructions like 'addi'. 537 return (int64_t)Imm == (short)Imm; 538}]>; 539def immZExt16 : PatLeaf<(imm), [{ 540 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 541 // field. Used by instructions like 'ori'. 542 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 543}], LO16>; 544def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 545 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 546}]>; 547def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 548def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 549 550// imm16Shifted* - These match immediates where the low 16-bits are zero. There 551// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 552// identical in 32-bit mode, but in 64-bit mode, they return true if the 553// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 554// clear). 555def imm16ShiftedZExt : PatLeaf<(imm), [{ 556 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 557 // immediate are set. Used by instructions like 'xoris'. 558 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 559}], HI16>; 560 561def imm16ShiftedSExt : PatLeaf<(imm), [{ 562 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 563 // immediate are set. Used by instructions like 'addis'. Identical to 564 // imm16ShiftedZExt in 32-bit mode. 565 if (N->getZExtValue() & 0xFFFF) return false; 566 if (N->getValueType(0) == MVT::i32) 567 return true; 568 // For 64-bit, make sure it is sext right. 569 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 570}], HI16>; 571 572def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 573 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 574 // zero extended field. 575 return isUInt<32>(Imm); 576}]>; 577 578// This is a somewhat weaker condition than actually checking for 4-byte 579// alignment. It is simply checking that the displacement can be represented 580// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 581// instructions). 582// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 583// restricted memrix (4-aligned) constants are alignment sensitive. If these 584// offsets are hidden behind TOC entries than the values of the lower-order 585// bits cannot be checked directly. As a result, we need to also incorporate 586// an alignment check into the relevant patterns. 587 588def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 589 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 590}]>; 591def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 592 (store node:$val, node:$ptr), [{ 593 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 594}]>; 595def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 596 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 597}]>; 598def DSFormPreStore : PatFrag< 599 (ops node:$val, node:$base, node:$offset), 600 (pre_store node:$val, node:$base, node:$offset), [{ 601 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 602}]>; 603 604def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 605 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 606}]>; 607def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 608 (store node:$val, node:$ptr), [{ 609 return cast<StoreSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 610}]>; 611def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 612 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 613}]>; 614 615// This is a somewhat weaker condition than actually checking for 16-byte 616// alignment. It is simply checking that the displacement can be represented 617// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 618// instructions). 619def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 620 return isOffsetMultipleOf(N, 16); 621}]>; 622def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 623 (store node:$val, node:$ptr), [{ 624 return isOffsetMultipleOf(N, 16); 625}]>; 626def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 627 return !isOffsetMultipleOf(N, 16); 628}]>; 629def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 630 (store node:$val, node:$ptr), [{ 631 return !isOffsetMultipleOf(N, 16); 632}]>; 633 634// PatFrag for binary operation whose operands are both non-constant 635class BinOpWithoutSImm16Operand<SDNode opcode> : 636 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 637 int16_t Imm; 638 return !isIntS16Immediate(N->getOperand(0), Imm) 639 && !isIntS16Immediate(N->getOperand(1), Imm); 640}]>; 641 642def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 643def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 644 645//===----------------------------------------------------------------------===// 646// PowerPC Flag Definitions. 647 648class isPPC64 { bit PPC64 = 1; } 649class isRecordForm { bit RC = 1; } 650 651class RegConstraint<string C> { 652 string Constraints = C; 653} 654class NoEncode<string E> { 655 string DisableEncoding = E; 656} 657 658 659// Define PowerPC specific addressing mode. 660 661// d-form 662def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 663// ds-form 664def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 665// dq-form 666def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 667// 8LS:d-form 668def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 669 670// Below forms are all x-form addressing mode, use three different ones so we 671// can make a accurate check for x-form instructions in ISEL. 672// x-form addressing mode whose associated displacement form is D. 673def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 674// x-form addressing mode whose associated displacement form is DS. 675def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 676// x-form addressing mode whose associated displacement form is DQ. 677def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 678 679def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 680 681// The address in a single register. This is used with the SjLj 682// pseudo-instructions. 683def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 684 685/// This is just the offset part of iaddr, used for preinc. 686def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 687 688// Load and Store Instruction Selection addressing modes. 689def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 690def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 691def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 692def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 693def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 694def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; 695def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; 696 697//===----------------------------------------------------------------------===// 698// PowerPC Instruction Predicate Definitions. 699def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 700def In64BitMode : Predicate<"Subtarget->isPPC64()">; 701def IsBookE : Predicate<"Subtarget->isBookE()">; 702def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 703def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 704def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 705def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 706def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 707def IsE500 : Predicate<"Subtarget->isE500()">; 708def HasSPE : Predicate<"Subtarget->hasSPE()">; 709def HasICBT : Predicate<"Subtarget->hasICBT()">; 710def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 711def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 712def NoNaNsFPMath 713 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 714def NaNsFPMath 715 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 716def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 717def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 718def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 719def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 720def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 721def HasFPU : Predicate<"Subtarget->hasFPU()">; 722def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 723def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 724 725// AIX assembler may not be modern enough to support some extended mne. 726def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 727 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 728def IsAIX : Predicate<"Subtarget->isAIXABI()">; 729def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 730def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; 731def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; 732 733//===----------------------------------------------------------------------===// 734// PowerPC Multiclass Definitions. 735multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 736 string asmbase, string asmstr, list<dag> pattern> { 737 let BaseName = asmbase in { 738 def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL, 739 !strconcat(asmbase, !strconcat(" ", asmstr)), 740 NoItinerary, pattern>, RecFormRel; 741 let Defs = [CR1] in 742 def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL, 743 !strconcat(asmbase, !strconcat(". ", asmstr)), 744 NoItinerary, []>, isRecordForm, RecFormRel; 745 } 746} 747 748multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 749 string asmbase, string asmstr, InstrItinClass itin, 750 list<dag> pattern> { 751 let BaseName = asmbase in { 752 def NAME : XForm_6<opcode, xo, OOL, IOL, 753 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 754 pattern>, RecFormRel; 755 let Defs = [CR0] in 756 def _rec : XForm_6<opcode, xo, OOL, IOL, 757 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 758 []>, isRecordForm, RecFormRel; 759 } 760} 761 762multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 763 string asmbase, string asmstr, InstrItinClass itin, 764 list<dag> pattern> { 765 let BaseName = asmbase in { 766 let Defs = [CARRY] in 767 def NAME : XForm_6<opcode, xo, OOL, IOL, 768 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 769 pattern>, RecFormRel; 770 let Defs = [CARRY, CR0] in 771 def _rec : XForm_6<opcode, xo, OOL, IOL, 772 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 773 []>, isRecordForm, RecFormRel; 774 } 775} 776 777multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 778 string asmbase, string asmstr, InstrItinClass itin, 779 list<dag> pattern> { 780 let BaseName = asmbase in { 781 let Defs = [CARRY] in 782 def NAME : XForm_10<opcode, xo, OOL, IOL, 783 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 784 pattern>, RecFormRel; 785 let Defs = [CARRY, CR0] in 786 def _rec : XForm_10<opcode, xo, OOL, IOL, 787 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 788 []>, isRecordForm, RecFormRel; 789 } 790} 791 792multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 793 string asmbase, string asmstr, InstrItinClass itin, 794 list<dag> pattern> { 795 let BaseName = asmbase in { 796 def NAME : XForm_11<opcode, xo, OOL, IOL, 797 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 798 pattern>, RecFormRel; 799 let Defs = [CR0] in 800 def _rec : XForm_11<opcode, xo, OOL, IOL, 801 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 802 []>, isRecordForm, RecFormRel; 803 } 804} 805 806multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 807 string asmbase, string asmstr, InstrItinClass itin, 808 list<dag> pattern> { 809 let BaseName = asmbase in { 810 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 811 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 812 pattern>, RecFormRel; 813 let Defs = [CR0] in 814 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 815 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 816 []>, isRecordForm, RecFormRel; 817 } 818} 819 820// Multiclass for instructions which have a record overflow form as well 821// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 822multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 823 string asmbase, string asmstr, InstrItinClass itin, 824 list<dag> pattern> { 825 let BaseName = asmbase in { 826 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 827 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 828 pattern>, RecFormRel; 829 let Defs = [CR0] in 830 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 831 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 832 []>, isRecordForm, RecFormRel; 833 } 834 let BaseName = !strconcat(asmbase, "O") in { 835 let Defs = [XER] in 836 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 837 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 838 []>, RecFormRel; 839 let Defs = [XER, CR0] in 840 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 841 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 842 []>, isRecordForm, RecFormRel; 843 } 844} 845 846// Multiclass for instructions for which the non record form is not cracked 847// and the record form is cracked (i.e. divw, mullw, etc.) 848multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 849 string asmbase, string asmstr, InstrItinClass itin, 850 list<dag> pattern> { 851 let BaseName = asmbase in { 852 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 853 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 854 pattern>, RecFormRel; 855 let Defs = [CR0] in 856 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 857 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 858 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 859 PPC970_DGroup_Cracked; 860 } 861 let BaseName = !strconcat(asmbase, "O") in { 862 let Defs = [XER] in 863 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 864 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 865 []>, RecFormRel; 866 let Defs = [XER, CR0] in 867 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 868 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 869 []>, isRecordForm, RecFormRel; 870 } 871} 872 873multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 874 string asmbase, string asmstr, InstrItinClass itin, 875 list<dag> pattern> { 876 let BaseName = asmbase in { 877 let Defs = [CARRY] in 878 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 879 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 880 pattern>, RecFormRel; 881 let Defs = [CARRY, CR0] in 882 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 883 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 884 []>, isRecordForm, RecFormRel; 885 } 886 let BaseName = !strconcat(asmbase, "O") in { 887 let Defs = [CARRY, XER] in 888 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 889 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 890 []>, RecFormRel; 891 let Defs = [CARRY, XER, CR0] in 892 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 893 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 894 []>, isRecordForm, RecFormRel; 895 } 896} 897 898multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 899 string asmbase, string asmstr, InstrItinClass itin, 900 list<dag> pattern> { 901 let BaseName = asmbase in { 902 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 903 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 904 pattern>, RecFormRel; 905 let Defs = [CR0] in 906 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 907 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 908 []>, isRecordForm, RecFormRel; 909 } 910 let BaseName = !strconcat(asmbase, "O") in { 911 let Defs = [XER] in 912 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 913 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 914 []>, RecFormRel; 915 let Defs = [XER, CR0] in 916 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 917 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 918 []>, isRecordForm, RecFormRel; 919 } 920} 921 922multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 923 string asmbase, string asmstr, InstrItinClass itin, 924 list<dag> pattern> { 925 let BaseName = asmbase in { 926 let Defs = [CARRY] in 927 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 928 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 929 pattern>, RecFormRel; 930 let Defs = [CARRY, CR0] in 931 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 932 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 933 []>, isRecordForm, RecFormRel; 934 } 935 let BaseName = !strconcat(asmbase, "O") in { 936 let Defs = [CARRY, XER] in 937 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 938 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 939 []>, RecFormRel; 940 let Defs = [CARRY, XER, CR0] in 941 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 942 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 943 []>, isRecordForm, RecFormRel; 944 } 945} 946 947multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL, 948 string asmbase, string asmstr, InstrItinClass itin, 949 list<dag> pattern> { 950 let BaseName = asmbase in { 951 def NAME : MForm_1<opcode, OOL, IOL, 952 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 953 pattern>, RecFormRel; 954 let Defs = [CR0] in 955 def _rec : MForm_1<opcode, OOL, IOL, 956 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 957 []>, isRecordForm, RecFormRel; 958 } 959} 960 961multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 962 string asmbase, string asmstr, InstrItinClass itin, 963 list<dag> pattern> { 964 let BaseName = asmbase in { 965 def NAME : MForm_2<opcode, OOL, IOL, 966 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 967 pattern>, RecFormRel; 968 let Defs = [CR0] in 969 def _rec : MForm_2<opcode, OOL, IOL, 970 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 971 []>, isRecordForm, RecFormRel; 972 } 973} 974 975multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 976 string asmbase, string asmstr, InstrItinClass itin, 977 list<dag> pattern> { 978 let BaseName = asmbase in { 979 def NAME : MDForm_1<opcode, xo, OOL, IOL, 980 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 981 pattern>, RecFormRel; 982 let Defs = [CR0] in 983 def _rec : MDForm_1<opcode, xo, OOL, IOL, 984 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 985 []>, isRecordForm, RecFormRel; 986 } 987} 988 989multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 990 string asmbase, string asmstr, InstrItinClass itin, 991 list<dag> pattern> { 992 let BaseName = asmbase in { 993 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 994 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 995 pattern>, RecFormRel; 996 let Defs = [CR0] in 997 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 998 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 999 []>, isRecordForm, RecFormRel; 1000 } 1001} 1002 1003multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1004 string asmbase, string asmstr, InstrItinClass itin, 1005 list<dag> pattern> { 1006 let BaseName = asmbase in { 1007 let Defs = [CARRY] in 1008 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1009 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1010 pattern>, RecFormRel; 1011 let Defs = [CARRY, CR0] in 1012 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1013 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1014 []>, isRecordForm, RecFormRel; 1015 } 1016} 1017 1018multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1019 string asmbase, string asmstr, InstrItinClass itin, 1020 list<dag> pattern> { 1021 let BaseName = asmbase in { 1022 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1023 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1024 pattern>, RecFormRel; 1025 let Defs = [CR0] in 1026 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1027 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1028 []>, isRecordForm, RecFormRel; 1029 } 1030} 1031 1032multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1033 string asmbase, string asmstr, InstrItinClass itin, 1034 list<dag> pattern> { 1035 let BaseName = asmbase in { 1036 def NAME : XForm_26<opcode, xo, OOL, IOL, 1037 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1038 pattern>, RecFormRel; 1039 let Defs = [CR1] in 1040 def _rec : XForm_26<opcode, xo, OOL, IOL, 1041 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1042 []>, isRecordForm, RecFormRel; 1043 } 1044} 1045 1046multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1047 string asmbase, string asmstr, InstrItinClass itin, 1048 list<dag> pattern> { 1049 let BaseName = asmbase in { 1050 def NAME : XForm_28<opcode, xo, OOL, IOL, 1051 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1052 pattern>, RecFormRel; 1053 let Defs = [CR1] in 1054 def _rec : XForm_28<opcode, xo, OOL, IOL, 1055 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1056 []>, isRecordForm, RecFormRel; 1057 } 1058} 1059 1060multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1061 string asmbase, string asmstr, list<dag> pattern> { 1062 let BaseName = asmbase in { 1063 def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1064 !strconcat(asmbase, !strconcat(" ", asmstr)), 1065 pattern, NoItinerary>, RecFormRel; 1066 let Defs = [CR1] in 1067 def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1068 !strconcat(asmbase, !strconcat(". ", asmstr)), 1069 [], NoItinerary>, isRecordForm, RecFormRel; 1070 } 1071} 1072 1073multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1074 string asmbase, string asmstr, list<dag> pattern> { 1075 let BaseName = asmbase in { 1076 def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1077 !strconcat(asmbase, !strconcat(" ", asmstr)), 1078 pattern, NoItinerary>, RecFormRel; 1079 let Defs = [CR1] in 1080 def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1081 !strconcat(asmbase, !strconcat(". ", asmstr)), [], 1082 NoItinerary>, isRecordForm, RecFormRel; 1083 } 1084} 1085 1086multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1087 string asmbase, string asmstr, InstrItinClass itin, 1088 list<dag> pattern> { 1089 let BaseName = asmbase in { 1090 def NAME : AForm_1<opcode, xo, OOL, IOL, 1091 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1092 pattern>, RecFormRel; 1093 let Defs = [CR1] in 1094 def _rec : AForm_1<opcode, xo, OOL, IOL, 1095 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1096 []>, isRecordForm, RecFormRel; 1097 } 1098} 1099 1100multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1101 string asmbase, string asmstr, InstrItinClass itin, 1102 list<dag> pattern> { 1103 let BaseName = asmbase in { 1104 def NAME : AForm_2<opcode, xo, OOL, IOL, 1105 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1106 pattern>, RecFormRel; 1107 let Defs = [CR1] in 1108 def _rec : AForm_2<opcode, xo, OOL, IOL, 1109 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1110 []>, isRecordForm, RecFormRel; 1111 } 1112} 1113 1114multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1115 string asmbase, string asmstr, InstrItinClass itin, 1116 list<dag> pattern> { 1117 let BaseName = asmbase in { 1118 def NAME : AForm_3<opcode, xo, OOL, IOL, 1119 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1120 pattern>, RecFormRel; 1121 let Defs = [CR1] in 1122 def _rec : AForm_3<opcode, xo, OOL, IOL, 1123 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1124 []>, isRecordForm, RecFormRel; 1125 } 1126} 1127 1128multiclass 1129 Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1130 string asmbase, string asmstr, list<dag> pattern> { 1131 let BaseName = asmbase in { 1132 def NAME 1133 : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1134 !strconcat(asmbase, !strconcat(" ", asmstr)), 1135 pattern>, RecFormRel; 1136 let Defs = [CR0] in 1137 def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1138 !strconcat(asmbase, !strconcat(". ", asmstr)), 1139 []>, isRecordForm, RecFormRel; 1140 } 1141} 1142 1143multiclass 1144 Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1145 string asmbase, string asmstr, list<dag> pattern> { 1146 let BaseName = asmbase in { 1147 def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1148 !strconcat(asmbase, !strconcat(" ", asmstr)), 1149 pattern>, RecFormRel; 1150 let Defs = [CR1] in 1151 def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1152 !strconcat(asmbase, !strconcat(". ", asmstr)), 1153 []>, isRecordForm, RecFormRel; 1154 } 1155} 1156 1157multiclass 1158 Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1159 string asmbase, string asmstr, list<dag> pattern> { 1160 let BaseName = asmbase in { 1161 def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1162 !strconcat(asmbase, !strconcat(" ", asmstr)), 1163 pattern>, RecFormRel; 1164 let Defs = [CR1] in 1165 def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1166 !strconcat(asmbase, !strconcat(". ", asmstr)), 1167 []>, isRecordForm, RecFormRel; 1168 } 1169} 1170 1171multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1172 string asmbase, string asmstr, list<dag> pattern> { 1173 let BaseName = asmbase in { 1174 def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1175 !strconcat(asmbase, !strconcat(" ", asmstr)), 1176 pattern, NoItinerary>, RecFormRel; 1177 let Defs = [CR1] in 1178 def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1179 !strconcat(asmbase, !strconcat(". ", asmstr)), 1180 [], NoItinerary>, isRecordForm, RecFormRel; 1181 } 1182} 1183 1184//===----------------------------------------------------------------------===// 1185// END OF MULTICLASS DEFINITIONS 1186//===----------------------------------------------------------------------===// 1187 1188//===----------------------------------------------------------------------===// 1189// PowerPC Instruction Definitions. 1190 1191// Pseudo instructions: 1192 1193let hasCtrlDep = 1 in { 1194let Defs = [R1], Uses = [R1] in { 1195def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1196 "#ADJCALLSTACKDOWN $amt1 $amt2", 1197 [(callseq_start timm:$amt1, timm:$amt2)]>; 1198def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1199 "#ADJCALLSTACKUP $amt1 $amt2", 1200 [(callseq_end timm:$amt1, timm:$amt2)]>; 1201} 1202} // hasCtrlDep 1203 1204let Defs = [R1], Uses = [R1] in 1205def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1206 [(set i32:$result, 1207 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1208def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1209 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1210// Probed alloca to support stack clash protection. 1211let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1212def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1213 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1214 [(set i32:$result, 1215 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1216def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1217 gprc:$fp, gprc:$actual_negsize), 1218 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1219def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1220 gprc:$fp, gprc:$actual_negsize), 1221 (ins gprc:$negsize, memri:$fpsi), 1222 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1223 RegConstraint<"$actual_negsize = $negsize">; 1224def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1225 (ins i64imm:$stacksize), 1226 "#PROBED_STACKALLOC_32", []>; 1227} 1228 1229// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1230// instruction selection into a branch sequence. 1231let PPC970_Single = 1 in { 1232 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1233 // because either operand might become the first operand in an isel, and 1234 // that operand cannot be r0. 1235 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1236 gprc_nor0:$T, gprc_nor0:$F, 1237 i32imm:$BROPC), "#SELECT_CC_I4", 1238 []>; 1239 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1240 g8rc_nox0:$T, g8rc_nox0:$F, 1241 i32imm:$BROPC), "#SELECT_CC_I8", 1242 []>; 1243 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1244 i32imm:$BROPC), "#SELECT_CC_F4", 1245 []>; 1246 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1247 i32imm:$BROPC), "#SELECT_CC_F8", 1248 []>; 1249 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1250 i32imm:$BROPC), "#SELECT_CC_F16", 1251 []>; 1252 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1253 i32imm:$BROPC), "#SELECT_CC_VRRC", 1254 []>; 1255 1256 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1257 // register bit directly. 1258 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1259 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1260 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1261 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1262 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1263 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1264let Predicates = [HasFPU] in { 1265 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1266 f4rc:$T, f4rc:$F), "#SELECT_F4", 1267 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1268 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1269 f8rc:$T, f8rc:$F), "#SELECT_F8", 1270 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1271 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1272 vrrc:$T, vrrc:$F), "#SELECT_F16", 1273 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1274} 1275 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1276 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1277 [(set v4i32:$dst, 1278 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1279} 1280 1281// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1282// scavenge a register for it. 1283let mayStore = 1 in { 1284def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1285 "#SPILL_CR", []>; 1286def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1287 "#SPILL_CRBIT", []>; 1288} 1289 1290// RESTORE_CR - Indicate that we're restoring the CR register (previously 1291// spilled), so we'll need to scavenge a register for it. 1292let mayLoad = 1 in { 1293def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1294 "#RESTORE_CR", []>; 1295def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1296 "#RESTORE_CRBIT", []>; 1297} 1298 1299let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1300 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1301 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1302 [(PPCretglue)]>, Requires<[In32BitMode]>; 1303 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1304 let isPredicable = 1 in 1305 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1306 []>; 1307 1308 let isCodeGenOnly = 1 in { 1309 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1310 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1311 []>; 1312 1313 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 1314 "bcctr 12, $BI, 0", IIC_BrB, []>; 1315 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 1316 "bcctr 4, $BI, 0", IIC_BrB, []>; 1317 } 1318 } 1319} 1320 1321// Set the float rounding mode. 1322let Uses = [RM], Defs = [RM] in { 1323def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1324 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1325 1326def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1327 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1328 1329def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1330 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1331} 1332 1333let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in 1334def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>; 1335 1336let Defs = [LR] in 1337 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1338 PPC970_Unit_BRU; 1339let Defs = [LR] in 1340 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1341 PPC970_Unit_BRU; 1342 1343let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1344 hasSideEffects = 0 in { 1345 let isBarrier = 1 in { 1346 let isPredicable = 1 in 1347 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI), 1348 "b $LI", IIC_BrB, 1349 [(br bb:$LI)]>; 1350 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI), 1351 "ba $LI", IIC_BrB, []>; 1352 } 1353 1354 // BCC represents an arbitrary conditional branch on a predicate. 1355 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1356 // a two-value operand where a dag node expects two operands. :( 1357 let isCodeGenOnly = 1 in { 1358 class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1359 "b${cond:cc}${cond:pm} ${cond:reg}, $BD" 1360 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>; 1361 def BCC : BCC_class; 1362 1363 // The same as BCC, except that it's not a terminator. Used for introducing 1364 // control flow dependency without creating new blocks. 1365 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1366 1367 def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1368 "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">; 1369 1370 let isReturn = 1, Uses = [LR, RM] in 1371 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1372 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1373 } 1374 1375 let isCodeGenOnly = 1 in { 1376 let Pattern = [(brcond i1:$BI, bb:$BD)] in 1377 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1378 "bc 12, $BI, $BD">; 1379 1380 let Pattern = [(brcond (not i1:$BI), bb:$BD)] in 1381 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1382 "bc 4, $BI, $BD">; 1383 1384 let isReturn = 1, Uses = [LR, RM] in { 1385 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI), 1386 "bclr 12, $BI, 0", IIC_BrB, []>; 1387 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI), 1388 "bclr 4, $BI, 0", IIC_BrB, []>; 1389 } 1390 } 1391 1392 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1393 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1394 "bdzlr", IIC_BrB, []>; 1395 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1396 "bdnzlr", IIC_BrB, []>; 1397 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1398 "bdzlr+", IIC_BrB, []>; 1399 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1400 "bdnzlr+", IIC_BrB, []>; 1401 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1402 "bdzlr-", IIC_BrB, []>; 1403 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1404 "bdnzlr-", IIC_BrB, []>; 1405 } 1406 1407 let Defs = [CTR], Uses = [CTR] in { 1408 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 1409 "bdz $BD">; 1410 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 1411 "bdnz $BD">; 1412 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD), 1413 "bdza $BD">; 1414 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD), 1415 "bdnza $BD">; 1416 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD), 1417 "bdz+ $BD">; 1418 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD), 1419 "bdnz+ $BD">; 1420 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD), 1421 "bdza+ $BD">; 1422 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD), 1423 "bdnza+ $BD">; 1424 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD), 1425 "bdz- $BD">; 1426 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD), 1427 "bdnz- $BD">; 1428 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD), 1429 "bdza- $BD">; 1430 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD), 1431 "bdnza- $BD">; 1432 } 1433} 1434 1435// The unconditional BCL used by the SjLj setjmp code. 1436let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1437 hasSideEffects = 0 in { 1438 let Defs = [LR], Uses = [RM] in { 1439 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD), 1440 "bcl 20, 31, $BD">; 1441 } 1442} 1443 1444let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1445 // Convenient aliases for call instructions 1446 let Uses = [RM] in { 1447 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1448 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1449 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1450 "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>; 1451 1452 let isCodeGenOnly = 1 in { 1453 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI), 1454 "bl $LI", IIC_BrB, []>; 1455 def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1456 "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">; 1457 def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1458 "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">; 1459 1460 def BCL : BForm_4<16, 12, 0, 1, (outs), 1461 (ins crbitrc:$BI, condbrtarget:$BD), 1462 "bcl 12, $BI, $BD">; 1463 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1464 (ins crbitrc:$BI, condbrtarget:$BD), 1465 "bcl 4, $BI, $BD">; 1466 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1467 (outs), (ins calltarget:$LI), 1468 "bl $LI\n\tnop", IIC_BrB, []>; 1469 } 1470 } 1471 let Uses = [CTR, RM] in { 1472 let isPredicable = 1 in 1473 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1474 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1475 Requires<[In32BitMode]>; 1476 1477 let isCodeGenOnly = 1 in { 1478 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1479 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1480 []>; 1481 1482 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 1483 "bcctrl 12, $BI, 0", IIC_BrB, []>; 1484 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 1485 "bcctrl 4, $BI, 0", IIC_BrB, []>; 1486 } 1487 } 1488 let Uses = [LR, RM] in { 1489 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1490 "blrl", IIC_BrB, []>; 1491 1492 let isCodeGenOnly = 1 in { 1493 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1494 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1495 []>; 1496 1497 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI), 1498 "bclrl 12, $BI, 0", IIC_BrB, []>; 1499 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI), 1500 "bclrl 4, $BI, 0", IIC_BrB, []>; 1501 } 1502 } 1503 let Defs = [CTR], Uses = [CTR, RM] in { 1504 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD), 1505 "bdzl $BD">; 1506 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD), 1507 "bdnzl $BD">; 1508 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD), 1509 "bdzla $BD">; 1510 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD), 1511 "bdnzla $BD">; 1512 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD), 1513 "bdzl+ $BD">; 1514 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD), 1515 "bdnzl+ $BD">; 1516 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD), 1517 "bdzla+ $BD">; 1518 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD), 1519 "bdnzla+ $BD">; 1520 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD), 1521 "bdzl- $BD">; 1522 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD), 1523 "bdnzl- $BD">; 1524 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD), 1525 "bdzla- $BD">; 1526 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD), 1527 "bdnzla- $BD">; 1528 } 1529 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1530 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1531 "bdzlrl", IIC_BrB, []>; 1532 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1533 "bdnzlrl", IIC_BrB, []>; 1534 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1535 "bdzlrl+", IIC_BrB, []>; 1536 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1537 "bdnzlrl+", IIC_BrB, []>; 1538 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1539 "bdzlrl-", IIC_BrB, []>; 1540 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1541 "bdnzlrl-", IIC_BrB, []>; 1542 } 1543} 1544 1545let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1546 // Convenient aliases for call instructions 1547 let Uses = [RM] in { 1548 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1549 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1550 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1551 "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>; 1552 1553 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1554 (outs), (ins calltarget:$LI), 1555 "bl $LI\n\tnop", IIC_BrB, []>; 1556 } 1557 let Uses = [CTR, RM] in { 1558 let isPredicable = 1 in 1559 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1560 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1561 Requires<[In32BitMode]>; 1562 } 1563} 1564 1565let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1566def TCRETURNdi :PPCEmitTimePseudo< (outs), 1567 (ins calltarget:$dst, i32imm:$offset), 1568 "#TC_RETURNd $dst $offset", 1569 []>; 1570 1571 1572let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1573def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1574 "#TC_RETURNa $func $offset", 1575 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1576 1577let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1578def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1579 "#TC_RETURNr $dst $offset", 1580 []>; 1581 1582let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1583 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1584 def BCTRL_LWZinto_toc: 1585 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1586 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1587 [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; 1588 1589} 1590 1591let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1592 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1593 def BCTRL_LWZinto_toc_RM: 1594 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1595 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1596 [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; 1597 1598} 1599 1600let isCodeGenOnly = 1, hasSideEffects = 0 in { 1601 1602let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1603 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1604def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1605 []>, Requires<[In32BitMode]>; 1606 1607let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1608 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1609def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 1610 "b $LI", IIC_BrB, 1611 []>; 1612 1613let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1614 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1615def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 1616 "ba $LI", IIC_BrB, 1617 []>; 1618 1619} 1620 1621// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1622// is not. 1623let hasSideEffects = 1 in { 1624 let Defs = [CTR] in 1625 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1626 "#EH_SJLJ_SETJMP32", 1627 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1628 Requires<[In32BitMode]>; 1629} 1630 1631let hasSideEffects = 1, isBarrier = 1 in { 1632 let isTerminator = 1 in 1633 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1634 "#EH_SJLJ_LONGJMP32", 1635 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1636 Requires<[In32BitMode]>; 1637} 1638 1639// This pseudo is never removed from the function, as it serves as 1640// a terminator. Size is set to 0 to prevent the builtin assembler 1641// from emitting it. 1642let isBranch = 1, isTerminator = 1, Size = 0 in { 1643 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1644 "#EH_SjLj_Setup\t$dst", []>; 1645} 1646 1647// System call. 1648let PPC970_Unit = 7 in { 1649 def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV), 1650 "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>; 1651} 1652 1653// We mark SCV as having no scheduling model since it is only meant to be used 1654// as inline assembly. If we implement a builtin pattern for it we will need to 1655// add it to the P9 and P10 scheduling models. 1656let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in { 1657 def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV), 1658 "scv $LEV", IIC_BrB, []>; 1659} 1660 1661// Branch history rolling buffer. 1662def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1663 [(PPCclrbhrb)]>, 1664 PPC970_DGroup_Single; 1665// The $dmy argument used for MFBHRBE is not needed; however, including 1666// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1667// interferes with necessary special handling (see PPCFastISel.cpp). 1668def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), 1669 (ins u10imm:$imm, u10imm:$dmy), 1670 "mfbhrbe $RT, $imm", IIC_BrB, 1671 [(set i32:$RT, 1672 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1673 PPC970_DGroup_First; 1674 1675def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", 1676 IIC_BrB, [(PPCrfebb (i32 imm:$S))]>, 1677 PPC970_DGroup_Single; 1678 1679def : InstAlias<"rfebb", (RFEBB 1)>; 1680 1681// DCB* instructions. 1682def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr", 1683 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>, 1684 PPC970_DGroup_Single; 1685def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr", 1686 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>, 1687 PPC970_DGroup_Single; 1688def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr", 1689 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>, 1690 PPC970_DGroup_Single; 1691def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr", 1692 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>, 1693 PPC970_DGroup_Single; 1694def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr", 1695 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>, 1696 PPC970_DGroup_Single; 1697 1698def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr), 1699 "dcbf $addr, $TH", IIC_LdStDCBF, []>, 1700 PPC970_DGroup_Single; 1701 1702let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1703def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1704 "dcbt $addr, $TH", IIC_LdStDCBF, []>, 1705 PPC970_DGroup_Single; 1706def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1707 "dcbtst $addr, $TH", IIC_LdStDCBF, []>, 1708 PPC970_DGroup_Single; 1709} // hasSideEffects = 0 1710 1711def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1712 "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>; 1713def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1714 "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1715def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1716 "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1717def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1718 "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1719 1720def : Pat<(int_ppc_dcbt xoaddr:$dst), 1721 (DCBT 0, xoaddr:$dst)>; 1722def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1723 (DCBTST 0, xoaddr:$dst)>; 1724def : Pat<(int_ppc_dcbf xoaddr:$dst), 1725 (DCBF 0, xoaddr:$dst)>; 1726def : Pat<(int_ppc_icbt xoaddr:$dst), 1727 (ICBT 0, xoaddr:$dst)>; 1728 1729def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 1)), 1730 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1731def : Pat<(prefetch xoaddr:$dst, (i32 1), timm, (i32 1)), 1732 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1733def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 0)), 1734 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1735 1736def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1737 (DCBT i32:$TH, xoaddr:$dst)>; 1738def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1739 (DCBTST i32:$TH, xoaddr:$dst)>; 1740 1741// Atomic operations 1742// FIXME: some of these might be used with constant operands. This will result 1743// in constant materialization instructions that may be redundant. We currently 1744// clean this up in PPCMIPeephole with calls to 1745// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1746// in the first place. 1747let Defs = [CR0] in { 1748 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1749 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1750 [(set i32:$dst, (atomic_load_add_i8 ForceXForm:$ptr, i32:$incr))]>; 1751 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1752 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1753 [(set i32:$dst, (atomic_load_sub_i8 ForceXForm:$ptr, i32:$incr))]>; 1754 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1755 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1756 [(set i32:$dst, (atomic_load_and_i8 ForceXForm:$ptr, i32:$incr))]>; 1757 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1758 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1759 [(set i32:$dst, (atomic_load_or_i8 ForceXForm:$ptr, i32:$incr))]>; 1760 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1761 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1762 [(set i32:$dst, (atomic_load_xor_i8 ForceXForm:$ptr, i32:$incr))]>; 1763 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1764 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1765 [(set i32:$dst, (atomic_load_nand_i8 ForceXForm:$ptr, i32:$incr))]>; 1766 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1767 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1768 [(set i32:$dst, (atomic_load_min_i8 ForceXForm:$ptr, i32:$incr))]>; 1769 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1770 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1771 [(set i32:$dst, (atomic_load_max_i8 ForceXForm:$ptr, i32:$incr))]>; 1772 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1773 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1774 [(set i32:$dst, (atomic_load_umin_i8 ForceXForm:$ptr, i32:$incr))]>; 1775 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1776 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1777 [(set i32:$dst, (atomic_load_umax_i8 ForceXForm:$ptr, i32:$incr))]>; 1778 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1779 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1780 [(set i32:$dst, (atomic_load_add_i16 ForceXForm:$ptr, i32:$incr))]>; 1781 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1782 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1783 [(set i32:$dst, (atomic_load_sub_i16 ForceXForm:$ptr, i32:$incr))]>; 1784 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1785 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1786 [(set i32:$dst, (atomic_load_and_i16 ForceXForm:$ptr, i32:$incr))]>; 1787 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1788 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1789 [(set i32:$dst, (atomic_load_or_i16 ForceXForm:$ptr, i32:$incr))]>; 1790 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1791 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1792 [(set i32:$dst, (atomic_load_xor_i16 ForceXForm:$ptr, i32:$incr))]>; 1793 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1794 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1795 [(set i32:$dst, (atomic_load_nand_i16 ForceXForm:$ptr, i32:$incr))]>; 1796 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1797 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1798 [(set i32:$dst, (atomic_load_min_i16 ForceXForm:$ptr, i32:$incr))]>; 1799 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1800 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1801 [(set i32:$dst, (atomic_load_max_i16 ForceXForm:$ptr, i32:$incr))]>; 1802 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1803 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1804 [(set i32:$dst, (atomic_load_umin_i16 ForceXForm:$ptr, i32:$incr))]>; 1805 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1806 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1807 [(set i32:$dst, (atomic_load_umax_i16 ForceXForm:$ptr, i32:$incr))]>; 1808 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1809 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1810 [(set i32:$dst, (atomic_load_add_i32 ForceXForm:$ptr, i32:$incr))]>; 1811 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1812 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1813 [(set i32:$dst, (atomic_load_sub_i32 ForceXForm:$ptr, i32:$incr))]>; 1814 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1815 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1816 [(set i32:$dst, (atomic_load_and_i32 ForceXForm:$ptr, i32:$incr))]>; 1817 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1818 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1819 [(set i32:$dst, (atomic_load_or_i32 ForceXForm:$ptr, i32:$incr))]>; 1820 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1821 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1822 [(set i32:$dst, (atomic_load_xor_i32 ForceXForm:$ptr, i32:$incr))]>; 1823 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1824 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1825 [(set i32:$dst, (atomic_load_nand_i32 ForceXForm:$ptr, i32:$incr))]>; 1826 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1827 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1828 [(set i32:$dst, (atomic_load_min_i32 ForceXForm:$ptr, i32:$incr))]>; 1829 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1830 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1831 [(set i32:$dst, (atomic_load_max_i32 ForceXForm:$ptr, i32:$incr))]>; 1832 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1833 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1834 [(set i32:$dst, (atomic_load_umin_i32 ForceXForm:$ptr, i32:$incr))]>; 1835 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1836 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1837 [(set i32:$dst, (atomic_load_umax_i32 ForceXForm:$ptr, i32:$incr))]>; 1838 1839 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1840 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1841 [(set i32:$dst, (atomic_cmp_swap_i8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1842 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1843 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1844 [(set i32:$dst, (atomic_cmp_swap_i16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1845 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1846 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1847 [(set i32:$dst, (atomic_cmp_swap_i32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1848 1849 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1850 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1851 [(set i32:$dst, (atomic_swap_i8 ForceXForm:$ptr, i32:$new))]>; 1852 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1853 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1854 [(set i32:$dst, (atomic_swap_i16 ForceXForm:$ptr, i32:$new))]>; 1855 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1856 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1857 [(set i32:$dst, (atomic_swap_i32 ForceXForm:$ptr, i32:$new))]>; 1858} 1859 1860def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1861 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1862def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1863 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1864 1865// Instructions to support atomic operations 1866let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1867def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1868 "lbarx $RST, $addr", IIC_LdStLWARX, []>, 1869 Requires<[HasPartwordAtomics]>; 1870 1871def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1872 "lharx $RST, $addr", IIC_LdStLWARX, []>, 1873 Requires<[HasPartwordAtomics]>; 1874 1875def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1876 "lwarx $RST, $addr", IIC_LdStLWARX, []>; 1877 1878// Instructions to support lock versions of atomics 1879// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1880def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1881 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1882 Requires<[HasPartwordAtomics]>; 1883 1884def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1885 "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1886 Requires<[HasPartwordAtomics]>; 1887 1888def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1889 "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm; 1890 1891// The atomic instructions use the destination register as well as the next one 1892// or two registers in order (modulo 31). 1893let hasExtraSrcRegAllocReq = 1 in 1894def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB), 1895 "lwat $RST, $RA, $RB", IIC_LdStLoad>, 1896 Requires<[IsISA3_0]>; 1897} 1898 1899let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1900def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1901 "stbcx. $RST, $addr", IIC_LdStSTWCX, []>, 1902 isRecordForm, Requires<[HasPartwordAtomics]>; 1903 1904def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1905 "sthcx. $RST, $addr", IIC_LdStSTWCX, []>, 1906 isRecordForm, Requires<[HasPartwordAtomics]>; 1907 1908def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1909 "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm; 1910} 1911 1912let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1913def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), 1914 "stwat $RST, $RA, $RB", IIC_LdStStore>, 1915 Requires<[IsISA3_0]>; 1916 1917let isTrap = 1, hasCtrlDep = 1 in 1918def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1919 1920def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), 1921 "twi $RST, $RA, $D", IIC_IntTrapW, []>; 1922def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops), 1923 "tw $RST, $RA, $RB", IIC_IntTrapW, []>; 1924def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops), 1925 "tdi $RST, $RA, $D", IIC_IntTrapD, []>; 1926def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops), 1927 "td $RST, $RA, $RB", IIC_IntTrapD, []>; 1928 1929def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST), 1930 "popcntb $RA, $RST", IIC_IntGeneral, 1931 [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>; 1932 1933def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST), 1934 "cdtbcd $RA, $RST", IIC_IntGeneral, []>; 1935def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST), 1936 "cbcdtd $RA, $RST", IIC_IntGeneral, []>; 1937 1938def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 1939 "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>; 1940 1941//===----------------------------------------------------------------------===// 1942// PPC32 Load Instructions. 1943// 1944 1945// Unindexed (r+i) Loads. 1946let PPC970_Unit = 2 in { 1947def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1948 "lbz $RST, $addr", IIC_LdStLoad, 1949 [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1950 SExt32To64; 1951def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1952 "lha $RST, $addr", IIC_LdStLHA, 1953 [(set i32:$RST, (sextloadi16 DForm:$addr))]>, 1954 PPC970_DGroup_Cracked, SExt32To64; 1955def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1956 "lhz $RST, $addr", IIC_LdStLoad, 1957 [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1958 SExt32To64; 1959def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1960 "lwz $RST, $addr", IIC_LdStLoad, 1961 [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64; 1962 1963let Predicates = [HasFPU] in { 1964def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr), 1965 "lfs $RST, $addr", IIC_LdStLFD, 1966 [(set f32:$RST, (load DForm:$addr))]>; 1967def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), 1968 "lfd $RST, $addr", IIC_LdStLFD, 1969 [(set f64:$RST, (load DForm:$addr))]>; 1970} 1971 1972 1973// Unindexed (r+i) Loads with Update (preinc). 1974let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1975def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1976 "lbzu $RST, $addr", IIC_LdStLoadUpd, 1977 []>, RegConstraint<"$RA = $ea_result">; 1978 1979def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1980 "lhau $RST, $addr", IIC_LdStLHAU, 1981 []>, RegConstraint<"$addr.reg = $ea_result">, 1982 NoEncode<"$ea_result">; 1983 1984def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1985 "lhzu $RST, $addr", IIC_LdStLoadUpd, 1986 []>, RegConstraint<"$addr.reg = $ea_result">, 1987 NoEncode<"$ea_result">; 1988 1989def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1990 "lwzu $RST, $addr", IIC_LdStLoadUpd, 1991 []>, RegConstraint<"$addr.reg = $ea_result">, 1992 NoEncode<"$ea_result">; 1993 1994let Predicates = [HasFPU] in { 1995def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1996 "lfsu $RST, $addr", IIC_LdStLFDU, 1997 []>, RegConstraint<"$addr.reg = $ea_result">, 1998 NoEncode<"$ea_result">; 1999 2000def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2001 "lfdu $RST, $addr", IIC_LdStLFDU, 2002 []>, RegConstraint<"$addr.reg = $ea_result">, 2003 NoEncode<"$ea_result">; 2004} 2005 2006 2007// Indexed (r+r) Loads with Update (preinc). 2008def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2009 (ins (memrr $RA, $RB):$addr), 2010 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 2011 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2012 NoEncode<"$ea_result">; 2013 2014def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2015 (ins (memrr $RA, $RB):$addr), 2016 "lhaux $RST, $addr", IIC_LdStLHAUX, 2017 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2018 NoEncode<"$ea_result">; 2019 2020def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2021 (ins (memrr $RA, $RB):$addr), 2022 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 2023 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2024 NoEncode<"$ea_result">; 2025 2026def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2027 (ins (memrr $RA, $RB):$addr), 2028 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 2029 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2030 NoEncode<"$ea_result">; 2031 2032let Predicates = [HasFPU] in { 2033def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), 2034 (ins (memrr $RA, $RB):$addr), 2035 "lfsux $RST, $addr", IIC_LdStLFDUX, 2036 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2037 NoEncode<"$ea_result">; 2038 2039def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), 2040 (ins (memrr $RA, $RB):$addr), 2041 "lfdux $RST, $addr", IIC_LdStLFDUX, 2042 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2043 NoEncode<"$ea_result">; 2044} 2045} 2046} 2047 2048// Indexed (r+r) Loads. 2049// 2050let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2051def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2052 "lbzx $RST, $addr", IIC_LdStLoad, 2053 [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 2054 SExt32To64; 2055def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2056 "lhax $RST, $addr", IIC_LdStLHA, 2057 [(set i32:$RST, (sextloadi16 XForm:$addr))]>, 2058 PPC970_DGroup_Cracked, SExt32To64; 2059def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2060 "lhzx $RST, $addr", IIC_LdStLoad, 2061 [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, 2062 SExt32To64; 2063def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2064 "lwzx $RST, $addr", IIC_LdStLoad, 2065 [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64; 2066def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2067 "lhbrx $RST, $addr", IIC_LdStLoad, 2068 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64; 2069def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2070 "lwbrx $RST, $addr", IIC_LdStLoad, 2071 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64; 2072 2073let Predicates = [HasFPU] in { 2074def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr), 2075 "lfsx $RST, $addr", IIC_LdStLFD, 2076 [(set f32:$RST, (load XForm:$addr))]>; 2077def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2078 "lfdx $RST, $addr", IIC_LdStLFD, 2079 [(set f64:$RST, (load XForm:$addr))]>; 2080 2081def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2082 "lfiwax $RST, $addr", IIC_LdStLFD, 2083 [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>; 2084def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2085 "lfiwzx $RST, $addr", IIC_LdStLFD, 2086 [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>; 2087} 2088} 2089 2090// Load Multiple 2091let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2092def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src), 2093 "lmw $RST, $src", IIC_LdStLMW, []>; 2094 2095//===----------------------------------------------------------------------===// 2096// PPC32 Store Instructions. 2097// 2098 2099// Unindexed (r+i) Stores. 2100let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2101def STB : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2102 "stb $RST, $dst", IIC_LdStStore, 2103 [(truncstorei8 i32:$RST, DForm:$dst)]>; 2104def STH : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2105 "sth $RST, $dst", IIC_LdStStore, 2106 [(truncstorei16 i32:$RST, DForm:$dst)]>; 2107def STW : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2108 "stw $RST, $dst", IIC_LdStStore, 2109 [(store i32:$RST, DForm:$dst)]>; 2110let Predicates = [HasFPU] in { 2111def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst), 2112 "stfs $RST, $dst", IIC_LdStSTFD, 2113 [(store f32:$RST, DForm:$dst)]>; 2114def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), 2115 "stfd $RST, $dst", IIC_LdStSTFD, 2116 [(store f64:$RST, DForm:$dst)]>; 2117} 2118} 2119 2120// Unindexed (r+i) Stores with Update (preinc). 2121let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2122def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2123 "stbu $RST, $dst", IIC_LdStSTU, []>, 2124 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2125def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2126 "sthu $RST, $dst", IIC_LdStSTU, []>, 2127 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2128def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2129 "stwu $RST, $dst", IIC_LdStSTU, []>, 2130 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2131let Predicates = [HasFPU] in { 2132def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), 2133 "stfsu $RST, $dst", IIC_LdStSTFDU, []>, 2134 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2135def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), 2136 "stfdu $RST, $dst", IIC_LdStSTFDU, []>, 2137 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2138} 2139} 2140 2141// Patterns to match the pre-inc stores. We can't put the patterns on 2142// the instruction definitions directly as ISel wants the address base 2143// and offset to be separate operands, not a single complex operand. 2144def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2145 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2146def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2147 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2148def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2149 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2150def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2151 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2152def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2153 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2154 2155// Indexed (r+r) Stores. 2156let PPC970_Unit = 2 in { 2157def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2158 "stbx $RST, $addr", IIC_LdStStore, 2159 [(truncstorei8 i32:$RST, XForm:$addr)]>, 2160 PPC970_DGroup_Cracked; 2161def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2162 "sthx $RST, $addr", IIC_LdStStore, 2163 [(truncstorei16 i32:$RST, XForm:$addr)]>, 2164 PPC970_DGroup_Cracked; 2165def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2166 "stwx $RST, $addr", IIC_LdStStore, 2167 [(store i32:$RST, XForm:$addr)]>, 2168 PPC970_DGroup_Cracked; 2169 2170def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2171 "sthbrx $RST, $addr", IIC_LdStStore, 2172 [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>, 2173 PPC970_DGroup_Cracked; 2174def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2175 "stwbrx $RST, $addr", IIC_LdStStore, 2176 [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>, 2177 PPC970_DGroup_Cracked; 2178 2179let Predicates = [HasFPU] in { 2180def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2181 "stfiwx $RST, $addr", IIC_LdStSTFD, 2182 [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>; 2183 2184def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2185 "stfsx $RST, $addr", IIC_LdStSTFD, 2186 [(store f32:$RST, XForm:$addr)]>; 2187def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2188 "stfdx $RST, $addr", IIC_LdStSTFD, 2189 [(store f64:$RST, XForm:$addr)]>; 2190} 2191} 2192 2193// Indexed (r+r) Stores with Update (preinc). 2194let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2195def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2196 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2197 "stbux $RST, $addr", IIC_LdStSTUX, []>, 2198 RegConstraint<"$addr.ptrreg = $ea_res">, 2199 NoEncode<"$ea_res">, 2200 PPC970_DGroup_Cracked; 2201def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2202 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2203 "sthux $RST, $addr", IIC_LdStSTUX, []>, 2204 RegConstraint<"$addr.ptrreg = $ea_res">, 2205 NoEncode<"$ea_res">, 2206 PPC970_DGroup_Cracked; 2207def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2208 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2209 "stwux $RST, $addr", IIC_LdStSTUX, []>, 2210 RegConstraint<"$addr.ptrreg = $ea_res">, 2211 NoEncode<"$ea_res">, 2212 PPC970_DGroup_Cracked; 2213let Predicates = [HasFPU] in { 2214def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2215 (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2216 "stfsux $RST, $addr", IIC_LdStSTFDU, []>, 2217 RegConstraint<"$addr.ptrreg = $ea_res">, 2218 NoEncode<"$ea_res">, 2219 PPC970_DGroup_Cracked; 2220def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2221 (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2222 "stfdux $RST, $addr", IIC_LdStSTFDU, []>, 2223 RegConstraint<"$addr.ptrreg = $ea_res">, 2224 NoEncode<"$ea_res">, 2225 PPC970_DGroup_Cracked; 2226} 2227} 2228 2229// Patterns to match the pre-inc stores. We can't put the patterns on 2230// the instruction definitions directly as ISel wants the address base 2231// and offset to be separate operands, not a single complex operand. 2232def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2233 (STBUX $rS, $ptrreg, $ptroff)>; 2234def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2235 (STHUX $rS, $ptrreg, $ptroff)>; 2236def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2237 (STWUX $rS, $ptrreg, $ptroff)>; 2238let Predicates = [HasFPU] in { 2239def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2240 (STFSUX $rS, $ptrreg, $ptroff)>; 2241def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2242 (STFDUX $rS, $ptrreg, $ptroff)>; 2243} 2244 2245// Store Multiple 2246let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2247def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2248 "stmw $RST, $dst", IIC_LdStLMW, []>; 2249 2250def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2251 "sync $L", IIC_LdStSync, []>; 2252 2253let isCodeGenOnly = 1 in { 2254 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2255 "msync", IIC_LdStSync, []> { 2256 let L = 0; 2257 } 2258} 2259 2260// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2261def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2262 "eieio", IIC_LdStLoad, []>; 2263 2264def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2265 [(int_ppc_eieio)]>; 2266 2267def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2268def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2269def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2270def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2271def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2272def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2273def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2274def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2275def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2276def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2277 2278//===----------------------------------------------------------------------===// 2279// PPC32 Arithmetic Instructions. 2280// 2281 2282let PPC970_Unit = 1 in { // FXU Operations. 2283def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2284 "addi $RST, $RA, $D", IIC_IntSimple, 2285 [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>; 2286let BaseName = "addic" in { 2287let Defs = [CARRY] in 2288def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2289 "addic $RST, $RA, $D", IIC_IntGeneral, 2290 [(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>, 2291 RecFormRel, PPC970_DGroup_Cracked; 2292let Defs = [CARRY, CR0] in 2293def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2294 "addic. $RST, $RA, $D", IIC_IntGeneral, 2295 []>, isRecordForm, RecFormRel; 2296} 2297def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D), 2298 "addis $RST, $RA, $D", IIC_IntSimple, 2299 [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>; 2300let isCodeGenOnly = 1 in 2301def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2302 "la $RST, $D($RA)", IIC_IntGeneral, 2303 [(set i32:$RST, (add i32:$RA, 2304 (PPClo tglobaladdr:$D, 0)))]>; 2305def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2306 "mulli $RST, $RA, $D", IIC_IntMulLI, 2307 [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>; 2308let Defs = [CARRY] in 2309def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2310 "subfic $RST, $RA, $D", IIC_IntGeneral, 2311 [(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>; 2312 2313let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2314 def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D), 2315 "li $RST, $D", IIC_IntSimple, 2316 [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64; 2317 def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D), 2318 "lis $RST, $D", IIC_IntSimple, 2319 [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 2320} 2321} 2322 2323def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2324def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2325 2326let PPC970_Unit = 1 in { // FXU Operations. 2327let Defs = [CR0] in { 2328def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2329 "andi. $RA, $RST, $D", IIC_IntGeneral, 2330 [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>, 2331 isRecordForm, ZExt32To64, SExt32To64; 2332def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2333 "andis. $RA, $RST, $D", IIC_IntGeneral, 2334 [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>, 2335 isRecordForm, ZExt32To64; 2336} 2337def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2338 "ori $RA, $RST, $D", IIC_IntSimple, 2339 [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>; 2340def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2341 "oris $RA, $RST, $D", IIC_IntSimple, 2342 [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>; 2343def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2344 "xori $RA, $RST, $D", IIC_IntSimple, 2345 [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>; 2346def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2347 "xoris $RA, $RST, $D", IIC_IntSimple, 2348 [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>; 2349 2350def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2351 []>; 2352let isCodeGenOnly = 1 in { 2353// The POWER6 and POWER7 have special group-terminating nops. 2354def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2355 "ori 1, 1, 0", IIC_IntSimple, []>; 2356def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2357 "ori 2, 2, 0", IIC_IntSimple, []>; 2358} 2359 2360let isCompare = 1, hasSideEffects = 0 in { 2361 def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D), 2362 "cmpwi $BF, $RA, $D", IIC_IntCompare>; 2363 def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D), 2364 "cmplwi $BF, $RA, $D", IIC_IntCompare>; 2365 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2366 (ins u1imm:$L, gprc:$RA, gprc:$RB), 2367 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 2368 Requires<[IsISA3_0]>; 2369} 2370} 2371 2372let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2373let isCommutable = 1 in { 2374defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2375 "nand", "$RA, $RST, $RB", IIC_IntSimple, 2376 [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>; 2377defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2378 "and", "$RA, $RST, $RB", IIC_IntSimple, 2379 [(set i32:$RA, (and i32:$RST, i32:$RB))]>; 2380} // isCommutable 2381defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2382 "andc", "$RA, $RST, $RB", IIC_IntSimple, 2383 [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>; 2384let isCommutable = 1 in { 2385defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2386 "or", "$RA, $RST, $RB", IIC_IntSimple, 2387 [(set i32:$RA, (or i32:$RST, i32:$RB))]>; 2388defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2389 "nor", "$RA, $RST, $RB", IIC_IntSimple, 2390 [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>; 2391} // isCommutable 2392defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2393 "orc", "$RA, $RST, $RB", IIC_IntSimple, 2394 [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>; 2395let isCommutable = 1 in { 2396defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2397 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 2398 [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>; 2399defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2400 "xor", "$RA, $RST, $RB", IIC_IntSimple, 2401 [(set i32:$RA, (xor i32:$RST, i32:$RB))]>; 2402} // isCommutable 2403defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2404 "slw", "$RA, $RST, $RB", IIC_IntGeneral, 2405 [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64; 2406defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2407 "srw", "$RA, $RST, $RB", IIC_IntGeneral, 2408 [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64; 2409defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2410 "sraw", "$RA, $RST, $RB", IIC_IntShift, 2411 [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64; 2412} 2413 2414def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2415def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2416 2417def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2418def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2419 2420def : InstAlias<"nop", (ORI R0, R0, 0)>; 2421 2422let PPC970_Unit = 1 in { // FXU Operations. 2423let hasSideEffects = 0 in { 2424defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB), 2425 "srawi", "$RA, $RST, $RB", IIC_IntShift, 2426 [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>, 2427 SExt32To64; 2428defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST), 2429 "cntlzw", "$RA, $RST", IIC_IntGeneral, 2430 [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64; 2431defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST), 2432 "cnttzw", "$RA, $RST", IIC_IntGeneral, 2433 [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>, 2434 ZExt32To64; 2435defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST), 2436 "extsb", "$RA, $RST", IIC_IntSimple, 2437 [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64; 2438defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST), 2439 "extsh", "$RA, $RST", IIC_IntSimple, 2440 [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64; 2441 2442let isCommutable = 1 in 2443def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2444 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 2445 [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>; 2446} 2447let isCompare = 1, hasSideEffects = 0 in { 2448 def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2449 "cmpw $BF, $RA, $RB", IIC_IntCompare>; 2450 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2451 "cmplw $BF, $RA, $RB", IIC_IntCompare>; 2452} 2453} 2454let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2455let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2456 def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2457 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2458 def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2459 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2460 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2461 def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2462 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2463 def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2464 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2465 } 2466} 2467 2468def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2469 "ftdiv $BF, $RA, $RB", IIC_FPCompare>; 2470def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB), 2471 "ftsqrt $BF, $RB", IIC_FPCompare, 2472 [(set i32:$BF, (PPCftsqrt f64:$RB))]>; 2473 2474let mayRaiseFPException = 1, hasSideEffects = 0 in { 2475 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2476 defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB), 2477 "frin", "$RST, $RB", IIC_FPGeneral, 2478 [(set f64:$RST, (any_fround f64:$RB))]>; 2479 defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB), 2480 "frin", "$RST, $RB", IIC_FPGeneral, 2481 [(set f32:$RST, (any_fround f32:$RB))]>; 2482 2483 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2484 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB), 2485 "frip", "$RST, $RB", IIC_FPGeneral, 2486 [(set f64:$RST, (any_fceil f64:$RB))]>; 2487 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB), 2488 "frip", "$RST, $RB", IIC_FPGeneral, 2489 [(set f32:$RST, (any_fceil f32:$RB))]>; 2490 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2491 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB), 2492 "friz", "$RST, $RB", IIC_FPGeneral, 2493 [(set f64:$RST, (any_ftrunc f64:$RB))]>; 2494 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB), 2495 "friz", "$RST, $RB", IIC_FPGeneral, 2496 [(set f32:$RST, (any_ftrunc f32:$RB))]>; 2497 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2498 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB), 2499 "frim", "$RST, $RB", IIC_FPGeneral, 2500 [(set f64:$RST, (any_ffloor f64:$RB))]>; 2501 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB), 2502 "frim", "$RST, $RB", IIC_FPGeneral, 2503 [(set f32:$RST, (any_ffloor f32:$RB))]>; 2504} 2505 2506let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2507 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB), 2508 "fctiw", "$RST, $RB", IIC_FPGeneral, 2509 []>; 2510 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB), 2511 "fctiwu", "$RST, $RB", IIC_FPGeneral, 2512 []>; 2513 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB), 2514 "fctiwz", "$RST, $RB", IIC_FPGeneral, 2515 [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>; 2516 2517 defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB), 2518 "frsp", "$RST, $RB", IIC_FPGeneral, 2519 [(set f32:$RST, (any_fpround f64:$RB))]>; 2520 2521 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB), 2522 "fsqrt", "$RST, $RB", IIC_FPSqrtD, 2523 [(set f64:$RST, (any_fsqrt f64:$RB))]>; 2524 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB), 2525 "fsqrts", "$RST, $RB", IIC_FPSqrtS, 2526 [(set f32:$RST, (any_fsqrt f32:$RB))]>; 2527} 2528} 2529 2530def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2531 2532/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2533/// often coalesced away and we don't want the dispatch group builder to think 2534/// that they will fill slots (which could cause the load of a LSU reject to 2535/// sneak into a d-group with a store). 2536let hasSideEffects = 0, Predicates = [HasFPU] in 2537defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB), 2538 "fmr", "$RST, $RB", IIC_FPGeneral, 2539 []>, // (set f32:$RST, f32:$RB) 2540 PPC970_Unit_Pseudo; 2541 2542let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2543// These are artificially split into two different forms, for 4/8 byte FP. 2544defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB), 2545 "fabs", "$RST, $RB", IIC_FPGeneral, 2546 [(set f32:$RST, (fabs f32:$RB))]>; 2547let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2548defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB), 2549 "fabs", "$RST, $RB", IIC_FPGeneral, 2550 [(set f64:$RST, (fabs f64:$RB))]>; 2551defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB), 2552 "fnabs", "$RST, $RB", IIC_FPGeneral, 2553 [(set f32:$RST, (fneg (fabs f32:$RB)))]>; 2554let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2555defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB), 2556 "fnabs", "$RST, $RB", IIC_FPGeneral, 2557 [(set f64:$RST, (fneg (fabs f64:$RB)))]>; 2558defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB), 2559 "fneg", "$RST, $RB", IIC_FPGeneral, 2560 [(set f32:$RST, (fneg f32:$RB))]>; 2561let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2562defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB), 2563 "fneg", "$RST, $RB", IIC_FPGeneral, 2564 [(set f64:$RST, (fneg f64:$RB))]>; 2565 2566defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB), 2567 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2568 [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>; 2569let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2570defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), 2571 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2572 [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>; 2573 2574// Reciprocal estimates. 2575let mayRaiseFPException = 1 in { 2576defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB), 2577 "fre", "$RST, $RB", IIC_FPGeneral, 2578 [(set f64:$RST, (PPCfre f64:$RB))]>; 2579defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB), 2580 "fres", "$RST, $RB", IIC_FPGeneral, 2581 [(set f32:$RST, (PPCfre f32:$RB))]>; 2582defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB), 2583 "frsqrte", "$RST, $RB", IIC_FPGeneral, 2584 [(set f64:$RST, (PPCfrsqrte f64:$RB))]>; 2585defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB), 2586 "frsqrtes", "$RST, $RB", IIC_FPGeneral, 2587 [(set f32:$RST, (PPCfrsqrte f32:$RB))]>; 2588} 2589} 2590 2591// XL-Form instructions. condition register logical ops. 2592// 2593let hasSideEffects = 0 in 2594def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2595 "mcrf $BF, $BFA", IIC_BrMCR>, 2596 PPC970_DGroup_First, PPC970_Unit_CRU; 2597 2598// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2599// condition-register logical instructions have preferred forms. Specifically, 2600// it is preferred that the bit specified by the BT field be in the same 2601// condition register as that specified by the bit BB. We might want to account 2602// for this via hinting the register allocator and anti-dep breakers, or we 2603// could constrain the register class to force this constraint and then loosen 2604// it during register allocation via convertToThreeAddress or some similar 2605// mechanism. 2606 2607let isCommutable = 1 in { 2608def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2609 (ins crbitrc:$CRA, crbitrc:$CRB), 2610 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2611 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2612 2613def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2614 (ins crbitrc:$CRA, crbitrc:$CRB), 2615 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2616 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2617 2618def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2619 (ins crbitrc:$CRA, crbitrc:$CRB), 2620 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2621 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2622 2623def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2624 (ins crbitrc:$CRA, crbitrc:$CRB), 2625 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2626 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2627 2628def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2629 (ins crbitrc:$CRA, crbitrc:$CRB), 2630 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2631 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2632def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2633 (ins crbitrc:$CRA, crbitrc:$CRB), 2634 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2635 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2636} // isCommutable 2637 2638let isCodeGenOnly = 1 in 2639def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA), 2640 "crnot $CRD, $CRA", IIC_BrCR, 2641 [(set i1:$CRD, (not i1:$CRA))]>; 2642 2643def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2644 (ins crbitrc:$CRA, crbitrc:$CRB), 2645 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2646 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2647 2648def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2649 (ins crbitrc:$CRA, crbitrc:$CRB), 2650 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2651 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2652 2653let isCodeGenOnly = 1 in { 2654let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2655def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins), 2656 "creqv $CRD, $CRD, $CRD", IIC_BrCR, 2657 [(set i1:$CRD, 1)]>; 2658 2659def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins), 2660 "crxor $CRD, $CRD, $CRD", IIC_BrCR, 2661 [(set i1:$CRD, 0)]>; 2662} 2663 2664let Defs = [CR1EQ], CRD = 6 in { 2665def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2666 "creqv 6, 6, 6", IIC_BrCR, 2667 [(PPCcr6set)]>; 2668 2669def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2670 "crxor 6, 6, 6", IIC_BrCR, 2671 [(PPCcr6unset)]>; 2672} 2673} 2674 2675// XFX-Form instructions. Instructions that deal with SPRs. 2676// 2677 2678def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR), 2679 "mfspr $RST, $SPR", IIC_SprMFSPR>; 2680def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST), 2681 "mtspr $SPR, $RST", IIC_SprMTSPR>; 2682 2683def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR), 2684 "mftb $RST, $SPR", IIC_SprMFTB>; 2685 2686def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR), 2687 "mfpmr $RST, $SPR", IIC_SprMFPMR>; 2688 2689def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST), 2690 "mtpmr $SPR, $RST", IIC_SprMTPMR>; 2691 2692 2693// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2694// on a 32-bit target. 2695let hasSideEffects = 1 in 2696def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2697 "#ReadTB", []>; 2698 2699let Uses = [CTR] in { 2700def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins), 2701 "mfctr $RST", IIC_SprMFSPR>, 2702 PPC970_DGroup_First, PPC970_Unit_FXU; 2703} 2704let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in { 2705def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2706 "mtctr $RST", IIC_SprMTSPR>, 2707 PPC970_DGroup_First, PPC970_Unit_FXU; 2708} 2709let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { 2710let Pattern = [(int_set_loop_iterations i32:$RST)] in 2711def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2712 "mtctr $RST", IIC_SprMTSPR>, 2713 PPC970_DGroup_First, PPC970_Unit_FXU; 2714} 2715 2716let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in 2717def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), 2718 "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; 2719 2720let hasSideEffects = 0 in { 2721let Defs = [LR] in { 2722def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST), 2723 "mtlr $RST", IIC_SprMTSPR>, 2724 PPC970_DGroup_First, PPC970_Unit_FXU; 2725} 2726let Uses = [LR] in { 2727def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins), 2728 "mflr $RST", IIC_SprMFSPR>, 2729 PPC970_DGroup_First, PPC970_Unit_FXU; 2730} 2731} 2732 2733let hasSideEffects = 1 in { 2734 def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST), 2735 "mtspr 3, $RST", IIC_SprMTSPR>, 2736 PPC970_DGroup_Single, PPC970_Unit_FXU; 2737 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins), 2738 "mfspr $RST, 3", IIC_SprMFSPR>, 2739 PPC970_DGroup_First, PPC970_Unit_FXU; 2740} 2741 2742// Disable these alias on AIX since they are not supported. 2743let Predicates = [ModernAs] in { 2744// Aliases for moving to/from dscr to mtspr/mfspr 2745def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2746def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2747} 2748 2749let isCodeGenOnly = 1 in { 2750 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2751 // like a GPR on the PPC970. As such, copies in and out have the same 2752 // performance characteristics as an OR instruction. 2753 def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST), 2754 "mtspr 256, $RST", IIC_IntGeneral>, 2755 PPC970_DGroup_Single, PPC970_Unit_FXU; 2756 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins), 2757 "mfspr $RST, 256", IIC_IntGeneral>, 2758 PPC970_DGroup_First, PPC970_Unit_FXU; 2759 2760 def MTVRSAVEv : XFXForm_1_ext<31, 467, 256, 2761 (outs VRSAVERC:$SPR), (ins gprc:$RST), 2762 "mtspr 256, $RST", IIC_IntGeneral>, 2763 PPC970_DGroup_Single, PPC970_Unit_FXU; 2764 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), 2765 (ins VRSAVERC:$SPR), 2766 "mfspr $RST, 256", IIC_IntGeneral>, 2767 PPC970_DGroup_First, PPC970_Unit_FXU; 2768} 2769 2770// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2771def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2772def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2773 2774let hasSideEffects = 0 in { 2775// mtocrf's input needs to be prepared by shifting by an amount dependent 2776// on the cr register selected. Thus, post-ra anti-dep breaking must not 2777// later change that register assignment. 2778let hasExtraDefRegAllocReq = 1 in { 2779def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST), 2780 "mtocrf $FXM, $RST", IIC_BrMCRX>, 2781 PPC970_DGroup_First, PPC970_Unit_CRU; 2782 2783// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2784// is dependent on the cr fields being set. 2785def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST), 2786 "mtcrf $FXM, $RST", IIC_BrMCRX>, 2787 PPC970_MicroCode, PPC970_Unit_CRU; 2788} // hasExtraDefRegAllocReq = 1 2789 2790// mfocrf's input needs to be prepared by shifting by an amount dependent 2791// on the cr register selected. Thus, post-ra anti-dep breaking must not 2792// later change that register assignment. 2793let hasExtraSrcRegAllocReq = 1 in { 2794def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM), 2795 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 2796 PPC970_DGroup_First, PPC970_Unit_CRU; 2797 2798// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2799// is dependent on the cr fields being copied. 2800def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins), 2801 "mfcr $RT", IIC_SprMFCR>, 2802 PPC970_MicroCode, PPC970_Unit_CRU; 2803} // hasExtraSrcRegAllocReq = 1 2804 2805def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2806 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2807} // hasSideEffects = 0 2808 2809def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2810 2811let Predicates = [HasFPU] in { 2812// Custom inserter instruction to perform FADD in round-to-zero mode. 2813let Uses = [RM], mayRaiseFPException = 1 in { 2814 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2815 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2816} 2817 2818// The above pseudo gets expanded to make use of the following instructions 2819// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2820 2821// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2822// RM should be set. 2823let hasSideEffects = 1, Defs = [RM] in { 2824def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2825 "mtfsb0 $FM", IIC_IntMTFSB0, 2826 [(int_ppc_mtfsb0 timm:$FM)]>, 2827 PPC970_DGroup_Single, PPC970_Unit_FPU; 2828def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2829 "mtfsb1 $FM", IIC_IntMTFSB0, 2830 [(int_ppc_mtfsb1 timm:$FM)]>, 2831 PPC970_DGroup_Single, PPC970_Unit_FPU; 2832} 2833 2834let Defs = [RM], hasSideEffects = 1 in { 2835 let isCodeGenOnly = 1 in 2836 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT), 2837 "mtfsf $FM, $RT", IIC_IntMTFSB0, 2838 [(int_ppc_mtfsf timm:$FM, f64:$RT)]>, 2839 PPC970_DGroup_Single, PPC970_Unit_FPU; 2840} 2841let Uses = [RM], hasSideEffects = 1 in { 2842 def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2843 "mffs $RST", IIC_IntMFFS, 2844 [(set f64:$RST, (PPCmffs))]>, 2845 PPC970_DGroup_Single, PPC970_Unit_FPU; 2846 2847 let Defs = [CR1] in 2848 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2849 "mffs. $RST", IIC_IntMFFS, []>, isRecordForm; 2850 2851 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins), 2852 "mffsce $RST", IIC_IntMFFS, []>, 2853 PPC970_DGroup_Single, PPC970_Unit_FPU; 2854 2855 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST), 2856 (ins f8rc:$FRB), "mffscdrn $RST, $FRB", 2857 IIC_IntMFFS, []>, 2858 PPC970_DGroup_Single, PPC970_Unit_FPU; 2859 2860 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST), 2861 (ins u3imm:$DRM), 2862 "mffscdrni $RST, $DRM", 2863 IIC_IntMFFS, []>, 2864 PPC970_DGroup_Single, PPC970_Unit_FPU; 2865 2866 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST), 2867 (ins f8rc:$FRB), "mffscrn $RST, $FRB", 2868 IIC_IntMFFS, []>, 2869 PPC970_DGroup_Single, PPC970_Unit_FPU; 2870 2871 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST), 2872 (ins u2imm:$RM), "mffscrni $RST, $RM", 2873 IIC_IntMFFS, []>, 2874 PPC970_DGroup_Single, PPC970_Unit_FPU; 2875 2876 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins), 2877 "mffsl $RST", IIC_IntMFFS, []>, 2878 PPC970_DGroup_Single, PPC970_Unit_FPU; 2879} 2880} 2881 2882let Predicates = [IsISA3_0] in { 2883def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2884 "modsw $RST, $RA, $RB", IIC_IntDivW, 2885 [(set i32:$RST, (srem i32:$RA, i32:$RB))]>; 2886def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2887 "moduw $RST, $RA, $RB", IIC_IntDivW, 2888 [(set i32:$RST, (urem i32:$RA, i32:$RB))]>; 2889let hasSideEffects = 1 in 2890def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT), 2891 (ins gprc:$RA, gprc:$RB, u2imm:$CY), 2892 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>; 2893} 2894 2895let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2896// XO-Form instructions. Arithmetic instructions that can set overflow bit 2897let isCommutable = 1 in 2898defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2899 "add", "$RT, $RA, $RB", IIC_IntSimple, 2900 [(set i32:$RT, (add i32:$RA, i32:$RB))]>; 2901let isCodeGenOnly = 1 in 2902def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB), 2903 "add $RT, $RA, $RB", IIC_IntSimple, 2904 [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>; 2905let isCommutable = 1 in 2906defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2907 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 2908 [(set i32:$RT, (addc i32:$RA, i32:$RB))]>, 2909 PPC970_DGroup_Cracked; 2910 2911defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2912 "divw", "$RT, $RA, $RB", IIC_IntDivW, 2913 [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>; 2914defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2915 "divwu", "$RT, $RA, $RB", IIC_IntDivW, 2916 [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>; 2917defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2918 "divwe", "$RT, $RA, $RB", IIC_IntDivW, 2919 [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>, 2920 Requires<[HasExtDiv]>; 2921defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2922 "divweu", "$RT, $RA, $RB", IIC_IntDivW, 2923 [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>, 2924 Requires<[HasExtDiv]>; 2925let isCommutable = 1 in { 2926defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2927 "mulhw", "$RT, $RA, $RB", IIC_IntMulHW, 2928 [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>; 2929defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2930 "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU, 2931 [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>; 2932defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2933 "mullw", "$RT, $RA, $RB", IIC_IntMulHW, 2934 [(set i32:$RT, (mul i32:$RA, i32:$RB))]>; 2935} // isCommutable 2936defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2937 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 2938 [(set i32:$RT, (sub i32:$RB, i32:$RA))]>; 2939defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2940 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 2941 [(set i32:$RT, (subc i32:$RB, i32:$RA))]>, 2942 PPC970_DGroup_Cracked; 2943defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA), 2944 "neg", "$RT, $RA", IIC_IntSimple, 2945 [(set i32:$RT, (ineg i32:$RA))]>; 2946let Uses = [CARRY] in { 2947let isCommutable = 1 in 2948defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2949 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 2950 [(set i32:$RT, (adde i32:$RA, i32:$RB))]>; 2951defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA), 2952 "addme", "$RT, $RA", IIC_IntGeneral, 2953 [(set i32:$RT, (adde i32:$RA, -1))]>; 2954defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA), 2955 "addze", "$RT, $RA", IIC_IntGeneral, 2956 [(set i32:$RT, (adde i32:$RA, 0))]>; 2957defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2958 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 2959 [(set i32:$RT, (sube i32:$RB, i32:$RA))]>; 2960defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA), 2961 "subfme", "$RT, $RA", IIC_IntGeneral, 2962 [(set i32:$RT, (sube -1, i32:$RA))]>; 2963defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA), 2964 "subfze", "$RT, $RA", IIC_IntGeneral, 2965 [(set i32:$RT, (sube 0, i32:$RA))]>; 2966} 2967} 2968 2969def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2970def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2971def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 2972def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2973 2974// A-Form instructions. Most of the instructions executed in the FPU are of 2975// this type. 2976// 2977let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2978let mayRaiseFPException = 1, Uses = [RM] in { 2979let isCommutable = 1 in { 2980 defm FMADD : AForm_1r<63, 29, 2981 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2982 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2983 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2984 defm FMADDS : AForm_1r<59, 29, 2985 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2986 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2987 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2988 defm FMSUB : AForm_1r<63, 28, 2989 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2990 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2991 [(set f64:$FRT, 2992 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2993 defm FMSUBS : AForm_1r<59, 28, 2994 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2995 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2996 [(set f32:$FRT, 2997 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2998 defm FNMADD : AForm_1r<63, 31, 2999 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3000 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3001 [(set f64:$FRT, 3002 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3003 defm FNMADDS : AForm_1r<59, 31, 3004 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3005 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3006 [(set f32:$FRT, 3007 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3008 defm FNMSUB : AForm_1r<63, 30, 3009 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3010 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3011 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3012 (fneg f64:$FRB))))]>; 3013 defm FNMSUBS : AForm_1r<59, 30, 3014 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3015 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3016 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3017 (fneg f32:$FRB))))]>; 3018} // isCommutable 3019} 3020// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3021// having 4 of these, force the comparison to always be an 8-byte double (code 3022// should use an FMRSD if the input comparison value really wants to be a float) 3023// and 4/8 byte forms for the result and operand type.. 3024let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3025defm FSELD : AForm_1r<63, 23, 3026 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3027 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3028 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3029defm FSELS : AForm_1r<63, 23, 3030 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3031 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3032 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3033let Uses = [RM], mayRaiseFPException = 1 in { 3034 let isCommutable = 1 in { 3035 defm FADD : AForm_2r<63, 21, 3036 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3037 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3038 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3039 defm FADDS : AForm_2r<59, 21, 3040 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3041 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3042 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3043 } // isCommutable 3044 defm FDIV : AForm_2r<63, 18, 3045 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3046 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3047 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3048 defm FDIVS : AForm_2r<59, 18, 3049 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3050 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3051 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3052 let isCommutable = 1 in { 3053 defm FMUL : AForm_3r<63, 25, 3054 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3055 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3056 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3057 defm FMULS : AForm_3r<59, 25, 3058 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3059 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3060 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3061 } // isCommutable 3062 defm FSUB : AForm_2r<63, 20, 3063 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3064 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3065 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3066 defm FSUBS : AForm_2r<59, 20, 3067 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3068 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3069 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3070 } 3071} 3072 3073let hasSideEffects = 0 in { 3074let PPC970_Unit = 1 in { // FXU Operations. 3075 let isSelect = 1 in 3076 def ISEL : AForm_4<31, 15, 3077 (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND), 3078 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 3079 []>; 3080} 3081 3082let PPC970_Unit = 1 in { // FXU Operations. 3083// M-Form instructions. rotate and mask instructions. 3084// 3085let isCommutable = 1 in { 3086// RLWIMI can be commuted if the rotate amount is zero. 3087defm RLWIMI : MForm_2r<20, (outs gprc:$RA), 3088 (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB, 3089 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 3090 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3091 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 3092} 3093let BaseName = "rlwinm" in { 3094def RLWINM : MForm_2<21, 3095 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3096 "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3097 []>, RecFormRel; 3098let Defs = [CR0] in 3099def RLWINM_rec : MForm_2<21, 3100 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3101 "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3102 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3103} 3104defm RLWNM : MForm_1r<23, (outs gprc:$RA), 3105 (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME), 3106 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 3107 []>; 3108} 3109} // hasSideEffects = 0 3110 3111//===----------------------------------------------------------------------===// 3112// PowerPC Instruction Patterns 3113// 3114 3115// Arbitrary immediate support. Implement in terms of LIS/ORI. 3116def : Pat<(i32 imm:$imm), 3117 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3118 3119// Implement the 'not' operation with the NOR instruction. 3120def i32not : OutPatFrag<(ops node:$in), 3121 (NOR $in, $in)>; 3122def : Pat<(not i32:$in), 3123 (i32not $in)>; 3124 3125// ADD an arbitrary immediate. 3126def : Pat<(add i32:$in, imm:$imm), 3127 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3128// OR an arbitrary immediate. 3129def : Pat<(or i32:$in, imm:$imm), 3130 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3131// XOR an arbitrary immediate. 3132def : Pat<(xor i32:$in, imm:$imm), 3133 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3134// SUBFIC 3135def : Pat<(sub imm32SExt16:$imm, i32:$in), 3136 (SUBFIC $in, imm:$imm)>; 3137 3138// SHL/SRL 3139def : Pat<(shl i32:$in, (i32 imm:$imm)), 3140 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3141def : Pat<(srl i32:$in, (i32 imm:$imm)), 3142 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3143 3144// ROTL 3145def : Pat<(rotl i32:$in, i32:$sh), 3146 (RLWNM $in, $sh, 0, 31)>; 3147def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3148 (RLWINM $in, imm:$imm, 0, 31)>; 3149 3150// RLWNM 3151def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3152 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3153 3154// Calls 3155def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3156 (BL tglobaladdr:$dst)>; 3157 3158def : Pat<(PPCcall (i32 texternalsym:$dst)), 3159 (BL texternalsym:$dst)>; 3160 3161def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3162 (BL_RM tglobaladdr:$dst)>; 3163 3164def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3165 (BL_RM texternalsym:$dst)>; 3166 3167// Calls for AIX only 3168def : Pat<(PPCcall (i32 mcsym:$dst)), 3169 (BL mcsym:$dst)>; 3170 3171def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3172 (BL_NOP mcsym:$dst)>; 3173 3174def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3175 (BL_NOP texternalsym:$dst)>; 3176 3177def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3178 (BL_RM mcsym:$dst)>; 3179 3180def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3181 (BL_NOP_RM mcsym:$dst)>; 3182 3183def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3184 (BL_NOP_RM texternalsym:$dst)>; 3185 3186def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3187 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3188 3189def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3190 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3191 3192def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3193 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3194 3195def : Pat<(int_ppc_fence), (FENCE)>; 3196def : Pat<(int_ppc_readflm), (MFFS)>; 3197def : Pat<(int_ppc_mffsl), (MFFSL)>; 3198 3199// Hi and Lo for Darwin Global Addresses. 3200def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3201def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3202def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3203def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3204def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3205def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3206def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3207def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3208def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3209 (ADDIS $in, tglobaltlsaddr:$g)>; 3210def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3211 (ADDI $in, tglobaltlsaddr:$g)>; 3212def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3213 (ADDIS $in, tglobaladdr:$g)>; 3214def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3215 (ADDIS $in, tconstpool:$g)>; 3216def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3217 (ADDIS $in, tjumptable:$g)>; 3218def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3219 (ADDIS $in, tblockaddress:$g)>; 3220 3221// Support for thread-local storage. 3222def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3223 [(set i32:$rD, (PPCppc32GOT))]>; 3224 3225// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3226// This uses two output registers, the first as the real output, the second as a 3227// temporary register, used internally in code generation. 3228def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3229 []>, NoEncode<"$rT">; 3230 3231def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3232 "#LDgotTprelL32", 3233 [(set i32:$rD, 3234 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3235def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3236 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3237 3238def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3239 "#ADDItlsgdL32", 3240 [(set i32:$rD, 3241 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3242// LR is a true define, while the rest of the Defs are clobbers. R3 is 3243// explicitly defined when this op is created, so not mentioned here. 3244let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3245 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3246def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3247 "GETtlsADDR32", 3248 [(set i32:$rD, 3249 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3250// R3 is explicitly defined when this op is created, so not mentioned here. 3251// The rest of the Defs are the exact set of registers that will be clobbered by 3252// the call. 3253let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3254 Defs = [R0,R4,R5,R11,LR,CR0] in { 3255def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3256 "GETtlsADDR32AIX", 3257 [(set i32:$rD, 3258 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3259def GETtlsMOD32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), 3260 "GETtlsMOD32AIX", 3261 [(set i32:$rD, 3262 (PPCgetTlsMod i32:$handle))]>; 3263} 3264 3265// For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is 3266// generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both 3267// R3 and the LR (link register). 3268let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3269 Defs = [R3,LR] in 3270def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins), 3271 "GETtlsTpointer32AIX", 3272 [(set i32:$rD, (PPCgetTpointer))]>; 3273 3274// The following pattern matches local- and initial-exec TLS accesses on 32-bit AIX. 3275// PPCaddTls is used in local- and initial-exec accesses in order to: 3276// - Get the address of a variable (add the variable offset to the thread 3277// pointer, retrieved by calling .__get_tpointer). 3278// - Create an opportunity to optimize the user of the loaded address. 3279def : Pat<(PPCaddTls i32:$in, i32:$addr), 3280 (ADD4TLS $in, $addr)>; 3281 3282// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3283// are true defines while the rest of the Defs are clobbers. 3284let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3285 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3286def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3287 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3288 "#ADDItlsgdLADDR32", 3289 [(set i32:$rD, 3290 (PPCaddiTlsgdLAddr i32:$reg, 3291 tglobaltlsaddr:$disp, 3292 tglobaltlsaddr:$sym))]>; 3293def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3294 "#ADDItlsldL32", 3295 [(set i32:$rD, 3296 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3297// This pseudo is expanded to two copies to put the variable offset in R4 and 3298// the region handle in R3 and GETtlsADDR32AIX. 3299def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3300 "#TLSGDAIX", 3301 [(set i32:$rD, 3302 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3303// This pseudo is expanded to the call to GETtlsMOD32AIX. 3304def TLSLDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), 3305 "#TLSLDAIX", [(set i32:$rD, (PPCTlsldAIX i32:$handle))]>; 3306// LR is a true define, while the rest of the Defs are clobbers. R3 is 3307// explicitly defined when this op is created, so not mentioned here. 3308let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3309 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3310def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3311 "GETtlsldADDR32", 3312 [(set i32:$rD, 3313 (PPCgetTlsldAddr i32:$reg, 3314 tglobaltlsaddr:$sym))]>; 3315// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3316// are true defines while the rest of the Defs are clobbers. 3317let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3318 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3319def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3320 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3321 "#ADDItlsldLADDR32", 3322 [(set i32:$rD, 3323 (PPCaddiTlsldLAddr i32:$reg, 3324 tglobaltlsaddr:$disp, 3325 tglobaltlsaddr:$sym))]>; 3326def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3327 "#ADDIdtprelL32", 3328 [(set i32:$rD, 3329 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3330def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3331 "#ADDISdtprelHA32", 3332 [(set i32:$rD, 3333 (PPCaddisDtprelHA i32:$reg, 3334 tglobaltlsaddr:$disp))]>; 3335 3336// Support for Position-independent code 3337def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3338 "#LWZtoc", 3339 [(set i32:$rD, 3340 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3341def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3342 "#LWZtocL", 3343 [(set i32:$rD, 3344 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3345def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3346 "#ADDIStocHA", []>; 3347// TOC Data Transform on AIX 3348def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tocentry32:$disp), 3349 "#ADDItoc", []>; 3350def ADDItocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3351 "#ADDItocL", []>; 3352 3353// Get Global (GOT) Base Register offset, from the word immediately preceding 3354// the function label. 3355def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3356 3357// Pseudo-instruction marked for deletion. When deleting the instruction would 3358// cause iterator invalidation in MIR transformation passes, this pseudo can be 3359// used instead. It will be removed unconditionally at pre-emit time (prior to 3360// branch selection). 3361def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3362 3363// Standard shifts. These are represented separately from the real shifts above 3364// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3365// amounts. 3366def : Pat<(sra i32:$rS, i32:$rB), 3367 (SRAW $rS, $rB)>; 3368def : Pat<(srl i32:$rS, i32:$rB), 3369 (SRW $rS, $rB)>; 3370def : Pat<(shl i32:$rS, i32:$rB), 3371 (SLW $rS, $rB)>; 3372 3373def : Pat<(i32 (zextloadi1 DForm:$src)), 3374 (LBZ DForm:$src)>; 3375def : Pat<(i32 (zextloadi1 XForm:$src)), 3376 (LBZX XForm:$src)>; 3377def : Pat<(i32 (extloadi1 DForm:$src)), 3378 (LBZ DForm:$src)>; 3379def : Pat<(i32 (extloadi1 XForm:$src)), 3380 (LBZX XForm:$src)>; 3381def : Pat<(i32 (extloadi8 DForm:$src)), 3382 (LBZ DForm:$src)>; 3383def : Pat<(i32 (extloadi8 XForm:$src)), 3384 (LBZX XForm:$src)>; 3385def : Pat<(i32 (extloadi16 DForm:$src)), 3386 (LHZ DForm:$src)>; 3387def : Pat<(i32 (extloadi16 XForm:$src)), 3388 (LHZX XForm:$src)>; 3389let Predicates = [HasFPU] in { 3390def : Pat<(f64 (extloadf32 DForm:$src)), 3391 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3392def : Pat<(f64 (extloadf32 XForm:$src)), 3393 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3394 3395def : Pat<(f64 (any_fpextend f32:$src)), 3396 (COPY_TO_REGCLASS $src, F8RC)>; 3397} 3398 3399// Only seq_cst fences require the heavyweight sync (SYNC 0). 3400// All others can use the lightweight sync (SYNC 1). 3401// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3402// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3403// versions of Power. 3404def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3405def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3406def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3407def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3408 3409let Predicates = [HasFPU] in { 3410// Additional fnmsub patterns for custom node 3411def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3412 (FNMSUB $A, $B, $C)>; 3413def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3414 (FNMSUBS $A, $B, $C)>; 3415def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3416 (FMSUB $A, $B, $C)>; 3417def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3418 (FMSUBS $A, $B, $C)>; 3419def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3420 (FNMADD $A, $B, $C)>; 3421def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3422 (FNMADDS $A, $B, $C)>; 3423 3424// FCOPYSIGN's operand types need not agree. 3425def : Pat<(fcopysign f64:$frB, f32:$frA), 3426 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3427def : Pat<(fcopysign f32:$frB, f64:$frA), 3428 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3429} 3430 3431// XL Compat intrinsics. 3432def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3433def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3434def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3435def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3436def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3437def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3438def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3439def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3440 3441include "PPCInstrAltivec.td" 3442include "PPCInstrSPE.td" 3443include "PPCInstr64Bit.td" 3444include "PPCInstrVSX.td" 3445include "PPCInstrHTM.td" 3446 3447def crnot : OutPatFrag<(ops node:$in), 3448 (CRNOT $in)>; 3449def : Pat<(not i1:$in), 3450 (crnot $in)>; 3451 3452// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3453// These are aliases that require C++ handling to convert to the target 3454// instruction, while InstAliases can be handled directly by tblgen. 3455class PPCAsmPseudo<string asm, dag iops> 3456 : Instruction { 3457 let Namespace = "PPC"; 3458 bit PPC64 = 0; // Default value, override with isPPC64 3459 3460 let OutOperandList = (outs); 3461 let InOperandList = iops; 3462 let Pattern = []; 3463 let AsmString = asm; 3464 let isAsmParserOnly = 1; 3465 let isPseudo = 1; 3466 let hasNoSchedulingInfo = 1; 3467} 3468 3469// Prefixed instructions may require access to the above defs at a later 3470// time so we include this after the def. 3471include "PPCInstrP10.td" 3472include "PPCInstrFutureMMA.td" 3473include "PPCInstrFuture.td" 3474include "PPCInstrMMA.td" 3475include "PPCInstrDFP.td" 3476 3477// Patterns for arithmetic i1 operations. 3478def : Pat<(add i1:$a, i1:$b), 3479 (CRXOR $a, $b)>; 3480def : Pat<(sub i1:$a, i1:$b), 3481 (CRXOR $a, $b)>; 3482def : Pat<(mul i1:$a, i1:$b), 3483 (CRAND $a, $b)>; 3484 3485// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3486// (-1 is used to mean all bits set). 3487def : Pat<(i1 -1), (CRSET)>; 3488 3489// i1 extensions, implemented in terms of isel. 3490def : Pat<(i32 (zext i1:$in)), 3491 (SELECT_I4 $in, (LI 1), (LI 0))>; 3492def : Pat<(i32 (sext i1:$in)), 3493 (SELECT_I4 $in, (LI -1), (LI 0))>; 3494 3495def : Pat<(i64 (zext i1:$in)), 3496 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3497def : Pat<(i64 (sext i1:$in)), 3498 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3499 3500// FIXME: We should choose either a zext or a sext based on other constants 3501// already around. 3502def : Pat<(i32 (anyext i1:$in)), 3503 (SELECT_I4 $in, (LI 1), (LI 0))>; 3504def : Pat<(i64 (anyext i1:$in)), 3505 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3506 3507// match setcc on i1 variables. 3508// CRANDC is: 3509// 1 1 : F 3510// 1 0 : T 3511// 0 1 : F 3512// 0 0 : F 3513// 3514// LT is: 3515// -1 -1 : F 3516// -1 0 : T 3517// 0 -1 : F 3518// 0 0 : F 3519// 3520// ULT is: 3521// 1 1 : F 3522// 1 0 : F 3523// 0 1 : T 3524// 0 0 : F 3525def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3526 (CRANDC $s1, $s2)>; 3527def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3528 (CRANDC $s2, $s1)>; 3529// CRORC is: 3530// 1 1 : T 3531// 1 0 : T 3532// 0 1 : F 3533// 0 0 : T 3534// 3535// LE is: 3536// -1 -1 : T 3537// -1 0 : T 3538// 0 -1 : F 3539// 0 0 : T 3540// 3541// ULE is: 3542// 1 1 : T 3543// 1 0 : F 3544// 0 1 : T 3545// 0 0 : T 3546def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3547 (CRORC $s1, $s2)>; 3548def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3549 (CRORC $s2, $s1)>; 3550 3551def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3552 (CREQV $s1, $s2)>; 3553 3554// GE is: 3555// -1 -1 : T 3556// -1 0 : F 3557// 0 -1 : T 3558// 0 0 : T 3559// 3560// UGE is: 3561// 1 1 : T 3562// 1 0 : T 3563// 0 1 : F 3564// 0 0 : T 3565def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3566 (CRORC $s2, $s1)>; 3567def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3568 (CRORC $s1, $s2)>; 3569 3570// GT is: 3571// -1 -1 : F 3572// -1 0 : F 3573// 0 -1 : T 3574// 0 0 : F 3575// 3576// UGT is: 3577// 1 1 : F 3578// 1 0 : T 3579// 0 1 : F 3580// 0 0 : F 3581def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3582 (CRANDC $s2, $s1)>; 3583def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3584 (CRANDC $s1, $s2)>; 3585 3586def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3587 (CRXOR $s1, $s2)>; 3588 3589// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3590// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3591// floating-point types. 3592 3593multiclass CRNotPat<dag pattern, dag result> { 3594 def : Pat<pattern, (crnot result)>; 3595 def : Pat<(not pattern), result>; 3596 3597 // We can also fold the crnot into an extension: 3598 def : Pat<(i32 (zext pattern)), 3599 (SELECT_I4 result, (LI 0), (LI 1))>; 3600 def : Pat<(i32 (sext pattern)), 3601 (SELECT_I4 result, (LI 0), (LI -1))>; 3602 3603 // We can also fold the crnot into an extension: 3604 def : Pat<(i64 (zext pattern)), 3605 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3606 def : Pat<(i64 (sext pattern)), 3607 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3608 3609 // FIXME: We should choose either a zext or a sext based on other constants 3610 // already around. 3611 def : Pat<(i32 (anyext pattern)), 3612 (SELECT_I4 result, (LI 0), (LI 1))>; 3613 3614 def : Pat<(i64 (anyext pattern)), 3615 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3616} 3617 3618// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3619// we need to write imm:$imm in the output patterns below, not just $imm, or 3620// else the resulting matcher will not correctly add the immediate operand 3621// (making it a register operand instead). 3622 3623// extended SETCC. 3624multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3625 OutPatFrag rfrag, OutPatFrag rfrag8> { 3626 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3627 (rfrag $s1)>; 3628 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3629 (rfrag8 $s1)>; 3630 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3631 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3632 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3633 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3634 3635 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3636 (rfrag $s1)>; 3637 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3638 (rfrag8 $s1)>; 3639 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3640 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3641 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3642 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3643} 3644 3645// Note that we do all inversions below with i(32|64)not, instead of using 3646// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3647// has 2-cycle latency. 3648 3649defm : ExtSetCCPat<SETEQ, 3650 PatFrag<(ops node:$in, node:$cc), 3651 (setcc $in, 0, $cc)>, 3652 OutPatFrag<(ops node:$in), 3653 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3654 OutPatFrag<(ops node:$in), 3655 (RLDICL (CNTLZD $in), 58, 63)> >; 3656 3657defm : ExtSetCCPat<SETNE, 3658 PatFrag<(ops node:$in, node:$cc), 3659 (setcc $in, 0, $cc)>, 3660 OutPatFrag<(ops node:$in), 3661 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3662 OutPatFrag<(ops node:$in), 3663 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3664 3665defm : ExtSetCCPat<SETLT, 3666 PatFrag<(ops node:$in, node:$cc), 3667 (setcc $in, 0, $cc)>, 3668 OutPatFrag<(ops node:$in), 3669 (RLWINM $in, 1, 31, 31)>, 3670 OutPatFrag<(ops node:$in), 3671 (RLDICL $in, 1, 63)> >; 3672 3673defm : ExtSetCCPat<SETGE, 3674 PatFrag<(ops node:$in, node:$cc), 3675 (setcc $in, 0, $cc)>, 3676 OutPatFrag<(ops node:$in), 3677 (RLWINM (i32not $in), 1, 31, 31)>, 3678 OutPatFrag<(ops node:$in), 3679 (RLDICL (i64not $in), 1, 63)> >; 3680 3681defm : ExtSetCCPat<SETGT, 3682 PatFrag<(ops node:$in, node:$cc), 3683 (setcc $in, 0, $cc)>, 3684 OutPatFrag<(ops node:$in), 3685 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3686 OutPatFrag<(ops node:$in), 3687 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3688 3689defm : ExtSetCCPat<SETLE, 3690 PatFrag<(ops node:$in, node:$cc), 3691 (setcc $in, 0, $cc)>, 3692 OutPatFrag<(ops node:$in), 3693 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3694 OutPatFrag<(ops node:$in), 3695 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3696 3697defm : ExtSetCCPat<SETLT, 3698 PatFrag<(ops node:$in, node:$cc), 3699 (setcc $in, -1, $cc)>, 3700 OutPatFrag<(ops node:$in), 3701 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3702 OutPatFrag<(ops node:$in), 3703 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3704 3705defm : ExtSetCCPat<SETGE, 3706 PatFrag<(ops node:$in, node:$cc), 3707 (setcc $in, -1, $cc)>, 3708 OutPatFrag<(ops node:$in), 3709 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3710 OutPatFrag<(ops node:$in), 3711 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3712 3713defm : ExtSetCCPat<SETGT, 3714 PatFrag<(ops node:$in, node:$cc), 3715 (setcc $in, -1, $cc)>, 3716 OutPatFrag<(ops node:$in), 3717 (RLWINM (i32not $in), 1, 31, 31)>, 3718 OutPatFrag<(ops node:$in), 3719 (RLDICL (i64not $in), 1, 63)> >; 3720 3721defm : ExtSetCCPat<SETLE, 3722 PatFrag<(ops node:$in, node:$cc), 3723 (setcc $in, -1, $cc)>, 3724 OutPatFrag<(ops node:$in), 3725 (RLWINM $in, 1, 31, 31)>, 3726 OutPatFrag<(ops node:$in), 3727 (RLDICL $in, 1, 63)> >; 3728 3729// An extended SETCC with shift amount. 3730multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3731 OutPatFrag rfrag, OutPatFrag rfrag8> { 3732 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3733 (rfrag $s1, $sa)>; 3734 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3735 (rfrag8 $s1, $sa)>; 3736 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3737 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3738 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3739 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3740 3741 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3742 (rfrag $s1, $sa)>; 3743 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3744 (rfrag8 $s1, $sa)>; 3745 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3746 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3747 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3748 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3749} 3750 3751defm : ExtSetCCShiftPat<SETNE, 3752 PatFrag<(ops node:$in, node:$sa, node:$cc), 3753 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3754 OutPatFrag<(ops node:$in, node:$sa), 3755 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3756 OutPatFrag<(ops node:$in, node:$sa), 3757 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3758 3759defm : ExtSetCCShiftPat<SETEQ, 3760 PatFrag<(ops node:$in, node:$sa, node:$cc), 3761 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3762 OutPatFrag<(ops node:$in, node:$sa), 3763 (RLWNM (i32not $in), 3764 (SUBFIC $sa, 32), 31, 31)>, 3765 OutPatFrag<(ops node:$in, node:$sa), 3766 (RLDCL (i64not $in), 3767 (SUBFIC $sa, 64), 63)> >; 3768 3769// SETCC for i32. 3770def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3771 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3772def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3773 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3774def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3775 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3776def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3777 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3778def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3779 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3780def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3781 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3782 3783// For non-equality comparisons, the default code would materialize the 3784// constant, then compare against it, like this: 3785// lis r2, 4660 3786// ori r2, r2, 22136 3787// cmpw cr0, r3, r2 3788// beq cr0,L6 3789// Since we are just comparing for equality, we can emit this instead: 3790// xoris r0,r3,0x1234 3791// cmplwi cr0,r0,0x5678 3792// beq cr0,L6 3793 3794def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3795 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3796 (LO16 imm:$imm)), sub_eq)>; 3797 3798def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3799 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3800def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3801 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3802def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3803 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3804def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3805 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3806def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3807 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3808 3809// SETCC for i64. 3810def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3811 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3812def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3813 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3814def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3815 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3816def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3817 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3818def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3819 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3820def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3821 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3822 3823// For non-equality comparisons, the default code would materialize the 3824// constant, then compare against it, like this: 3825// lis r2, 4660 3826// ori r2, r2, 22136 3827// cmpd cr0, r3, r2 3828// beq cr0,L6 3829// Since we are just comparing for equality, we can emit this instead: 3830// xoris r0,r3,0x1234 3831// cmpldi cr0,r0,0x5678 3832// beq cr0,L6 3833 3834def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3835 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3836 (LO16 imm:$imm)), sub_eq)>; 3837 3838def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3839 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3840def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3841 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3842def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3843 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3844def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3845 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3846def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3847 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3848 3849let Predicates = [IsNotISA3_1] in { 3850// Instantiations of CRNotPat for i32. 3851defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3852 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3853defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3854 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3855defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3856 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3857defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3858 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3859defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3860 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3861defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3862 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3863 3864defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3865 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3866 (LO16 imm:$imm)), sub_eq)>; 3867 3868defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3869 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3870defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3871 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3872defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3873 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3874defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3875 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3876defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3877 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3878 3879// Instantiations of CRNotPat for i64. 3880defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3881 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3882defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3883 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3884defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3885 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3886defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3887 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3888defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3889 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3890defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3891 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3892 3893defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3894 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3895 (LO16 imm:$imm)), sub_eq)>; 3896 3897defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3898 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3899defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3900 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3901defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3902 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3903defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3904 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3905defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3906 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3907} 3908 3909multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3910 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3911 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3912 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3913 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3914 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3915 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3916 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3917 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3918 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3919 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3920 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3921 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3922 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3923 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3924 3925 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3926 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3927 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3928 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3929 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3930 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3931 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3932 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3933 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3934 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3935 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3936 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3937 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3938 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3939} 3940 3941let Predicates = [HasFPU] in { 3942// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3943// SETCC for f32. 3944defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3945 3946// SETCC for f64. 3947defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3948 3949// SETCC for f128. 3950defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3951 3952// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3953// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3954// then VXVC is set. 3955// SETCCS for f32. 3956defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3957 3958// SETCCS for f64. 3959defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 3960 3961// SETCCS for f128. 3962defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 3963} 3964 3965// This must be in this file because it relies on patterns defined in this file 3966// after the inclusion of the instruction sets. 3967let Predicates = [HasSPE] in { 3968// SETCC for f32. 3969def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 3970 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3971def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 3972 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3973def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 3974 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3975def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 3976 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3977def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 3978 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3979def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 3980 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3981 3982defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 3983 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3984defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 3985 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3986defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 3987 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3988defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 3989 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3990defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 3991 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3992defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 3993 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3994 3995// SETCC for f64. 3996def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 3997 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3998def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 3999 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4000def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 4001 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4002def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 4003 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4004def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 4005 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4006def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 4007 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4008 4009defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 4010 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4011defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4012 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4013defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4014 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4015defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4016 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4017defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4018 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4019defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4020 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4021} 4022// match select on i1 variables: 4023def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4024 (CROR (CRAND $cond , $tval), 4025 (CRAND (crnot $cond), $fval))>; 4026 4027// match selectcc on i1 variables: 4028// select (lhs == rhs), tval, fval is: 4029// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4030def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4031 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4032 (CRAND (CRORC $rhs, $lhs), $fval))>; 4033def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4034 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4035 (CRAND (CRORC $lhs, $rhs), $fval))>; 4036def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4037 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4038 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4039def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4040 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4041 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4042def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4043 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4044 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4045def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4046 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4047 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4048def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4049 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4050 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4051def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4052 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4053 (CRAND (CRORC $lhs, $rhs), $fval))>; 4054def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4055 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4056 (CRAND (CRORC $rhs, $lhs), $fval))>; 4057def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4058 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4059 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4060 4061// match selectcc on i1 variables with non-i1 output. 4062def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4063 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4064def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4065 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4066def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4067 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4068def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4069 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4070def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4071 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4072def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4073 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4074def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4075 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4076def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4077 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4078def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4079 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4080def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4081 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4082 4083def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4084 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4085def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4086 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4087def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4088 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4089def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4090 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4091def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4092 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4093def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4094 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4095def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4096 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4097def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4098 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4099def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4100 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4101def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4102 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4103 4104let Predicates = [HasFPU] in { 4105def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4106 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4107def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4108 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4109def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4110 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4111def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4112 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4113def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4114 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4115def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4116 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4117def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4118 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4119def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4120 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4121def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4122 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4123def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4124 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4125 4126def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4127 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4128def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4129 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4130def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4131 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4132def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4133 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4134def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4135 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4136def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4137 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4138def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4139 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4140def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4141 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4142def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4143 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4144def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4145 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4146} 4147 4148def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4149 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4150def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4151 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4152def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4153 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4154def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4155 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4156def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4157 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4158def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4159 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4160def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4161 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4162def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4163 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4164def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4165 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4166def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4167 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4168 4169def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4170 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4171def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4172 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4173def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4174 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4175def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4176 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4177def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4178 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4179def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4180 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4181def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4182 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4183def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4184 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4185def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4186 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4187def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4188 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4189 4190let Defs = [CR0] in { 4191def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4192 "#ANDI_rec_1_EQ_BIT", 4193 [(set i1:$dst, (trunc (not i32:$in)))]>; 4194def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4195 "#ANDI_rec_1_GT_BIT", 4196 [(set i1:$dst, (trunc i32:$in))]>; 4197 4198def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4199 "#ANDI_rec_1_EQ_BIT8", 4200 [(set i1:$dst, (trunc (not i64:$in)))]>; 4201def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4202 "#ANDI_rec_1_GT_BIT8", 4203 [(set i1:$dst, (trunc i64:$in))]>; 4204} 4205 4206def : Pat<(i1 (not (trunc i32:$in))), 4207 (ANDI_rec_1_EQ_BIT $in)>; 4208def : Pat<(i1 (not (trunc i64:$in))), 4209 (ANDI_rec_1_EQ_BIT8 $in)>; 4210 4211def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4212def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4213def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4214 4215//===----------------------------------------------------------------------===// 4216// PowerPC Instructions used for assembler/disassembler only 4217// 4218 4219// FIXME: For B=0 or B > 8, the registers following RT are used. 4220// WARNING: Do not add patterns for this instruction without fixing this. 4221def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST), 4222 (ins gprc:$RA, u5imm:$RB), 4223 "lswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4224 4225// FIXME: For B=0 or B > 8, the registers following RT are used. 4226// WARNING: Do not add patterns for this instruction without fixing this. 4227def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4228 (ins gprc:$RST, gprc:$RA, u5imm:$RB), 4229 "stswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4230 4231def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4232 "isync", IIC_SprISYNC, []>; 4233 4234def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr), 4235 "icbi $addr", IIC_LdStICBI, []>; 4236 4237def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4238 "wait $L", IIC_LdStLoad, []>; 4239 4240def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4241 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4242 4243def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4244 "mtsr $SR, $RS", IIC_SprMTSR>; 4245 4246def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4247 "mfsr $RS, $SR", IIC_SprMFSR>; 4248 4249def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4250 "mtsrin $RS, $RB", IIC_SprMTSR>; 4251 4252def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4253 "mfsrin $RS, $RB", IIC_SprMFSR>; 4254 4255def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4256 "mtmsr $RS, $L", IIC_SprMTMSR>; 4257 4258def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4259 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4260 let L = 0; 4261} 4262 4263def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4264 Requires<[IsBookE]> { 4265 bits<1> E; 4266 4267 let Inst{16} = E; 4268 let Inst{21-30} = 163; 4269} 4270 4271def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB), 4272 "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4273def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB), 4274 "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4275 4276def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4277def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4278def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4279def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4280 4281def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins), 4282 "mfmsr $RST", IIC_SprMFMSR, []>; 4283 4284def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4285 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4286 4287def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4288 "mcrfs $BF, $BFA", IIC_BrMCR>; 4289 4290// All MTFSF variants may change the rounding mode so conservatively set it 4291// as an implicit def for all of them. 4292let Predicates = [HasFPU] in { 4293let Defs = [RM], hasSideEffects = 1 in { 4294let isCodeGenOnly = 1, 4295 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4296def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4297 "mtfsfi $BF, $U", IIC_IntMFFS>; 4298def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4299 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4300let Defs = [CR1] in 4301def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4302 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4303 4304def MTFSF : XFLForm_1<63, 711, (outs), 4305 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4306 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4307let Defs = [CR1] in 4308def MTFSF_rec : XFLForm_1<63, 711, (outs), 4309 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4310 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4311} 4312 4313def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4314def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4315def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4316def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4317} 4318 4319def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4320 "slbie $RB", IIC_SprSLBIE, []>; 4321 4322def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB), 4323 "slbmte $RST, $RB", IIC_SprSLBMTE, []>; 4324 4325def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB), 4326 "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>; 4327 4328def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4329 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4330 4331def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4332 4333let Defs = [CR0] in 4334def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB), 4335 "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4336 4337def TLBIA : XForm_0<31, 370, (outs), (ins), 4338 "tlbia", IIC_SprTLBIA, []>; 4339 4340def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4341 "tlbsync", IIC_SprTLBSYNC, []>; 4342 4343def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4344 "tlbiel $RB", IIC_SprTLBIEL, []>; 4345 4346def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4347 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4348def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4349 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4350 4351def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB), 4352 "tlbie $RB,$RST", IIC_SprTLBIE, []>; 4353 4354def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB", 4355 IIC_LdStLoad>, Requires<[IsBookE]>; 4356 4357def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB", 4358 IIC_LdStLoad>, Requires<[IsBookE]>; 4359 4360def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB), 4361 "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; 4362 4363def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4364 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4365 4366def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4367 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4368 4369def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS), 4370 "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4371 4372def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS), 4373 "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4374 4375def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB), 4376 "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>, 4377 Requires<[IsPPC4xx]>; 4378def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4379 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4380 "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>, 4381 Requires<[IsPPC4xx]>, isRecordForm; 4382 4383def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4384 4385def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4386 Requires<[IsBookE]>; 4387def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4388 Requires<[IsBookE]>; 4389 4390def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4391 Requires<[IsE500]>; 4392def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4393 Requires<[IsE500]>; 4394 4395def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR), 4396 "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4397def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR), 4398 "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4399 4400def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4401def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4402 4403def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4404 4405def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4406 (ins gprc:$RA, gprc:$RB), 4407 "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4408def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4409 (ins gprc:$RA, gprc:$RB), 4410 "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4411def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4412 (ins gprc:$RA, gprc:$RB), 4413 "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4414def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4415 (ins gprc:$RA, gprc:$RB), 4416 "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4417 4418def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4419 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4420 "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4421def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4422 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4423 "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4424def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4425 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4426 "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4427def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4428 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4429 "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4430 4431// External PID Load Store Instructions 4432 4433def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4434 "lbepx $RST, $addr", IIC_LdStLoad, []>, 4435 Requires<[IsE500]>; 4436 4437def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 4438 "lfdepx $RST, $addr", IIC_LdStLFD, []>, 4439 Requires<[IsE500]>; 4440 4441def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4442 "lhepx $RST, $addr", IIC_LdStLoad, []>, 4443 Requires<[IsE500]>; 4444 4445def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4446 "lwepx $RST, $addr", IIC_LdStLoad, []>, 4447 Requires<[IsE500]>; 4448 4449def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4450 "stbepx $RST, $addr", IIC_LdStStore, []>, 4451 Requires<[IsE500]>; 4452 4453def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 4454 "stfdepx $RST, $addr", IIC_LdStSTFD, []>, 4455 Requires<[IsE500]>; 4456 4457def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4458 "sthepx $RST, $addr", IIC_LdStStore, []>, 4459 Requires<[IsE500]>; 4460 4461def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4462 "stwepx $RST, $addr", IIC_LdStStore, []>, 4463 Requires<[IsE500]>; 4464 4465def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr", 4466 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4467 4468def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr", 4469 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4470 4471def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4472 "dcbtep $TH, $addr", IIC_LdStDCBF, []>, 4473 Requires<[IsE500]>; 4474 4475def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4476 "dcbtstep $TH, $addr", IIC_LdStDCBF, []>, 4477 Requires<[IsE500]>; 4478 4479def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr", 4480 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4481 4482def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr", 4483 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4484 4485def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr", 4486 IIC_LdStICBI, []>, Requires<[IsE500]>; 4487 4488//===----------------------------------------------------------------------===// 4489// PowerPC Assembler Instruction Aliases 4490// 4491 4492def : InstAlias<"sc", (SC 0)>; 4493 4494def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4495def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4496def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4497def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4498def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4499 4500def : InstAlias<"wait", (WAIT 0)>; 4501def : InstAlias<"waitrsv", (WAIT 1)>; 4502def : InstAlias<"waitimpl", (WAIT 2)>; 4503 4504def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4505 4506def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4507def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4508 4509def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4510def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4511def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4512 4513def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4514def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4515def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4516 4517def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4518def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4519def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4520 4521def : Pat<(int_ppc_isync), (ISYNC)>; 4522def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4523 (DCBF 1, xoaddr:$dst)>; 4524def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4525 (DCBF 3, xoaddr:$dst)>; 4526 4527let Predicates = [IsISA3_1] in { 4528 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4529 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4530 4531 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4532 (DCBF 4, xoaddr:$dst)>; 4533 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4534 (DCBF 6, xoaddr:$dst)>; 4535} 4536 4537def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4538def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4539def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4540def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4541 4542def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4543def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4544def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4545 4546def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4547 4548def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4549def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4550 4551//Disable this alias on AIX for now because as does not support them. 4552let Predicates = [ModernAs] in { 4553 4554foreach BR = 0-7 in { 4555 def : InstAlias<"mfbr"#BR#" $Rx", 4556 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4557 Requires<[IsPPC4xx]>; 4558 def : InstAlias<"mtbr"#BR#" $Rx", 4559 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4560 Requires<[IsPPC4xx]>; 4561} 4562 4563def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4564def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4565def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4566def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4567 4568def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4569def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4570 4571def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4572def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4573 4574def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4575def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4576 4577def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4578def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4579 4580def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4581def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4582 4583def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4584def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4585 4586def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4587def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4588 4589def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4590def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4591 4592def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4593def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4594 4595def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4596def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4597 4598def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4599def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4600 4601def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4602def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4603 4604def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4605def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4606 4607def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4608def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4609 4610foreach SPRG = 4-7 in { 4611 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4612 Requires<[IsBookE]>; 4613 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4614 Requires<[IsBookE]>; 4615 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4616 Requires<[IsBookE]>; 4617 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4618 Requires<[IsBookE]>; 4619} 4620 4621foreach SPRG = 0-3 in { 4622 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4623 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4624 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4625 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4626} 4627 4628def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4629def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4630 4631def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4632def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4633 4634def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4635 4636def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4637def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4638 4639foreach BATR = 0-3 in { 4640 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4641 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4642 Requires<[IsPPC6xx]>; 4643 def : InstAlias<"mfdbatu $Rx, "#BATR, 4644 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4645 Requires<[IsPPC6xx]>; 4646 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4647 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4648 Requires<[IsPPC6xx]>; 4649 def : InstAlias<"mfdbatl $Rx, "#BATR, 4650 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4651 Requires<[IsPPC6xx]>; 4652 def : InstAlias<"mtibatu "#BATR#", $Rx", 4653 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4654 Requires<[IsPPC6xx]>; 4655 def : InstAlias<"mfibatu $Rx, "#BATR, 4656 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4657 Requires<[IsPPC6xx]>; 4658 def : InstAlias<"mtibatl "#BATR#", $Rx", 4659 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4660 Requires<[IsPPC6xx]>; 4661 def : InstAlias<"mfibatl $Rx, "#BATR, 4662 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4663 Requires<[IsPPC6xx]>; 4664} 4665 4666def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4667def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4668 4669def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4670def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4671 4672def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4673def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4674 4675def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4676def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4677 4678def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4679def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4680 4681def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4682def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4683 4684def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4685def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4686 4687def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4688def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4689 4690def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4691def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4692 4693def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4694def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4695 4696} 4697 4698def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4699 4700def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4701 Requires<[IsPPC4xx]>; 4702def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4703 Requires<[IsPPC4xx]>; 4704def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4705 Requires<[IsPPC4xx]>; 4706def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4707 Requires<[IsPPC4xx]>; 4708 4709def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>; 4710def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>; 4711def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>, 4712 Requires<[IsBookE]>; 4713def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>; 4714 4715def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4716 4717def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4718 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4719def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4720 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4721def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4722 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4723def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4724 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4725 4726def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4727 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4728 ZExt32To64; 4729def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4730 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4731 ZExt32To64; 4732def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4733 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4734def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4735 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4736def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4737 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4738def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4739 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4740def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4741 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4742def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4743 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4744def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4745 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4746def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4747 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4748def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4749 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4750def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4751 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4752def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4753 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4754def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4755 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4756def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4757 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4758def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4759 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4760def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4761 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4762def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4763 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4764 4765def : InstAlias<"isellt $rT, $rA, $rB", 4766 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4767def : InstAlias<"iselgt $rT, $rA, $rB", 4768 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4769def : InstAlias<"iseleq $rT, $rA, $rB", 4770 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4771 4772def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4773def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4774def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4775def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4776def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4777def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4778 4779def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4780def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4781// The POWER variant 4782def : MnemonicAlias<"cntlz", "cntlzw">; 4783def : MnemonicAlias<"cntlz.", "cntlzw.">; 4784 4785def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4786 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4787def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4788 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4789def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4790 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4791def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4792 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4793def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4794 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4795def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4796 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4797def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4798 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4799def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4800 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4801def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4802 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4803def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4804 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4805def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4806 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4807def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4808 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4809def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4810 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4811def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4812 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4813def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4814 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4815def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4816 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4817def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4818 4819def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4820def : InstAlias<"rotldi $rA, $rS, $n", 4821 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4822def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4823def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4824def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4825def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4826def : InstAlias<"clrldi $rA, $rS, $n", 4827 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4828def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4829def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4830 4831def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4832 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4833def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4834 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4835def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4836 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4837def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4838 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4839def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4840 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4841def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4842 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4843def PPCLdFixedAddr : 4844 PPCPostRAExpPseudo<(outs gprc:$rT), (ins i32imm:$imm), "#FA_LOAD", 4845 [(set i32:$rT, (int_ppc_fixed_addr_ld timm:$imm))]>; 4846 4847// These generic branch instruction forms are used for the assembler parser only. 4848// Defs and Uses are conservative, since we don't know the BO value. 4849let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4850 let Defs = [CTR], Uses = [CTR, RM] in { 4851 def gBC : BForm_3<16, 0, 0, (outs), 4852 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4853 "bc $BO, $BI, $BD">; 4854 def gBCA : BForm_3<16, 1, 0, (outs), 4855 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4856 "bca $BO, $BI, $BD">; 4857 let isAsmParserOnly = 1 in { 4858 def gBCat : BForm_3_at<16, 0, 0, (outs), 4859 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4860 condbrtarget:$BD), 4861 "bc$at $BO, $BI, $BD">; 4862 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4863 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4864 abscondbrtarget:$BD), 4865 "bca$at $BO, $BI, $BD">; 4866 } // isAsmParserOnly = 1 4867 } 4868 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4869 def gBCL : BForm_3<16, 0, 1, (outs), 4870 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4871 "bcl $BO, $BI, $BD">; 4872 def gBCLA : BForm_3<16, 1, 1, (outs), 4873 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4874 "bcla $BO, $BI, $BD">; 4875 let isAsmParserOnly = 1 in { 4876 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4877 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4878 condbrtarget:$BD), 4879 "bcl$at $BO, $BI, $BD">; 4880 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4881 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4882 abscondbrtarget:$BD), 4883 "bcla$at $BO, $BI, $BD">; 4884 } // // isAsmParserOnly = 1 4885 } 4886 let Defs = [CTR], Uses = [CTR, LR, RM] in 4887 def gBCLR : XLForm_2<19, 16, 0, (outs), 4888 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4889 "bclr $BO, $BI, $BH", IIC_BrB, []>; 4890 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4891 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4892 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4893 "bclrl $BO, $BI, $BH", IIC_BrB, []>; 4894 let Defs = [CTR], Uses = [CTR, LR, RM] in 4895 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4896 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4897 "bcctr $BO, $BI, $BH", IIC_BrB, []>; 4898 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4899 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4900 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4901 "bcctrl $BO, $BI, $BH", IIC_BrB, []>; 4902} 4903 4904multiclass BranchSimpleMnemonicAT<string pm, int at> { 4905 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4906 condbrtarget:$dst)>; 4907 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4908 condbrtarget:$dst)>; 4909 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4910 condbrtarget:$dst)>; 4911 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4912 condbrtarget:$dst)>; 4913} 4914defm : BranchSimpleMnemonicAT<"+", 3>; 4915defm : BranchSimpleMnemonicAT<"-", 2>; 4916 4917def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4918def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4919def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4920def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4921 4922multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4923 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4924 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4925 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4926 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4927 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4928 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4929} 4930multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4931 : BranchSimpleMnemonic1<name, pm, bo> { 4932 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4933 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4934} 4935defm : BranchSimpleMnemonic2<"t", "", 12>; 4936defm : BranchSimpleMnemonic2<"f", "", 4>; 4937defm : BranchSimpleMnemonic2<"t", "-", 14>; 4938defm : BranchSimpleMnemonic2<"f", "-", 6>; 4939defm : BranchSimpleMnemonic2<"t", "+", 15>; 4940defm : BranchSimpleMnemonic2<"f", "+", 7>; 4941defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4942defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4943defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4944defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4945 4946multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4947 def : InstAlias<"b"#name#pm#" $cc, $dst", 4948 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4949 def : InstAlias<"b"#name#pm#" $dst", 4950 (BCC bibo, CR0, condbrtarget:$dst)>; 4951 4952 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4953 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4954 def : InstAlias<"b"#name#"a"#pm#" $dst", 4955 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4956 4957 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4958 (BCCLR bibo, crrc:$cc)>; 4959 def : InstAlias<"b"#name#"lr"#pm, 4960 (BCCLR bibo, CR0)>; 4961 4962 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4963 (BCCCTR bibo, crrc:$cc)>; 4964 def : InstAlias<"b"#name#"ctr"#pm, 4965 (BCCCTR bibo, CR0)>; 4966 4967 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4968 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4969 def : InstAlias<"b"#name#"l"#pm#" $dst", 4970 (BCCL bibo, CR0, condbrtarget:$dst)>; 4971 4972 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4973 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4974 def : InstAlias<"b"#name#"la"#pm#" $dst", 4975 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4976 4977 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4978 (BCCLRL bibo, crrc:$cc)>; 4979 def : InstAlias<"b"#name#"lrl"#pm, 4980 (BCCLRL bibo, CR0)>; 4981 4982 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4983 (BCCCTRL bibo, crrc:$cc)>; 4984 def : InstAlias<"b"#name#"ctrl"#pm, 4985 (BCCCTRL bibo, CR0)>; 4986} 4987multiclass BranchExtendedMnemonic<string name, int bibo> { 4988 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4989 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4990 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4991} 4992defm : BranchExtendedMnemonic<"lt", 12>; 4993defm : BranchExtendedMnemonic<"gt", 44>; 4994defm : BranchExtendedMnemonic<"eq", 76>; 4995defm : BranchExtendedMnemonic<"un", 108>; 4996defm : BranchExtendedMnemonic<"so", 108>; 4997defm : BranchExtendedMnemonic<"ge", 4>; 4998defm : BranchExtendedMnemonic<"nl", 4>; 4999defm : BranchExtendedMnemonic<"le", 36>; 5000defm : BranchExtendedMnemonic<"ng", 36>; 5001defm : BranchExtendedMnemonic<"ne", 68>; 5002defm : BranchExtendedMnemonic<"nu", 100>; 5003defm : BranchExtendedMnemonic<"ns", 100>; 5004 5005def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 5006def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 5007def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 5008def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 5009def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 5010def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 5011def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 5012def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5013 5014def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5015def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5016def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5017def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5018def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5019def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5020def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5021def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5022 5023def : InstAlias<"trap", (TW 31, R0, R0)>; 5024 5025multiclass TrapExtendedMnemonic<string name, int to> { 5026 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5027 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5028 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5029 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5030} 5031defm : TrapExtendedMnemonic<"lt", 16>; 5032defm : TrapExtendedMnemonic<"le", 20>; 5033defm : TrapExtendedMnemonic<"eq", 4>; 5034defm : TrapExtendedMnemonic<"ge", 12>; 5035defm : TrapExtendedMnemonic<"gt", 8>; 5036defm : TrapExtendedMnemonic<"nl", 12>; 5037defm : TrapExtendedMnemonic<"ne", 24>; 5038defm : TrapExtendedMnemonic<"ng", 20>; 5039defm : TrapExtendedMnemonic<"llt", 2>; 5040defm : TrapExtendedMnemonic<"lle", 6>; 5041defm : TrapExtendedMnemonic<"lge", 5>; 5042defm : TrapExtendedMnemonic<"lgt", 1>; 5043defm : TrapExtendedMnemonic<"lnl", 5>; 5044defm : TrapExtendedMnemonic<"lng", 6>; 5045defm : TrapExtendedMnemonic<"u", 31>; 5046 5047// Atomic loads 5048def : Pat<(i32 (atomic_load_8 DForm:$src)), (LBZ memri:$src)>; 5049def : Pat<(i32 (atomic_load_16 DForm:$src)), (LHZ memri:$src)>; 5050def : Pat<(i32 (atomic_load_32 DForm:$src)), (LWZ memri:$src)>; 5051def : Pat<(i32 (atomic_load_8 XForm:$src)), (LBZX memrr:$src)>; 5052def : Pat<(i32 (atomic_load_16 XForm:$src)), (LHZX memrr:$src)>; 5053def : Pat<(i32 (atomic_load_32 XForm:$src)), (LWZX memrr:$src)>; 5054 5055// Atomic stores 5056def : Pat<(atomic_store_8 i32:$val, DForm:$ptr), (STB gprc:$val, memri:$ptr)>; 5057def : Pat<(atomic_store_16 i32:$val, DForm:$ptr), (STH gprc:$val, memri:$ptr)>; 5058def : Pat<(atomic_store_32 i32:$val, DForm:$ptr), (STW gprc:$val, memri:$ptr)>; 5059def : Pat<(atomic_store_8 i32:$val, XForm:$ptr), (STBX gprc:$val, memrr:$ptr)>; 5060def : Pat<(atomic_store_16 i32:$val, XForm:$ptr), (STHX gprc:$val, memrr:$ptr)>; 5061def : Pat<(atomic_store_32 i32:$val, XForm:$ptr), (STWX gprc:$val, memrr:$ptr)>; 5062 5063let Predicates = [IsISA3_0] in { 5064 5065// Copy-Paste Facility 5066// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5067// PASTE for naming consistency. 5068let mayLoad = 1 in 5069def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5070 5071let mayStore = 1, Defs = [CR0] in 5072def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5073 5074def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5075def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5076 5077// Message Synchronize 5078def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5079 5080// Power-Saving Mode Instruction: 5081def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5082 5083def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5084 "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64; 5085} // IsISA3_0 5086 5087let Predicates = [IsISA3_0] in { 5088def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5089 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5090} 5091def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5092 (i32 (MULHW $a, $b))>; 5093def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5094 (i32 (MULHWU $a, $b))>; 5095def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5096 (i32 (CMPB $a, $b))>; 5097 5098def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5099 (LHBRX ForceXForm:$ptr)>; 5100def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5101 (LWBRX ForceXForm:$ptr)>; 5102def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5103 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5104def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5105 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5106 5107 5108// Fast 32-bit reverse bits algorithm: 5109// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5110// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5111// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5112// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5113// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5114// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5115// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5116// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5117// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5118// Step 4.2: Insert B3 to the right position: 5119// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5120// Step 4.3: Insert B1 to the right position: 5121// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5122def MaskValues { 5123 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5124 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5125 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5126 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5127 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5128 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5129} 5130 5131def Shift1 { 5132 dag Right = (RLWINM $A, 31, 1, 31); 5133 dag Left = (RLWINM $A, 1, 0, 30); 5134} 5135 5136def Swap1 { 5137 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5138 (AND Shift1.Left, MaskValues.Hi1)); 5139} 5140 5141def Shift2 { 5142 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5143 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5144} 5145 5146def Swap2 { 5147 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5148 (AND Shift2.Left, MaskValues.Hi2)); 5149} 5150 5151def Shift4 { 5152 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5153 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5154} 5155 5156def Swap4 { 5157 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5158 (AND Shift4.Left, MaskValues.Hi4)); 5159} 5160 5161def Rotate { 5162 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5163} 5164 5165def RotateInsertByte3 { 5166 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5167} 5168 5169def RotateInsertByte1 { 5170 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5171} 5172 5173// Clear the upper half of the register when in 64-bit mode 5174let Predicates = [In64BitMode] in 5175def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5176let Predicates = [In32BitMode] in 5177def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5178 5179// Fast 64-bit reverse bits algorithm: 5180// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5181// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5182// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5183// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5184// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5185// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5186// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5187// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5188// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5189// then OR them together to get the final result. 5190def MaskValues64 { 5191 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5192 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5193 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5194 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5195 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5196 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5197} 5198 5199def DWMaskValues { 5200 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5201 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5202 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5203 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5204 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5205 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5206} 5207 5208def DWSwapInByte { 5209 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5210 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5211 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5212 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5213 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5214 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5215} 5216 5217// Intra-byte swap is done, now start inter-byte swap. 5218def DWBytes4567 { 5219 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5220} 5221 5222def DWBytes7456 { 5223 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5224} 5225 5226def DWBytes7656 { 5227 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5228} 5229 5230// B7 B6 B5 B4 in the right order 5231def DWBytes7654 { 5232 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5233 dag DWord = 5234 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5235} 5236 5237def DWBytes0123 { 5238 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5239} 5240 5241def DWBytes3012 { 5242 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5243} 5244 5245def DWBytes3212 { 5246 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5247} 5248 5249// B3 B2 B1 B0 in the right order 5250def DWBytes3210 { 5251 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5252 dag DWord = 5253 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5254} 5255 5256// These instructions store a hash computed from the value of the link register 5257// and the value of the stack pointer. 5258let mayStore = 1 in { 5259def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5260 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5261 "hashst $RB, $addr", IIC_IntGeneral, []>; 5262def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5263 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5264 "hashstp $RB, $addr", IIC_IntGeneral, []>; 5265} 5266 5267// These instructions check a hash computed from the value of the link register 5268// and the value of the stack pointer. The hasSideEffects flag is needed as the 5269// instruction may TRAP if the hash does not match the hash stored at the 5270// specified address. 5271let mayLoad = 1, hasSideEffects = 1 in { 5272def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5273 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5274 "hashchk $RB, $addr", IIC_IntGeneral, []>; 5275def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5276 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5277 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 5278} 5279 5280let Defs = [CR7], Itinerary = IIC_LdStSync in 5281def CFENCE : PPCPostRAExpPseudo<(outs), (ins gprc:$cr), "#CFENCE", []>; 5282 5283// Now both high word and low word are reversed, next 5284// swap the high word and low word. 5285def : Pat<(i64 (bitreverse i64:$A)), 5286 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5287 5288def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5289 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5290def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4), 5291 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5292def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5293 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5294def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1), 5295 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5296 5297def : Pat<(int_ppc_fcfid f64:$A), 5298 (XSCVSXDDP $A)>; 5299def : Pat<(int_ppc_fcfud f64:$A), 5300 (XSCVUXDDP $A)>; 5301def : Pat<(int_ppc_fctid f64:$A), 5302 (FCTID $A)>; 5303def : Pat<(int_ppc_fctidz f64:$A), 5304 (XSCVDPSXDS $A)>; 5305def : Pat<(int_ppc_fctiw f64:$A), 5306 (FCTIW $A)>; 5307def : Pat<(int_ppc_fctiwz f64:$A), 5308 (XSCVDPSXWS $A)>; 5309def : Pat<(int_ppc_fctudz f64:$A), 5310 (XSCVDPUXDS $A)>; 5311def : Pat<(int_ppc_fctuwz f64:$A), 5312 (XSCVDPUXWS $A)>; 5313 5314def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5315def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5316def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5317 (MFSPR $SPR)>; 5318def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5319 (MTSPR $SPR, $RT)>; 5320def : Pat<(int_ppc_mtmsr gprc:$RS), 5321 (MTMSR $RS, 0)>; 5322 5323let Predicates = [IsISA2_07] in { 5324 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5325 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5326 def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2), 5327 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5328} 5329def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5330 (DCBTST 16, ForceXForm:$dst)>; 5331def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5332 (DCBT 16, ForceXForm:$dst)>; 5333 5334def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5335 (STFIWX f64:$XT, ForceXForm:$dst)>; 5336