1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_VRSaveSpill, 126 SOK_QuadFloat8Spill, 127 SOK_QuadFloat4Spill, 128 SOK_QuadBitSpill, 129 SOK_SpillToVSR, 130 SOK_SPESpill, 131 SOK_LastOpcodeSpill // This must be last on the enum. 132 }; 133 134 // Define list of load and store spill opcodes. 135 #define Pwr8LoadOpcodes \ 136 { \ 137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 139 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, \ 140 PPC::SPILLTOVSR_LD, PPC::EVLDD \ 141 } 142 143 #define Pwr9LoadOpcodes \ 144 { \ 145 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 146 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 147 PPC::DFLOADf32, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, \ 148 PPC::QVLFDXb, PPC::SPILLTOVSR_LD \ 149 } 150 151 #define Pwr8StoreOpcodes \ 152 { \ 153 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 154 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, \ 155 PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILLTOVSR_ST, \ 156 PPC::EVSTDD \ 157 } 158 159 #define Pwr9StoreOpcodes \ 160 { \ 161 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 162 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 163 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, \ 164 PPC::SPILLTOVSR_ST \ 165 } 166 167 // Initialize arrays for load and store spill opcodes on supported subtargets. 168 #define StoreOpcodesForSpill \ 169 { Pwr8StoreOpcodes, Pwr9StoreOpcodes } 170 #define LoadOpcodesForSpill \ 171 { Pwr8LoadOpcodes, Pwr9LoadOpcodes } 172 173 class PPCSubtarget; 174 class PPCInstrInfo : public PPCGenInstrInfo { 175 PPCSubtarget &Subtarget; 176 const PPCRegisterInfo RI; 177 const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 178 StoreOpcodesForSpill; 179 const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 180 LoadOpcodesForSpill; 181 182 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 183 int FrameIdx, const TargetRegisterClass *RC, 184 SmallVectorImpl<MachineInstr *> &NewMIs) const; 185 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 186 unsigned DestReg, int FrameIdx, 187 const TargetRegisterClass *RC, 188 SmallVectorImpl<MachineInstr *> &NewMIs) const; 189 190 // Replace the instruction with single LI if possible. \p DefMI must be LI or 191 // LI8. 192 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 193 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 194 // If the inst is imm-form and its register operand is produced by a ADDI, put 195 // the imm into the inst directly and remove the ADDI if possible. 196 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 197 unsigned OpNoForForwarding) const; 198 // If the inst is x-form and has imm-form and one of its operand is produced 199 // by a LI, put the imm into the inst directly and remove the LI if possible. 200 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 201 unsigned ConstantOpNo, 202 MachineInstr &DefMI) const; 203 // If the inst is x-form and has imm-form and one of its operand is produced 204 // by an add-immediate, try to transform it when possible. 205 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 206 unsigned ConstantOpNo, MachineInstr &DefMI, 207 bool KillDefMI) const; 208 // Try to find that, if the instruction 'MI' contains any operand that 209 // could be forwarded from some inst that feeds it. If yes, return the 210 // Def of that operand. And OpNoForForwarding is the operand index in 211 // the 'MI' for that 'Def'. If we see another use of this Def between 212 // the Def and the MI, SeenIntermediateUse becomes 'true'. 213 MachineInstr *getForwardingDefMI(MachineInstr &MI, 214 unsigned &OpNoForForwarding, 215 bool &SeenIntermediateUse) const; 216 217 // Can the user MI have it's source at index \p OpNoForForwarding 218 // forwarded from an add-immediate that feeds it? 219 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 220 unsigned OpNoForForwarding) const; 221 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 222 const ImmInstrInfo &III, 223 MachineOperand *&ImmMO, 224 MachineOperand *&RegMO) const; 225 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 226 const MachineInstr &DefMI, 227 const ImmInstrInfo &III, 228 int64_t &Imm, 229 int64_t BaseImm = 0) const; 230 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 231 const MachineInstr &DefMI, 232 const MachineInstr &MI, bool KillDefMI, 233 bool &IsFwdFeederRegKilled) const; 234 unsigned getSpillTarget() const; 235 const unsigned *getStoreOpcodesForSpillArray() const; 236 const unsigned *getLoadOpcodesForSpillArray() const; 237 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 238 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, 239 SmallVectorImpl<MachineInstr *> &InsInstrs, 240 SmallVectorImpl<MachineInstr *> &DelInstrs, 241 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 242 virtual void anchor(); 243 244 protected: 245 /// Commutes the operands in the given instruction. 246 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 247 /// 248 /// Do not call this method for a non-commutable instruction or for 249 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 250 /// Even though the instruction is commutable, the method may still 251 /// fail to commute the operands, null pointer is returned in such cases. 252 /// 253 /// For example, we can commute rlwimi instructions, but only if the 254 /// rotate amt is zero. We also have to munge the immediates a bit. 255 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 256 unsigned OpIdx1, 257 unsigned OpIdx2) const override; 258 259 public: 260 explicit PPCInstrInfo(PPCSubtarget &STI); 261 262 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 263 /// such, whenever a client has an instance of instruction info, it should 264 /// always be able to get register info as well (through this method). 265 /// 266 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 267 268 bool isXFormMemOp(unsigned Opcode) const { 269 return get(Opcode).TSFlags & PPCII::XFormMemOp; 270 } 271 bool isPrefixed(unsigned Opcode) const { 272 return get(Opcode).TSFlags & PPCII::Prefixed; 273 } 274 275 static bool isSameClassPhysRegCopy(unsigned Opcode) { 276 unsigned CopyOpcodes[] = 277 { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf, 278 PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb, 279 PPC::CROR, PPC::EVOR, -1U }; 280 for (int i = 0; CopyOpcodes[i] != -1U; i++) 281 if (Opcode == CopyOpcodes[i]) 282 return true; 283 return false; 284 } 285 286 ScheduleHazardRecognizer * 287 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 288 const ScheduleDAG *DAG) const override; 289 ScheduleHazardRecognizer * 290 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 291 const ScheduleDAG *DAG) const override; 292 293 unsigned getInstrLatency(const InstrItineraryData *ItinData, 294 const MachineInstr &MI, 295 unsigned *PredCost = nullptr) const override; 296 297 int getOperandLatency(const InstrItineraryData *ItinData, 298 const MachineInstr &DefMI, unsigned DefIdx, 299 const MachineInstr &UseMI, 300 unsigned UseIdx) const override; 301 int getOperandLatency(const InstrItineraryData *ItinData, 302 SDNode *DefNode, unsigned DefIdx, 303 SDNode *UseNode, unsigned UseIdx) const override { 304 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 305 UseNode, UseIdx); 306 } 307 308 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 309 const MachineInstr &DefMI, 310 unsigned DefIdx) const override { 311 // Machine LICM should hoist all instructions in low-register-pressure 312 // situations; none are sufficiently free to justify leaving in a loop 313 // body. 314 return false; 315 } 316 317 bool useMachineCombiner() const override { 318 return true; 319 } 320 321 /// When getMachineCombinerPatterns() finds patterns, this function generates 322 /// the instructions that could replace the original code sequence 323 void genAlternativeCodeSequence( 324 MachineInstr &Root, MachineCombinerPattern Pattern, 325 SmallVectorImpl<MachineInstr *> &InsInstrs, 326 SmallVectorImpl<MachineInstr *> &DelInstrs, 327 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 328 329 /// Return true when there is potentially a faster code sequence for a fma 330 /// chain ending in \p Root. All potential patterns are output in the \p 331 /// P array. 332 bool getFMAPatterns(MachineInstr &Root, 333 SmallVectorImpl<MachineCombinerPattern> &P) const; 334 335 /// Return true when there is potentially a faster code sequence 336 /// for an instruction chain ending in <Root>. All potential patterns are 337 /// output in the <Pattern> array. 338 bool getMachineCombinerPatterns( 339 MachineInstr &Root, 340 SmallVectorImpl<MachineCombinerPattern> &P) const override; 341 342 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 343 344 /// On PowerPC, we try to reassociate FMA chain which will increase 345 /// instruction size. Set extension resource length limit to 1 for edge case. 346 /// Resource Length is calculated by scaled resource usage in getCycles(). 347 /// Because of the division in getCycles(), it returns different cycles due to 348 /// legacy scaled resource usage. So new resource length may be same with 349 /// legacy or 1 bigger than legacy. 350 /// We need to execlude the 1 bigger case even the resource length is not 351 /// perserved for more FMA chain reassociations on PowerPC. 352 int getExtendResourceLenLimit() const override { return 1; } 353 354 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 355 MachineInstr &NewMI1, 356 MachineInstr &NewMI2) const override; 357 358 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 359 360 bool isCoalescableExtInstr(const MachineInstr &MI, 361 Register &SrcReg, Register &DstReg, 362 unsigned &SubIdx) const override; 363 unsigned isLoadFromStackSlot(const MachineInstr &MI, 364 int &FrameIndex) const override; 365 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 366 AAResults *AA) const override; 367 unsigned isStoreToStackSlot(const MachineInstr &MI, 368 int &FrameIndex) const override; 369 370 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 371 unsigned &SrcOpIdx2) const override; 372 373 void insertNoop(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MI) const override; 375 376 377 // Branch analysis. 378 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 379 MachineBasicBlock *&FBB, 380 SmallVectorImpl<MachineOperand> &Cond, 381 bool AllowModify) const override; 382 unsigned removeBranch(MachineBasicBlock &MBB, 383 int *BytesRemoved = nullptr) const override; 384 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 385 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 386 const DebugLoc &DL, 387 int *BytesAdded = nullptr) const override; 388 389 // Select analysis. 390 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 391 Register, Register, Register, int &, int &, 392 int &) const override; 393 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 394 const DebugLoc &DL, Register DstReg, 395 ArrayRef<MachineOperand> Cond, Register TrueReg, 396 Register FalseReg) const override; 397 398 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 399 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 400 bool KillSrc) const override; 401 402 void storeRegToStackSlot(MachineBasicBlock &MBB, 403 MachineBasicBlock::iterator MBBI, 404 Register SrcReg, bool isKill, int FrameIndex, 405 const TargetRegisterClass *RC, 406 const TargetRegisterInfo *TRI) const override; 407 408 // Emits a register spill without updating the register class for vector 409 // registers. This ensures that when we spill a vector register the 410 // element order in the register is the same as it was in memory. 411 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 412 MachineBasicBlock::iterator MBBI, 413 unsigned SrcReg, bool isKill, int FrameIndex, 414 const TargetRegisterClass *RC, 415 const TargetRegisterInfo *TRI) const; 416 417 void loadRegFromStackSlot(MachineBasicBlock &MBB, 418 MachineBasicBlock::iterator MBBI, 419 Register DestReg, int FrameIndex, 420 const TargetRegisterClass *RC, 421 const TargetRegisterInfo *TRI) const override; 422 423 // Emits a register reload without updating the register class for vector 424 // registers. This ensures that when we reload a vector register the 425 // element order in the register is the same as it was in memory. 426 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 427 MachineBasicBlock::iterator MBBI, 428 unsigned DestReg, int FrameIndex, 429 const TargetRegisterClass *RC, 430 const TargetRegisterInfo *TRI) const; 431 432 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 433 434 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 435 436 bool 437 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 438 439 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 440 MachineRegisterInfo *MRI) const override; 441 442 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 443 Register Reg) const; 444 445 // If conversion by predication (only supported by some branch instructions). 446 // All of the profitability checks always return true; it is always 447 // profitable to use the predicated branches. 448 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 449 unsigned NumCycles, unsigned ExtraPredCycles, 450 BranchProbability Probability) const override { 451 return true; 452 } 453 454 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 455 unsigned NumT, unsigned ExtraT, 456 MachineBasicBlock &FMBB, 457 unsigned NumF, unsigned ExtraF, 458 BranchProbability Probability) const override; 459 460 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 461 BranchProbability Probability) const override { 462 return true; 463 } 464 465 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 466 MachineBasicBlock &FMBB) const override { 467 return false; 468 } 469 470 // Predication support. 471 bool isPredicated(const MachineInstr &MI) const override; 472 473 bool PredicateInstruction(MachineInstr &MI, 474 ArrayRef<MachineOperand> Pred) const override; 475 476 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 477 ArrayRef<MachineOperand> Pred2) const override; 478 479 bool DefinesPredicate(MachineInstr &MI, 480 std::vector<MachineOperand> &Pred) const override; 481 482 // Comparison optimization. 483 484 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 485 Register &SrcReg2, int &Mask, int &Value) const override; 486 487 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 488 Register SrcReg2, int Mask, int Value, 489 const MachineRegisterInfo *MRI) const override; 490 491 492 /// Return true if get the base operand, byte offset of an instruction and 493 /// the memory width. Width is the size of memory that is being 494 /// loaded/stored (e.g. 1, 2, 4, 8). 495 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 496 const MachineOperand *&BaseOp, 497 int64_t &Offset, unsigned &Width, 498 const TargetRegisterInfo *TRI) const; 499 500 /// Return true if two MIs access different memory addresses and false 501 /// otherwise 502 bool 503 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 504 const MachineInstr &MIb) const override; 505 506 /// GetInstSize - Return the number of bytes of code the specified 507 /// instruction may be. This returns the maximum number of bytes. 508 /// 509 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 510 511 void getNoop(MCInst &NopInst) const override; 512 513 std::pair<unsigned, unsigned> 514 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 515 516 ArrayRef<std::pair<unsigned, const char *>> 517 getSerializableDirectMachineOperandTargetFlags() const override; 518 519 ArrayRef<std::pair<unsigned, const char *>> 520 getSerializableBitmaskMachineOperandTargetFlags() const override; 521 522 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 523 bool expandVSXMemPseudo(MachineInstr &MI) const; 524 525 // Lower pseudo instructions after register allocation. 526 bool expandPostRAPseudo(MachineInstr &MI) const override; 527 528 static bool isVFRegister(unsigned Reg) { 529 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 530 } 531 static bool isVRRegister(unsigned Reg) { 532 return Reg >= PPC::V0 && Reg <= PPC::V31; 533 } 534 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 535 static int getRecordFormOpcode(unsigned Opcode); 536 537 bool isTOCSaveMI(const MachineInstr &MI) const; 538 539 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 540 const unsigned PhiDepth) const; 541 542 /// Return true if the output of the instruction is always a sign-extended, 543 /// i.e. 0 to 31-th bits are same as 32-th bit. 544 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 545 return isSignOrZeroExtended(MI, true, depth); 546 } 547 548 /// Return true if the output of the instruction is always zero-extended, 549 /// i.e. 0 to 31-th bits are all zeros 550 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 551 return isSignOrZeroExtended(MI, false, depth); 552 } 553 554 bool convertToImmediateForm(MachineInstr &MI, 555 MachineInstr **KilledDef = nullptr) const; 556 bool foldFrameOffset(MachineInstr &MI) const; 557 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 558 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 559 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 560 unsigned &XFormOpcode, 561 int64_t &OffsetOfImmInstr, 562 ImmInstrInfo &III) const; 563 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 564 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 565 int64_t OffsetImm) const; 566 567 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 568 /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate 569 /// register killed/dead flags semantics, this function can be called to fix 570 /// up. Before calling this function, 571 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 572 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 573 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For 574 /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI 575 /// will be adjust to true definition. 576 /// 3. We can do accurate fixup for the case when all instructions between 577 /// [\p StartMI, \p EndMI] are in same basic block. 578 /// 4. For the case when \p StartMI and \p EndMI are not in same basic block, 579 /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA 580 /// and for post-RA, we give an assertion as without reaching definition 581 /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right. 582 void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, 583 unsigned RegNo) const; 584 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 585 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 586 int64_t Imm) const; 587 588 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 589 bool PostRA) const; 590 591 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 592 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 593 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 594 bool &SeenIntermediateUse) const; 595 596 /// getRegNumForOperand - some operands use different numbering schemes 597 /// for the same registers. For example, a VSX instruction may have any of 598 /// vs0-vs63 allocated whereas an Altivec instruction could only have 599 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 600 /// register number needed for the opcode/operand number combination. 601 /// The operand number argument will be useful when we need to extend this 602 /// to instructions that use both Altivec and VSX numbering (for different 603 /// operands). 604 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 605 unsigned OpNo) { 606 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 607 switch (regClass) { 608 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 609 // VSX32-VSX63 during encoding/disassembling 610 case PPC::VSSRCRegClassID: 611 case PPC::VSFRCRegClassID: 612 if (isVFRegister(Reg)) 613 return PPC::VSX32 + (Reg - PPC::VF0); 614 break; 615 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 616 // VSX32-VSX63 during encoding/disassembling 617 case PPC::VSRCRegClassID: 618 if (isVRRegister(Reg)) 619 return PPC::VSX32 + (Reg - PPC::V0); 620 break; 621 // Other RegClass doesn't need mapping 622 default: 623 break; 624 } 625 return Reg; 626 } 627 628 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 629 bool isBDNZ(unsigned Opcode) const; 630 631 /// Find the hardware loop instruction used to set-up the specified loop. 632 /// On PPC, we have two instructions used to set-up the hardware loop 633 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 634 /// instructions to indicate the end of a loop. 635 MachineInstr * 636 findLoopInstr(MachineBasicBlock &PreHeader, 637 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 638 639 /// Analyze loop L, which must be a single-basic-block loop, and if the 640 /// conditions can be understood enough produce a PipelinerLoopInfo object. 641 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 642 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 643 }; 644 645 } 646 647 #endif 648