1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_SpillToVSR, 126 SOK_PairedVecSpill, 127 SOK_AccumulatorSpill, 128 SOK_UAccumulatorSpill, 129 SOK_SPESpill, 130 SOK_PairedG8Spill, 131 SOK_LastOpcodeSpill // This must be last on the enum. 132 }; 133 134 // Define list of load and store spill opcodes. 135 #define NoInstr PPC::INSTRUCTION_LIST_END 136 #define Pwr8LoadOpcodes \ 137 { \ 138 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 139 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 140 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \ 141 PPC::RESTORE_QUADWORD \ 142 } 143 144 #define Pwr9LoadOpcodes \ 145 { \ 146 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 147 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 148 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \ 149 NoInstr, PPC::RESTORE_QUADWORD \ 150 } 151 152 #define Pwr10LoadOpcodes \ 153 { \ 154 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 155 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 156 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \ 157 PPC::RESTORE_UACC, NoInstr, PPC::RESTORE_QUADWORD \ 158 } 159 160 #define Pwr8StoreOpcodes \ 161 { \ 162 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 163 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \ 164 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \ 165 PPC::SPILL_QUADWORD \ 166 } 167 168 #define Pwr9StoreOpcodes \ 169 { \ 170 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 171 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 172 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, \ 173 PPC::SPILL_QUADWORD \ 174 } 175 176 #define Pwr10StoreOpcodes \ 177 { \ 178 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 179 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 180 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \ 181 NoInstr, PPC::SPILL_QUADWORD \ 182 } 183 184 // Initialize arrays for load and store spill opcodes on supported subtargets. 185 #define StoreOpcodesForSpill \ 186 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes } 187 #define LoadOpcodesForSpill \ 188 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes } 189 190 class PPCSubtarget; 191 class PPCInstrInfo : public PPCGenInstrInfo { 192 PPCSubtarget &Subtarget; 193 const PPCRegisterInfo RI; 194 const unsigned StoreSpillOpcodesArray[3][SOK_LastOpcodeSpill] = 195 StoreOpcodesForSpill; 196 const unsigned LoadSpillOpcodesArray[3][SOK_LastOpcodeSpill] = 197 LoadOpcodesForSpill; 198 199 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 200 int FrameIdx, const TargetRegisterClass *RC, 201 SmallVectorImpl<MachineInstr *> &NewMIs) const; 202 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 203 unsigned DestReg, int FrameIdx, 204 const TargetRegisterClass *RC, 205 SmallVectorImpl<MachineInstr *> &NewMIs) const; 206 207 // Replace the instruction with single LI if possible. \p DefMI must be LI or 208 // LI8. 209 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 210 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 211 // If the inst is imm-form and its register operand is produced by a ADDI, put 212 // the imm into the inst directly and remove the ADDI if possible. 213 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 214 unsigned OpNoForForwarding) const; 215 // If the inst is x-form and has imm-form and one of its operand is produced 216 // by a LI, put the imm into the inst directly and remove the LI if possible. 217 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 218 unsigned ConstantOpNo, 219 MachineInstr &DefMI) const; 220 // If the inst is x-form and has imm-form and one of its operand is produced 221 // by an add-immediate, try to transform it when possible. 222 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 223 unsigned ConstantOpNo, MachineInstr &DefMI, 224 bool KillDefMI) const; 225 // Try to find that, if the instruction 'MI' contains any operand that 226 // could be forwarded from some inst that feeds it. If yes, return the 227 // Def of that operand. And OpNoForForwarding is the operand index in 228 // the 'MI' for that 'Def'. If we see another use of this Def between 229 // the Def and the MI, SeenIntermediateUse becomes 'true'. 230 MachineInstr *getForwardingDefMI(MachineInstr &MI, 231 unsigned &OpNoForForwarding, 232 bool &SeenIntermediateUse) const; 233 234 // Can the user MI have it's source at index \p OpNoForForwarding 235 // forwarded from an add-immediate that feeds it? 236 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 237 unsigned OpNoForForwarding) const; 238 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 239 const ImmInstrInfo &III, 240 MachineOperand *&ImmMO, 241 MachineOperand *&RegMO) const; 242 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 243 const MachineInstr &DefMI, 244 const ImmInstrInfo &III, 245 int64_t &Imm, 246 int64_t BaseImm = 0) const; 247 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 248 const MachineInstr &DefMI, 249 const MachineInstr &MI, bool KillDefMI, 250 bool &IsFwdFeederRegKilled) const; 251 unsigned getSpillTarget() const; 252 const unsigned *getStoreOpcodesForSpillArray() const; 253 const unsigned *getLoadOpcodesForSpillArray() const; 254 unsigned getSpillIndex(const TargetRegisterClass *RC) const; 255 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 256 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, 257 SmallVectorImpl<MachineInstr *> &InsInstrs, 258 SmallVectorImpl<MachineInstr *> &DelInstrs, 259 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 260 bool isLoadFromConstantPool(MachineInstr *I) const; 261 Register 262 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty, 263 SmallVectorImpl<MachineInstr *> &InsInstrs) const; 264 const Constant *getConstantFromConstantPool(MachineInstr *I) const; 265 virtual void anchor(); 266 267 protected: 268 /// Commutes the operands in the given instruction. 269 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 270 /// 271 /// Do not call this method for a non-commutable instruction or for 272 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 273 /// Even though the instruction is commutable, the method may still 274 /// fail to commute the operands, null pointer is returned in such cases. 275 /// 276 /// For example, we can commute rlwimi instructions, but only if the 277 /// rotate amt is zero. We also have to munge the immediates a bit. 278 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 279 unsigned OpIdx1, 280 unsigned OpIdx2) const override; 281 282 public: 283 explicit PPCInstrInfo(PPCSubtarget &STI); 284 285 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 286 /// such, whenever a client has an instance of instruction info, it should 287 /// always be able to get register info as well (through this method). 288 /// 289 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 290 291 bool isXFormMemOp(unsigned Opcode) const { 292 return get(Opcode).TSFlags & PPCII::XFormMemOp; 293 } 294 bool isPrefixed(unsigned Opcode) const { 295 return get(Opcode).TSFlags & PPCII::Prefixed; 296 } 297 298 /// Check if Opcode corresponds to a call instruction that should be marked 299 /// with the NOTOC relocation. 300 bool isNoTOCCallInstr(unsigned Opcode) const { 301 if (!get(Opcode).isCall()) 302 return false; 303 304 switch (Opcode) { 305 default: 306 #ifndef NDEBUG 307 llvm_unreachable("Unknown call opcode"); 308 #endif 309 return false; 310 case PPC::BL8_NOTOC: 311 case PPC::BL8_NOTOC_TLS: 312 case PPC::BL8_NOTOC_RM: 313 return true; 314 #ifndef NDEBUG 315 case PPC::BL8: 316 case PPC::BL: 317 case PPC::BL8_TLS: 318 case PPC::BL_TLS: 319 case PPC::BLA8: 320 case PPC::BLA: 321 case PPC::BCCL: 322 case PPC::BCCLA: 323 case PPC::BCL: 324 case PPC::BCLn: 325 case PPC::BL8_NOP: 326 case PPC::BL_NOP: 327 case PPC::BL8_NOP_TLS: 328 case PPC::BLA8_NOP: 329 case PPC::BCTRL8: 330 case PPC::BCTRL: 331 case PPC::BCCCTRL8: 332 case PPC::BCCCTRL: 333 case PPC::BCCTRL8: 334 case PPC::BCCTRL: 335 case PPC::BCCTRL8n: 336 case PPC::BCCTRLn: 337 case PPC::BL8_RM: 338 case PPC::BLA8_RM: 339 case PPC::BL8_NOP_RM: 340 case PPC::BLA8_NOP_RM: 341 case PPC::BCTRL8_RM: 342 case PPC::BCTRL8_LDinto_toc: 343 case PPC::BCTRL8_LDinto_toc_RM: 344 case PPC::BL8_TLS_: 345 case PPC::TCRETURNdi8: 346 case PPC::TCRETURNai8: 347 case PPC::TCRETURNri8: 348 case PPC::TAILBCTR8: 349 case PPC::TAILB8: 350 case PPC::TAILBA8: 351 case PPC::BCLalways: 352 case PPC::BLRL: 353 case PPC::BCCLRL: 354 case PPC::BCLRL: 355 case PPC::BCLRLn: 356 case PPC::BDZL: 357 case PPC::BDNZL: 358 case PPC::BDZLA: 359 case PPC::BDNZLA: 360 case PPC::BDZLp: 361 case PPC::BDNZLp: 362 case PPC::BDZLAp: 363 case PPC::BDNZLAp: 364 case PPC::BDZLm: 365 case PPC::BDNZLm: 366 case PPC::BDZLAm: 367 case PPC::BDNZLAm: 368 case PPC::BDZLRL: 369 case PPC::BDNZLRL: 370 case PPC::BDZLRLp: 371 case PPC::BDNZLRLp: 372 case PPC::BDZLRLm: 373 case PPC::BDNZLRLm: 374 case PPC::BL_RM: 375 case PPC::BLA_RM: 376 case PPC::BL_NOP_RM: 377 case PPC::BCTRL_RM: 378 case PPC::TCRETURNdi: 379 case PPC::TCRETURNai: 380 case PPC::TCRETURNri: 381 case PPC::BCTRL_LWZinto_toc: 382 case PPC::BCTRL_LWZinto_toc_RM: 383 case PPC::TAILBCTR: 384 case PPC::TAILB: 385 case PPC::TAILBA: 386 return false; 387 #endif 388 } 389 } 390 391 static bool isSameClassPhysRegCopy(unsigned Opcode) { 392 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR, 393 PPC::VOR, PPC::XXLOR, PPC::XXLORf, 394 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR, 395 PPC::EVOR, -1U}; 396 for (int i = 0; CopyOpcodes[i] != -1U; i++) 397 if (Opcode == CopyOpcodes[i]) 398 return true; 399 return false; 400 } 401 402 ScheduleHazardRecognizer * 403 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 404 const ScheduleDAG *DAG) const override; 405 ScheduleHazardRecognizer * 406 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 407 const ScheduleDAG *DAG) const override; 408 409 unsigned getInstrLatency(const InstrItineraryData *ItinData, 410 const MachineInstr &MI, 411 unsigned *PredCost = nullptr) const override; 412 413 int getOperandLatency(const InstrItineraryData *ItinData, 414 const MachineInstr &DefMI, unsigned DefIdx, 415 const MachineInstr &UseMI, 416 unsigned UseIdx) const override; 417 int getOperandLatency(const InstrItineraryData *ItinData, 418 SDNode *DefNode, unsigned DefIdx, 419 SDNode *UseNode, unsigned UseIdx) const override { 420 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 421 UseNode, UseIdx); 422 } 423 424 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 425 const MachineInstr &DefMI, 426 unsigned DefIdx) const override { 427 // Machine LICM should hoist all instructions in low-register-pressure 428 // situations; none are sufficiently free to justify leaving in a loop 429 // body. 430 return false; 431 } 432 433 bool useMachineCombiner() const override { 434 return true; 435 } 436 437 /// When getMachineCombinerPatterns() finds patterns, this function generates 438 /// the instructions that could replace the original code sequence 439 void genAlternativeCodeSequence( 440 MachineInstr &Root, MachineCombinerPattern Pattern, 441 SmallVectorImpl<MachineInstr *> &InsInstrs, 442 SmallVectorImpl<MachineInstr *> &DelInstrs, 443 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 444 445 /// Return true when there is potentially a faster code sequence for a fma 446 /// chain ending in \p Root. All potential patterns are output in the \p 447 /// P array. 448 bool getFMAPatterns(MachineInstr &Root, 449 SmallVectorImpl<MachineCombinerPattern> &P, 450 bool DoRegPressureReduce) const; 451 452 /// Return true when there is potentially a faster code sequence 453 /// for an instruction chain ending in <Root>. All potential patterns are 454 /// output in the <Pattern> array. 455 bool getMachineCombinerPatterns(MachineInstr &Root, 456 SmallVectorImpl<MachineCombinerPattern> &P, 457 bool DoRegPressureReduce) const override; 458 459 /// On PowerPC, we leverage machine combiner pass to reduce register pressure 460 /// when the register pressure is high for one BB. 461 /// Return true if register pressure for \p MBB is high and ABI is supported 462 /// to reduce register pressure. Otherwise return false. 463 bool 464 shouldReduceRegisterPressure(MachineBasicBlock *MBB, 465 RegisterClassInfo *RegClassInfo) const override; 466 467 /// Fixup the placeholders we put in genAlternativeCodeSequence() for 468 /// MachineCombiner. 469 void 470 finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, 471 SmallVectorImpl<MachineInstr *> &InsInstrs) const override; 472 473 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 474 475 /// On PowerPC, we try to reassociate FMA chain which will increase 476 /// instruction size. Set extension resource length limit to 1 for edge case. 477 /// Resource Length is calculated by scaled resource usage in getCycles(). 478 /// Because of the division in getCycles(), it returns different cycles due to 479 /// legacy scaled resource usage. So new resource length may be same with 480 /// legacy or 1 bigger than legacy. 481 /// We need to execlude the 1 bigger case even the resource length is not 482 /// perserved for more FMA chain reassociations on PowerPC. 483 int getExtendResourceLenLimit() const override { return 1; } 484 485 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 486 MachineInstr &NewMI1, 487 MachineInstr &NewMI2) const override; 488 489 // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI 490 // and clears nuw, nsw, and exact flags. 491 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const; 492 493 bool isCoalescableExtInstr(const MachineInstr &MI, 494 Register &SrcReg, Register &DstReg, 495 unsigned &SubIdx) const override; 496 unsigned isLoadFromStackSlot(const MachineInstr &MI, 497 int &FrameIndex) const override; 498 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 499 AAResults *AA) const override; 500 unsigned isStoreToStackSlot(const MachineInstr &MI, 501 int &FrameIndex) const override; 502 503 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 504 unsigned &SrcOpIdx2) const override; 505 506 void insertNoop(MachineBasicBlock &MBB, 507 MachineBasicBlock::iterator MI) const override; 508 509 510 // Branch analysis. 511 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 512 MachineBasicBlock *&FBB, 513 SmallVectorImpl<MachineOperand> &Cond, 514 bool AllowModify) const override; 515 unsigned removeBranch(MachineBasicBlock &MBB, 516 int *BytesRemoved = nullptr) const override; 517 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 518 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 519 const DebugLoc &DL, 520 int *BytesAdded = nullptr) const override; 521 522 // Select analysis. 523 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 524 Register, Register, Register, int &, int &, 525 int &) const override; 526 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 527 const DebugLoc &DL, Register DstReg, 528 ArrayRef<MachineOperand> Cond, Register TrueReg, 529 Register FalseReg) const override; 530 531 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 532 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 533 bool KillSrc) const override; 534 535 void storeRegToStackSlot(MachineBasicBlock &MBB, 536 MachineBasicBlock::iterator MBBI, 537 Register SrcReg, bool isKill, int FrameIndex, 538 const TargetRegisterClass *RC, 539 const TargetRegisterInfo *TRI) const override; 540 541 // Emits a register spill without updating the register class for vector 542 // registers. This ensures that when we spill a vector register the 543 // element order in the register is the same as it was in memory. 544 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 545 MachineBasicBlock::iterator MBBI, 546 unsigned SrcReg, bool isKill, int FrameIndex, 547 const TargetRegisterClass *RC, 548 const TargetRegisterInfo *TRI) const; 549 550 void loadRegFromStackSlot(MachineBasicBlock &MBB, 551 MachineBasicBlock::iterator MBBI, 552 Register DestReg, int FrameIndex, 553 const TargetRegisterClass *RC, 554 const TargetRegisterInfo *TRI) const override; 555 556 // Emits a register reload without updating the register class for vector 557 // registers. This ensures that when we reload a vector register the 558 // element order in the register is the same as it was in memory. 559 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 560 MachineBasicBlock::iterator MBBI, 561 unsigned DestReg, int FrameIndex, 562 const TargetRegisterClass *RC, 563 const TargetRegisterInfo *TRI) const; 564 565 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 566 567 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 568 569 bool 570 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 571 572 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 573 MachineRegisterInfo *MRI) const override; 574 575 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 576 Register Reg) const; 577 578 // If conversion by predication (only supported by some branch instructions). 579 // All of the profitability checks always return true; it is always 580 // profitable to use the predicated branches. 581 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 582 unsigned NumCycles, unsigned ExtraPredCycles, 583 BranchProbability Probability) const override { 584 return true; 585 } 586 587 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 588 unsigned NumT, unsigned ExtraT, 589 MachineBasicBlock &FMBB, 590 unsigned NumF, unsigned ExtraF, 591 BranchProbability Probability) const override; 592 593 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 594 BranchProbability Probability) const override { 595 return true; 596 } 597 598 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 599 MachineBasicBlock &FMBB) const override { 600 return false; 601 } 602 603 // Predication support. 604 bool isPredicated(const MachineInstr &MI) const override; 605 606 bool isSchedulingBoundary(const MachineInstr &MI, 607 const MachineBasicBlock *MBB, 608 const MachineFunction &MF) const override; 609 610 bool PredicateInstruction(MachineInstr &MI, 611 ArrayRef<MachineOperand> Pred) const override; 612 613 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 614 ArrayRef<MachineOperand> Pred2) const override; 615 616 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 617 bool SkipDead) const override; 618 619 // Comparison optimization. 620 621 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 622 Register &SrcReg2, int64_t &Mask, 623 int64_t &Value) const override; 624 625 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 626 Register SrcReg2, int64_t Mask, int64_t Value, 627 const MachineRegisterInfo *MRI) const override; 628 629 630 /// Return true if get the base operand, byte offset of an instruction and 631 /// the memory width. Width is the size of memory that is being 632 /// loaded/stored (e.g. 1, 2, 4, 8). 633 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 634 const MachineOperand *&BaseOp, 635 int64_t &Offset, unsigned &Width, 636 const TargetRegisterInfo *TRI) const; 637 638 /// Get the base operand and byte offset of an instruction that reads/writes 639 /// memory. 640 bool getMemOperandsWithOffsetWidth( 641 const MachineInstr &LdSt, 642 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 643 bool &OffsetIsScalable, unsigned &Width, 644 const TargetRegisterInfo *TRI) const override; 645 646 /// Returns true if the two given memory operations should be scheduled 647 /// adjacent. 648 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 649 ArrayRef<const MachineOperand *> BaseOps2, 650 unsigned NumLoads, unsigned NumBytes) const override; 651 652 /// Return true if two MIs access different memory addresses and false 653 /// otherwise 654 bool 655 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 656 const MachineInstr &MIb) const override; 657 658 /// GetInstSize - Return the number of bytes of code the specified 659 /// instruction may be. This returns the maximum number of bytes. 660 /// 661 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 662 663 MCInst getNop() const override; 664 665 std::pair<unsigned, unsigned> 666 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 667 668 ArrayRef<std::pair<unsigned, const char *>> 669 getSerializableDirectMachineOperandTargetFlags() const override; 670 671 ArrayRef<std::pair<unsigned, const char *>> 672 getSerializableBitmaskMachineOperandTargetFlags() const override; 673 674 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 675 bool expandVSXMemPseudo(MachineInstr &MI) const; 676 677 // Lower pseudo instructions after register allocation. 678 bool expandPostRAPseudo(MachineInstr &MI) const override; 679 680 static bool isVFRegister(unsigned Reg) { 681 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 682 } 683 static bool isVRRegister(unsigned Reg) { 684 return Reg >= PPC::V0 && Reg <= PPC::V31; 685 } 686 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 687 static int getRecordFormOpcode(unsigned Opcode); 688 689 bool isTOCSaveMI(const MachineInstr &MI) const; 690 691 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 692 const unsigned PhiDepth) const; 693 694 /// Return true if the output of the instruction is always a sign-extended, 695 /// i.e. 0 to 31-th bits are same as 32-th bit. 696 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 697 return isSignOrZeroExtended(MI, true, depth); 698 } 699 700 /// Return true if the output of the instruction is always zero-extended, 701 /// i.e. 0 to 31-th bits are all zeros 702 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 703 return isSignOrZeroExtended(MI, false, depth); 704 } 705 706 bool convertToImmediateForm(MachineInstr &MI, 707 MachineInstr **KilledDef = nullptr) const; 708 bool foldFrameOffset(MachineInstr &MI) const; 709 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const; 710 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 711 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 712 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 713 unsigned &XFormOpcode, 714 int64_t &OffsetOfImmInstr, 715 ImmInstrInfo &III) const; 716 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 717 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 718 int64_t OffsetImm) const; 719 720 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 721 /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate 722 /// register killed/dead flags semantics, this function can be called to fix 723 /// up. Before calling this function, 724 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 725 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 726 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For 727 /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI 728 /// will be adjust to true definition. 729 /// 3. We can do accurate fixup for the case when all instructions between 730 /// [\p StartMI, \p EndMI] are in same basic block. 731 /// 4. For the case when \p StartMI and \p EndMI are not in same basic block, 732 /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA 733 /// and for post-RA, we give an assertion as without reaching definition 734 /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right. 735 void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, 736 unsigned RegNo) const; 737 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 738 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 739 int64_t Imm) const; 740 741 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 742 bool PostRA) const; 743 744 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 745 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 746 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 747 bool &SeenIntermediateUse) const; 748 749 // Materialize immediate after RA. 750 void materializeImmPostRA(MachineBasicBlock &MBB, 751 MachineBasicBlock::iterator MBBI, 752 const DebugLoc &DL, Register Reg, 753 int64_t Imm) const; 754 755 /// getRegNumForOperand - some operands use different numbering schemes 756 /// for the same registers. For example, a VSX instruction may have any of 757 /// vs0-vs63 allocated whereas an Altivec instruction could only have 758 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 759 /// register number needed for the opcode/operand number combination. 760 /// The operand number argument will be useful when we need to extend this 761 /// to instructions that use both Altivec and VSX numbering (for different 762 /// operands). 763 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 764 unsigned OpNo) { 765 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 766 switch (regClass) { 767 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 768 // VSX32-VSX63 during encoding/disassembling 769 case PPC::VSSRCRegClassID: 770 case PPC::VSFRCRegClassID: 771 if (isVFRegister(Reg)) 772 return PPC::VSX32 + (Reg - PPC::VF0); 773 break; 774 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 775 // VSX32-VSX63 during encoding/disassembling 776 case PPC::VSRCRegClassID: 777 if (isVRRegister(Reg)) 778 return PPC::VSX32 + (Reg - PPC::V0); 779 break; 780 // Other RegClass doesn't need mapping 781 default: 782 break; 783 } 784 return Reg; 785 } 786 787 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 788 bool isBDNZ(unsigned Opcode) const; 789 790 /// Find the hardware loop instruction used to set-up the specified loop. 791 /// On PPC, we have two instructions used to set-up the hardware loop 792 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 793 /// instructions to indicate the end of a loop. 794 MachineInstr * 795 findLoopInstr(MachineBasicBlock &PreHeader, 796 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 797 798 /// Analyze loop L, which must be a single-basic-block loop, and if the 799 /// conditions can be understood enough produce a PipelinerLoopInfo object. 800 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 801 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 802 }; 803 804 } 805 806 #endif 807