xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrHTM.td (revision 397e83df75e0fcd0d3fcb95ae4d794cb7600fc89) 
1//===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory  -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the Hardware Transactional Memory extension to the
10// PowerPC instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14
15
16def HasHTM : Predicate<"Subtarget->hasHTM()">;
17
18def HTM_get_imm : SDNodeXForm<imm, [{
19  return getI32Imm (N->getZExtValue(), SDLoc(N));
20}]>;
21
22let hasSideEffects = 1 in {
23def TCHECK_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins), "#TCHECK_RET", []>;
24def TBEGIN_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>;
25}
26
27
28let Predicates = [HasHTM] in {
29
30let Defs = [CR0] in {
31def TBEGIN : XForm_htm0 <31, 654,
32                         (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR>;
33
34def TEND : XForm_htm1 <31, 686,
35                       (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>;
36
37def TABORT : XForm_base_r3xo <31, 910,
38                              (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR,
39                              []>, isRecordForm {
40  let RST = 0;
41  let RB = 0;
42}
43
44def TABORTWC : XForm_base_r3xo <31, 782,
45                                (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
46                                "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
47                                isRecordForm;
48
49def TABORTWCI : XForm_base_r3xo <31, 846,
50                                 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
51                                 "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
52                                 isRecordForm;
53
54def TABORTDC : XForm_base_r3xo <31, 814,
55                                (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
56                                "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
57                                isRecordForm;
58
59def TABORTDCI : XForm_base_r3xo <31, 878,
60                                 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
61                                 "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
62                                 isRecordForm;
63
64def TSR : XForm_htm2 <31, 750,
65                      (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR>,
66                      isRecordForm;
67
68def TRECLAIM : XForm_base_r3xo <31, 942,
69                                (outs), (ins gprc:$RA), "treclaim. $RA",
70                                IIC_SprMTSPR, []>,
71                                isRecordForm {
72  let RST = 0;
73  let RB = 0;
74}
75
76def TRECHKPT : XForm_base_r3xo <31, 1006,
77                                (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>,
78                                isRecordForm {
79  let RST = 0;
80  let RA = 0;
81  let RB = 0;
82}
83
84}
85
86def TCHECK : XForm_htm3 <31, 718,
87                        (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR>;
88// Builtins
89
90// All HTM instructions, with the exception of tcheck, set CR0 with the
91// value of the MSR Transaction State (TS) bits that exist before the
92// instruction is executed.  For tbegin., the EQ bit in CR0 can be used
93// to determine whether the transaction was successfully started (0) or
94// failed (1).  We use an XORI pattern to 'flip' the bit to match the
95// tbegin builtin API which defines a return value of 1 as success.
96
97def : Pat<(int_ppc_tbegin i32:$R),
98           (XORI (TBEGIN_RET(HTM_get_imm imm:$R)), 1)>;
99
100def : Pat<(int_ppc_tend i32:$R),
101          (TEND (HTM_get_imm imm:$R))>;
102
103def : Pat<(int_ppc_tabort i32:$R),
104          (TABORT $R)>;
105
106def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107          (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
108
109def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
110          (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
111
112def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113          (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
114
115def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
116          (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
117
118def : Pat<(int_ppc_tcheck),
119          (TCHECK_RET)>;
120
121def : Pat<(int_ppc_treclaim i32:$RA),
122          (TRECLAIM $RA)>;
123
124def : Pat<(int_ppc_trechkpt),
125          (TRECHKPT)>;
126
127def : Pat<(int_ppc_tsr i32:$L),
128          (TSR (HTM_get_imm imm:$L))>;
129
130def : Pat<(int_ppc_get_texasr),
131          (MFSPR8 130)>;
132
133def : Pat<(int_ppc_get_texasru),
134          (MFSPR8 131)>;
135
136def : Pat<(int_ppc_get_tfhar),
137          (MFSPR8 128)>;
138
139def : Pat<(int_ppc_get_tfiar),
140          (MFSPR8 129)>;
141
142
143def : Pat<(int_ppc_set_texasr i64:$V),
144          (MTSPR8 130, $V)>;
145
146def : Pat<(int_ppc_set_texasru i64:$V),
147          (MTSPR8 131, $V)>;
148
149def : Pat<(int_ppc_set_tfhar i64:$V),
150          (MTSPR8 128, $V)>;
151
152def : Pat<(int_ppc_set_tfiar i64:$V),
153          (MTSPR8 129, $V)>;
154
155
156// Extended mnemonics
157def : Pat<(int_ppc_tendall),
158          (TEND 1)>;
159
160def : Pat<(int_ppc_tresume),
161          (TSR 1)>;
162
163def : Pat<(int_ppc_tsuspend),
164          (TSR 0)>;
165
166def : Pat<(i64 (int_ppc_ttest)),
167          (i64 (INSERT_SUBREG
168                (i64 (IMPLICIT_DEF)), (TABORTWCI 0, (LI 0), 0), sub_32))>;
169
170} // [HasHTM]
171
172def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;
173def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;
174def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
175def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;
176