1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{7} = XFormMemOp; 43 44 // Fields used for relation models. 45 string BaseName = ""; 46 47 // For cases where multiple instruction definitions really represent the 48 // same underlying instruction but with one definition for 64-bit arguments 49 // and one for 32-bit arguments, this bit breaks the degeneracy between 50 // the two forms and allows TableGen to generate mapping tables. 51 bit Interpretation64Bit = 0; 52} 53 54class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 55class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 56class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 57class PPC970_MicroCode; 58 59class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 60class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 61class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 62class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 63class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 64class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 65class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 66class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 67 68class XFormMemOp { bits<1> XFormMemOp = 1; } 69 70// Two joined instructions; used to emit two adjacent instructions as one. 71// The itinerary from the first instruction is used for scheduling and 72// classification. 73class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 74 InstrItinClass itin> 75 : Instruction { 76 field bits<64> Inst; 77 field bits<64> SoftFail = 0; 78 let Size = 8; 79 80 bit PPC64 = 0; // Default value, override with isPPC64 81 82 let Namespace = "PPC"; 83 let Inst{0-5} = opcode1; 84 let Inst{32-37} = opcode2; 85 let OutOperandList = OOL; 86 let InOperandList = IOL; 87 let AsmString = asmstr; 88 let Itinerary = itin; 89 90 bits<1> PPC970_First = 0; 91 bits<1> PPC970_Single = 0; 92 bits<1> PPC970_Cracked = 0; 93 bits<3> PPC970_Unit = 0; 94 95 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 96 /// these must be reflected there! See comments there for what these are. 97 let TSFlags{0} = PPC970_First; 98 let TSFlags{1} = PPC970_Single; 99 let TSFlags{2} = PPC970_Cracked; 100 let TSFlags{5-3} = PPC970_Unit; 101 102 // Fields used for relation models. 103 string BaseName = ""; 104 bit Interpretation64Bit = 0; 105} 106 107// Base class for all X-Form memory instructions 108class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 109 InstrItinClass itin> 110 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 111 112// 1.7.1 I-Form 113class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 114 InstrItinClass itin, list<dag> pattern> 115 : I<opcode, OOL, IOL, asmstr, itin> { 116 let Pattern = pattern; 117 bits<24> LI; 118 119 let Inst{6-29} = LI; 120 let Inst{30} = aa; 121 let Inst{31} = lk; 122} 123 124// 1.7.2 B-Form 125class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 128 bits<3> CR; 129 bits<14> BD; 130 131 bits<5> BI; 132 let BI{0-1} = BIBO{5-6}; 133 let BI{2-4} = CR{0-2}; 134 135 let Inst{6-10} = BIBO{4-0}; 136 let Inst{11-15} = BI; 137 let Inst{16-29} = BD; 138 let Inst{30} = aa; 139 let Inst{31} = lk; 140} 141 142class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 143 string asmstr> 144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 145 let BIBO{4-0} = bo; 146 let BIBO{6-5} = 0; 147 let CR = 0; 148} 149 150class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 151 dag OOL, dag IOL, string asmstr> 152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 153 bits<14> BD; 154 155 let Inst{6-10} = bo; 156 let Inst{11-15} = bi; 157 let Inst{16-29} = BD; 158 let Inst{30} = aa; 159 let Inst{31} = lk; 160} 161 162class BForm_3<bits<6> opcode, bit aa, bit lk, 163 dag OOL, dag IOL, string asmstr> 164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 165 bits<5> BO; 166 bits<5> BI; 167 bits<14> BD; 168 169 let Inst{6-10} = BO; 170 let Inst{11-15} = BI; 171 let Inst{16-29} = BD; 172 let Inst{30} = aa; 173 let Inst{31} = lk; 174} 175 176class BForm_3_at<bits<6> opcode, bit aa, bit lk, 177 dag OOL, dag IOL, string asmstr> 178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 179 bits<5> BO; 180 bits<2> at; 181 bits<5> BI; 182 bits<14> BD; 183 184 let Inst{6-8} = BO{4-2}; 185 let Inst{9-10} = at; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BI; 196 bits<14> BD; 197 198 let Inst{6-10} = bo; 199 let Inst{11-15} = BI; 200 let Inst{16-29} = BD; 201 let Inst{30} = aa; 202 let Inst{31} = lk; 203} 204 205// 1.7.3 SC-Form 206class SCForm<bits<6> opcode, bits<1> xo, 207 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 208 list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<7> LEV; 211 212 let Pattern = pattern; 213 214 let Inst{20-26} = LEV; 215 let Inst{30} = xo; 216} 217 218// 1.7.4 D-Form 219class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 220 InstrItinClass itin, list<dag> pattern> 221 : I<opcode, OOL, IOL, asmstr, itin> { 222 bits<5> A; 223 bits<5> B; 224 bits<16> C; 225 226 let Pattern = pattern; 227 228 let Inst{6-10} = A; 229 let Inst{11-15} = B; 230 let Inst{16-31} = C; 231} 232 233class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 234 InstrItinClass itin, list<dag> pattern> 235 : I<opcode, OOL, IOL, asmstr, itin> { 236 bits<5> A; 237 bits<21> Addr; 238 239 let Pattern = pattern; 240 241 let Inst{6-10} = A; 242 let Inst{11-15} = Addr{20-16}; // Base Reg 243 let Inst{16-31} = Addr{15-0}; // Displacement 244} 245 246class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 247 InstrItinClass itin, list<dag> pattern> 248 : I<opcode, OOL, IOL, asmstr, itin> { 249 bits<5> A; 250 bits<16> C; 251 bits<5> B; 252 253 let Pattern = pattern; 254 255 let Inst{6-10} = A; 256 let Inst{11-15} = B; 257 let Inst{16-31} = C; 258} 259 260 261class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 262 InstrItinClass itin, list<dag> pattern> 263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 264 265 // Even though ADDICo does not really have an RC bit, provide 266 // the declaration of one here so that isDOT has something to set. 267 bit RC = 0; 268} 269 270class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 271 InstrItinClass itin, list<dag> pattern> 272 : I<opcode, OOL, IOL, asmstr, itin> { 273 bits<5> A; 274 bits<16> B; 275 276 let Pattern = pattern; 277 278 let Inst{6-10} = A; 279 let Inst{11-15} = 0; 280 let Inst{16-31} = B; 281} 282 283class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 284 InstrItinClass itin, list<dag> pattern> 285 : I<opcode, OOL, IOL, asmstr, itin> { 286 bits<5> B; 287 bits<5> A; 288 bits<16> C; 289 290 let Pattern = pattern; 291 292 let Inst{6-10} = A; 293 let Inst{11-15} = B; 294 let Inst{16-31} = C; 295} 296 297class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 298 InstrItinClass itin, list<dag> pattern> 299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 300 let A = 0; 301 let Addr = 0; 302} 303 304class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 305 string asmstr, InstrItinClass itin, 306 list<dag> pattern> 307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 308 let A = R; 309 let B = R; 310 let C = 0; 311} 312 313class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 314 dag OOL, dag IOL, string asmstr, 315 InstrItinClass itin, list<dag> pattern> 316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 317 bits<5> A; 318 bits<21> Addr; 319 320 let Pattern = pattern; 321 bits<24> LI; 322 323 let Inst{6-29} = LI; 324 let Inst{30} = aa; 325 let Inst{31} = lk; 326 327 let Inst{38-42} = A; 328 let Inst{43-47} = Addr{20-16}; // Base Reg 329 let Inst{48-63} = Addr{15-0}; // Displacement 330} 331 332// This is used to emit BL8+NOP. 333class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 334 dag OOL, dag IOL, string asmstr, 335 InstrItinClass itin, list<dag> pattern> 336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 337 OOL, IOL, asmstr, itin, pattern> { 338 let A = 0; 339 let Addr = 0; 340} 341 342class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 343 InstrItinClass itin> 344 : I<opcode, OOL, IOL, asmstr, itin> { 345 bits<3> BF; 346 bits<1> L; 347 bits<5> RA; 348 bits<16> I; 349 350 let Inst{6-8} = BF; 351 let Inst{9} = 0; 352 let Inst{10} = L; 353 let Inst{11-15} = RA; 354 let Inst{16-31} = I; 355} 356 357class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 358 InstrItinClass itin> 359 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 360 let L = PPC64; 361} 362 363class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 364 InstrItinClass itin> 365 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 366 367class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 370 let L = PPC64; 371} 372 373 374// 1.7.5 DS-Form 375class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 376 InstrItinClass itin, list<dag> pattern> 377 : I<opcode, OOL, IOL, asmstr, itin> { 378 bits<5> RST; 379 bits<19> DS_RA; 380 381 let Pattern = pattern; 382 383 let Inst{6-10} = RST; 384 let Inst{11-15} = DS_RA{18-14}; // Register # 385 let Inst{16-29} = DS_RA{13-0}; // Displacement. 386 let Inst{30-31} = xo; 387} 388 389// ISA V3.0B 1.6.6 DX-Form 390class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 391 InstrItinClass itin, list<dag> pattern> 392 : I<opcode, OOL, IOL, asmstr, itin> { 393 bits<5> RT; 394 bits<16> D; 395 396 let Pattern = pattern; 397 398 let Inst{6-10} = RT; 399 let Inst{11-15} = D{5-1}; // d1 400 let Inst{16-25} = D{15-6}; // d0 401 let Inst{26-30} = xo; 402 let Inst{31} = D{0}; // d2 403} 404 405// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 406class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 407 string asmstr, InstrItinClass itin, list<dag> pattern> 408 : I<opcode, OOL, IOL, asmstr, itin> { 409 bits<6> XT; 410 bits<17> DS_RA; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = XT{4-0}; 415 let Inst{11-15} = DS_RA{16-12}; // Register # 416 let Inst{16-27} = DS_RA{11-0}; // Displacement. 417 let Inst{28} = XT{5}; 418 let Inst{29-31} = xo; 419} 420 421// 1.7.6 X-Form 422class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 423 InstrItinClass itin, list<dag> pattern> 424 : I<opcode, OOL, IOL, asmstr, itin> { 425 bits<5> RST; 426 bits<5> A; 427 bits<5> B; 428 429 let Pattern = pattern; 430 431 bit RC = 0; // set by isDOT 432 433 let Inst{6-10} = RST; 434 let Inst{11-15} = A; 435 let Inst{16-20} = B; 436 let Inst{21-30} = xo; 437 let Inst{31} = RC; 438} 439 440class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 441 string asmstr, InstrItinClass itin, 442 list<dag> pattern> 443 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 444 445class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 446 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 447 let RST = 0; 448} 449 450class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 451 InstrItinClass itin> 452 : I<opcode, OOL, IOL, asmstr, itin> { 453 let Inst{21-30} = xo; 454} 455 456// This is the same as XForm_base_r3xo, but the first two operands are swapped 457// when code is emitted. 458class XForm_base_r3xo_swapped 459 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 460 InstrItinClass itin> 461 : I<opcode, OOL, IOL, asmstr, itin> { 462 bits<5> A; 463 bits<5> RST; 464 bits<5> B; 465 466 bit RC = 0; // set by isDOT 467 468 let Inst{6-10} = RST; 469 let Inst{11-15} = A; 470 let Inst{16-20} = B; 471 let Inst{21-30} = xo; 472 let Inst{31} = RC; 473} 474 475 476class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 477 InstrItinClass itin, list<dag> pattern> 478 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 479 480class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 481 InstrItinClass itin, list<dag> pattern> 482 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 483 484class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 485 InstrItinClass itin, list<dag> pattern> 486 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 487 let RST = 0; 488} 489 490class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 491 InstrItinClass itin, list<dag> pattern> 492 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 493 let A = 0; 494 let B = 0; 495} 496 497class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 498 InstrItinClass itin, list<dag> pattern> 499 : I<opcode, OOL, IOL, asmstr, itin> { 500 bits<5> RST; 501 bits<5> A; 502 bits<1> WS; 503 504 let Pattern = pattern; 505 506 let Inst{6-10} = RST; 507 let Inst{11-15} = A; 508 let Inst{20} = WS; 509 let Inst{21-30} = xo; 510 let Inst{31} = 0; 511} 512 513class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 514 InstrItinClass itin, list<dag> pattern> 515 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 516 let Pattern = pattern; 517} 518 519class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 520 InstrItinClass itin, list<dag> pattern> 521 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 522 523class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin, list<dag> pattern> 525 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 526 527class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin, list<dag> pattern> 529 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 530 let Pattern = pattern; 531} 532 533class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin, list<dag> pattern> 535 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 536 let B = 0; 537 let Pattern = pattern; 538} 539 540class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 541 InstrItinClass itin> 542 : I<opcode, OOL, IOL, asmstr, itin> { 543 bits<3> BF; 544 bits<1> L; 545 bits<5> RA; 546 bits<5> RB; 547 548 let Inst{6-8} = BF; 549 let Inst{9} = 0; 550 let Inst{10} = L; 551 let Inst{11-15} = RA; 552 let Inst{16-20} = RB; 553 let Inst{21-30} = xo; 554 let Inst{31} = 0; 555} 556 557class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 558 InstrItinClass itin> 559 : I<opcode, OOL, IOL, asmstr, itin> { 560 bits<4> CT; 561 bits<5> RA; 562 bits<5> RB; 563 564 let Inst{6} = 0; 565 let Inst{7-10} = CT; 566 let Inst{11-15} = RA; 567 let Inst{16-20} = RB; 568 let Inst{21-30} = xo; 569 let Inst{31} = 0; 570} 571 572class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 573 InstrItinClass itin> 574 : I<opcode, OOL, IOL, asmstr, itin> { 575 bits<5> RS; 576 bits<4> SR; 577 578 let Inst{6-10} = RS; 579 let Inst{12-15} = SR; 580 let Inst{21-30} = xo; 581} 582 583class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 584 InstrItinClass itin> 585 : I<opcode, OOL, IOL, asmstr, itin> { 586 bits<5> MO; 587 588 let Inst{6-10} = MO; 589 let Inst{21-30} = xo; 590} 591 592class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 593 InstrItinClass itin> 594 : I<opcode, OOL, IOL, asmstr, itin> { 595 bits<5> RS; 596 bits<5> RB; 597 598 let Inst{6-10} = RS; 599 let Inst{16-20} = RB; 600 let Inst{21-30} = xo; 601} 602 603class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 604 InstrItinClass itin> 605 : I<opcode, OOL, IOL, asmstr, itin> { 606 bits<5> RS; 607 bits<1> L; 608 609 let Inst{6-10} = RS; 610 let Inst{15} = L; 611 let Inst{21-30} = xo; 612} 613 614class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 615 InstrItinClass itin> 616 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 617 let L = PPC64; 618} 619 620class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 621 InstrItinClass itin> 622 : I<opcode, OOL, IOL, asmstr, itin> { 623 bits<3> BF; 624 bits<5> FRA; 625 bits<5> FRB; 626 627 let Inst{6-8} = BF; 628 let Inst{9-10} = 0; 629 let Inst{11-15} = FRA; 630 let Inst{16-20} = FRB; 631 let Inst{21-30} = xo; 632 let Inst{31} = 0; 633} 634 635class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 636 InstrItinClass itin> 637 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 638 let FRA = 0; 639} 640 641// Used for QPX 642class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 643 InstrItinClass itin, list<dag> pattern> 644 : I<opcode, OOL, IOL, asmstr, itin> { 645 bits<5> FRT; 646 bits<5> FRA; 647 bits<5> FRB; 648 649 let Pattern = pattern; 650 651 let Inst{6-10} = FRT; 652 let Inst{11-15} = FRA; 653 let Inst{16-20} = FRB; 654 let Inst{21-30} = xo; 655 let Inst{31} = 0; 656} 657 658class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 659 InstrItinClass itin, list<dag> pattern> 660 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 661 let FRA = 0; 662} 663 664class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 665 InstrItinClass itin, list<dag> pattern> 666 : I<opcode, OOL, IOL, asmstr, itin> { 667 bits<5> FRT; 668 bits<5> FRA; 669 bits<5> FRB; 670 bits<4> tttt; 671 672 let Pattern = pattern; 673 674 let Inst{6-10} = FRT; 675 let Inst{11-15} = FRA; 676 let Inst{16-20} = FRB; 677 let Inst{21-24} = tttt; 678 let Inst{25-30} = xo; 679 let Inst{31} = 0; 680} 681 682class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 683 InstrItinClass itin, list<dag> pattern> 684 : I<opcode, OOL, IOL, asmstr, itin> { 685 let Pattern = pattern; 686 let Inst{6-10} = 31; 687 let Inst{11-15} = 0; 688 let Inst{16-20} = 0; 689 let Inst{21-30} = xo; 690 let Inst{31} = 0; 691} 692 693class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 694 string asmstr, InstrItinClass itin, list<dag> pattern> 695 : I<opcode, OOL, IOL, asmstr, itin> { 696 bits<2> L; 697 698 let Pattern = pattern; 699 let Inst{6-8} = 0; 700 let Inst{9-10} = L; 701 let Inst{11-15} = 0; 702 let Inst{16-20} = 0; 703 let Inst{21-30} = xo; 704 let Inst{31} = 0; 705} 706 707class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 708 string asmstr, InstrItinClass itin, list<dag> pattern> 709 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 710 let L = 0; 711} 712 713class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 714 InstrItinClass itin, list<dag> pattern> 715 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 716} 717 718class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 719 string asmstr, InstrItinClass itin, list<dag> pattern> 720 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 721} 722 723// [PO RT /// RB XO RC] 724class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 725 InstrItinClass itin, list<dag> pattern> 726 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 727 let A = 0; 728} 729 730class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 731 string asmstr, InstrItinClass itin, list<dag> pattern> 732 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 733} 734 735class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 736 InstrItinClass itin, list<dag> pattern> 737 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 738} 739 740// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 741// numbers presumably relates to some document, but I haven't found it. 742class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 743 InstrItinClass itin, list<dag> pattern> 744 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 745 let Pattern = pattern; 746 747 bit RC = 0; // set by isDOT 748 749 let Inst{6-10} = RST; 750 let Inst{11-20} = 0; 751 let Inst{21-30} = xo; 752 let Inst{31} = RC; 753} 754class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 755 InstrItinClass itin, list<dag> pattern> 756 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 757 let Pattern = pattern; 758 bits<5> FM; 759 760 bit RC = 0; // set by isDOT 761 762 let Inst{6-10} = FM; 763 let Inst{11-20} = 0; 764 let Inst{21-30} = xo; 765 let Inst{31} = RC; 766} 767 768class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 769 InstrItinClass itin> 770 : I<opcode, OOL, IOL, asmstr, itin> { 771 bits<5> RT; 772 bits<3> BFA; 773 774 let Inst{6-10} = RT; 775 let Inst{11-13} = BFA; 776 let Inst{14-15} = 0; 777 let Inst{16-20} = 0; 778 let Inst{21-30} = xo; 779 let Inst{31} = 0; 780} 781 782class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 783 InstrItinClass itin> 784 : I<opcode, OOL, IOL, asmstr, itin> { 785 bits<5> RT; 786 bits<2> L; 787 788 let Inst{6-10} = RT; 789 let Inst{11-13} = 0; 790 let Inst{14-15} = L; 791 let Inst{16-20} = 0; 792 let Inst{21-30} = xo; 793 let Inst{31} = 0; 794} 795 796class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 797 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 798 list<dag> pattern> 799 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 800 let Pattern = pattern; 801 802 let Inst{6-10} = RST; 803 let Inst{11-12} = xo1; 804 let Inst{13-15} = xo2; 805 let Inst{16-20} = 0; 806 let Inst{21-30} = xo; 807 let Inst{31} = 0; 808} 809 810class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 811 bits<10> xo, dag OOL, dag IOL, string asmstr, 812 InstrItinClass itin, list<dag> pattern> 813 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 814 let Pattern = pattern; 815 bits<5> FRB; 816 817 let Inst{6-10} = RST; 818 let Inst{11-12} = xo1; 819 let Inst{13-15} = xo2; 820 let Inst{16-20} = FRB; 821 let Inst{21-30} = xo; 822 let Inst{31} = 0; 823} 824 825class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 826 bits<10> xo, dag OOL, dag IOL, string asmstr, 827 InstrItinClass itin, list<dag> pattern> 828 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 829 let Pattern = pattern; 830 bits<3> DRM; 831 832 let Inst{6-10} = RST; 833 let Inst{11-12} = xo1; 834 let Inst{13-15} = xo2; 835 let Inst{16-17} = 0; 836 let Inst{18-20} = DRM; 837 let Inst{21-30} = xo; 838 let Inst{31} = 0; 839} 840 841class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 842 bits<10> xo, dag OOL, dag IOL, string asmstr, 843 InstrItinClass itin, list<dag> pattern> 844 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 845 let Pattern = pattern; 846 bits<2> RM; 847 848 let Inst{6-10} = RST; 849 let Inst{11-12} = xo1; 850 let Inst{13-15} = xo2; 851 let Inst{16-18} = 0; 852 let Inst{19-20} = RM; 853 let Inst{21-30} = xo; 854 let Inst{31} = 0; 855} 856 857 858class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 859 InstrItinClass itin, list<dag> pattern> 860 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 861 let RST = 0; 862 let A = 0; 863 let B = 0; 864} 865 866class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 867 InstrItinClass itin, list<dag> pattern> 868 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 869 let RST = 0; 870 let A = 0; 871} 872 873class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 874 string asmstr, InstrItinClass itin, list<dag> pattern> 875 : I<opcode, OOL, IOL, asmstr, itin> { 876 bit R; 877 878 bit RC = 1; 879 880 let Inst{6-9} = 0; 881 let Inst{10} = R; 882 let Inst{11-20} = 0; 883 let Inst{21-30} = xo; 884 let Inst{31} = RC; 885} 886 887class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 888 string asmstr, InstrItinClass itin, list<dag> pattern> 889 : I<opcode, OOL, IOL, asmstr, itin> { 890 bit A; 891 892 bit RC = 1; 893 894 let Inst{6} = A; 895 let Inst{7-20} = 0; 896 let Inst{21-30} = xo; 897 let Inst{31} = RC; 898} 899 900class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 901 InstrItinClass itin, list<dag> pattern> 902 : I<opcode, OOL, IOL, asmstr, itin> { 903 bit L; 904 905 bit RC = 0; // set by isDOT 906 907 let Inst{7-9} = 0; 908 let Inst{10} = L; 909 let Inst{11-20} = 0; 910 let Inst{21-30} = xo; 911 let Inst{31} = RC; 912} 913 914class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 915 InstrItinClass itin, list<dag> pattern> 916 : I<opcode, OOL, IOL, asmstr, itin> { 917 bits<3> BF; 918 919 bit RC = 0; 920 921 let Inst{6-8} = BF; 922 let Inst{9-20} = 0; 923 let Inst{21-30} = xo; 924 let Inst{31} = RC; 925} 926 927// [PO RT RA RB XO /] 928class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 929 string asmstr, InstrItinClass itin, list<dag> pattern> 930 : I<opcode, OOL, IOL, asmstr, itin> { 931 bits<3> BF; 932 bits<1> L; 933 bits<5> RA; 934 bits<5> RB; 935 936 let Pattern = pattern; 937 938 let Inst{6-8} = BF; 939 let Inst{9} = 0; 940 let Inst{10} = L; 941 let Inst{11-15} = RA; 942 let Inst{16-20} = RB; 943 let Inst{21-30} = xo; 944 let Inst{31} = 0; 945} 946 947// Same as XForm_17 but with GPR's and new naming convention 948class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 949 string asmstr, InstrItinClass itin, list<dag> pattern> 950 : I<opcode, OOL, IOL, asmstr, itin> { 951 bits<3> BF; 952 bits<5> RA; 953 bits<5> RB; 954 955 let Pattern = pattern; 956 957 let Inst{6-8} = BF; 958 let Inst{9-10} = 0; 959 let Inst{11-15} = RA; 960 let Inst{16-20} = RB; 961 let Inst{21-30} = xo; 962 let Inst{31} = 0; 963} 964 965// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 966class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 967 string asmstr, InstrItinClass itin, list<dag> pattern> 968 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 969 let A = xo2; 970} 971 972class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 973 string asmstr, InstrItinClass itin, list<dag> pattern> 974 : I<opcode, OOL, IOL, asmstr, itin> { 975 bits<3> BF; 976 bits<7> DCMX; 977 bits<5> VB; 978 979 let Pattern = pattern; 980 981 let Inst{6-8} = BF; 982 let Inst{9-15} = DCMX; 983 let Inst{16-20} = VB; 984 let Inst{21-30} = xo; 985 let Inst{31} = 0; 986} 987 988class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 989 string asmstr, InstrItinClass itin, list<dag> pattern> 990 : I<opcode, OOL, IOL, asmstr, itin> { 991 bits<6> XT; 992 bits<8> IMM8; 993 994 let Pattern = pattern; 995 996 let Inst{6-10} = XT{4-0}; 997 let Inst{11-12} = 0; 998 let Inst{13-20} = IMM8; 999 let Inst{21-30} = xo; 1000 let Inst{31} = XT{5}; 1001} 1002 1003// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1004// to specify an SDAG pattern for matching. 1005class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1006 string asmstr, InstrItinClass itin> 1007 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1008} 1009 1010class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1011 InstrItinClass itin> 1012 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1013 let FRA = 0; 1014 let FRB = 0; 1015} 1016 1017// [PO /// L RA RB XO /] 1018class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1019 string asmstr, InstrItinClass itin, list<dag> pattern> 1020 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1021 let BF = 0; 1022 let Pattern = pattern; 1023 1024 bit RC = 0; 1025 let Inst{31} = RC; 1026} 1027 1028// XX*-Form (VSX) 1029class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1030 InstrItinClass itin, list<dag> pattern> 1031 : I<opcode, OOL, IOL, asmstr, itin> { 1032 bits<6> XT; 1033 bits<5> A; 1034 bits<5> B; 1035 1036 let Pattern = pattern; 1037 1038 let Inst{6-10} = XT{4-0}; 1039 let Inst{11-15} = A; 1040 let Inst{16-20} = B; 1041 let Inst{21-30} = xo; 1042 let Inst{31} = XT{5}; 1043} 1044 1045class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1046 string asmstr, InstrItinClass itin, list<dag> pattern> 1047 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1048 1049class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1050 string asmstr, InstrItinClass itin, list<dag> pattern> 1051 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1052 let B = 0; 1053} 1054 1055class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1056 InstrItinClass itin, list<dag> pattern> 1057 : I<opcode, OOL, IOL, asmstr, itin> { 1058 bits<6> XT; 1059 bits<6> XB; 1060 1061 let Pattern = pattern; 1062 1063 let Inst{6-10} = XT{4-0}; 1064 let Inst{11-15} = 0; 1065 let Inst{16-20} = XB{4-0}; 1066 let Inst{21-29} = xo; 1067 let Inst{30} = XB{5}; 1068 let Inst{31} = XT{5}; 1069} 1070 1071class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1072 InstrItinClass itin, list<dag> pattern> 1073 : I<opcode, OOL, IOL, asmstr, itin> { 1074 bits<3> CR; 1075 bits<6> XB; 1076 1077 let Pattern = pattern; 1078 1079 let Inst{6-8} = CR; 1080 let Inst{9-15} = 0; 1081 let Inst{16-20} = XB{4-0}; 1082 let Inst{21-29} = xo; 1083 let Inst{30} = XB{5}; 1084 let Inst{31} = 0; 1085} 1086 1087class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1088 InstrItinClass itin, list<dag> pattern> 1089 : I<opcode, OOL, IOL, asmstr, itin> { 1090 bits<6> XT; 1091 bits<6> XB; 1092 bits<2> D; 1093 1094 let Pattern = pattern; 1095 1096 let Inst{6-10} = XT{4-0}; 1097 let Inst{11-13} = 0; 1098 let Inst{14-15} = D; 1099 let Inst{16-20} = XB{4-0}; 1100 let Inst{21-29} = xo; 1101 let Inst{30} = XB{5}; 1102 let Inst{31} = XT{5}; 1103} 1104 1105class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1106 string asmstr, InstrItinClass itin, list<dag> pattern> 1107 : I<opcode, OOL, IOL, asmstr, itin> { 1108 bits<6> XT; 1109 bits<6> XB; 1110 bits<5> UIM5; 1111 1112 let Pattern = pattern; 1113 1114 let Inst{6-10} = XT{4-0}; 1115 let Inst{11-15} = UIM5; 1116 let Inst{16-20} = XB{4-0}; 1117 let Inst{21-29} = xo; 1118 let Inst{30} = XB{5}; 1119 let Inst{31} = XT{5}; 1120} 1121 1122// [PO T XO B XO BX /] 1123class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1124 string asmstr, InstrItinClass itin, list<dag> pattern> 1125 : I<opcode, OOL, IOL, asmstr, itin> { 1126 bits<5> RT; 1127 bits<6> XB; 1128 1129 let Pattern = pattern; 1130 1131 let Inst{6-10} = RT; 1132 let Inst{11-15} = xo2; 1133 let Inst{16-20} = XB{4-0}; 1134 let Inst{21-29} = xo; 1135 let Inst{30} = XB{5}; 1136 let Inst{31} = 0; 1137} 1138 1139// [PO T XO B XO BX TX] 1140class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1141 string asmstr, InstrItinClass itin, list<dag> pattern> 1142 : I<opcode, OOL, IOL, asmstr, itin> { 1143 bits<6> XT; 1144 bits<6> XB; 1145 1146 let Pattern = pattern; 1147 1148 let Inst{6-10} = XT{4-0}; 1149 let Inst{11-15} = xo2; 1150 let Inst{16-20} = XB{4-0}; 1151 let Inst{21-29} = xo; 1152 let Inst{30} = XB{5}; 1153 let Inst{31} = XT{5}; 1154} 1155 1156class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1157 string asmstr, InstrItinClass itin, list<dag> pattern> 1158 : I<opcode, OOL, IOL, asmstr, itin> { 1159 bits<3> BF; 1160 bits<7> DCMX; 1161 bits<6> XB; 1162 1163 let Pattern = pattern; 1164 1165 let Inst{6-8} = BF; 1166 let Inst{9-15} = DCMX; 1167 let Inst{16-20} = XB{4-0}; 1168 let Inst{21-29} = xo; 1169 let Inst{30} = XB{5}; 1170 let Inst{31} = 0; 1171} 1172 1173class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1174 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1175 list<dag> pattern> 1176 : I<opcode, OOL, IOL, asmstr, itin> { 1177 bits<6> XT; 1178 bits<7> DCMX; 1179 bits<6> XB; 1180 1181 let Pattern = pattern; 1182 1183 let Inst{6-10} = XT{4-0}; 1184 let Inst{11-15} = DCMX{4-0}; 1185 let Inst{16-20} = XB{4-0}; 1186 let Inst{21-24} = xo1; 1187 let Inst{25} = DCMX{6}; 1188 let Inst{26-28} = xo2; 1189 let Inst{29} = DCMX{5}; 1190 let Inst{30} = XB{5}; 1191 let Inst{31} = XT{5}; 1192} 1193 1194class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1195 InstrItinClass itin, list<dag> pattern> 1196 : I<opcode, OOL, IOL, asmstr, itin> { 1197 bits<6> XT; 1198 bits<6> XA; 1199 bits<6> XB; 1200 1201 let Pattern = pattern; 1202 1203 let Inst{6-10} = XT{4-0}; 1204 let Inst{11-15} = XA{4-0}; 1205 let Inst{16-20} = XB{4-0}; 1206 let Inst{21-28} = xo; 1207 let Inst{29} = XA{5}; 1208 let Inst{30} = XB{5}; 1209 let Inst{31} = XT{5}; 1210} 1211 1212class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1213 InstrItinClass itin, list<dag> pattern> 1214 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1215 let XA = XT; 1216 let XB = XT; 1217} 1218 1219class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1220 InstrItinClass itin, list<dag> pattern> 1221 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1222 let XB = XT; 1223 let XA = XT; 1224} 1225 1226class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1227 InstrItinClass itin, list<dag> pattern> 1228 : I<opcode, OOL, IOL, asmstr, itin> { 1229 bits<3> CR; 1230 bits<6> XA; 1231 bits<6> XB; 1232 1233 let Pattern = pattern; 1234 1235 let Inst{6-8} = CR; 1236 let Inst{9-10} = 0; 1237 let Inst{11-15} = XA{4-0}; 1238 let Inst{16-20} = XB{4-0}; 1239 let Inst{21-28} = xo; 1240 let Inst{29} = XA{5}; 1241 let Inst{30} = XB{5}; 1242 let Inst{31} = 0; 1243} 1244 1245class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1246 InstrItinClass itin, list<dag> pattern> 1247 : I<opcode, OOL, IOL, asmstr, itin> { 1248 bits<6> XT; 1249 bits<6> XA; 1250 bits<6> XB; 1251 bits<2> D; 1252 1253 let Pattern = pattern; 1254 1255 let Inst{6-10} = XT{4-0}; 1256 let Inst{11-15} = XA{4-0}; 1257 let Inst{16-20} = XB{4-0}; 1258 let Inst{21} = 0; 1259 let Inst{22-23} = D; 1260 let Inst{24-28} = xo; 1261 let Inst{29} = XA{5}; 1262 let Inst{30} = XB{5}; 1263 let Inst{31} = XT{5}; 1264} 1265 1266class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1267 InstrItinClass itin, list<dag> pattern> 1268 : I<opcode, OOL, IOL, asmstr, itin> { 1269 bits<6> XT; 1270 bits<6> XA; 1271 bits<6> XB; 1272 1273 let Pattern = pattern; 1274 1275 bit RC = 0; // set by isDOT 1276 1277 let Inst{6-10} = XT{4-0}; 1278 let Inst{11-15} = XA{4-0}; 1279 let Inst{16-20} = XB{4-0}; 1280 let Inst{21} = RC; 1281 let Inst{22-28} = xo; 1282 let Inst{29} = XA{5}; 1283 let Inst{30} = XB{5}; 1284 let Inst{31} = XT{5}; 1285} 1286 1287class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1288 InstrItinClass itin, list<dag> pattern> 1289 : I<opcode, OOL, IOL, asmstr, itin> { 1290 bits<6> XT; 1291 bits<6> XA; 1292 bits<6> XB; 1293 bits<6> XC; 1294 1295 let Pattern = pattern; 1296 1297 let Inst{6-10} = XT{4-0}; 1298 let Inst{11-15} = XA{4-0}; 1299 let Inst{16-20} = XB{4-0}; 1300 let Inst{21-25} = XC{4-0}; 1301 let Inst{26-27} = xo; 1302 let Inst{28} = XC{5}; 1303 let Inst{29} = XA{5}; 1304 let Inst{30} = XB{5}; 1305 let Inst{31} = XT{5}; 1306} 1307 1308// DCB_Form - Form X instruction, used for dcb* instructions. 1309class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1310 InstrItinClass itin, list<dag> pattern> 1311 : I<31, OOL, IOL, asmstr, itin> { 1312 bits<5> A; 1313 bits<5> B; 1314 1315 let Pattern = pattern; 1316 1317 let Inst{6-10} = immfield; 1318 let Inst{11-15} = A; 1319 let Inst{16-20} = B; 1320 let Inst{21-30} = xo; 1321 let Inst{31} = 0; 1322} 1323 1324class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1325 InstrItinClass itin, list<dag> pattern> 1326 : I<31, OOL, IOL, asmstr, itin> { 1327 bits<5> TH; 1328 bits<5> A; 1329 bits<5> B; 1330 1331 let Pattern = pattern; 1332 1333 let Inst{6-10} = TH; 1334 let Inst{11-15} = A; 1335 let Inst{16-20} = B; 1336 let Inst{21-30} = xo; 1337 let Inst{31} = 0; 1338} 1339 1340// DSS_Form - Form X instruction, used for altivec dss* instructions. 1341class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1342 InstrItinClass itin, list<dag> pattern> 1343 : I<31, OOL, IOL, asmstr, itin> { 1344 bits<2> STRM; 1345 bits<5> A; 1346 bits<5> B; 1347 1348 let Pattern = pattern; 1349 1350 let Inst{6} = T; 1351 let Inst{7-8} = 0; 1352 let Inst{9-10} = STRM; 1353 let Inst{11-15} = A; 1354 let Inst{16-20} = B; 1355 let Inst{21-30} = xo; 1356 let Inst{31} = 0; 1357} 1358 1359// 1.7.7 XL-Form 1360class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1361 InstrItinClass itin, list<dag> pattern> 1362 : I<opcode, OOL, IOL, asmstr, itin> { 1363 bits<5> CRD; 1364 bits<5> CRA; 1365 bits<5> CRB; 1366 1367 let Pattern = pattern; 1368 1369 let Inst{6-10} = CRD; 1370 let Inst{11-15} = CRA; 1371 let Inst{16-20} = CRB; 1372 let Inst{21-30} = xo; 1373 let Inst{31} = 0; 1374} 1375 1376class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1377 InstrItinClass itin, list<dag> pattern> 1378 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1379 let CRD = 0; 1380 let CRA = 0; 1381 let CRB = 0; 1382} 1383 1384class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1385 InstrItinClass itin, list<dag> pattern> 1386 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1387 bits<5> RT; 1388 bits<5> RB; 1389 1390 let CRD = RT; 1391 let CRA = 0; 1392 let CRB = RB; 1393} 1394 1395class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1396 InstrItinClass itin, list<dag> pattern> 1397 : I<opcode, OOL, IOL, asmstr, itin> { 1398 bits<5> CRD; 1399 1400 let Pattern = pattern; 1401 1402 let Inst{6-10} = CRD; 1403 let Inst{11-15} = CRD; 1404 let Inst{16-20} = CRD; 1405 let Inst{21-30} = xo; 1406 let Inst{31} = 0; 1407} 1408 1409class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1410 InstrItinClass itin, list<dag> pattern> 1411 : I<opcode, OOL, IOL, asmstr, itin> { 1412 bits<5> BO; 1413 bits<5> BI; 1414 bits<2> BH; 1415 1416 let Pattern = pattern; 1417 1418 let Inst{6-10} = BO; 1419 let Inst{11-15} = BI; 1420 let Inst{16-18} = 0; 1421 let Inst{19-20} = BH; 1422 let Inst{21-30} = xo; 1423 let Inst{31} = lk; 1424} 1425 1426class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1427 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1428 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1429 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1430 bits<3> CR; 1431 1432 let BO = BIBO{4-0}; 1433 let BI{0-1} = BIBO{5-6}; 1434 let BI{2-4} = CR{0-2}; 1435 let BH = 0; 1436} 1437 1438class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1439 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1440 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1441 let BO = bo; 1442 let BH = 0; 1443} 1444 1445class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1446 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1447 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1448 let BO = bo; 1449 let BI = bi; 1450 let BH = 0; 1451} 1452 1453class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1454 InstrItinClass itin> 1455 : I<opcode, OOL, IOL, asmstr, itin> { 1456 bits<3> BF; 1457 bits<3> BFA; 1458 1459 let Inst{6-8} = BF; 1460 let Inst{9-10} = 0; 1461 let Inst{11-13} = BFA; 1462 let Inst{14-15} = 0; 1463 let Inst{16-20} = 0; 1464 let Inst{21-30} = xo; 1465 let Inst{31} = 0; 1466} 1467 1468class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1469 InstrItinClass itin> 1470 : I<opcode, OOL, IOL, asmstr, itin> { 1471 bits<3> BF; 1472 bit W; 1473 bits<4> U; 1474 1475 bit RC = 0; 1476 1477 let Inst{6-8} = BF; 1478 let Inst{9-10} = 0; 1479 let Inst{11-14} = 0; 1480 let Inst{15} = W; 1481 let Inst{16-19} = U; 1482 let Inst{20} = 0; 1483 let Inst{21-30} = xo; 1484 let Inst{31} = RC; 1485} 1486 1487class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1488 InstrItinClass itin, list<dag> pattern> 1489 : I<opcode, OOL, IOL, asmstr, itin> { 1490 bits<1> S; 1491 1492 let Pattern = pattern; 1493 1494 let Inst{6-19} = 0; 1495 let Inst{20} = S; 1496 let Inst{21-30} = xo; 1497 let Inst{31} = 0; 1498} 1499 1500class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1501 bits<6> opcode2, bits<2> xo2, 1502 dag OOL, dag IOL, string asmstr, 1503 InstrItinClass itin, list<dag> pattern> 1504 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1505 bits<5> BO; 1506 bits<5> BI; 1507 bits<2> BH; 1508 1509 bits<5> RST; 1510 bits<19> DS_RA; 1511 1512 let Pattern = pattern; 1513 1514 let Inst{6-10} = BO; 1515 let Inst{11-15} = BI; 1516 let Inst{16-18} = 0; 1517 let Inst{19-20} = BH; 1518 let Inst{21-30} = xo1; 1519 let Inst{31} = lk; 1520 1521 let Inst{38-42} = RST; 1522 let Inst{43-47} = DS_RA{18-14}; // Register # 1523 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1524 let Inst{62-63} = xo2; 1525} 1526 1527class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1528 bits<5> bo, bits<5> bi, bit lk, 1529 bits<6> opcode2, bits<2> xo2, 1530 dag OOL, dag IOL, string asmstr, 1531 InstrItinClass itin, list<dag> pattern> 1532 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1533 OOL, IOL, asmstr, itin, pattern> { 1534 let BO = bo; 1535 let BI = bi; 1536 let BH = 0; 1537} 1538 1539// 1.7.8 XFX-Form 1540class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1541 InstrItinClass itin> 1542 : I<opcode, OOL, IOL, asmstr, itin> { 1543 bits<5> RT; 1544 bits<10> SPR; 1545 1546 let Inst{6-10} = RT; 1547 let Inst{11} = SPR{4}; 1548 let Inst{12} = SPR{3}; 1549 let Inst{13} = SPR{2}; 1550 let Inst{14} = SPR{1}; 1551 let Inst{15} = SPR{0}; 1552 let Inst{16} = SPR{9}; 1553 let Inst{17} = SPR{8}; 1554 let Inst{18} = SPR{7}; 1555 let Inst{19} = SPR{6}; 1556 let Inst{20} = SPR{5}; 1557 let Inst{21-30} = xo; 1558 let Inst{31} = 0; 1559} 1560 1561class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1562 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1563 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1564 let SPR = spr; 1565} 1566 1567class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1568 InstrItinClass itin> 1569 : I<opcode, OOL, IOL, asmstr, itin> { 1570 bits<5> RT; 1571 1572 let Inst{6-10} = RT; 1573 let Inst{11-20} = 0; 1574 let Inst{21-30} = xo; 1575 let Inst{31} = 0; 1576} 1577 1578class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1579 InstrItinClass itin, list<dag> pattern> 1580 : I<opcode, OOL, IOL, asmstr, itin> { 1581 bits<5> RT; 1582 bits<10> Entry; 1583 let Pattern = pattern; 1584 1585 let Inst{6-10} = RT; 1586 let Inst{11-20} = Entry; 1587 let Inst{21-30} = xo; 1588 let Inst{31} = 0; 1589} 1590 1591class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1592 InstrItinClass itin> 1593 : I<opcode, OOL, IOL, asmstr, itin> { 1594 bits<8> FXM; 1595 bits<5> rS; 1596 1597 let Inst{6-10} = rS; 1598 let Inst{11} = 0; 1599 let Inst{12-19} = FXM; 1600 let Inst{20} = 0; 1601 let Inst{21-30} = xo; 1602 let Inst{31} = 0; 1603} 1604 1605class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1606 InstrItinClass itin> 1607 : I<opcode, OOL, IOL, asmstr, itin> { 1608 bits<5> ST; 1609 bits<8> FXM; 1610 1611 let Inst{6-10} = ST; 1612 let Inst{11} = 1; 1613 let Inst{12-19} = FXM; 1614 let Inst{20} = 0; 1615 let Inst{21-30} = xo; 1616 let Inst{31} = 0; 1617} 1618 1619class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1620 InstrItinClass itin> 1621 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1622 1623class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1624 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1625 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1626 let SPR = spr; 1627} 1628 1629// XFL-Form - MTFSF 1630// This is probably 1.7.9, but I don't have the reference that uses this 1631// numbering scheme... 1632class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1633 InstrItinClass itin, list<dag>pattern> 1634 : I<opcode, OOL, IOL, asmstr, itin> { 1635 bits<8> FM; 1636 bits<5> rT; 1637 1638 bit RC = 0; // set by isDOT 1639 let Pattern = pattern; 1640 1641 let Inst{6} = 0; 1642 let Inst{7-14} = FM; 1643 let Inst{15} = 0; 1644 let Inst{16-20} = rT; 1645 let Inst{21-30} = xo; 1646 let Inst{31} = RC; 1647} 1648 1649class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1650 InstrItinClass itin, list<dag>pattern> 1651 : I<opcode, OOL, IOL, asmstr, itin> { 1652 bit L; 1653 bits<8> FLM; 1654 bit W; 1655 bits<5> FRB; 1656 1657 bit RC = 0; // set by isDOT 1658 let Pattern = pattern; 1659 1660 let Inst{6} = L; 1661 let Inst{7-14} = FLM; 1662 let Inst{15} = W; 1663 let Inst{16-20} = FRB; 1664 let Inst{21-30} = xo; 1665 let Inst{31} = RC; 1666} 1667 1668// 1.7.10 XS-Form - SRADI. 1669class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1670 InstrItinClass itin, list<dag> pattern> 1671 : I<opcode, OOL, IOL, asmstr, itin> { 1672 bits<5> A; 1673 bits<5> RS; 1674 bits<6> SH; 1675 1676 bit RC = 0; // set by isDOT 1677 let Pattern = pattern; 1678 1679 let Inst{6-10} = RS; 1680 let Inst{11-15} = A; 1681 let Inst{16-20} = SH{4,3,2,1,0}; 1682 let Inst{21-29} = xo; 1683 let Inst{30} = SH{5}; 1684 let Inst{31} = RC; 1685} 1686 1687// 1.7.11 XO-Form 1688class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1689 InstrItinClass itin, list<dag> pattern> 1690 : I<opcode, OOL, IOL, asmstr, itin> { 1691 bits<5> RT; 1692 bits<5> RA; 1693 bits<5> RB; 1694 1695 let Pattern = pattern; 1696 1697 bit RC = 0; // set by isDOT 1698 1699 let Inst{6-10} = RT; 1700 let Inst{11-15} = RA; 1701 let Inst{16-20} = RB; 1702 let Inst{21} = oe; 1703 let Inst{22-30} = xo; 1704 let Inst{31} = RC; 1705} 1706 1707class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1708 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1709 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1710 let RB = 0; 1711} 1712 1713// 1.7.12 A-Form 1714class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1715 InstrItinClass itin, list<dag> pattern> 1716 : I<opcode, OOL, IOL, asmstr, itin> { 1717 bits<5> FRT; 1718 bits<5> FRA; 1719 bits<5> FRC; 1720 bits<5> FRB; 1721 1722 let Pattern = pattern; 1723 1724 bit RC = 0; // set by isDOT 1725 1726 let Inst{6-10} = FRT; 1727 let Inst{11-15} = FRA; 1728 let Inst{16-20} = FRB; 1729 let Inst{21-25} = FRC; 1730 let Inst{26-30} = xo; 1731 let Inst{31} = RC; 1732} 1733 1734class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1735 InstrItinClass itin, list<dag> pattern> 1736 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1737 let FRC = 0; 1738} 1739 1740class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1741 InstrItinClass itin, list<dag> pattern> 1742 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1743 let FRB = 0; 1744} 1745 1746class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1747 InstrItinClass itin, list<dag> pattern> 1748 : I<opcode, OOL, IOL, asmstr, itin> { 1749 bits<5> RT; 1750 bits<5> RA; 1751 bits<5> RB; 1752 bits<5> COND; 1753 1754 let Pattern = pattern; 1755 1756 let Inst{6-10} = RT; 1757 let Inst{11-15} = RA; 1758 let Inst{16-20} = RB; 1759 let Inst{21-25} = COND; 1760 let Inst{26-30} = xo; 1761 let Inst{31} = 0; 1762} 1763 1764// Used for QPX 1765class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1766 InstrItinClass itin, list<dag> pattern> 1767 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1768 let FRA = 0; 1769 let FRC = 0; 1770} 1771 1772// 1.7.13 M-Form 1773class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1774 InstrItinClass itin, list<dag> pattern> 1775 : I<opcode, OOL, IOL, asmstr, itin> { 1776 bits<5> RA; 1777 bits<5> RS; 1778 bits<5> RB; 1779 bits<5> MB; 1780 bits<5> ME; 1781 1782 let Pattern = pattern; 1783 1784 bit RC = 0; // set by isDOT 1785 1786 let Inst{6-10} = RS; 1787 let Inst{11-15} = RA; 1788 let Inst{16-20} = RB; 1789 let Inst{21-25} = MB; 1790 let Inst{26-30} = ME; 1791 let Inst{31} = RC; 1792} 1793 1794class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1795 InstrItinClass itin, list<dag> pattern> 1796 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1797} 1798 1799// 1.7.14 MD-Form 1800class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1801 InstrItinClass itin, list<dag> pattern> 1802 : I<opcode, OOL, IOL, asmstr, itin> { 1803 bits<5> RA; 1804 bits<5> RS; 1805 bits<6> SH; 1806 bits<6> MBE; 1807 1808 let Pattern = pattern; 1809 1810 bit RC = 0; // set by isDOT 1811 1812 let Inst{6-10} = RS; 1813 let Inst{11-15} = RA; 1814 let Inst{16-20} = SH{4,3,2,1,0}; 1815 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1816 let Inst{27-29} = xo; 1817 let Inst{30} = SH{5}; 1818 let Inst{31} = RC; 1819} 1820 1821class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1822 InstrItinClass itin, list<dag> pattern> 1823 : I<opcode, OOL, IOL, asmstr, itin> { 1824 bits<5> RA; 1825 bits<5> RS; 1826 bits<5> RB; 1827 bits<6> MBE; 1828 1829 let Pattern = pattern; 1830 1831 bit RC = 0; // set by isDOT 1832 1833 let Inst{6-10} = RS; 1834 let Inst{11-15} = RA; 1835 let Inst{16-20} = RB; 1836 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1837 let Inst{27-30} = xo; 1838 let Inst{31} = RC; 1839} 1840 1841 1842// E-1 VA-Form 1843 1844// VAForm_1 - DACB ordering. 1845class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1846 InstrItinClass itin, list<dag> pattern> 1847 : I<4, OOL, IOL, asmstr, itin> { 1848 bits<5> VD; 1849 bits<5> VA; 1850 bits<5> VC; 1851 bits<5> VB; 1852 1853 let Pattern = pattern; 1854 1855 let Inst{6-10} = VD; 1856 let Inst{11-15} = VA; 1857 let Inst{16-20} = VB; 1858 let Inst{21-25} = VC; 1859 let Inst{26-31} = xo; 1860} 1861 1862// VAForm_1a - DABC ordering. 1863class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1864 InstrItinClass itin, list<dag> pattern> 1865 : I<4, OOL, IOL, asmstr, itin> { 1866 bits<5> VD; 1867 bits<5> VA; 1868 bits<5> VB; 1869 bits<5> VC; 1870 1871 let Pattern = pattern; 1872 1873 let Inst{6-10} = VD; 1874 let Inst{11-15} = VA; 1875 let Inst{16-20} = VB; 1876 let Inst{21-25} = VC; 1877 let Inst{26-31} = xo; 1878} 1879 1880class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1881 InstrItinClass itin, list<dag> pattern> 1882 : I<4, OOL, IOL, asmstr, itin> { 1883 bits<5> VD; 1884 bits<5> VA; 1885 bits<5> VB; 1886 bits<4> SH; 1887 1888 let Pattern = pattern; 1889 1890 let Inst{6-10} = VD; 1891 let Inst{11-15} = VA; 1892 let Inst{16-20} = VB; 1893 let Inst{21} = 0; 1894 let Inst{22-25} = SH; 1895 let Inst{26-31} = xo; 1896} 1897 1898// E-2 VX-Form 1899class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1900 InstrItinClass itin, list<dag> pattern> 1901 : I<4, OOL, IOL, asmstr, itin> { 1902 bits<5> VD; 1903 bits<5> VA; 1904 bits<5> VB; 1905 1906 let Pattern = pattern; 1907 1908 let Inst{6-10} = VD; 1909 let Inst{11-15} = VA; 1910 let Inst{16-20} = VB; 1911 let Inst{21-31} = xo; 1912} 1913 1914class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1915 InstrItinClass itin, list<dag> pattern> 1916 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1917 let VA = VD; 1918 let VB = VD; 1919} 1920 1921 1922class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1923 InstrItinClass itin, list<dag> pattern> 1924 : I<4, OOL, IOL, asmstr, itin> { 1925 bits<5> VD; 1926 bits<5> VB; 1927 1928 let Pattern = pattern; 1929 1930 let Inst{6-10} = VD; 1931 let Inst{11-15} = 0; 1932 let Inst{16-20} = VB; 1933 let Inst{21-31} = xo; 1934} 1935 1936class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1937 InstrItinClass itin, list<dag> pattern> 1938 : I<4, OOL, IOL, asmstr, itin> { 1939 bits<5> VD; 1940 bits<5> IMM; 1941 1942 let Pattern = pattern; 1943 1944 let Inst{6-10} = VD; 1945 let Inst{11-15} = IMM; 1946 let Inst{16-20} = 0; 1947 let Inst{21-31} = xo; 1948} 1949 1950/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1951class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1952 InstrItinClass itin, list<dag> pattern> 1953 : I<4, OOL, IOL, asmstr, itin> { 1954 bits<5> VD; 1955 1956 let Pattern = pattern; 1957 1958 let Inst{6-10} = VD; 1959 let Inst{11-15} = 0; 1960 let Inst{16-20} = 0; 1961 let Inst{21-31} = xo; 1962} 1963 1964/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1965class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1966 InstrItinClass itin, list<dag> pattern> 1967 : I<4, OOL, IOL, asmstr, itin> { 1968 bits<5> VB; 1969 1970 let Pattern = pattern; 1971 1972 let Inst{6-10} = 0; 1973 let Inst{11-15} = 0; 1974 let Inst{16-20} = VB; 1975 let Inst{21-31} = xo; 1976} 1977 1978// e.g. [PO VRT EO VRB XO] 1979class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1980 string asmstr, InstrItinClass itin, list<dag> pattern> 1981 : I<4, OOL, IOL, asmstr, itin> { 1982 bits<5> RD; 1983 bits<5> VB; 1984 1985 let Pattern = pattern; 1986 1987 let Inst{6-10} = RD; 1988 let Inst{11-15} = eo; 1989 let Inst{16-20} = VB; 1990 let Inst{21-31} = xo; 1991} 1992 1993/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 1994class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 1995 InstrItinClass itin, list<dag> pattern> 1996 : I<4, OOL, IOL, asmstr, itin> { 1997 bits<5> VD; 1998 bits<5> VA; 1999 bits<1> ST; 2000 bits<4> SIX; 2001 2002 let Pattern = pattern; 2003 2004 let Inst{6-10} = VD; 2005 let Inst{11-15} = VA; 2006 let Inst{16} = ST; 2007 let Inst{17-20} = SIX; 2008 let Inst{21-31} = xo; 2009} 2010 2011/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2012class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2013 InstrItinClass itin, list<dag> pattern> 2014 : I<4, OOL, IOL, asmstr, itin> { 2015 bits<5> VD; 2016 bits<5> VA; 2017 2018 let Pattern = pattern; 2019 2020 let Inst{6-10} = VD; 2021 let Inst{11-15} = VA; 2022 let Inst{16-20} = 0; 2023 let Inst{21-31} = xo; 2024} 2025 2026// E-4 VXR-Form 2027class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2028 InstrItinClass itin, list<dag> pattern> 2029 : I<4, OOL, IOL, asmstr, itin> { 2030 bits<5> VD; 2031 bits<5> VA; 2032 bits<5> VB; 2033 bit RC = 0; 2034 2035 let Pattern = pattern; 2036 2037 let Inst{6-10} = VD; 2038 let Inst{11-15} = VA; 2039 let Inst{16-20} = VB; 2040 let Inst{21} = RC; 2041 let Inst{22-31} = xo; 2042} 2043 2044// VX-Form: [PO VRT EO VRB 1 PS XO] 2045class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2046 dag OOL, dag IOL, string asmstr, 2047 InstrItinClass itin, list<dag> pattern> 2048 : I<4, OOL, IOL, asmstr, itin> { 2049 bits<5> VD; 2050 bits<5> VB; 2051 bit PS; 2052 2053 let Pattern = pattern; 2054 2055 let Inst{6-10} = VD; 2056 let Inst{11-15} = eo; 2057 let Inst{16-20} = VB; 2058 let Inst{21} = 1; 2059 let Inst{22} = PS; 2060 let Inst{23-31} = xo; 2061} 2062 2063// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2064class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2065 InstrItinClass itin, list<dag> pattern> 2066 : I<4, OOL, IOL, asmstr, itin> { 2067 bits<5> VD; 2068 bits<5> VA; 2069 bits<5> VB; 2070 bit PS; 2071 2072 let Pattern = pattern; 2073 2074 let Inst{6-10} = VD; 2075 let Inst{11-15} = VA; 2076 let Inst{16-20} = VB; 2077 let Inst{21} = 1; 2078 let Inst{22} = PS; 2079 let Inst{23-31} = xo; 2080} 2081 2082// Z23-Form (used by QPX) 2083class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2084 InstrItinClass itin, list<dag> pattern> 2085 : I<opcode, OOL, IOL, asmstr, itin> { 2086 bits<5> FRT; 2087 bits<5> FRA; 2088 bits<5> FRB; 2089 bits<2> idx; 2090 2091 let Pattern = pattern; 2092 2093 bit RC = 0; // set by isDOT 2094 2095 let Inst{6-10} = FRT; 2096 let Inst{11-15} = FRA; 2097 let Inst{16-20} = FRB; 2098 let Inst{21-22} = idx; 2099 let Inst{23-30} = xo; 2100 let Inst{31} = RC; 2101} 2102 2103class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2104 InstrItinClass itin, list<dag> pattern> 2105 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 2106 let FRB = 0; 2107} 2108 2109class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2110 InstrItinClass itin, list<dag> pattern> 2111 : I<opcode, OOL, IOL, asmstr, itin> { 2112 bits<5> FRT; 2113 bits<12> idx; 2114 2115 let Pattern = pattern; 2116 2117 bit RC = 0; // set by isDOT 2118 2119 let Inst{6-10} = FRT; 2120 let Inst{11-22} = idx; 2121 let Inst{23-30} = xo; 2122 let Inst{31} = RC; 2123} 2124 2125class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2126 InstrItinClass itin, list<dag> pattern> 2127 : I<opcode, OOL, IOL, asmstr, itin> { 2128 bits<5> VRT; 2129 bit R; 2130 bits<5> VRB; 2131 bits<2> idx; 2132 2133 let Pattern = pattern; 2134 2135 bit RC = 0; // set by isDOT 2136 2137 let Inst{6-10} = VRT; 2138 let Inst{11-14} = 0; 2139 let Inst{15} = R; 2140 let Inst{16-20} = VRB; 2141 let Inst{21-22} = idx; 2142 let Inst{23-30} = xo; 2143 let Inst{31} = RC; 2144} 2145 2146//===----------------------------------------------------------------------===// 2147// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2148// stuff 2149class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2150 : I<0, OOL, IOL, asmstr, NoItinerary> { 2151 let isCodeGenOnly = 1; 2152 let PPC64 = 0; 2153 let Pattern = pattern; 2154 let Inst{31-0} = 0; 2155 let hasNoSchedulingInfo = 1; 2156} 2157 2158// Instruction that require custom insertion support 2159// a.k.a. ISelPseudos, however, these won't have isPseudo set 2160class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2161 list<dag> pattern> 2162 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2163 let usesCustomInserter = 1; 2164} 2165 2166// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2167// files is set only for PostRAPseudo 2168class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2169 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2170 let isPseudo = 1; 2171} 2172 2173class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2174 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2175 2176