1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Fields used for relation models. 49 string BaseName = ""; 50 51 // For cases where multiple instruction definitions really represent the 52 // same underlying instruction but with one definition for 64-bit arguments 53 // and one for 32-bit arguments, this bit breaks the degeneracy between 54 // the two forms and allows TableGen to generate mapping tables. 55 bit Interpretation64Bit = 0; 56} 57 58class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 59class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 60class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 61class PPC970_MicroCode; 62 63class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 64class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 65class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 66class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 67class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 68class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 69class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 70class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 71 72class XFormMemOp { bits<1> XFormMemOp = 1; } 73 74// Two joined instructions; used to emit two adjacent instructions as one. 75// The itinerary from the first instruction is used for scheduling and 76// classification. 77class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 78 InstrItinClass itin> 79 : Instruction { 80 field bits<64> Inst; 81 field bits<64> SoftFail = 0; 82 let Size = 8; 83 84 bit PPC64 = 0; // Default value, override with isPPC64 85 86 let Namespace = "PPC"; 87 let Inst{0-5} = opcode1; 88 let Inst{32-37} = opcode2; 89 let OutOperandList = OOL; 90 let InOperandList = IOL; 91 let AsmString = asmstr; 92 let Itinerary = itin; 93 94 bits<1> PPC970_First = 0; 95 bits<1> PPC970_Single = 0; 96 bits<1> PPC970_Cracked = 0; 97 bits<3> PPC970_Unit = 0; 98 99 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 100 /// these must be reflected there! See comments there for what these are. 101 let TSFlags{0} = PPC970_First; 102 let TSFlags{1} = PPC970_Single; 103 let TSFlags{2} = PPC970_Cracked; 104 let TSFlags{5-3} = PPC970_Unit; 105 106 // Fields used for relation models. 107 string BaseName = ""; 108 bit Interpretation64Bit = 0; 109} 110 111// Base class for all X-Form memory instructions 112class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 113 InstrItinClass itin> 114 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 115 116// 1.7.1 I-Form 117class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 118 InstrItinClass itin, list<dag> pattern> 119 : I<opcode, OOL, IOL, asmstr, itin> { 120 let Pattern = pattern; 121 bits<24> LI; 122 123 let Inst{6-29} = LI; 124 let Inst{30} = aa; 125 let Inst{31} = lk; 126} 127 128// 1.7.2 B-Form 129class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 130 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 131 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 132 bits<3> CR; 133 bits<14> BD; 134 135 bits<5> BI; 136 let BI{0-1} = BIBO{5-6}; 137 let BI{2-4} = CR{0-2}; 138 139 let Inst{6-10} = BIBO{4-0}; 140 let Inst{11-15} = BI; 141 let Inst{16-29} = BD; 142 let Inst{30} = aa; 143 let Inst{31} = lk; 144} 145 146class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 147 string asmstr> 148 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 149 let BIBO{4-0} = bo; 150 let BIBO{6-5} = 0; 151 let CR = 0; 152} 153 154class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 155 dag OOL, dag IOL, string asmstr> 156 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 157 bits<14> BD; 158 159 let Inst{6-10} = bo; 160 let Inst{11-15} = bi; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_3<bits<6> opcode, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BO; 170 bits<5> BI; 171 bits<14> BD; 172 173 let Inst{6-10} = BO; 174 let Inst{11-15} = BI; 175 let Inst{16-29} = BD; 176 let Inst{30} = aa; 177 let Inst{31} = lk; 178} 179 180class BForm_3_at<bits<6> opcode, bit aa, bit lk, 181 dag OOL, dag IOL, string asmstr> 182 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 183 bits<5> BO; 184 bits<2> at; 185 bits<5> BI; 186 bits<14> BD; 187 188 let Inst{6-8} = BO{4-2}; 189 let Inst{9-10} = at; 190 let Inst{11-15} = BI; 191 let Inst{16-29} = BD; 192 let Inst{30} = aa; 193 let Inst{31} = lk; 194} 195 196class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 197 dag OOL, dag IOL, string asmstr> 198 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 199 bits<5> BI; 200 bits<14> BD; 201 202 let Inst{6-10} = bo; 203 let Inst{11-15} = BI; 204 let Inst{16-29} = BD; 205 let Inst{30} = aa; 206 let Inst{31} = lk; 207} 208 209// 1.7.3 SC-Form 210class SCForm<bits<6> opcode, bits<1> xo, 211 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 212 list<dag> pattern> 213 : I<opcode, OOL, IOL, asmstr, itin> { 214 bits<7> LEV; 215 216 let Pattern = pattern; 217 218 let Inst{20-26} = LEV; 219 let Inst{30} = xo; 220} 221 222// 1.7.4 D-Form 223class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 224 InstrItinClass itin, list<dag> pattern> 225 : I<opcode, OOL, IOL, asmstr, itin> { 226 bits<5> A; 227 bits<5> B; 228 bits<16> C; 229 230 let Pattern = pattern; 231 232 let Inst{6-10} = A; 233 let Inst{11-15} = B; 234 let Inst{16-31} = C; 235} 236 237class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 238 InstrItinClass itin, list<dag> pattern> 239 : I<opcode, OOL, IOL, asmstr, itin> { 240 bits<5> A; 241 bits<21> Addr; 242 243 let Pattern = pattern; 244 245 let Inst{6-10} = A; 246 let Inst{11-15} = Addr{20-16}; // Base Reg 247 let Inst{16-31} = Addr{15-0}; // Displacement 248} 249 250class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 251 InstrItinClass itin, list<dag> pattern> 252 : I<opcode, OOL, IOL, asmstr, itin> { 253 bits<5> A; 254 bits<16> C; 255 bits<5> B; 256 257 let Pattern = pattern; 258 259 let Inst{6-10} = A; 260 let Inst{11-15} = B; 261 let Inst{16-31} = C; 262} 263 264 265class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 266 InstrItinClass itin, list<dag> pattern> 267 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 268 269 // Even though ADDIC_rec does not really have an RC bit, provide 270 // the declaration of one here so that isRecordForm has something to set. 271 bit RC = 0; 272} 273 274class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 275 InstrItinClass itin, list<dag> pattern> 276 : I<opcode, OOL, IOL, asmstr, itin> { 277 bits<5> A; 278 bits<16> B; 279 280 let Pattern = pattern; 281 282 let Inst{6-10} = A; 283 let Inst{11-15} = 0; 284 let Inst{16-31} = B; 285} 286 287class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 288 InstrItinClass itin, list<dag> pattern> 289 : I<opcode, OOL, IOL, asmstr, itin> { 290 bits<5> B; 291 bits<5> A; 292 bits<16> C; 293 294 let Pattern = pattern; 295 296 let Inst{6-10} = A; 297 let Inst{11-15} = B; 298 let Inst{16-31} = C; 299} 300 301class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 302 InstrItinClass itin, list<dag> pattern> 303 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 304 let A = 0; 305 let Addr = 0; 306} 307 308class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 309 string asmstr, InstrItinClass itin, 310 list<dag> pattern> 311 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 312 let A = R; 313 let B = R; 314 let C = 0; 315} 316 317class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 318 dag OOL, dag IOL, string asmstr, 319 InstrItinClass itin, list<dag> pattern> 320 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 321 bits<5> A; 322 bits<21> Addr; 323 324 let Pattern = pattern; 325 bits<24> LI; 326 327 let Inst{6-29} = LI; 328 let Inst{30} = aa; 329 let Inst{31} = lk; 330 331 let Inst{38-42} = A; 332 let Inst{43-47} = Addr{20-16}; // Base Reg 333 let Inst{48-63} = Addr{15-0}; // Displacement 334} 335 336// This is used to emit BL8+NOP. 337class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 338 dag OOL, dag IOL, string asmstr, 339 InstrItinClass itin, list<dag> pattern> 340 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 341 OOL, IOL, asmstr, itin, pattern> { 342 let A = 0; 343 let Addr = 0; 344} 345 346class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 347 InstrItinClass itin> 348 : I<opcode, OOL, IOL, asmstr, itin> { 349 bits<3> BF; 350 bits<1> L; 351 bits<5> RA; 352 bits<16> I; 353 354 let Inst{6-8} = BF; 355 let Inst{9} = 0; 356 let Inst{10} = L; 357 let Inst{11-15} = RA; 358 let Inst{16-31} = I; 359} 360 361class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 362 InstrItinClass itin> 363 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 364 let L = PPC64; 365} 366 367class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 370 371class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 372 InstrItinClass itin> 373 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 374 let L = PPC64; 375} 376 377 378// 1.7.5 DS-Form 379class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 380 InstrItinClass itin, list<dag> pattern> 381 : I<opcode, OOL, IOL, asmstr, itin> { 382 bits<5> RST; 383 bits<19> DS_RA; 384 385 let Pattern = pattern; 386 387 let Inst{6-10} = RST; 388 let Inst{11-15} = DS_RA{18-14}; // Register # 389 let Inst{16-29} = DS_RA{13-0}; // Displacement. 390 let Inst{30-31} = xo; 391} 392 393// ISA V3.0B 1.6.6 DX-Form 394class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 395 InstrItinClass itin, list<dag> pattern> 396 : I<opcode, OOL, IOL, asmstr, itin> { 397 bits<5> RT; 398 bits<16> D; 399 400 let Pattern = pattern; 401 402 let Inst{6-10} = RT; 403 let Inst{11-15} = D{5-1}; // d1 404 let Inst{16-25} = D{15-6}; // d0 405 let Inst{26-30} = xo; 406 let Inst{31} = D{0}; // d2 407} 408 409// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 410class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 411 string asmstr, InstrItinClass itin, list<dag> pattern> 412 : I<opcode, OOL, IOL, asmstr, itin> { 413 bits<6> XT; 414 bits<17> DS_RA; 415 416 let Pattern = pattern; 417 418 let Inst{6-10} = XT{4-0}; 419 let Inst{11-15} = DS_RA{16-12}; // Register # 420 let Inst{16-27} = DS_RA{11-0}; // Displacement. 421 let Inst{28} = XT{5}; 422 let Inst{29-31} = xo; 423} 424 425// 1.7.6 X-Form 426class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 427 InstrItinClass itin, list<dag> pattern> 428 : I<opcode, OOL, IOL, asmstr, itin> { 429 bits<5> RST; 430 bits<5> A; 431 bits<5> B; 432 433 let Pattern = pattern; 434 435 bit RC = 0; // set by isRecordForm 436 437 let Inst{6-10} = RST; 438 let Inst{11-15} = A; 439 let Inst{16-20} = B; 440 let Inst{21-30} = xo; 441 let Inst{31} = RC; 442} 443 444class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 445 string asmstr, InstrItinClass itin, 446 list<dag> pattern> 447 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 448 449class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 450 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 451 let RST = 0; 452} 453 454class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 455 InstrItinClass itin> 456 : I<opcode, OOL, IOL, asmstr, itin> { 457 let Inst{21-30} = xo; 458} 459 460// This is the same as XForm_base_r3xo, but the first two operands are swapped 461// when code is emitted. 462class XForm_base_r3xo_swapped 463 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 464 InstrItinClass itin> 465 : I<opcode, OOL, IOL, asmstr, itin> { 466 bits<5> A; 467 bits<5> RST; 468 bits<5> B; 469 470 bit RC = 0; // set by isRecordForm 471 472 let Inst{6-10} = RST; 473 let Inst{11-15} = A; 474 let Inst{16-20} = B; 475 let Inst{21-30} = xo; 476 let Inst{31} = RC; 477} 478 479 480class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 481 InstrItinClass itin, list<dag> pattern> 482 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 483 484class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 485 InstrItinClass itin, list<dag> pattern> 486 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 487 488class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 489 InstrItinClass itin, list<dag> pattern> 490 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 491 let RST = 0; 492} 493 494class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 495 InstrItinClass itin, list<dag> pattern> 496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 497 let A = 0; 498 let B = 0; 499} 500 501class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 502 InstrItinClass itin, list<dag> pattern> 503 : I<opcode, OOL, IOL, asmstr, itin> { 504 bits<5> RST; 505 bits<5> A; 506 bits<1> WS; 507 508 let Pattern = pattern; 509 510 let Inst{6-10} = RST; 511 let Inst{11-15} = A; 512 let Inst{20} = WS; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 518 InstrItinClass itin, list<dag> pattern> 519 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 520 let Pattern = pattern; 521} 522 523class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin, list<dag> pattern> 525 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 526 527class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin, list<dag> pattern> 529 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 530 531class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 532 InstrItinClass itin, list<dag> pattern> 533 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 534 let Pattern = pattern; 535} 536 537class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin, list<dag> pattern> 539 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 540 let B = 0; 541 let Pattern = pattern; 542} 543 544class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin> 546 : I<opcode, OOL, IOL, asmstr, itin> { 547 bits<3> BF; 548 bits<1> L; 549 bits<5> RA; 550 bits<5> RB; 551 552 let Inst{6-8} = BF; 553 let Inst{9} = 0; 554 let Inst{10} = L; 555 let Inst{11-15} = RA; 556 let Inst{16-20} = RB; 557 let Inst{21-30} = xo; 558 let Inst{31} = 0; 559} 560 561class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 562 InstrItinClass itin> 563 : I<opcode, OOL, IOL, asmstr, itin> { 564 bits<4> CT; 565 bits<5> RA; 566 bits<5> RB; 567 568 let Inst{6} = 0; 569 let Inst{7-10} = CT; 570 let Inst{11-15} = RA; 571 let Inst{16-20} = RB; 572 let Inst{21-30} = xo; 573 let Inst{31} = 0; 574} 575 576class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 577 InstrItinClass itin> 578 : I<opcode, OOL, IOL, asmstr, itin> { 579 bits<5> RS; 580 bits<4> SR; 581 582 let Inst{6-10} = RS; 583 let Inst{12-15} = SR; 584 let Inst{21-30} = xo; 585} 586 587class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 588 InstrItinClass itin> 589 : I<opcode, OOL, IOL, asmstr, itin> { 590 bits<5> MO; 591 592 let Inst{6-10} = MO; 593 let Inst{21-30} = xo; 594} 595 596class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 597 InstrItinClass itin> 598 : I<opcode, OOL, IOL, asmstr, itin> { 599 bits<5> RS; 600 bits<5> RB; 601 602 let Inst{6-10} = RS; 603 let Inst{16-20} = RB; 604 let Inst{21-30} = xo; 605} 606 607class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 608 InstrItinClass itin> 609 : I<opcode, OOL, IOL, asmstr, itin> { 610 bits<5> RS; 611 bits<1> L; 612 613 let Inst{6-10} = RS; 614 let Inst{15} = L; 615 let Inst{21-30} = xo; 616} 617 618class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 619 InstrItinClass itin> 620 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 621 let L = PPC64; 622} 623 624class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 625 InstrItinClass itin> 626 : I<opcode, OOL, IOL, asmstr, itin> { 627 bits<3> BF; 628 bits<5> FRA; 629 bits<5> FRB; 630 631 let Inst{6-8} = BF; 632 let Inst{9-10} = 0; 633 let Inst{11-15} = FRA; 634 let Inst{16-20} = FRB; 635 let Inst{21-30} = xo; 636 let Inst{31} = 0; 637} 638 639class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 640 InstrItinClass itin> 641 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 642 let FRA = 0; 643} 644 645// Used for QPX 646class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 647 InstrItinClass itin, list<dag> pattern> 648 : I<opcode, OOL, IOL, asmstr, itin> { 649 bits<5> FRT; 650 bits<5> FRA; 651 bits<5> FRB; 652 653 let Pattern = pattern; 654 655 let Inst{6-10} = FRT; 656 let Inst{11-15} = FRA; 657 let Inst{16-20} = FRB; 658 let Inst{21-30} = xo; 659 let Inst{31} = 0; 660} 661 662class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 663 InstrItinClass itin, list<dag> pattern> 664 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 665 let FRA = 0; 666} 667 668class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 669 InstrItinClass itin, list<dag> pattern> 670 : I<opcode, OOL, IOL, asmstr, itin> { 671 bits<5> FRT; 672 bits<5> FRA; 673 bits<5> FRB; 674 bits<4> tttt; 675 676 let Pattern = pattern; 677 678 let Inst{6-10} = FRT; 679 let Inst{11-15} = FRA; 680 let Inst{16-20} = FRB; 681 let Inst{21-24} = tttt; 682 let Inst{25-30} = xo; 683 let Inst{31} = 0; 684} 685 686class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 687 InstrItinClass itin, list<dag> pattern> 688 : I<opcode, OOL, IOL, asmstr, itin> { 689 let Pattern = pattern; 690 let Inst{6-10} = 31; 691 let Inst{11-15} = 0; 692 let Inst{16-20} = 0; 693 let Inst{21-30} = xo; 694 let Inst{31} = 0; 695} 696 697class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 698 string asmstr, InstrItinClass itin, list<dag> pattern> 699 : I<opcode, OOL, IOL, asmstr, itin> { 700 bits<2> L; 701 702 let Pattern = pattern; 703 let Inst{6-8} = 0; 704 let Inst{9-10} = L; 705 let Inst{11-15} = 0; 706 let Inst{16-20} = 0; 707 let Inst{21-30} = xo; 708 let Inst{31} = 0; 709} 710 711class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 712 string asmstr, InstrItinClass itin, list<dag> pattern> 713 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 714 let L = 0; 715} 716 717class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 718 InstrItinClass itin, list<dag> pattern> 719 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 720} 721 722class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 723 string asmstr, InstrItinClass itin, list<dag> pattern> 724 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 725} 726 727// [PO RT /// RB XO RC] 728class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 729 InstrItinClass itin, list<dag> pattern> 730 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 731 let A = 0; 732} 733 734class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 735 string asmstr, InstrItinClass itin, list<dag> pattern> 736 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 737} 738 739class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 740 InstrItinClass itin, list<dag> pattern> 741 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 742} 743 744// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 745// numbers presumably relates to some document, but I haven't found it. 746class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 747 InstrItinClass itin, list<dag> pattern> 748 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 749 let Pattern = pattern; 750 751 bit RC = 0; // set by isRecordForm 752 753 let Inst{6-10} = RST; 754 let Inst{11-20} = 0; 755 let Inst{21-30} = xo; 756 let Inst{31} = RC; 757} 758class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 759 InstrItinClass itin, list<dag> pattern> 760 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 761 let Pattern = pattern; 762 bits<5> FM; 763 764 bit RC = 0; // set by isRecordForm 765 766 let Inst{6-10} = FM; 767 let Inst{11-20} = 0; 768 let Inst{21-30} = xo; 769 let Inst{31} = RC; 770} 771 772class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 773 InstrItinClass itin> 774 : I<opcode, OOL, IOL, asmstr, itin> { 775 bits<5> RT; 776 bits<3> BFA; 777 778 let Inst{6-10} = RT; 779 let Inst{11-13} = BFA; 780 let Inst{14-15} = 0; 781 let Inst{16-20} = 0; 782 let Inst{21-30} = xo; 783 let Inst{31} = 0; 784} 785 786class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 787 InstrItinClass itin> 788 : I<opcode, OOL, IOL, asmstr, itin> { 789 bits<5> RT; 790 bits<2> L; 791 792 let Inst{6-10} = RT; 793 let Inst{11-13} = 0; 794 let Inst{14-15} = L; 795 let Inst{16-20} = 0; 796 let Inst{21-30} = xo; 797 let Inst{31} = 0; 798} 799 800class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 801 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 802 list<dag> pattern> 803 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 804 let Pattern = pattern; 805 806 let Inst{6-10} = RST; 807 let Inst{11-12} = xo1; 808 let Inst{13-15} = xo2; 809 let Inst{16-20} = 0; 810 let Inst{21-30} = xo; 811 let Inst{31} = 0; 812} 813 814class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 815 bits<10> xo, dag OOL, dag IOL, string asmstr, 816 InstrItinClass itin, list<dag> pattern> 817 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 818 let Pattern = pattern; 819 bits<5> FRB; 820 821 let Inst{6-10} = RST; 822 let Inst{11-12} = xo1; 823 let Inst{13-15} = xo2; 824 let Inst{16-20} = FRB; 825 let Inst{21-30} = xo; 826 let Inst{31} = 0; 827} 828 829class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 830 bits<10> xo, dag OOL, dag IOL, string asmstr, 831 InstrItinClass itin, list<dag> pattern> 832 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 833 let Pattern = pattern; 834 bits<3> DRM; 835 836 let Inst{6-10} = RST; 837 let Inst{11-12} = xo1; 838 let Inst{13-15} = xo2; 839 let Inst{16-17} = 0; 840 let Inst{18-20} = DRM; 841 let Inst{21-30} = xo; 842 let Inst{31} = 0; 843} 844 845class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 846 bits<10> xo, dag OOL, dag IOL, string asmstr, 847 InstrItinClass itin, list<dag> pattern> 848 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 849 let Pattern = pattern; 850 bits<2> RM; 851 852 let Inst{6-10} = RST; 853 let Inst{11-12} = xo1; 854 let Inst{13-15} = xo2; 855 let Inst{16-18} = 0; 856 let Inst{19-20} = RM; 857 let Inst{21-30} = xo; 858 let Inst{31} = 0; 859} 860 861 862class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 863 InstrItinClass itin, list<dag> pattern> 864 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 865 let RST = 0; 866 let A = 0; 867 let B = 0; 868} 869 870class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 871 InstrItinClass itin, list<dag> pattern> 872 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 873 let RST = 0; 874 let A = 0; 875} 876 877class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 878 string asmstr, InstrItinClass itin, list<dag> pattern> 879 : I<opcode, OOL, IOL, asmstr, itin> { 880 bit R; 881 882 bit RC = 1; 883 884 let Inst{6-9} = 0; 885 let Inst{10} = R; 886 let Inst{11-20} = 0; 887 let Inst{21-30} = xo; 888 let Inst{31} = RC; 889} 890 891class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 892 string asmstr, InstrItinClass itin, list<dag> pattern> 893 : I<opcode, OOL, IOL, asmstr, itin> { 894 bit A; 895 896 bit RC = 1; 897 898 let Inst{6} = A; 899 let Inst{7-20} = 0; 900 let Inst{21-30} = xo; 901 let Inst{31} = RC; 902} 903 904class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 905 InstrItinClass itin, list<dag> pattern> 906 : I<opcode, OOL, IOL, asmstr, itin> { 907 bit L; 908 909 bit RC = 0; // set by isRecordForm 910 911 let Inst{7-9} = 0; 912 let Inst{10} = L; 913 let Inst{11-20} = 0; 914 let Inst{21-30} = xo; 915 let Inst{31} = RC; 916} 917 918class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 919 InstrItinClass itin, list<dag> pattern> 920 : I<opcode, OOL, IOL, asmstr, itin> { 921 bits<3> BF; 922 923 bit RC = 0; 924 925 let Inst{6-8} = BF; 926 let Inst{9-20} = 0; 927 let Inst{21-30} = xo; 928 let Inst{31} = RC; 929} 930 931// [PO RT RA RB XO /] 932class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 933 string asmstr, InstrItinClass itin, list<dag> pattern> 934 : I<opcode, OOL, IOL, asmstr, itin> { 935 bits<3> BF; 936 bits<1> L; 937 bits<5> RA; 938 bits<5> RB; 939 940 let Pattern = pattern; 941 942 let Inst{6-8} = BF; 943 let Inst{9} = 0; 944 let Inst{10} = L; 945 let Inst{11-15} = RA; 946 let Inst{16-20} = RB; 947 let Inst{21-30} = xo; 948 let Inst{31} = 0; 949} 950 951// Same as XForm_17 but with GPR's and new naming convention 952class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 953 string asmstr, InstrItinClass itin, list<dag> pattern> 954 : I<opcode, OOL, IOL, asmstr, itin> { 955 bits<3> BF; 956 bits<5> RA; 957 bits<5> RB; 958 959 let Pattern = pattern; 960 961 let Inst{6-8} = BF; 962 let Inst{9-10} = 0; 963 let Inst{11-15} = RA; 964 let Inst{16-20} = RB; 965 let Inst{21-30} = xo; 966 let Inst{31} = 0; 967} 968 969// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 970class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 971 string asmstr, InstrItinClass itin, list<dag> pattern> 972 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 973 let A = xo2; 974} 975 976class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 977 string asmstr, InstrItinClass itin, list<dag> pattern> 978 : I<opcode, OOL, IOL, asmstr, itin> { 979 bits<3> BF; 980 bits<7> DCMX; 981 bits<5> VB; 982 983 let Pattern = pattern; 984 985 let Inst{6-8} = BF; 986 let Inst{9-15} = DCMX; 987 let Inst{16-20} = VB; 988 let Inst{21-30} = xo; 989 let Inst{31} = 0; 990} 991 992class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 993 string asmstr, InstrItinClass itin, list<dag> pattern> 994 : I<opcode, OOL, IOL, asmstr, itin> { 995 bits<6> XT; 996 bits<8> IMM8; 997 998 let Pattern = pattern; 999 1000 let Inst{6-10} = XT{4-0}; 1001 let Inst{11-12} = 0; 1002 let Inst{13-20} = IMM8; 1003 let Inst{21-30} = xo; 1004 let Inst{31} = XT{5}; 1005} 1006 1007// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1008// to specify an SDAG pattern for matching. 1009class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1010 string asmstr, InstrItinClass itin> 1011 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1012} 1013 1014class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1015 InstrItinClass itin> 1016 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1017 let FRA = 0; 1018 let FRB = 0; 1019} 1020 1021// [PO /// L RA RB XO /] 1022class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1023 string asmstr, InstrItinClass itin, list<dag> pattern> 1024 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1025 let BF = 0; 1026 let Pattern = pattern; 1027 1028 bit RC = 0; 1029 let Inst{31} = RC; 1030} 1031 1032// XX*-Form (VSX) 1033class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1034 InstrItinClass itin, list<dag> pattern> 1035 : I<opcode, OOL, IOL, asmstr, itin> { 1036 bits<6> XT; 1037 bits<5> A; 1038 bits<5> B; 1039 1040 let Pattern = pattern; 1041 1042 let Inst{6-10} = XT{4-0}; 1043 let Inst{11-15} = A; 1044 let Inst{16-20} = B; 1045 let Inst{21-30} = xo; 1046 let Inst{31} = XT{5}; 1047} 1048 1049class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1050 string asmstr, InstrItinClass itin, list<dag> pattern> 1051 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1052 1053class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1054 string asmstr, InstrItinClass itin, list<dag> pattern> 1055 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1056 let B = 0; 1057} 1058 1059class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1060 InstrItinClass itin, list<dag> pattern> 1061 : I<opcode, OOL, IOL, asmstr, itin> { 1062 bits<6> XT; 1063 bits<6> XB; 1064 1065 let Pattern = pattern; 1066 1067 let Inst{6-10} = XT{4-0}; 1068 let Inst{11-15} = 0; 1069 let Inst{16-20} = XB{4-0}; 1070 let Inst{21-29} = xo; 1071 let Inst{30} = XB{5}; 1072 let Inst{31} = XT{5}; 1073} 1074 1075class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1076 InstrItinClass itin, list<dag> pattern> 1077 : I<opcode, OOL, IOL, asmstr, itin> { 1078 bits<3> CR; 1079 bits<6> XB; 1080 1081 let Pattern = pattern; 1082 1083 let Inst{6-8} = CR; 1084 let Inst{9-15} = 0; 1085 let Inst{16-20} = XB{4-0}; 1086 let Inst{21-29} = xo; 1087 let Inst{30} = XB{5}; 1088 let Inst{31} = 0; 1089} 1090 1091class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1092 InstrItinClass itin, list<dag> pattern> 1093 : I<opcode, OOL, IOL, asmstr, itin> { 1094 bits<6> XT; 1095 bits<6> XB; 1096 bits<2> D; 1097 1098 let Pattern = pattern; 1099 1100 let Inst{6-10} = XT{4-0}; 1101 let Inst{11-13} = 0; 1102 let Inst{14-15} = D; 1103 let Inst{16-20} = XB{4-0}; 1104 let Inst{21-29} = xo; 1105 let Inst{30} = XB{5}; 1106 let Inst{31} = XT{5}; 1107} 1108 1109class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1110 string asmstr, InstrItinClass itin, list<dag> pattern> 1111 : I<opcode, OOL, IOL, asmstr, itin> { 1112 bits<6> XT; 1113 bits<6> XB; 1114 bits<5> UIM5; 1115 1116 let Pattern = pattern; 1117 1118 let Inst{6-10} = XT{4-0}; 1119 let Inst{11-15} = UIM5; 1120 let Inst{16-20} = XB{4-0}; 1121 let Inst{21-29} = xo; 1122 let Inst{30} = XB{5}; 1123 let Inst{31} = XT{5}; 1124} 1125 1126// [PO T XO B XO BX /] 1127class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1128 string asmstr, InstrItinClass itin, list<dag> pattern> 1129 : I<opcode, OOL, IOL, asmstr, itin> { 1130 bits<5> RT; 1131 bits<6> XB; 1132 1133 let Pattern = pattern; 1134 1135 let Inst{6-10} = RT; 1136 let Inst{11-15} = xo2; 1137 let Inst{16-20} = XB{4-0}; 1138 let Inst{21-29} = xo; 1139 let Inst{30} = XB{5}; 1140 let Inst{31} = 0; 1141} 1142 1143// [PO T XO B XO BX TX] 1144class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1145 string asmstr, InstrItinClass itin, list<dag> pattern> 1146 : I<opcode, OOL, IOL, asmstr, itin> { 1147 bits<6> XT; 1148 bits<6> XB; 1149 1150 let Pattern = pattern; 1151 1152 let Inst{6-10} = XT{4-0}; 1153 let Inst{11-15} = xo2; 1154 let Inst{16-20} = XB{4-0}; 1155 let Inst{21-29} = xo; 1156 let Inst{30} = XB{5}; 1157 let Inst{31} = XT{5}; 1158} 1159 1160class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1161 string asmstr, InstrItinClass itin, list<dag> pattern> 1162 : I<opcode, OOL, IOL, asmstr, itin> { 1163 bits<3> BF; 1164 bits<7> DCMX; 1165 bits<6> XB; 1166 1167 let Pattern = pattern; 1168 1169 let Inst{6-8} = BF; 1170 let Inst{9-15} = DCMX; 1171 let Inst{16-20} = XB{4-0}; 1172 let Inst{21-29} = xo; 1173 let Inst{30} = XB{5}; 1174 let Inst{31} = 0; 1175} 1176 1177class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1178 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1179 list<dag> pattern> 1180 : I<opcode, OOL, IOL, asmstr, itin> { 1181 bits<6> XT; 1182 bits<7> DCMX; 1183 bits<6> XB; 1184 1185 let Pattern = pattern; 1186 1187 let Inst{6-10} = XT{4-0}; 1188 let Inst{11-15} = DCMX{4-0}; 1189 let Inst{16-20} = XB{4-0}; 1190 let Inst{21-24} = xo1; 1191 let Inst{25} = DCMX{6}; 1192 let Inst{26-28} = xo2; 1193 let Inst{29} = DCMX{5}; 1194 let Inst{30} = XB{5}; 1195 let Inst{31} = XT{5}; 1196} 1197 1198class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1199 InstrItinClass itin, list<dag> pattern> 1200 : I<opcode, OOL, IOL, asmstr, itin> { 1201 bits<6> XT; 1202 bits<6> XA; 1203 bits<6> XB; 1204 1205 let Pattern = pattern; 1206 1207 let Inst{6-10} = XT{4-0}; 1208 let Inst{11-15} = XA{4-0}; 1209 let Inst{16-20} = XB{4-0}; 1210 let Inst{21-28} = xo; 1211 let Inst{29} = XA{5}; 1212 let Inst{30} = XB{5}; 1213 let Inst{31} = XT{5}; 1214} 1215 1216class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1217 InstrItinClass itin, list<dag> pattern> 1218 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1219 let XA = XT; 1220 let XB = XT; 1221} 1222 1223class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1224 InstrItinClass itin, list<dag> pattern> 1225 : I<opcode, OOL, IOL, asmstr, itin> { 1226 bits<3> CR; 1227 bits<6> XA; 1228 bits<6> XB; 1229 1230 let Pattern = pattern; 1231 1232 let Inst{6-8} = CR; 1233 let Inst{9-10} = 0; 1234 let Inst{11-15} = XA{4-0}; 1235 let Inst{16-20} = XB{4-0}; 1236 let Inst{21-28} = xo; 1237 let Inst{29} = XA{5}; 1238 let Inst{30} = XB{5}; 1239 let Inst{31} = 0; 1240} 1241 1242class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1243 InstrItinClass itin, list<dag> pattern> 1244 : I<opcode, OOL, IOL, asmstr, itin> { 1245 bits<6> XT; 1246 bits<6> XA; 1247 bits<6> XB; 1248 bits<2> D; 1249 1250 let Pattern = pattern; 1251 1252 let Inst{6-10} = XT{4-0}; 1253 let Inst{11-15} = XA{4-0}; 1254 let Inst{16-20} = XB{4-0}; 1255 let Inst{21} = 0; 1256 let Inst{22-23} = D; 1257 let Inst{24-28} = xo; 1258 let Inst{29} = XA{5}; 1259 let Inst{30} = XB{5}; 1260 let Inst{31} = XT{5}; 1261} 1262 1263class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1264 InstrItinClass itin, list<dag> pattern> 1265 : I<opcode, OOL, IOL, asmstr, itin> { 1266 bits<6> XT; 1267 bits<6> XA; 1268 bits<6> XB; 1269 1270 let Pattern = pattern; 1271 1272 bit RC = 0; // set by isRecordForm 1273 1274 let Inst{6-10} = XT{4-0}; 1275 let Inst{11-15} = XA{4-0}; 1276 let Inst{16-20} = XB{4-0}; 1277 let Inst{21} = RC; 1278 let Inst{22-28} = xo; 1279 let Inst{29} = XA{5}; 1280 let Inst{30} = XB{5}; 1281 let Inst{31} = XT{5}; 1282} 1283 1284class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1285 InstrItinClass itin, list<dag> pattern> 1286 : I<opcode, OOL, IOL, asmstr, itin> { 1287 bits<6> XT; 1288 bits<6> XA; 1289 bits<6> XB; 1290 bits<6> XC; 1291 1292 let Pattern = pattern; 1293 1294 let Inst{6-10} = XT{4-0}; 1295 let Inst{11-15} = XA{4-0}; 1296 let Inst{16-20} = XB{4-0}; 1297 let Inst{21-25} = XC{4-0}; 1298 let Inst{26-27} = xo; 1299 let Inst{28} = XC{5}; 1300 let Inst{29} = XA{5}; 1301 let Inst{30} = XB{5}; 1302 let Inst{31} = XT{5}; 1303} 1304 1305// DCB_Form - Form X instruction, used for dcb* instructions. 1306class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1307 InstrItinClass itin, list<dag> pattern> 1308 : I<31, OOL, IOL, asmstr, itin> { 1309 bits<5> A; 1310 bits<5> B; 1311 1312 let Pattern = pattern; 1313 1314 let Inst{6-10} = immfield; 1315 let Inst{11-15} = A; 1316 let Inst{16-20} = B; 1317 let Inst{21-30} = xo; 1318 let Inst{31} = 0; 1319} 1320 1321class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1322 InstrItinClass itin, list<dag> pattern> 1323 : I<31, OOL, IOL, asmstr, itin> { 1324 bits<5> TH; 1325 bits<5> A; 1326 bits<5> B; 1327 1328 let Pattern = pattern; 1329 1330 let Inst{6-10} = TH; 1331 let Inst{11-15} = A; 1332 let Inst{16-20} = B; 1333 let Inst{21-30} = xo; 1334 let Inst{31} = 0; 1335} 1336 1337// DSS_Form - Form X instruction, used for altivec dss* instructions. 1338class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1339 InstrItinClass itin, list<dag> pattern> 1340 : I<31, OOL, IOL, asmstr, itin> { 1341 bits<2> STRM; 1342 bits<5> A; 1343 bits<5> B; 1344 1345 let Pattern = pattern; 1346 1347 let Inst{6} = T; 1348 let Inst{7-8} = 0; 1349 let Inst{9-10} = STRM; 1350 let Inst{11-15} = A; 1351 let Inst{16-20} = B; 1352 let Inst{21-30} = xo; 1353 let Inst{31} = 0; 1354} 1355 1356// 1.7.7 XL-Form 1357class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1358 InstrItinClass itin, list<dag> pattern> 1359 : I<opcode, OOL, IOL, asmstr, itin> { 1360 bits<5> CRD; 1361 bits<5> CRA; 1362 bits<5> CRB; 1363 1364 let Pattern = pattern; 1365 1366 let Inst{6-10} = CRD; 1367 let Inst{11-15} = CRA; 1368 let Inst{16-20} = CRB; 1369 let Inst{21-30} = xo; 1370 let Inst{31} = 0; 1371} 1372 1373class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1374 InstrItinClass itin, list<dag> pattern> 1375 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1376 let CRD = 0; 1377 let CRA = 0; 1378 let CRB = 0; 1379} 1380 1381class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1382 InstrItinClass itin, list<dag> pattern> 1383 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1384 bits<5> RT; 1385 bits<5> RB; 1386 1387 let CRD = RT; 1388 let CRA = 0; 1389 let CRB = RB; 1390} 1391 1392class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1393 InstrItinClass itin, list<dag> pattern> 1394 : I<opcode, OOL, IOL, asmstr, itin> { 1395 bits<5> CRD; 1396 1397 let Pattern = pattern; 1398 1399 let Inst{6-10} = CRD; 1400 let Inst{11-15} = CRD; 1401 let Inst{16-20} = CRD; 1402 let Inst{21-30} = xo; 1403 let Inst{31} = 0; 1404} 1405 1406class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1407 InstrItinClass itin, list<dag> pattern> 1408 : I<opcode, OOL, IOL, asmstr, itin> { 1409 bits<5> BO; 1410 bits<5> BI; 1411 bits<2> BH; 1412 1413 let Pattern = pattern; 1414 1415 let Inst{6-10} = BO; 1416 let Inst{11-15} = BI; 1417 let Inst{16-18} = 0; 1418 let Inst{19-20} = BH; 1419 let Inst{21-30} = xo; 1420 let Inst{31} = lk; 1421} 1422 1423class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1424 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1425 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1426 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1427 bits<3> CR; 1428 1429 let BO = BIBO{4-0}; 1430 let BI{0-1} = BIBO{5-6}; 1431 let BI{2-4} = CR{0-2}; 1432 let BH = 0; 1433} 1434 1435class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1436 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1437 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1438 let BO = bo; 1439 let BH = 0; 1440} 1441 1442class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1443 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1444 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1445 let BO = bo; 1446 let BI = bi; 1447 let BH = 0; 1448} 1449 1450class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1451 InstrItinClass itin> 1452 : I<opcode, OOL, IOL, asmstr, itin> { 1453 bits<3> BF; 1454 bits<3> BFA; 1455 1456 let Inst{6-8} = BF; 1457 let Inst{9-10} = 0; 1458 let Inst{11-13} = BFA; 1459 let Inst{14-15} = 0; 1460 let Inst{16-20} = 0; 1461 let Inst{21-30} = xo; 1462 let Inst{31} = 0; 1463} 1464 1465class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1466 InstrItinClass itin> 1467 : I<opcode, OOL, IOL, asmstr, itin> { 1468 bits<3> BF; 1469 bit W; 1470 bits<4> U; 1471 1472 bit RC = 0; 1473 1474 let Inst{6-8} = BF; 1475 let Inst{9-10} = 0; 1476 let Inst{11-14} = 0; 1477 let Inst{15} = W; 1478 let Inst{16-19} = U; 1479 let Inst{20} = 0; 1480 let Inst{21-30} = xo; 1481 let Inst{31} = RC; 1482} 1483 1484class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1485 InstrItinClass itin, list<dag> pattern> 1486 : I<opcode, OOL, IOL, asmstr, itin> { 1487 bits<1> S; 1488 1489 let Pattern = pattern; 1490 1491 let Inst{6-19} = 0; 1492 let Inst{20} = S; 1493 let Inst{21-30} = xo; 1494 let Inst{31} = 0; 1495} 1496 1497class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1498 bits<6> opcode2, bits<2> xo2, 1499 dag OOL, dag IOL, string asmstr, 1500 InstrItinClass itin, list<dag> pattern> 1501 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1502 bits<5> BO; 1503 bits<5> BI; 1504 bits<2> BH; 1505 1506 bits<5> RST; 1507 bits<19> DS_RA; 1508 1509 let Pattern = pattern; 1510 1511 let Inst{6-10} = BO; 1512 let Inst{11-15} = BI; 1513 let Inst{16-18} = 0; 1514 let Inst{19-20} = BH; 1515 let Inst{21-30} = xo1; 1516 let Inst{31} = lk; 1517 1518 let Inst{38-42} = RST; 1519 let Inst{43-47} = DS_RA{18-14}; // Register # 1520 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1521 let Inst{62-63} = xo2; 1522} 1523 1524class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1525 bits<5> bo, bits<5> bi, bit lk, 1526 bits<6> opcode2, bits<2> xo2, 1527 dag OOL, dag IOL, string asmstr, 1528 InstrItinClass itin, list<dag> pattern> 1529 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1530 OOL, IOL, asmstr, itin, pattern> { 1531 let BO = bo; 1532 let BI = bi; 1533 let BH = 0; 1534} 1535 1536class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1537 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1538 dag IOL, string asmstr, InstrItinClass itin, 1539 list<dag> pattern> 1540 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1541 1542 bits<5> RST; 1543 bits<21> D_RA; 1544 1545 let Pattern = pattern; 1546 1547 let Inst{6-10} = bo; 1548 let Inst{11-15} = bi; 1549 let Inst{16-18} = 0; 1550 let Inst{19-20} = 0; // Unused (BH) 1551 let Inst{21-30} = xo1; 1552 let Inst{31} = lk; 1553 1554 let Inst{38-42} = RST; 1555 let Inst{43-47} = D_RA{20-16}; // Base Register 1556 let Inst{48-63} = D_RA{15-0}; // Displacement 1557} 1558 1559// 1.7.8 XFX-Form 1560class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1561 InstrItinClass itin> 1562 : I<opcode, OOL, IOL, asmstr, itin> { 1563 bits<5> RT; 1564 bits<10> SPR; 1565 1566 let Inst{6-10} = RT; 1567 let Inst{11} = SPR{4}; 1568 let Inst{12} = SPR{3}; 1569 let Inst{13} = SPR{2}; 1570 let Inst{14} = SPR{1}; 1571 let Inst{15} = SPR{0}; 1572 let Inst{16} = SPR{9}; 1573 let Inst{17} = SPR{8}; 1574 let Inst{18} = SPR{7}; 1575 let Inst{19} = SPR{6}; 1576 let Inst{20} = SPR{5}; 1577 let Inst{21-30} = xo; 1578 let Inst{31} = 0; 1579} 1580 1581class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1582 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1583 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1584 let SPR = spr; 1585} 1586 1587class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1588 InstrItinClass itin> 1589 : I<opcode, OOL, IOL, asmstr, itin> { 1590 bits<5> RT; 1591 1592 let Inst{6-10} = RT; 1593 let Inst{11-20} = 0; 1594 let Inst{21-30} = xo; 1595 let Inst{31} = 0; 1596} 1597 1598class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1599 InstrItinClass itin, list<dag> pattern> 1600 : I<opcode, OOL, IOL, asmstr, itin> { 1601 bits<5> RT; 1602 bits<10> Entry; 1603 let Pattern = pattern; 1604 1605 let Inst{6-10} = RT; 1606 let Inst{11-20} = Entry; 1607 let Inst{21-30} = xo; 1608 let Inst{31} = 0; 1609} 1610 1611class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1612 InstrItinClass itin> 1613 : I<opcode, OOL, IOL, asmstr, itin> { 1614 bits<8> FXM; 1615 bits<5> rS; 1616 1617 let Inst{6-10} = rS; 1618 let Inst{11} = 0; 1619 let Inst{12-19} = FXM; 1620 let Inst{20} = 0; 1621 let Inst{21-30} = xo; 1622 let Inst{31} = 0; 1623} 1624 1625class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1626 InstrItinClass itin> 1627 : I<opcode, OOL, IOL, asmstr, itin> { 1628 bits<5> ST; 1629 bits<8> FXM; 1630 1631 let Inst{6-10} = ST; 1632 let Inst{11} = 1; 1633 let Inst{12-19} = FXM; 1634 let Inst{20} = 0; 1635 let Inst{21-30} = xo; 1636 let Inst{31} = 0; 1637} 1638 1639class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1640 InstrItinClass itin> 1641 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1642 1643class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1644 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1645 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1646 let SPR = spr; 1647} 1648 1649// XFL-Form - MTFSF 1650// This is probably 1.7.9, but I don't have the reference that uses this 1651// numbering scheme... 1652class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1653 InstrItinClass itin, list<dag>pattern> 1654 : I<opcode, OOL, IOL, asmstr, itin> { 1655 bits<8> FM; 1656 bits<5> rT; 1657 1658 bit RC = 0; // set by isRecordForm 1659 let Pattern = pattern; 1660 1661 let Inst{6} = 0; 1662 let Inst{7-14} = FM; 1663 let Inst{15} = 0; 1664 let Inst{16-20} = rT; 1665 let Inst{21-30} = xo; 1666 let Inst{31} = RC; 1667} 1668 1669class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1670 InstrItinClass itin, list<dag>pattern> 1671 : I<opcode, OOL, IOL, asmstr, itin> { 1672 bit L; 1673 bits<8> FLM; 1674 bit W; 1675 bits<5> FRB; 1676 1677 bit RC = 0; // set by isRecordForm 1678 let Pattern = pattern; 1679 1680 let Inst{6} = L; 1681 let Inst{7-14} = FLM; 1682 let Inst{15} = W; 1683 let Inst{16-20} = FRB; 1684 let Inst{21-30} = xo; 1685 let Inst{31} = RC; 1686} 1687 1688// 1.7.10 XS-Form - SRADI. 1689class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1690 InstrItinClass itin, list<dag> pattern> 1691 : I<opcode, OOL, IOL, asmstr, itin> { 1692 bits<5> A; 1693 bits<5> RS; 1694 bits<6> SH; 1695 1696 bit RC = 0; // set by isRecordForm 1697 let Pattern = pattern; 1698 1699 let Inst{6-10} = RS; 1700 let Inst{11-15} = A; 1701 let Inst{16-20} = SH{4,3,2,1,0}; 1702 let Inst{21-29} = xo; 1703 let Inst{30} = SH{5}; 1704 let Inst{31} = RC; 1705} 1706 1707// 1.7.11 XO-Form 1708class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1709 InstrItinClass itin, list<dag> pattern> 1710 : I<opcode, OOL, IOL, asmstr, itin> { 1711 bits<5> RT; 1712 bits<5> RA; 1713 bits<5> RB; 1714 1715 let Pattern = pattern; 1716 1717 bit RC = 0; // set by isRecordForm 1718 1719 let Inst{6-10} = RT; 1720 let Inst{11-15} = RA; 1721 let Inst{16-20} = RB; 1722 let Inst{21} = oe; 1723 let Inst{22-30} = xo; 1724 let Inst{31} = RC; 1725} 1726 1727class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1728 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1729 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1730 let RB = 0; 1731} 1732 1733// 1.7.12 A-Form 1734class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1735 InstrItinClass itin, list<dag> pattern> 1736 : I<opcode, OOL, IOL, asmstr, itin> { 1737 bits<5> FRT; 1738 bits<5> FRA; 1739 bits<5> FRC; 1740 bits<5> FRB; 1741 1742 let Pattern = pattern; 1743 1744 bit RC = 0; // set by isRecordForm 1745 1746 let Inst{6-10} = FRT; 1747 let Inst{11-15} = FRA; 1748 let Inst{16-20} = FRB; 1749 let Inst{21-25} = FRC; 1750 let Inst{26-30} = xo; 1751 let Inst{31} = RC; 1752} 1753 1754class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1755 InstrItinClass itin, list<dag> pattern> 1756 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1757 let FRC = 0; 1758} 1759 1760class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1761 InstrItinClass itin, list<dag> pattern> 1762 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1763 let FRB = 0; 1764} 1765 1766class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1767 InstrItinClass itin, list<dag> pattern> 1768 : I<opcode, OOL, IOL, asmstr, itin> { 1769 bits<5> RT; 1770 bits<5> RA; 1771 bits<5> RB; 1772 bits<5> COND; 1773 1774 let Pattern = pattern; 1775 1776 let Inst{6-10} = RT; 1777 let Inst{11-15} = RA; 1778 let Inst{16-20} = RB; 1779 let Inst{21-25} = COND; 1780 let Inst{26-30} = xo; 1781 let Inst{31} = 0; 1782} 1783 1784// Used for QPX 1785class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1786 InstrItinClass itin, list<dag> pattern> 1787 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1788 let FRA = 0; 1789 let FRC = 0; 1790} 1791 1792// 1.7.13 M-Form 1793class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1794 InstrItinClass itin, list<dag> pattern> 1795 : I<opcode, OOL, IOL, asmstr, itin> { 1796 bits<5> RA; 1797 bits<5> RS; 1798 bits<5> RB; 1799 bits<5> MB; 1800 bits<5> ME; 1801 1802 let Pattern = pattern; 1803 1804 bit RC = 0; // set by isRecordForm 1805 1806 let Inst{6-10} = RS; 1807 let Inst{11-15} = RA; 1808 let Inst{16-20} = RB; 1809 let Inst{21-25} = MB; 1810 let Inst{26-30} = ME; 1811 let Inst{31} = RC; 1812} 1813 1814class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1815 InstrItinClass itin, list<dag> pattern> 1816 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1817} 1818 1819// 1.7.14 MD-Form 1820class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1821 InstrItinClass itin, list<dag> pattern> 1822 : I<opcode, OOL, IOL, asmstr, itin> { 1823 bits<5> RA; 1824 bits<5> RS; 1825 bits<6> SH; 1826 bits<6> MBE; 1827 1828 let Pattern = pattern; 1829 1830 bit RC = 0; // set by isRecordForm 1831 1832 let Inst{6-10} = RS; 1833 let Inst{11-15} = RA; 1834 let Inst{16-20} = SH{4,3,2,1,0}; 1835 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1836 let Inst{27-29} = xo; 1837 let Inst{30} = SH{5}; 1838 let Inst{31} = RC; 1839} 1840 1841class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1842 InstrItinClass itin, list<dag> pattern> 1843 : I<opcode, OOL, IOL, asmstr, itin> { 1844 bits<5> RA; 1845 bits<5> RS; 1846 bits<5> RB; 1847 bits<6> MBE; 1848 1849 let Pattern = pattern; 1850 1851 bit RC = 0; // set by isRecordForm 1852 1853 let Inst{6-10} = RS; 1854 let Inst{11-15} = RA; 1855 let Inst{16-20} = RB; 1856 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1857 let Inst{27-30} = xo; 1858 let Inst{31} = RC; 1859} 1860 1861 1862// E-1 VA-Form 1863 1864// VAForm_1 - DACB ordering. 1865class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1866 InstrItinClass itin, list<dag> pattern> 1867 : I<4, OOL, IOL, asmstr, itin> { 1868 bits<5> VD; 1869 bits<5> VA; 1870 bits<5> VC; 1871 bits<5> VB; 1872 1873 let Pattern = pattern; 1874 1875 let Inst{6-10} = VD; 1876 let Inst{11-15} = VA; 1877 let Inst{16-20} = VB; 1878 let Inst{21-25} = VC; 1879 let Inst{26-31} = xo; 1880} 1881 1882// VAForm_1a - DABC ordering. 1883class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1884 InstrItinClass itin, list<dag> pattern> 1885 : I<4, OOL, IOL, asmstr, itin> { 1886 bits<5> VD; 1887 bits<5> VA; 1888 bits<5> VB; 1889 bits<5> VC; 1890 1891 let Pattern = pattern; 1892 1893 let Inst{6-10} = VD; 1894 let Inst{11-15} = VA; 1895 let Inst{16-20} = VB; 1896 let Inst{21-25} = VC; 1897 let Inst{26-31} = xo; 1898} 1899 1900class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1901 InstrItinClass itin, list<dag> pattern> 1902 : I<4, OOL, IOL, asmstr, itin> { 1903 bits<5> VD; 1904 bits<5> VA; 1905 bits<5> VB; 1906 bits<4> SH; 1907 1908 let Pattern = pattern; 1909 1910 let Inst{6-10} = VD; 1911 let Inst{11-15} = VA; 1912 let Inst{16-20} = VB; 1913 let Inst{21} = 0; 1914 let Inst{22-25} = SH; 1915 let Inst{26-31} = xo; 1916} 1917 1918// E-2 VX-Form 1919class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1920 InstrItinClass itin, list<dag> pattern> 1921 : I<4, OOL, IOL, asmstr, itin> { 1922 bits<5> VD; 1923 bits<5> VA; 1924 bits<5> VB; 1925 1926 let Pattern = pattern; 1927 1928 let Inst{6-10} = VD; 1929 let Inst{11-15} = VA; 1930 let Inst{16-20} = VB; 1931 let Inst{21-31} = xo; 1932} 1933 1934class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1935 InstrItinClass itin, list<dag> pattern> 1936 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1937 let VA = VD; 1938 let VB = VD; 1939} 1940 1941 1942class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1943 InstrItinClass itin, list<dag> pattern> 1944 : I<4, OOL, IOL, asmstr, itin> { 1945 bits<5> VD; 1946 bits<5> VB; 1947 1948 let Pattern = pattern; 1949 1950 let Inst{6-10} = VD; 1951 let Inst{11-15} = 0; 1952 let Inst{16-20} = VB; 1953 let Inst{21-31} = xo; 1954} 1955 1956class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1957 InstrItinClass itin, list<dag> pattern> 1958 : I<4, OOL, IOL, asmstr, itin> { 1959 bits<5> VD; 1960 bits<5> IMM; 1961 1962 let Pattern = pattern; 1963 1964 let Inst{6-10} = VD; 1965 let Inst{11-15} = IMM; 1966 let Inst{16-20} = 0; 1967 let Inst{21-31} = xo; 1968} 1969 1970/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1971class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1972 InstrItinClass itin, list<dag> pattern> 1973 : I<4, OOL, IOL, asmstr, itin> { 1974 bits<5> VD; 1975 1976 let Pattern = pattern; 1977 1978 let Inst{6-10} = VD; 1979 let Inst{11-15} = 0; 1980 let Inst{16-20} = 0; 1981 let Inst{21-31} = xo; 1982} 1983 1984/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1985class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1986 InstrItinClass itin, list<dag> pattern> 1987 : I<4, OOL, IOL, asmstr, itin> { 1988 bits<5> VB; 1989 1990 let Pattern = pattern; 1991 1992 let Inst{6-10} = 0; 1993 let Inst{11-15} = 0; 1994 let Inst{16-20} = VB; 1995 let Inst{21-31} = xo; 1996} 1997 1998// e.g. [PO VRT EO VRB XO] 1999class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 2000 string asmstr, InstrItinClass itin, list<dag> pattern> 2001 : I<4, OOL, IOL, asmstr, itin> { 2002 bits<5> RD; 2003 bits<5> VB; 2004 2005 let Pattern = pattern; 2006 2007 let Inst{6-10} = RD; 2008 let Inst{11-15} = eo; 2009 let Inst{16-20} = VB; 2010 let Inst{21-31} = xo; 2011} 2012 2013/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2014class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2015 InstrItinClass itin, list<dag> pattern> 2016 : I<4, OOL, IOL, asmstr, itin> { 2017 bits<5> VD; 2018 bits<5> VA; 2019 bits<1> ST; 2020 bits<4> SIX; 2021 2022 let Pattern = pattern; 2023 2024 let Inst{6-10} = VD; 2025 let Inst{11-15} = VA; 2026 let Inst{16} = ST; 2027 let Inst{17-20} = SIX; 2028 let Inst{21-31} = xo; 2029} 2030 2031/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2032class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2033 InstrItinClass itin, list<dag> pattern> 2034 : I<4, OOL, IOL, asmstr, itin> { 2035 bits<5> VD; 2036 bits<5> VA; 2037 2038 let Pattern = pattern; 2039 2040 let Inst{6-10} = VD; 2041 let Inst{11-15} = VA; 2042 let Inst{16-20} = 0; 2043 let Inst{21-31} = xo; 2044} 2045 2046// E-4 VXR-Form 2047class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2048 InstrItinClass itin, list<dag> pattern> 2049 : I<4, OOL, IOL, asmstr, itin> { 2050 bits<5> VD; 2051 bits<5> VA; 2052 bits<5> VB; 2053 bit RC = 0; 2054 2055 let Pattern = pattern; 2056 2057 let Inst{6-10} = VD; 2058 let Inst{11-15} = VA; 2059 let Inst{16-20} = VB; 2060 let Inst{21} = RC; 2061 let Inst{22-31} = xo; 2062} 2063 2064// VX-Form: [PO VRT EO VRB 1 PS XO] 2065class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2066 dag OOL, dag IOL, string asmstr, 2067 InstrItinClass itin, list<dag> pattern> 2068 : I<4, OOL, IOL, asmstr, itin> { 2069 bits<5> VD; 2070 bits<5> VB; 2071 bit PS; 2072 2073 let Pattern = pattern; 2074 2075 let Inst{6-10} = VD; 2076 let Inst{11-15} = eo; 2077 let Inst{16-20} = VB; 2078 let Inst{21} = 1; 2079 let Inst{22} = PS; 2080 let Inst{23-31} = xo; 2081} 2082 2083// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2084class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2085 InstrItinClass itin, list<dag> pattern> 2086 : I<4, OOL, IOL, asmstr, itin> { 2087 bits<5> VD; 2088 bits<5> VA; 2089 bits<5> VB; 2090 bit PS; 2091 2092 let Pattern = pattern; 2093 2094 let Inst{6-10} = VD; 2095 let Inst{11-15} = VA; 2096 let Inst{16-20} = VB; 2097 let Inst{21} = 1; 2098 let Inst{22} = PS; 2099 let Inst{23-31} = xo; 2100} 2101 2102// Z23-Form (used by QPX) 2103class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2104 InstrItinClass itin, list<dag> pattern> 2105 : I<opcode, OOL, IOL, asmstr, itin> { 2106 bits<5> FRT; 2107 bits<5> FRA; 2108 bits<5> FRB; 2109 bits<2> idx; 2110 2111 let Pattern = pattern; 2112 2113 bit RC = 0; // set by isRecordForm 2114 2115 let Inst{6-10} = FRT; 2116 let Inst{11-15} = FRA; 2117 let Inst{16-20} = FRB; 2118 let Inst{21-22} = idx; 2119 let Inst{23-30} = xo; 2120 let Inst{31} = RC; 2121} 2122 2123class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2124 InstrItinClass itin, list<dag> pattern> 2125 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 2126 let FRB = 0; 2127} 2128 2129class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2130 InstrItinClass itin, list<dag> pattern> 2131 : I<opcode, OOL, IOL, asmstr, itin> { 2132 bits<5> FRT; 2133 bits<12> idx; 2134 2135 let Pattern = pattern; 2136 2137 bit RC = 0; // set by isRecordForm 2138 2139 let Inst{6-10} = FRT; 2140 let Inst{11-22} = idx; 2141 let Inst{23-30} = xo; 2142 let Inst{31} = RC; 2143} 2144 2145class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2146 InstrItinClass itin, list<dag> pattern> 2147 : I<opcode, OOL, IOL, asmstr, itin> { 2148 bits<5> VRT; 2149 bit R; 2150 bits<5> VRB; 2151 bits<2> idx; 2152 2153 let Pattern = pattern; 2154 2155 bit RC = 0; // set by isRecordForm 2156 2157 let Inst{6-10} = VRT; 2158 let Inst{11-14} = 0; 2159 let Inst{15} = R; 2160 let Inst{16-20} = VRB; 2161 let Inst{21-22} = idx; 2162 let Inst{23-30} = xo; 2163 let Inst{31} = RC; 2164} 2165 2166//===----------------------------------------------------------------------===// 2167// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2168// stuff 2169class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2170 : I<0, OOL, IOL, asmstr, NoItinerary> { 2171 let isCodeGenOnly = 1; 2172 let PPC64 = 0; 2173 let Pattern = pattern; 2174 let Inst{31-0} = 0; 2175 let hasNoSchedulingInfo = 1; 2176} 2177 2178// Instruction that require custom insertion support 2179// a.k.a. ISelPseudos, however, these won't have isPseudo set 2180class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2181 list<dag> pattern> 2182 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2183 let usesCustomInserter = 1; 2184} 2185 2186// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2187// files is set only for PostRAPseudo 2188class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2189 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2190 let isPseudo = 1; 2191} 2192 2193class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2194 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2195 2196