1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Indicate that this instruction produces a result that is sign extended from 49 // 32 bits to 64 bits. 50 bits<1> SExt32To64 = 0; 51 let TSFlags{8} = SExt32To64; 52 53 // Indicate that this instruction produces a result that is zero extended from 54 // 32 bits to 64 bits. 55 bits<1> ZExt32To64 = 0; 56 let TSFlags{9} = ZExt32To64; 57 58 // Fields used for relation models. 59 string BaseName = ""; 60 61 // For cases where multiple instruction definitions really represent the 62 // same underlying instruction but with one definition for 64-bit arguments 63 // and one for 32-bit arguments, this bit breaks the degeneracy between 64 // the two forms and allows TableGen to generate mapping tables. 65 bit Interpretation64Bit = 0; 66} 67 68class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 69class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 70class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 71class PPC970_MicroCode; 72 73class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 74class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 75class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 76class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 77class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 78class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 79class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 80class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 81 82class XFormMemOp { bits<1> XFormMemOp = 1; } 83class SExt32To64 { bits<1> SExt32To64 = 1; } 84class ZExt32To64 { bits<1> ZExt32To64 = 1; } 85 86// Two joined instructions; used to emit two adjacent instructions as one. 87// The itinerary from the first instruction is used for scheduling and 88// classification. 89class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 90 InstrItinClass itin> 91 : Instruction { 92 field bits<64> Inst; 93 field bits<64> SoftFail = 0; 94 let Size = 8; 95 96 bit PPC64 = 0; // Default value, override with isPPC64 97 98 let Namespace = "PPC"; 99 let Inst{0-5} = opcode1; 100 let Inst{32-37} = opcode2; 101 let OutOperandList = OOL; 102 let InOperandList = IOL; 103 let AsmString = asmstr; 104 let Itinerary = itin; 105 106 bits<1> PPC970_First = 0; 107 bits<1> PPC970_Single = 0; 108 bits<1> PPC970_Cracked = 0; 109 bits<3> PPC970_Unit = 0; 110 111 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 112 /// these must be reflected there! See comments there for what these are. 113 let TSFlags{0} = PPC970_First; 114 let TSFlags{1} = PPC970_Single; 115 let TSFlags{2} = PPC970_Cracked; 116 let TSFlags{5-3} = PPC970_Unit; 117 118 // Fields used for relation models. 119 string BaseName = ""; 120 bit Interpretation64Bit = 0; 121} 122 123// Base class for all X-Form memory instructions 124class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 125 InstrItinClass itin> 126 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 127 128// 1.7.1 I-Form 129class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 130 InstrItinClass itin, list<dag> pattern> 131 : I<opcode, OOL, IOL, asmstr, itin> { 132 let Pattern = pattern; 133 bits<24> LI; 134 135 let Inst{6-29} = LI; 136 let Inst{30} = aa; 137 let Inst{31} = lk; 138} 139 140// 1.7.2 B-Form 141class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 144 bits<3> CR; 145 bits<14> BD; 146 147 bits<5> BI; 148 let BI{0-1} = BIBO{5-6}; 149 let BI{2-4} = CR{0-2}; 150 151 let Inst{6-10} = BIBO{4-0}; 152 let Inst{11-15} = BI; 153 let Inst{16-29} = BD; 154 let Inst{30} = aa; 155 let Inst{31} = lk; 156} 157 158class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 159 string asmstr> 160 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 161 let BIBO{4-0} = bo; 162 let BIBO{6-5} = 0; 163 let CR = 0; 164} 165 166class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<14> BD; 170 171 let Inst{6-10} = bo; 172 let Inst{11-15} = bi; 173 let Inst{16-29} = BD; 174 let Inst{30} = aa; 175 let Inst{31} = lk; 176} 177 178class BForm_3<bits<6> opcode, bit aa, bit lk, 179 dag OOL, dag IOL, string asmstr> 180 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 181 bits<5> BO; 182 bits<5> BI; 183 bits<14> BD; 184 185 let Inst{6-10} = BO; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_3_at<bits<6> opcode, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BO; 196 bits<2> at; 197 bits<5> BI; 198 bits<14> BD; 199 200 let Inst{6-8} = BO{4-2}; 201 let Inst{9-10} = at; 202 let Inst{11-15} = BI; 203 let Inst{16-29} = BD; 204 let Inst{30} = aa; 205 let Inst{31} = lk; 206} 207 208class 209BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 210 dag OOL, dag IOL, string asmstr> 211 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 212 bits<5> BI; 213 bits<14> BD; 214 215 let Inst{6-10} = bo; 216 let Inst{11-15} = BI; 217 let Inst{16-29} = BD; 218 let Inst{30} = aa; 219 let Inst{31} = lk; 220} 221 222// 1.7.3 SC-Form 223class SCForm<bits<6> opcode, bits<1> xo, 224 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 225 list<dag> pattern> 226 : I<opcode, OOL, IOL, asmstr, itin> { 227 bits<7> LEV; 228 229 let Pattern = pattern; 230 231 let Inst{20-26} = LEV; 232 let Inst{30} = xo; 233} 234 235// 1.7.4 D-Form 236class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 237 InstrItinClass itin, list<dag> pattern> 238 : I<opcode, OOL, IOL, asmstr, itin> { 239 bits<5> RST; 240 bits<5> RA; 241 bits<16> D; 242 243 let Pattern = pattern; 244 245 let Inst{6-10} = RST; 246 let Inst{11-15} = RA; 247 let Inst{16-31} = D; 248} 249 250class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 251 InstrItinClass itin, list<dag> pattern> 252 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 253} 254 255class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 256 InstrItinClass itin, list<dag> pattern> 257 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 258 259 // Even though ADDIC_rec does not really have an RC bit, provide 260 // the declaration of one here so that isRecordForm has something to set. 261 bit RC = 0; 262} 263 264class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 265 InstrItinClass itin, list<dag> pattern> 266 : I<opcode, OOL, IOL, asmstr, itin> { 267 bits<5> RST; 268 bits<16> D; 269 270 let Pattern = pattern; 271 272 let Inst{6-10} = RST; 273 let Inst{11-15} = 0; 274 let Inst{16-31} = D; 275} 276 277class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 278 InstrItinClass itin, list<dag> pattern> 279 : I<opcode, OOL, IOL, asmstr, itin> { 280 bits<5> RA; 281 bits<5> RST; 282 bits<16> D; 283 284 let Pattern = pattern; 285 286 let Inst{6-10} = RST; 287 let Inst{11-15} = RA; 288 let Inst{16-31} = D; 289} 290 291class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 292 InstrItinClass itin, list<dag> pattern> 293 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 294 let RST = 0; 295 let RA = 0; 296 let D = 0; 297} 298 299class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 300 string asmstr, InstrItinClass itin, 301 list<dag> pattern> 302 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 303 let RST = R; 304 let RA = R; 305 let D = 0; 306} 307 308class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 309 dag OOL, dag IOL, string asmstr, 310 InstrItinClass itin, list<dag> pattern> 311 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 312 bits<5> RST; 313 bits<5> RA; 314 bits<16> D; 315 316 let Pattern = pattern; 317 bits<24> LI; 318 319 let Inst{6-29} = LI; 320 let Inst{30} = aa; 321 let Inst{31} = lk; 322 323 let Inst{38-42} = RST; 324 let Inst{43-47} = RA; 325 let Inst{48-63} = D; 326} 327 328// This is used to emit BL8+NOP. 329class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 330 dag OOL, dag IOL, string asmstr, 331 InstrItinClass itin, list<dag> pattern> 332 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 333 OOL, IOL, asmstr, itin, pattern> { 334 let RST = 0; 335 let RA = 0; 336 let D = 0; 337} 338 339class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 340 InstrItinClass itin> 341 : I<opcode, OOL, IOL, asmstr, itin> { 342 bits<3> BF; 343 bits<1> L; 344 bits<5> RA; 345 bits<16> D; 346 347 let Inst{6-8} = BF; 348 let Inst{9} = 0; 349 let Inst{10} = L; 350 let Inst{11-15} = RA; 351 let Inst{16-31} = D; 352} 353 354class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 355 InstrItinClass itin> 356 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 357 let L = PPC64; 358} 359 360class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 361 InstrItinClass itin> 362 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 363 364class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 365 InstrItinClass itin> 366 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 367 let L = PPC64; 368} 369 370 371// 1.7.5 DS-Form 372class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 373 InstrItinClass itin, list<dag> pattern> 374 : I<opcode, OOL, IOL, asmstr, itin> { 375 bits<5> RST; 376 bits<5> RA; 377 bits<14> D; 378 379 let Pattern = pattern; 380 381 let Inst{6-10} = RST; 382 let Inst{11-15} = RA; 383 let Inst{16-29} = D; 384 let Inst{30-31} = xo; 385} 386 387// ISA V3.0B 1.6.6 DX-Form 388class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 389 InstrItinClass itin, list<dag> pattern> 390 : I<opcode, OOL, IOL, asmstr, itin> { 391 bits<5> RT; 392 bits<16> D; 393 394 let Pattern = pattern; 395 396 let Inst{6-10} = RT; 397 let Inst{11-15} = D{5-1}; // d1 398 let Inst{16-25} = D{15-6}; // d0 399 let Inst{26-30} = xo; 400 let Inst{31} = D{0}; // d2 401} 402 403// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 404class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 405 string asmstr, InstrItinClass itin, list<dag> pattern> 406 : I<opcode, OOL, IOL, asmstr, itin> { 407 bits<6> XT; 408 bits<5> RA; 409 bits<12> DQ; 410 411 let Pattern = pattern; 412 413 let Inst{6-10} = XT{4-0}; 414 let Inst{11-15} = RA; 415 let Inst{16-27} = DQ; 416 let Inst{28} = XT{5}; 417 let Inst{29-31} = xo; 418} 419 420class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 421 string asmstr, InstrItinClass itin, 422 list<dag> pattern> 423 : I<opcode, OOL, IOL, asmstr, itin> { 424 bits<5> RTp; 425 bits<5> RA; 426 bits<12> DQ; 427 let Pattern = pattern; 428 429 let Inst{6-10} = RTp{4-0}; 430 let Inst{11-15} = RA; 431 let Inst{16-27} = DQ; 432 let Inst{28-31} = xo; 433} 434 435// 1.7.6 X-Form 436class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 437 InstrItinClass itin, list<dag> pattern> 438 : I<opcode, OOL, IOL, asmstr, itin> { 439 bits<5> RST; 440 bits<5> RA; 441 bits<5> RB; 442 443 let Pattern = pattern; 444 445 bit RC = 0; // set by isRecordForm 446 447 let Inst{6-10} = RST; 448 let Inst{11-15} = RA; 449 let Inst{16-20} = RB; 450 let Inst{21-30} = xo; 451 let Inst{31} = RC; 452} 453 454class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 455 string asmstr, InstrItinClass itin, 456 list<dag> pattern> 457 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 458 459class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 460 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 461 let RST = 0; 462} 463 464class XForm_tlbilx<bits<10> xo, dag OOL, dag IOL, string asmstr, 465 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 466 bits<5> T; 467 let RST = T; 468} 469 470class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 471 InstrItinClass itin> 472 : I<opcode, OOL, IOL, asmstr, itin> { 473 let Inst{21-30} = xo; 474} 475 476// This is the same as XForm_base_r3xo, but the first two operands are swapped 477// when code is emitted. 478class XForm_base_r3xo_swapped 479 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 480 InstrItinClass itin> 481 : I<opcode, OOL, IOL, asmstr, itin> { 482 bits<5> RA; 483 bits<5> RST; 484 bits<5> RB; 485 486 bit RC = 0; // set by isRecordForm 487 488 let Inst{6-10} = RST; 489 let Inst{11-15} = RA; 490 let Inst{16-20} = RB; 491 let Inst{21-30} = xo; 492 let Inst{31} = RC; 493} 494 495 496class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 497 InstrItinClass itin, list<dag> pattern> 498 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 499 500class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 501 InstrItinClass itin, list<dag> pattern> 502 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 503 504class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 505 InstrItinClass itin, list<dag> pattern> 506 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 507 let RST = 0; 508} 509 510class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 511 InstrItinClass itin, list<dag> pattern> 512 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 513 let RA = 0; 514 let RB = 0; 515} 516 517class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 518 InstrItinClass itin, list<dag> pattern> 519 : I<opcode, OOL, IOL, asmstr, itin> { 520 bits<5> RST; 521 bits<5> RA; 522 bits<1> WS; 523 524 let Pattern = pattern; 525 526 let Inst{6-10} = RST; 527 let Inst{11-15} = RA; 528 let Inst{20} = WS; 529 let Inst{21-30} = xo; 530 let Inst{31} = 0; 531} 532 533class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin, list<dag> pattern> 535 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 536 let Pattern = pattern; 537} 538 539class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 540 InstrItinClass itin, list<dag> pattern> 541 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 542 543class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 544 InstrItinClass itin, list<dag> pattern> 545 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 546 547class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 548 InstrItinClass itin, list<dag> pattern> 549 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 550 let Pattern = pattern; 551} 552 553class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 554 InstrItinClass itin, list<dag> pattern> 555 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 556 let RB = 0; 557 let Pattern = pattern; 558} 559 560class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 561 InstrItinClass itin> 562 : I<opcode, OOL, IOL, asmstr, itin> { 563 bits<3> BF; 564 bits<1> L; 565 bits<5> RA; 566 bits<5> RB; 567 568 let Inst{6-8} = BF; 569 let Inst{9} = 0; 570 let Inst{10} = L; 571 let Inst{11-15} = RA; 572 let Inst{16-20} = RB; 573 let Inst{21-30} = xo; 574 let Inst{31} = 0; 575} 576 577class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 578 InstrItinClass itin> 579 : I<opcode, OOL, IOL, asmstr, itin> { 580 bits<4> CT; 581 bits<5> RA; 582 bits<5> RB; 583 584 let Inst{6} = 0; 585 let Inst{7-10} = CT; 586 let Inst{11-15} = RA; 587 let Inst{16-20} = RB; 588 let Inst{21-30} = xo; 589 let Inst{31} = 0; 590} 591 592class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 593 InstrItinClass itin> 594 : I<opcode, OOL, IOL, asmstr, itin> { 595 bits<5> RS; 596 bits<4> SR; 597 598 let Inst{6-10} = RS; 599 let Inst{12-15} = SR; 600 let Inst{21-30} = xo; 601} 602 603class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 604 InstrItinClass itin> 605 : I<opcode, OOL, IOL, asmstr, itin> { 606 bits<5> MO; 607 608 let Inst{6-10} = MO; 609 let Inst{21-30} = xo; 610} 611 612class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 613 InstrItinClass itin> 614 : I<opcode, OOL, IOL, asmstr, itin> { 615 bits<5> RS; 616 bits<5> RB; 617 618 let Inst{6-10} = RS; 619 let Inst{16-20} = RB; 620 let Inst{21-30} = xo; 621} 622 623class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 624 InstrItinClass itin> 625 : I<opcode, OOL, IOL, asmstr, itin> { 626 bits<5> RS; 627 bits<1> L; 628 629 let Inst{6-10} = RS; 630 let Inst{15} = L; 631 let Inst{21-30} = xo; 632} 633 634class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 635 InstrItinClass itin> 636 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 637 let L = PPC64; 638} 639 640class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 641 InstrItinClass itin> 642 : I<opcode, OOL, IOL, asmstr, itin> { 643 bits<3> BF; 644 bits<5> RA; 645 bits<5> RB; 646 647 let Inst{6-8} = BF; 648 let Inst{9-10} = 0; 649 let Inst{11-15} = RA; 650 let Inst{16-20} = RB; 651 let Inst{21-30} = xo; 652 let Inst{31} = 0; 653} 654 655class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 656 InstrItinClass itin, list<dag> pattern> 657 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 658 let RA = 0; 659 let Pattern = pattern; 660} 661 662class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 663 InstrItinClass itin, list<dag> pattern> 664 : I<opcode, OOL, IOL, asmstr, itin> { 665 bits<5> FRT; 666 bits<5> FRA; 667 bits<5> FRB; 668 669 let Pattern = pattern; 670 671 let Inst{6-10} = FRT; 672 let Inst{11-15} = FRA; 673 let Inst{16-20} = FRB; 674 let Inst{21-30} = xo; 675 let Inst{31} = 0; 676} 677 678class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 679 InstrItinClass itin, list<dag> pattern> 680 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 681 let FRA = 0; 682} 683 684class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 685 InstrItinClass itin, list<dag> pattern> 686 : I<opcode, OOL, IOL, asmstr, itin> { 687 bits<5> FRT; 688 bits<5> FRA; 689 bits<5> FRB; 690 bits<4> tttt; 691 692 let Pattern = pattern; 693 694 let Inst{6-10} = FRT; 695 let Inst{11-15} = FRA; 696 let Inst{16-20} = FRB; 697 let Inst{21-24} = tttt; 698 let Inst{25-30} = xo; 699 let Inst{31} = 0; 700} 701 702class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 703 InstrItinClass itin, list<dag> pattern> 704 : I<opcode, OOL, IOL, asmstr, itin> { 705 let Pattern = pattern; 706 let Inst{6-10} = 31; 707 let Inst{11-15} = 0; 708 let Inst{16-20} = 0; 709 let Inst{21-30} = xo; 710 let Inst{31} = 0; 711} 712 713class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 714 string asmstr, InstrItinClass itin, list<dag> pattern> 715 : I<opcode, OOL, IOL, asmstr, itin> { 716 bits<2> L; 717 718 let Pattern = pattern; 719 let Inst{6-8} = 0; 720 let Inst{9-10} = L; 721 let Inst{11-15} = 0; 722 let Inst{16-20} = 0; 723 let Inst{21-30} = xo; 724 let Inst{31} = 0; 725} 726 727class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 728 string asmstr, InstrItinClass itin, list<dag> pattern> 729 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 730 let L = 0; 731} 732 733class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 734 InstrItinClass itin, list<dag> pattern> 735 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 736} 737 738class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 739 string asmstr, InstrItinClass itin, list<dag> pattern> 740 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 741} 742 743// [PO RT /// RB XO RC] 744class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 745 InstrItinClass itin, list<dag> pattern> 746 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 747 let RA = 0; 748} 749 750class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 751 string asmstr, InstrItinClass itin, list<dag> pattern> 752 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 753} 754 755class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 756 InstrItinClass itin, list<dag> pattern> 757 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 758} 759 760// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 761// numbers presumably relates to some document, but I haven't found it. 762class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 763 InstrItinClass itin, list<dag> pattern> 764 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 765 let Pattern = pattern; 766 767 bit RC = 0; // set by isRecordForm 768 769 let Inst{6-10} = RST; 770 let Inst{11-20} = 0; 771 let Inst{21-30} = xo; 772 let Inst{31} = RC; 773} 774class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 775 InstrItinClass itin, list<dag> pattern> 776 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 777 let Pattern = pattern; 778 bits<5> FM; 779 780 bit RC = 0; // set by isRecordForm 781 782 let Inst{6-10} = FM; 783 let Inst{11-20} = 0; 784 let Inst{21-30} = xo; 785 let Inst{31} = RC; 786} 787 788class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 789 InstrItinClass itin> 790 : I<opcode, OOL, IOL, asmstr, itin> { 791 bits<5> RT; 792 bits<3> BFA; 793 794 let Inst{6-10} = RT; 795 let Inst{11-13} = BFA; 796 let Inst{14-15} = 0; 797 let Inst{16-20} = 0; 798 let Inst{21-30} = xo; 799 let Inst{31} = 0; 800} 801 802class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 803 InstrItinClass itin> 804 : I<opcode, OOL, IOL, asmstr, itin> { 805 bits<5> RT; 806 bits<2> L; 807 808 let Inst{6-10} = RT; 809 let Inst{11-13} = 0; 810 let Inst{14-15} = L; 811 let Inst{16-20} = 0; 812 let Inst{21-30} = xo; 813 let Inst{31} = 0; 814} 815 816class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 817 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 818 list<dag> pattern> 819 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 820 let Pattern = pattern; 821 822 let Inst{6-10} = RST; 823 let Inst{11-12} = xo1; 824 let Inst{13-15} = xo2; 825 let Inst{16-20} = 0; 826 let Inst{21-30} = xo; 827 let Inst{31} = 0; 828} 829 830class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 831 bits<10> xo, dag OOL, dag IOL, string asmstr, 832 InstrItinClass itin, list<dag> pattern> 833 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 834 let Pattern = pattern; 835 bits<5> FRB; 836 837 let Inst{6-10} = RST; 838 let Inst{11-12} = xo1; 839 let Inst{13-15} = xo2; 840 let Inst{16-20} = FRB; 841 let Inst{21-30} = xo; 842 let Inst{31} = 0; 843} 844 845class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 846 bits<10> xo, dag OOL, dag IOL, string asmstr, 847 InstrItinClass itin, list<dag> pattern> 848 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 849 let Pattern = pattern; 850 bits<3> DRM; 851 852 let Inst{6-10} = RST; 853 let Inst{11-12} = xo1; 854 let Inst{13-15} = xo2; 855 let Inst{16-17} = 0; 856 let Inst{18-20} = DRM; 857 let Inst{21-30} = xo; 858 let Inst{31} = 0; 859} 860 861class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 862 bits<10> xo, dag OOL, dag IOL, string asmstr, 863 InstrItinClass itin, list<dag> pattern> 864 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 865 let Pattern = pattern; 866 bits<2> RM; 867 868 let Inst{6-10} = RST; 869 let Inst{11-12} = xo1; 870 let Inst{13-15} = xo2; 871 let Inst{16-18} = 0; 872 let Inst{19-20} = RM; 873 let Inst{21-30} = xo; 874 let Inst{31} = 0; 875} 876 877 878class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 879 InstrItinClass itin, list<dag> pattern> 880 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 881 let RST = 0; 882 let RA = 0; 883 let RB = 0; 884} 885 886class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 887 InstrItinClass itin, list<dag> pattern> 888 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 889 let RST = 0; 890 let RA = 0; 891} 892 893class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 894 string asmstr, InstrItinClass itin> 895 : I<opcode, OOL, IOL, asmstr, itin> { 896 bit R; 897 898 bit RC = 1; 899 900 let Inst{6-9} = 0; 901 let Inst{10} = R; 902 let Inst{11-20} = 0; 903 let Inst{21-30} = xo; 904 let Inst{31} = RC; 905} 906 907class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 908 string asmstr, InstrItinClass itin> 909 : I<opcode, OOL, IOL, asmstr, itin> { 910 bit A; 911 912 bit RC = 1; 913 914 let Inst{6} = A; 915 let Inst{7-20} = 0; 916 let Inst{21-30} = xo; 917 let Inst{31} = RC; 918} 919 920class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 921 InstrItinClass itin> 922 : I<opcode, OOL, IOL, asmstr, itin> { 923 bit L; 924 925 bit RC = 0; // set by isRecordForm 926 927 let Inst{7-9} = 0; 928 let Inst{10} = L; 929 let Inst{11-20} = 0; 930 let Inst{21-30} = xo; 931 let Inst{31} = RC; 932} 933 934class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 935 InstrItinClass itin> 936 : I<opcode, OOL, IOL, asmstr, itin> { 937 bits<3> BF; 938 939 bit RC = 0; 940 941 let Inst{6-8} = BF; 942 let Inst{9-20} = 0; 943 let Inst{21-30} = xo; 944 let Inst{31} = RC; 945} 946 947// [PO RT RA RB XO /] 948class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 949 string asmstr, InstrItinClass itin, list<dag> pattern> 950 : I<opcode, OOL, IOL, asmstr, itin> { 951 bits<3> BF; 952 bits<1> L; 953 bits<5> RA; 954 bits<5> RB; 955 956 let Pattern = pattern; 957 958 let Inst{6-8} = BF; 959 let Inst{9} = 0; 960 let Inst{10} = L; 961 let Inst{11-15} = RA; 962 let Inst{16-20} = RB; 963 let Inst{21-30} = xo; 964 let Inst{31} = 0; 965} 966 967// Same as XForm_17 but with GPR's and new naming convention 968class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 969 string asmstr, InstrItinClass itin, list<dag> pattern> 970 : I<opcode, OOL, IOL, asmstr, itin> { 971 bits<3> BF; 972 bits<5> RA; 973 bits<5> RB; 974 975 let Pattern = pattern; 976 977 let Inst{6-8} = BF; 978 let Inst{9-10} = 0; 979 let Inst{11-15} = RA; 980 let Inst{16-20} = RB; 981 let Inst{21-30} = xo; 982 let Inst{31} = 0; 983} 984 985// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 986class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 987 string asmstr, InstrItinClass itin, list<dag> pattern> 988 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 989 let RA = xo2; 990} 991 992class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 993 string asmstr, InstrItinClass itin, list<dag> pattern> 994 : I<opcode, OOL, IOL, asmstr, itin> { 995 bits<3> BF; 996 bits<7> DCMX; 997 bits<5> VB; 998 999 let Pattern = pattern; 1000 1001 let Inst{6-8} = BF; 1002 let Inst{9-15} = DCMX; 1003 let Inst{16-20} = VB; 1004 let Inst{21-30} = xo; 1005 let Inst{31} = 0; 1006} 1007 1008class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1009 string asmstr, InstrItinClass itin, list<dag> pattern> 1010 : I<opcode, OOL, IOL, asmstr, itin> { 1011 bits<6> XT; 1012 bits<8> IMM8; 1013 1014 let Pattern = pattern; 1015 1016 let Inst{6-10} = XT{4-0}; 1017 let Inst{11-12} = 0; 1018 let Inst{13-20} = IMM8; 1019 let Inst{21-30} = xo; 1020 let Inst{31} = XT{5}; 1021} 1022 1023// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1024// to specify an SDAG pattern for matching. 1025class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1026 string asmstr, InstrItinClass itin> 1027 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1028} 1029 1030class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1031 InstrItinClass itin> 1032 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1033 let RA = 0; 1034 let RB = 0; 1035} 1036 1037// [PO /// L RA RB XO /] 1038class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1039 string asmstr, InstrItinClass itin, list<dag> pattern> 1040 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1041 let BF = 0; 1042 let Pattern = pattern; 1043 1044 bit RC = 0; 1045 let Inst{31} = RC; 1046} 1047 1048// XX*-Form (VSX) 1049class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1050 InstrItinClass itin, list<dag> pattern> 1051 : I<opcode, OOL, IOL, asmstr, itin> { 1052 bits<6> XT; 1053 bits<5> RA; 1054 bits<5> RB; 1055 1056 let Pattern = pattern; 1057 1058 let Inst{6-10} = XT{4-0}; 1059 let Inst{11-15} = RA; 1060 let Inst{16-20} = RB; 1061 let Inst{21-30} = xo; 1062 let Inst{31} = XT{5}; 1063} 1064 1065class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1066 string asmstr, InstrItinClass itin, list<dag> pattern> 1067 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1068 1069class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1070 string asmstr, InstrItinClass itin, list<dag> pattern> 1071 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1072 let RB = 0; 1073} 1074 1075class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1076 InstrItinClass itin, list<dag> pattern> 1077 : I<opcode, OOL, IOL, asmstr, itin> { 1078 bits<6> XT; 1079 bits<6> XB; 1080 1081 let Pattern = pattern; 1082 1083 let Inst{6-10} = XT{4-0}; 1084 let Inst{11-15} = 0; 1085 let Inst{16-20} = XB{4-0}; 1086 let Inst{21-29} = xo; 1087 let Inst{30} = XB{5}; 1088 let Inst{31} = XT{5}; 1089} 1090 1091class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1092 InstrItinClass itin, list<dag> pattern> 1093 : I<opcode, OOL, IOL, asmstr, itin> { 1094 bits<3> CR; 1095 bits<6> XB; 1096 1097 let Pattern = pattern; 1098 1099 let Inst{6-8} = CR; 1100 let Inst{9-15} = 0; 1101 let Inst{16-20} = XB{4-0}; 1102 let Inst{21-29} = xo; 1103 let Inst{30} = XB{5}; 1104 let Inst{31} = 0; 1105} 1106 1107class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1108 InstrItinClass itin, list<dag> pattern> 1109 : I<opcode, OOL, IOL, asmstr, itin> { 1110 bits<6> XT; 1111 bits<6> XB; 1112 bits<2> D; 1113 1114 let Pattern = pattern; 1115 1116 let Inst{6-10} = XT{4-0}; 1117 let Inst{11-13} = 0; 1118 let Inst{14-15} = D; 1119 let Inst{16-20} = XB{4-0}; 1120 let Inst{21-29} = xo; 1121 let Inst{30} = XB{5}; 1122 let Inst{31} = XT{5}; 1123} 1124 1125class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1126 string asmstr, InstrItinClass itin, list<dag> pattern> 1127 : I<opcode, OOL, IOL, asmstr, itin> { 1128 bits<6> XT; 1129 bits<6> XB; 1130 bits<5> UIM5; 1131 1132 let Pattern = pattern; 1133 1134 let Inst{6-10} = XT{4-0}; 1135 let Inst{11-15} = UIM5; 1136 let Inst{16-20} = XB{4-0}; 1137 let Inst{21-29} = xo; 1138 let Inst{30} = XB{5}; 1139 let Inst{31} = XT{5}; 1140} 1141 1142// [PO T XO B XO BX /] 1143class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1144 string asmstr, InstrItinClass itin, list<dag> pattern> 1145 : I<opcode, OOL, IOL, asmstr, itin> { 1146 bits<5> RT; 1147 bits<6> XB; 1148 1149 let Pattern = pattern; 1150 1151 let Inst{6-10} = RT; 1152 let Inst{11-15} = xo2; 1153 let Inst{16-20} = XB{4-0}; 1154 let Inst{21-29} = xo; 1155 let Inst{30} = XB{5}; 1156 let Inst{31} = 0; 1157} 1158 1159// [PO T XO B XO BX TX] 1160class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1161 string asmstr, InstrItinClass itin, list<dag> pattern> 1162 : I<opcode, OOL, IOL, asmstr, itin> { 1163 bits<6> XT; 1164 bits<6> XB; 1165 1166 let Pattern = pattern; 1167 1168 let Inst{6-10} = XT{4-0}; 1169 let Inst{11-15} = xo2; 1170 let Inst{16-20} = XB{4-0}; 1171 let Inst{21-29} = xo; 1172 let Inst{30} = XB{5}; 1173 let Inst{31} = XT{5}; 1174} 1175 1176class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1177 string asmstr, InstrItinClass itin, list<dag> pattern> 1178 : I<opcode, OOL, IOL, asmstr, itin> { 1179 bits<3> BF; 1180 bits<7> DCMX; 1181 bits<6> XB; 1182 1183 let Pattern = pattern; 1184 1185 let Inst{6-8} = BF; 1186 let Inst{9-15} = DCMX; 1187 let Inst{16-20} = XB{4-0}; 1188 let Inst{21-29} = xo; 1189 let Inst{30} = XB{5}; 1190 let Inst{31} = 0; 1191} 1192 1193class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1194 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1195 list<dag> pattern> 1196 : I<opcode, OOL, IOL, asmstr, itin> { 1197 bits<6> XT; 1198 bits<7> DCMX; 1199 bits<6> XB; 1200 1201 let Pattern = pattern; 1202 1203 let Inst{6-10} = XT{4-0}; 1204 let Inst{11-15} = DCMX{4-0}; 1205 let Inst{16-20} = XB{4-0}; 1206 let Inst{21-24} = xo1; 1207 let Inst{25} = DCMX{6}; 1208 let Inst{26-28} = xo2; 1209 let Inst{29} = DCMX{5}; 1210 let Inst{30} = XB{5}; 1211 let Inst{31} = XT{5}; 1212} 1213 1214class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1215 string asmstr, InstrItinClass itin, list<dag> pattern> 1216 : I<opcode, OOL, IOL, asmstr, itin> { 1217 bits<5> RA; 1218 bits<6> D; 1219 bits<5> RB; 1220 1221 let Pattern = pattern; 1222 1223 let Inst{6-10} = D{4-0}; // D 1224 let Inst{11-15} = RA; 1225 let Inst{16-20} = RB; 1226 let Inst{21-30} = xo; 1227 let Inst{31} = D{5}; // DX 1228} 1229 1230class XForm_BF3_UIM6_FRB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1231 string asmstr, InstrItinClass itin, list<dag> pattern> 1232 : I<opcode, OOL, IOL, asmstr, itin> { 1233 bits<3> BF; 1234 bits<6> UIM; 1235 bits<5> FRB; 1236 1237 let Pattern = pattern; 1238 1239 let Inst{6-8} = BF; 1240 let Inst{9} = 0; 1241 let Inst{10-15} = UIM; 1242 let Inst{16-20} = FRB; 1243 let Inst{21-30} = xo; 1244 let Inst{31} = 0; 1245} 1246 1247class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1248 list<dag> pattern, InstrItinClass itin> 1249 : I<opcode, OOL, IOL, asmstr, itin> { 1250 bits<2> SP; 1251 bits<5> FRT; 1252 bits<5> FRB; 1253 1254 let Pattern = pattern; 1255 1256 bit RC = 0; // set by isRecordForm 1257 1258 let Inst{6 - 10} = FRT; 1259 let Inst{11 - 12} = SP; 1260 let Inst{13 - 15} = 0; 1261 let Inst{16 - 20} = FRB; 1262 let Inst{21 - 30} = xo; 1263 let Inst{31} = RC; 1264} 1265 1266class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1267 string asmstr, list<dag> pattern, InstrItinClass itin> 1268 : I<opcode, OOL, IOL, asmstr, itin> { 1269 bit S; 1270 bits<5> FRT; 1271 bits<5> FRB; 1272 1273 let Pattern = pattern; 1274 1275 bit RC = 0; // set by isRecordForm 1276 1277 let Inst{6 - 10} = FRT; 1278 let Inst{11} = S; 1279 let Inst{12 - 15} = 0; 1280 let Inst{16 - 20} = FRB; 1281 let Inst{21 - 30} = xo; 1282 let Inst{31} = RC; 1283} 1284 1285class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1286 InstrItinClass itin, list<dag> pattern> 1287 : I<opcode, OOL, IOL, asmstr, itin> { 1288 bits<6> XT; 1289 bits<6> XA; 1290 bits<6> XB; 1291 1292 let Pattern = pattern; 1293 1294 let Inst{6-10} = XT{4-0}; 1295 let Inst{11-15} = XA{4-0}; 1296 let Inst{16-20} = XB{4-0}; 1297 let Inst{21-28} = xo; 1298 let Inst{29} = XA{5}; 1299 let Inst{30} = XB{5}; 1300 let Inst{31} = XT{5}; 1301} 1302 1303class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1304 InstrItinClass itin, list<dag> pattern> 1305 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1306 let XA = XT; 1307 let XB = XT; 1308} 1309 1310class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1311 InstrItinClass itin, list<dag> pattern> 1312 : I<opcode, OOL, IOL, asmstr, itin> { 1313 bits<3> CR; 1314 bits<6> XA; 1315 bits<6> XB; 1316 1317 let Pattern = pattern; 1318 1319 let Inst{6-8} = CR; 1320 let Inst{9-10} = 0; 1321 let Inst{11-15} = XA{4-0}; 1322 let Inst{16-20} = XB{4-0}; 1323 let Inst{21-28} = xo; 1324 let Inst{29} = XA{5}; 1325 let Inst{30} = XB{5}; 1326 let Inst{31} = 0; 1327} 1328 1329class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1330 InstrItinClass itin, list<dag> pattern> 1331 : I<opcode, OOL, IOL, asmstr, itin> { 1332 bits<6> XT; 1333 bits<6> XA; 1334 bits<6> XB; 1335 bits<2> D; 1336 1337 let Pattern = pattern; 1338 1339 let Inst{6-10} = XT{4-0}; 1340 let Inst{11-15} = XA{4-0}; 1341 let Inst{16-20} = XB{4-0}; 1342 let Inst{21} = 0; 1343 let Inst{22-23} = D; 1344 let Inst{24-28} = xo; 1345 let Inst{29} = XA{5}; 1346 let Inst{30} = XB{5}; 1347 let Inst{31} = XT{5}; 1348} 1349 1350class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1351 InstrItinClass itin, list<dag> pattern> 1352 : I<opcode, OOL, IOL, asmstr, itin> { 1353 bits<6> XT; 1354 bits<6> XA; 1355 bits<6> XB; 1356 1357 let Pattern = pattern; 1358 1359 bit RC = 0; // set by isRecordForm 1360 1361 let Inst{6-10} = XT{4-0}; 1362 let Inst{11-15} = XA{4-0}; 1363 let Inst{16-20} = XB{4-0}; 1364 let Inst{21} = RC; 1365 let Inst{22-28} = xo; 1366 let Inst{29} = XA{5}; 1367 let Inst{30} = XB{5}; 1368 let Inst{31} = XT{5}; 1369} 1370 1371class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1372 InstrItinClass itin, list<dag> pattern> 1373 : I<opcode, OOL, IOL, asmstr, itin> { 1374 bits<6> XT; 1375 bits<6> XA; 1376 bits<6> XB; 1377 bits<6> XC; 1378 1379 let Pattern = pattern; 1380 1381 let Inst{6-10} = XT{4-0}; 1382 let Inst{11-15} = XA{4-0}; 1383 let Inst{16-20} = XB{4-0}; 1384 let Inst{21-25} = XC{4-0}; 1385 let Inst{26-27} = xo; 1386 let Inst{28} = XC{5}; 1387 let Inst{29} = XA{5}; 1388 let Inst{30} = XB{5}; 1389 let Inst{31} = XT{5}; 1390} 1391 1392// DCB_Form - Form X instruction, used for dcb* instructions. 1393class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1394 InstrItinClass itin, list<dag> pattern> 1395 : I<31, OOL, IOL, asmstr, itin> { 1396 bits<5> RA; 1397 bits<5> RB; 1398 1399 let Pattern = pattern; 1400 1401 let Inst{6-10} = immfield; 1402 let Inst{11-15} = RA; 1403 let Inst{16-20} = RB; 1404 let Inst{21-30} = xo; 1405 let Inst{31} = 0; 1406} 1407 1408class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1409 InstrItinClass itin, list<dag> pattern> 1410 : I<31, OOL, IOL, asmstr, itin> { 1411 bits<5> TH; 1412 bits<5> RA; 1413 bits<5> RB; 1414 1415 let Pattern = pattern; 1416 1417 let Inst{6-10} = TH; 1418 let Inst{11-15} = RA; 1419 let Inst{16-20} = RB; 1420 let Inst{21-30} = xo; 1421 let Inst{31} = 0; 1422} 1423 1424// DSS_Form - Form X instruction, used for altivec dss* instructions. 1425class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1426 InstrItinClass itin, list<dag> pattern> 1427 : I<31, OOL, IOL, asmstr, itin> { 1428 bits<2> STRM; 1429 bits<5> RA; 1430 bits<5> RB; 1431 1432 let Pattern = pattern; 1433 1434 let Inst{6} = T; 1435 let Inst{7-8} = 0; 1436 let Inst{9-10} = STRM; 1437 let Inst{11-15} = RA; 1438 let Inst{16-20} = RB; 1439 let Inst{21-30} = xo; 1440 let Inst{31} = 0; 1441} 1442 1443// 1.7.7 XL-Form 1444class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1445 InstrItinClass itin, list<dag> pattern> 1446 : I<opcode, OOL, IOL, asmstr, itin> { 1447 bits<5> CRD; 1448 bits<5> CRA; 1449 bits<5> CRB; 1450 1451 let Pattern = pattern; 1452 1453 let Inst{6-10} = CRD; 1454 let Inst{11-15} = CRA; 1455 let Inst{16-20} = CRB; 1456 let Inst{21-30} = xo; 1457 let Inst{31} = 0; 1458} 1459 1460// XL-Form for unary alias for CRNOR (CRNOT) 1461class XLForm_1s<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1462 InstrItinClass itin, list<dag> pattern> 1463 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1464 let CRB = CRA; 1465} 1466 1467class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1468 InstrItinClass itin, list<dag> pattern> 1469 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1470 let CRD = 0; 1471 let CRA = 0; 1472 let CRB = 0; 1473} 1474 1475class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1476 InstrItinClass itin, list<dag> pattern> 1477 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1478 bits<5> RT; 1479 bits<5> RB; 1480 1481 let CRD = RT; 1482 let CRA = 0; 1483 let CRB = RB; 1484} 1485 1486class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1487 InstrItinClass itin, list<dag> pattern> 1488 : I<opcode, OOL, IOL, asmstr, itin> { 1489 bits<5> CRD; 1490 1491 let Pattern = pattern; 1492 1493 let Inst{6-10} = CRD; 1494 let Inst{11-15} = CRD; 1495 let Inst{16-20} = CRD; 1496 let Inst{21-30} = xo; 1497 let Inst{31} = 0; 1498} 1499 1500class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1501 InstrItinClass itin, list<dag> pattern> 1502 : I<opcode, OOL, IOL, asmstr, itin> { 1503 bits<5> BO; 1504 bits<5> BI; 1505 bits<2> BH; 1506 1507 let Pattern = pattern; 1508 1509 let Inst{6-10} = BO; 1510 let Inst{11-15} = BI; 1511 let Inst{16-18} = 0; 1512 let Inst{19-20} = BH; 1513 let Inst{21-30} = xo; 1514 let Inst{31} = lk; 1515} 1516 1517class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1518 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1519 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1520 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1521 bits<3> CR; 1522 1523 let BO = BIBO{4-0}; 1524 let BI{0-1} = BIBO{5-6}; 1525 let BI{2-4} = CR{0-2}; 1526 let BH = 0; 1527} 1528 1529class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1530 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1531 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1532 let BO = bo; 1533 let BH = 0; 1534} 1535 1536class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1537 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1538 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1539 let BO = bo; 1540 let BI = bi; 1541 let BH = 0; 1542} 1543 1544class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1545 InstrItinClass itin> 1546 : I<opcode, OOL, IOL, asmstr, itin> { 1547 bits<3> BF; 1548 bits<3> BFA; 1549 1550 let Inst{6-8} = BF; 1551 let Inst{9-10} = 0; 1552 let Inst{11-13} = BFA; 1553 let Inst{14-15} = 0; 1554 let Inst{16-20} = 0; 1555 let Inst{21-30} = xo; 1556 let Inst{31} = 0; 1557} 1558 1559class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1560 InstrItinClass itin> 1561 : I<opcode, OOL, IOL, asmstr, itin> { 1562 bits<3> BF; 1563 bit W; 1564 bits<4> U; 1565 1566 bit RC = 0; 1567 1568 let Inst{6-8} = BF; 1569 let Inst{9-10} = 0; 1570 let Inst{11-14} = 0; 1571 let Inst{15} = W; 1572 let Inst{16-19} = U; 1573 let Inst{20} = 0; 1574 let Inst{21-30} = xo; 1575 let Inst{31} = RC; 1576} 1577 1578class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1579 InstrItinClass itin, list<dag> pattern> 1580 : I<opcode, OOL, IOL, asmstr, itin> { 1581 bits<1> S; 1582 1583 let Pattern = pattern; 1584 1585 let Inst{6-19} = 0; 1586 let Inst{20} = S; 1587 let Inst{21-30} = xo; 1588 let Inst{31} = 0; 1589} 1590 1591class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1592 bits<6> opcode2, bits<2> xo2, 1593 dag OOL, dag IOL, string asmstr, 1594 InstrItinClass itin, list<dag> pattern> 1595 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1596 bits<5> BO; 1597 bits<5> BI; 1598 bits<2> BH; 1599 1600 bits<5> RST; 1601 bits<5> RA; 1602 bits<14> D; 1603 1604 let Pattern = pattern; 1605 1606 let Inst{6-10} = BO; 1607 let Inst{11-15} = BI; 1608 let Inst{16-18} = 0; 1609 let Inst{19-20} = BH; 1610 let Inst{21-30} = xo1; 1611 let Inst{31} = lk; 1612 1613 let Inst{38-42} = RST; 1614 let Inst{43-47} = RA; 1615 let Inst{48-61} = D; 1616 let Inst{62-63} = xo2; 1617} 1618 1619class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1620 bits<5> bo, bits<5> bi, bit lk, 1621 bits<6> opcode2, bits<2> xo2, 1622 dag OOL, dag IOL, string asmstr, 1623 InstrItinClass itin, list<dag> pattern> 1624 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1625 OOL, IOL, asmstr, itin, pattern> { 1626 let BO = bo; 1627 let BI = bi; 1628 let BH = 0; 1629} 1630 1631class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1632 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1633 dag IOL, string asmstr, InstrItinClass itin, 1634 list<dag> pattern> 1635 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1636 1637 bits<5> RST; 1638 bits<5> RA; 1639 bits<16> D; 1640 1641 let Pattern = pattern; 1642 1643 let Inst{6-10} = bo; 1644 let Inst{11-15} = bi; 1645 let Inst{16-18} = 0; 1646 let Inst{19-20} = 0; // Unused (BH) 1647 let Inst{21-30} = xo1; 1648 let Inst{31} = lk; 1649 1650 let Inst{38-42} = RST; 1651 let Inst{43-47} = RA; 1652 let Inst{48-63} = D; 1653} 1654 1655// 1.7.8 XFX-Form 1656class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1657 InstrItinClass itin> 1658 : I<opcode, OOL, IOL, asmstr, itin> { 1659 bits<5> RST; 1660 bits<10> SPR; 1661 1662 let Inst{6-10} = RST; 1663 let Inst{11} = SPR{4}; 1664 let Inst{12} = SPR{3}; 1665 let Inst{13} = SPR{2}; 1666 let Inst{14} = SPR{1}; 1667 let Inst{15} = SPR{0}; 1668 let Inst{16} = SPR{9}; 1669 let Inst{17} = SPR{8}; 1670 let Inst{18} = SPR{7}; 1671 let Inst{19} = SPR{6}; 1672 let Inst{20} = SPR{5}; 1673 let Inst{21-30} = xo; 1674 let Inst{31} = 0; 1675} 1676 1677class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1678 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1679 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1680 let SPR = spr; 1681} 1682 1683class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1684 InstrItinClass itin> 1685 : I<opcode, OOL, IOL, asmstr, itin> { 1686 bits<5> RT; 1687 1688 let Inst{6-10} = RT; 1689 let Inst{11-20} = 0; 1690 let Inst{21-30} = xo; 1691 let Inst{31} = 0; 1692} 1693 1694class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1695 InstrItinClass itin, list<dag> pattern> 1696 : I<opcode, OOL, IOL, asmstr, itin> { 1697 bits<5> RT; 1698 bits<10> imm; 1699 let Pattern = pattern; 1700 1701 let Inst{6-10} = RT; 1702 let Inst{11-20} = imm; 1703 let Inst{21-30} = xo; 1704 let Inst{31} = 0; 1705} 1706 1707class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1708 InstrItinClass itin> 1709 : I<opcode, OOL, IOL, asmstr, itin> { 1710 bits<8> FXM; 1711 bits<5> RST; 1712 1713 let Inst{6-10} = RST; 1714 let Inst{11} = 0; 1715 let Inst{12-19} = FXM; 1716 let Inst{20} = 0; 1717 let Inst{21-30} = xo; 1718 let Inst{31} = 0; 1719} 1720 1721class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1722 InstrItinClass itin> 1723 : I<opcode, OOL, IOL, asmstr, itin> { 1724 bits<5> RST; 1725 bits<8> FXM; 1726 1727 let Inst{6-10} = RST; 1728 let Inst{11} = 1; 1729 let Inst{12-19} = FXM; 1730 let Inst{20} = 0; 1731 let Inst{21-30} = xo; 1732 let Inst{31} = 0; 1733} 1734 1735// XFL-Form - MTFSF 1736// This is probably 1.7.9, but I don't have the reference that uses this 1737// numbering scheme... 1738class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1739 InstrItinClass itin, list<dag>pattern> 1740 : I<opcode, OOL, IOL, asmstr, itin> { 1741 bits<8> FM; 1742 bits<5> RT; 1743 1744 bit RC = 0; // set by isRecordForm 1745 let Pattern = pattern; 1746 1747 let Inst{6} = 0; 1748 let Inst{7-14} = FM; 1749 let Inst{15} = 0; 1750 let Inst{16-20} = RT; 1751 let Inst{21-30} = xo; 1752 let Inst{31} = RC; 1753} 1754 1755class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1756 InstrItinClass itin, list<dag>pattern> 1757 : I<opcode, OOL, IOL, asmstr, itin> { 1758 bit L; 1759 bits<8> FLM; 1760 bit W; 1761 bits<5> FRB; 1762 1763 bit RC = 0; // set by isRecordForm 1764 let Pattern = pattern; 1765 1766 let Inst{6} = L; 1767 let Inst{7-14} = FLM; 1768 let Inst{15} = W; 1769 let Inst{16-20} = FRB; 1770 let Inst{21-30} = xo; 1771 let Inst{31} = RC; 1772} 1773 1774// 1.7.10 XS-Form - SRADI. 1775class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1776 InstrItinClass itin, list<dag> pattern> 1777 : I<opcode, OOL, IOL, asmstr, itin> { 1778 bits<5> RA; 1779 bits<5> RS; 1780 bits<6> SH; 1781 1782 bit RC = 0; // set by isRecordForm 1783 let Pattern = pattern; 1784 1785 let Inst{6-10} = RS; 1786 let Inst{11-15} = RA; 1787 let Inst{16-20} = SH{4,3,2,1,0}; 1788 let Inst{21-29} = xo; 1789 let Inst{30} = SH{5}; 1790 let Inst{31} = RC; 1791} 1792 1793// 1.7.11 XO-Form 1794class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1795 InstrItinClass itin, list<dag> pattern> 1796 : I<opcode, OOL, IOL, asmstr, itin> { 1797 bits<5> RT; 1798 bits<5> RA; 1799 bits<5> RB; 1800 1801 let Pattern = pattern; 1802 1803 bit RC = 0; // set by isRecordForm 1804 1805 let Inst{6-10} = RT; 1806 let Inst{11-15} = RA; 1807 let Inst{16-20} = RB; 1808 let Inst{21} = oe; 1809 let Inst{22-30} = xo; 1810 let Inst{31} = RC; 1811} 1812 1813class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1814 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1815 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1816 let RB = 0; 1817} 1818 1819// 1.7.12 A-Form 1820class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1821 InstrItinClass itin, list<dag> pattern> 1822 : I<opcode, OOL, IOL, asmstr, itin> { 1823 bits<5> FRT; 1824 bits<5> FRA; 1825 bits<5> FRC; 1826 bits<5> FRB; 1827 1828 let Pattern = pattern; 1829 1830 bit RC = 0; // set by isRecordForm 1831 1832 let Inst{6-10} = FRT; 1833 let Inst{11-15} = FRA; 1834 let Inst{16-20} = FRB; 1835 let Inst{21-25} = FRC; 1836 let Inst{26-30} = xo; 1837 let Inst{31} = RC; 1838} 1839 1840class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1841 InstrItinClass itin, list<dag> pattern> 1842 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1843 let FRC = 0; 1844} 1845 1846class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1847 InstrItinClass itin, list<dag> pattern> 1848 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1849 let FRB = 0; 1850} 1851 1852class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1853 InstrItinClass itin, list<dag> pattern> 1854 : I<opcode, OOL, IOL, asmstr, itin> { 1855 bits<5> RT; 1856 bits<5> RA; 1857 bits<5> RB; 1858 bits<5> COND; 1859 1860 let Pattern = pattern; 1861 1862 let Inst{6-10} = RT; 1863 let Inst{11-15} = RA; 1864 let Inst{16-20} = RB; 1865 let Inst{21-25} = COND; 1866 let Inst{26-30} = xo; 1867 let Inst{31} = 0; 1868} 1869 1870// 1.7.13 M-Form 1871class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1872 InstrItinClass itin, list<dag> pattern> 1873 : I<opcode, OOL, IOL, asmstr, itin> { 1874 bits<5> RA; 1875 bits<5> RS; 1876 bits<5> RB; 1877 bits<5> MB; 1878 bits<5> ME; 1879 1880 let Pattern = pattern; 1881 1882 bit RC = 0; // set by isRecordForm 1883 1884 let Inst{6-10} = RS; 1885 let Inst{11-15} = RA; 1886 let Inst{16-20} = RB; 1887 let Inst{21-25} = MB; 1888 let Inst{26-30} = ME; 1889 let Inst{31} = RC; 1890} 1891 1892class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1893 InstrItinClass itin, list<dag> pattern> 1894 : I<opcode, OOL, IOL, asmstr, itin> { 1895 bits<5> RA; 1896 bits<5> RS; 1897 bits<5> SH; 1898 bits<5> MB; 1899 bits<5> ME; 1900 1901 let Pattern = pattern; 1902 1903 bit RC = 0; // set by isRecordForm 1904 1905 let Inst{6-10} = RS; 1906 let Inst{11-15} = RA; 1907 let Inst{16-20} = SH; 1908 let Inst{21-25} = MB; 1909 let Inst{26-30} = ME; 1910 let Inst{31} = RC; 1911} 1912 1913// 1.7.14 MD-Form 1914class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1915 InstrItinClass itin, list<dag> pattern> 1916 : I<opcode, OOL, IOL, asmstr, itin> { 1917 bits<5> RA; 1918 bits<5> RS; 1919 bits<6> SH; 1920 bits<6> MBE; 1921 1922 let Pattern = pattern; 1923 1924 bit RC = 0; // set by isRecordForm 1925 1926 let Inst{6-10} = RS; 1927 let Inst{11-15} = RA; 1928 let Inst{16-20} = SH{4,3,2,1,0}; 1929 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1930 let Inst{27-29} = xo; 1931 let Inst{30} = SH{5}; 1932 let Inst{31} = RC; 1933} 1934 1935class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1936 InstrItinClass itin, list<dag> pattern> 1937 : I<opcode, OOL, IOL, asmstr, itin> { 1938 bits<5> RA; 1939 bits<5> RS; 1940 bits<5> RB; 1941 bits<6> MBE; 1942 1943 let Pattern = pattern; 1944 1945 bit RC = 0; // set by isRecordForm 1946 1947 let Inst{6-10} = RS; 1948 let Inst{11-15} = RA; 1949 let Inst{16-20} = RB; 1950 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1951 let Inst{27-30} = xo; 1952 let Inst{31} = RC; 1953} 1954 1955 1956// E-1 VA-Form 1957 1958// VAForm_1 - DACB ordering. 1959class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1960 InstrItinClass itin, list<dag> pattern> 1961 : I<4, OOL, IOL, asmstr, itin> { 1962 bits<5> RT; 1963 bits<5> RA; 1964 bits<5> RC; 1965 bits<5> RB; 1966 1967 let Pattern = pattern; 1968 1969 let Inst{6-10} = RT; 1970 let Inst{11-15} = RA; 1971 let Inst{16-20} = RB; 1972 let Inst{21-25} = RC; 1973 let Inst{26-31} = xo; 1974} 1975 1976// VAForm_1a - DABC ordering. 1977class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1978 InstrItinClass itin, list<dag> pattern> 1979 : I<4, OOL, IOL, asmstr, itin> { 1980 bits<5> RT; 1981 bits<5> RA; 1982 bits<5> RB; 1983 bits<5> RC; 1984 1985 let Pattern = pattern; 1986 1987 let Inst{6-10} = RT; 1988 let Inst{11-15} = RA; 1989 let Inst{16-20} = RB; 1990 let Inst{21-25} = RC; 1991 let Inst{26-31} = xo; 1992} 1993 1994class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1995 InstrItinClass itin, list<dag> pattern> 1996 : I<4, OOL, IOL, asmstr, itin> { 1997 bits<5> RT; 1998 bits<5> RA; 1999 bits<5> RB; 2000 bits<4> SH; 2001 2002 let Pattern = pattern; 2003 2004 let Inst{6-10} = RT; 2005 let Inst{11-15} = RA; 2006 let Inst{16-20} = RB; 2007 let Inst{21} = 0; 2008 let Inst{22-25} = SH; 2009 let Inst{26-31} = xo; 2010} 2011 2012// E-2 VX-Form 2013class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 2014 InstrItinClass itin, list<dag> pattern> 2015 : I<4, OOL, IOL, asmstr, itin> { 2016 bits<5> VD; 2017 bits<5> VA; 2018 bits<5> VB; 2019 2020 let Pattern = pattern; 2021 2022 let Inst{6-10} = VD; 2023 let Inst{11-15} = VA; 2024 let Inst{16-20} = VB; 2025 let Inst{21-31} = xo; 2026} 2027 2028class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 2029 InstrItinClass itin, list<dag> pattern> 2030 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 2031 let VA = VD; 2032 let VB = VD; 2033} 2034 2035 2036class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 2037 InstrItinClass itin, list<dag> pattern> 2038 : I<4, OOL, IOL, asmstr, itin> { 2039 bits<5> VD; 2040 bits<5> VB; 2041 2042 let Pattern = pattern; 2043 2044 let Inst{6-10} = VD; 2045 let Inst{11-15} = 0; 2046 let Inst{16-20} = VB; 2047 let Inst{21-31} = xo; 2048} 2049 2050class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 2051 InstrItinClass itin, list<dag> pattern> 2052 : I<4, OOL, IOL, asmstr, itin> { 2053 bits<5> VD; 2054 bits<5> IMM; 2055 2056 let Pattern = pattern; 2057 2058 let Inst{6-10} = VD; 2059 let Inst{11-15} = IMM; 2060 let Inst{16-20} = 0; 2061 let Inst{21-31} = xo; 2062} 2063 2064/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 2065class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 2066 InstrItinClass itin, list<dag> pattern> 2067 : I<4, OOL, IOL, asmstr, itin> { 2068 bits<5> VD; 2069 2070 let Pattern = pattern; 2071 2072 let Inst{6-10} = VD; 2073 let Inst{11-15} = 0; 2074 let Inst{16-20} = 0; 2075 let Inst{21-31} = xo; 2076} 2077 2078/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 2079class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 2080 InstrItinClass itin, list<dag> pattern> 2081 : I<4, OOL, IOL, asmstr, itin> { 2082 bits<5> VB; 2083 2084 let Pattern = pattern; 2085 2086 let Inst{6-10} = 0; 2087 let Inst{11-15} = 0; 2088 let Inst{16-20} = VB; 2089 let Inst{21-31} = xo; 2090} 2091 2092// e.g. [PO VRT EO VRB XO] 2093class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 2094 string asmstr, InstrItinClass itin, list<dag> pattern> 2095 : I<4, OOL, IOL, asmstr, itin> { 2096 bits<5> VD; 2097 bits<5> VB; 2098 2099 let Pattern = pattern; 2100 2101 let Inst{6-10} = VD; 2102 let Inst{11-15} = eo; 2103 let Inst{16-20} = VB; 2104 let Inst{21-31} = xo; 2105} 2106 2107/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2108class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2109 InstrItinClass itin, list<dag> pattern> 2110 : I<4, OOL, IOL, asmstr, itin> { 2111 bits<5> VD; 2112 bits<5> VA; 2113 bits<1> ST; 2114 bits<4> SIX; 2115 2116 let Pattern = pattern; 2117 2118 let Inst{6-10} = VD; 2119 let Inst{11-15} = VA; 2120 let Inst{16} = ST; 2121 let Inst{17-20} = SIX; 2122 let Inst{21-31} = xo; 2123} 2124 2125/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2126class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2127 InstrItinClass itin, list<dag> pattern> 2128 : I<4, OOL, IOL, asmstr, itin> { 2129 bits<5> VD; 2130 bits<5> VA; 2131 2132 let Pattern = pattern; 2133 2134 let Inst{6-10} = VD; 2135 let Inst{11-15} = VA; 2136 let Inst{16-20} = 0; 2137 let Inst{21-31} = xo; 2138} 2139 2140// E-4 VXR-Form 2141class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2142 InstrItinClass itin, list<dag> pattern> 2143 : I<4, OOL, IOL, asmstr, itin> { 2144 bits<5> VD; 2145 bits<5> VA; 2146 bits<5> VB; 2147 bit RC = 0; 2148 2149 let Pattern = pattern; 2150 2151 let Inst{6-10} = VD; 2152 let Inst{11-15} = VA; 2153 let Inst{16-20} = VB; 2154 let Inst{21} = RC; 2155 let Inst{22-31} = xo; 2156} 2157 2158// VX-Form: [PO VRT EO VRB 1 PS XO] 2159class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2160 dag OOL, dag IOL, string asmstr, 2161 InstrItinClass itin, list<dag> pattern> 2162 : I<4, OOL, IOL, asmstr, itin> { 2163 bits<5> VD; 2164 bits<5> VB; 2165 bit PS; 2166 2167 let Pattern = pattern; 2168 2169 let Inst{6-10} = VD; 2170 let Inst{11-15} = eo; 2171 let Inst{16-20} = VB; 2172 let Inst{21} = 1; 2173 let Inst{22} = PS; 2174 let Inst{23-31} = xo; 2175} 2176 2177// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2178class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2179 InstrItinClass itin, list<dag> pattern> 2180 : I<4, OOL, IOL, asmstr, itin> { 2181 bits<5> VD; 2182 bits<5> VA; 2183 bits<5> VB; 2184 bit PS; 2185 2186 let Pattern = pattern; 2187 2188 let Inst{6-10} = VD; 2189 let Inst{11-15} = VA; 2190 let Inst{16-20} = VB; 2191 let Inst{21} = 1; 2192 let Inst{22} = PS; 2193 let Inst{23-31} = xo; 2194} 2195 2196class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 2197 string asmstr, InstrItinClass itin, 2198 list<dag> pattern> 2199 : I<opcode, OOL, IOL, asmstr, itin> { 2200 bits<3> BF; 2201 bits<5> FRA; 2202 bits<6> DCM; 2203 2204 let Pattern = pattern; 2205 2206 let Inst{6-8} = BF; 2207 let Inst{9-10} = 0; 2208 let Inst{11-15} = FRA; 2209 let Inst{16-21} = DCM; 2210 let Inst{22-30} = xo; 2211 let Inst{31} = 0; 2212} 2213 2214class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 2215 string asmstr, list<dag> pattern, InstrItinClass itin> 2216 : I<opcode, OOL, IOL, asmstr, itin> { 2217 2218 bits<5> FRT; 2219 bits<5> FRA; 2220 bits<6> SH; 2221 2222 let Pattern = pattern; 2223 2224 bit RC = 0; // set by isRecordForm 2225 2226 let Inst{6 - 10} = FRT; 2227 let Inst{11 - 15} = FRA; 2228 let Inst{16 - 21} = SH; 2229 let Inst{22 - 30} = xo; 2230 let Inst{31} = RC; 2231} 2232 2233class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2234 InstrItinClass itin, list<dag> pattern> 2235 : I<opcode, OOL, IOL, asmstr, itin> { 2236 bits<5> VRT; 2237 bit R; 2238 bits<5> VRB; 2239 bits<2> idx; 2240 2241 let Pattern = pattern; 2242 2243 bit RC = 0; // set by isRecordForm 2244 2245 let Inst{6-10} = VRT; 2246 let Inst{11-14} = 0; 2247 let Inst{15} = R; 2248 let Inst{16-20} = VRB; 2249 let Inst{21-22} = idx; 2250 let Inst{23-30} = xo; 2251 let Inst{31} = RC; 2252} 2253 2254class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2255 string asmstr, InstrItinClass itin, list<dag> pattern> 2256 : I<opcode, OOL, IOL, asmstr, itin> { 2257 bits<5> RT; 2258 bits<5> RA; 2259 bits<5> RB; 2260 bits<2> CY; 2261 2262 let Pattern = pattern; 2263 2264 let Inst{6-10} = RT; 2265 let Inst{11-15} = RA; 2266 let Inst{16-20} = RB; 2267 let Inst{21-22} = CY; 2268 let Inst{23-30} = xo; 2269 let Inst{31} = 0; 2270} 2271 2272class Z23Form_FRTAB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2273 string asmstr, list<dag> pattern> 2274 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 2275 bits<5> FRT; 2276 bits<5> FRA; 2277 bits<5> FRB; 2278 bits<2> RMC; 2279 2280 let Pattern = pattern; 2281 2282 bit RC = 0; // set by isRecordForm 2283 2284 let Inst{6 - 10} = FRT; 2285 let Inst{11 - 15} = FRA; 2286 let Inst{16 - 20} = FRB; 2287 let Inst{21 - 22} = RMC; 2288 let Inst{23 - 30} = xo; 2289 let Inst{31} = RC; 2290} 2291 2292class Z23Form_TE5_FRTB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2293 string asmstr, list<dag> pattern> 2294 : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, asmstr, pattern> { 2295 bits<5> TE; 2296 let FRA = TE; 2297} 2298 2299class Z23Form_FRTB5_R1_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2300 string asmstr, list<dag> pattern> 2301 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 2302 bits<5> FRT; 2303 bits<1> R; 2304 bits<5> FRB; 2305 bits<2> RMC; 2306 2307 let Pattern = pattern; 2308 2309 bit RC = 0; // set by isRecordForm 2310 2311 let Inst{6 - 10} = FRT; 2312 let Inst{11 - 14} = 0; 2313 let Inst{15} = R; 2314 let Inst{16 - 20} = FRB; 2315 let Inst{21 - 22} = RMC; 2316 let Inst{23 - 30} = xo; 2317 let Inst{31} = RC; 2318} 2319 2320//===----------------------------------------------------------------------===// 2321// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2322// stuff 2323class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2324 : I<0, OOL, IOL, asmstr, NoItinerary> { 2325 let isCodeGenOnly = 1; 2326 let PPC64 = 0; 2327 let Pattern = pattern; 2328 let Inst{31-0} = 0; 2329 let hasNoSchedulingInfo = 1; 2330} 2331 2332// Instruction that require custom insertion support 2333// a.k.a. ISelPseudos, however, these won't have isPseudo set 2334class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2335 list<dag> pattern> 2336 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2337 let usesCustomInserter = 1; 2338} 2339 2340// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2341// files is set only for PostRAPseudo 2342class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2343 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2344 let isPseudo = 1; 2345} 2346 2347class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2348 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2349 2350