1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Indicate that this instruction produces a result that is sign extended from 49 // 32 bits to 64 bits. 50 bits<1> SExt32To64 = 0; 51 let TSFlags{8} = SExt32To64; 52 53 // Indicate that this instruction produces a result that is zero extended from 54 // 32 bits to 64 bits. 55 bits<1> ZExt32To64 = 0; 56 let TSFlags{9} = ZExt32To64; 57 58 // Fields used for relation models. 59 string BaseName = ""; 60 61 // For cases where multiple instruction definitions really represent the 62 // same underlying instruction but with one definition for 64-bit arguments 63 // and one for 32-bit arguments, this bit breaks the degeneracy between 64 // the two forms and allows TableGen to generate mapping tables. 65 bit Interpretation64Bit = 0; 66} 67 68class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 69class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 70class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 71class PPC970_MicroCode; 72 73class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 74class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 75class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 76class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 77class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 78class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 79class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 80class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 81 82class XFormMemOp { bits<1> XFormMemOp = 1; } 83class SExt32To64 { bits<1> SExt32To64 = 1; } 84class ZExt32To64 { bits<1> ZExt32To64 = 1; } 85 86// Two joined instructions; used to emit two adjacent instructions as one. 87// The itinerary from the first instruction is used for scheduling and 88// classification. 89class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 90 InstrItinClass itin> 91 : Instruction { 92 field bits<64> Inst; 93 field bits<64> SoftFail = 0; 94 let Size = 8; 95 96 bit PPC64 = 0; // Default value, override with isPPC64 97 98 let Namespace = "PPC"; 99 let Inst{0-5} = opcode1; 100 let Inst{32-37} = opcode2; 101 let OutOperandList = OOL; 102 let InOperandList = IOL; 103 let AsmString = asmstr; 104 let Itinerary = itin; 105 106 bits<1> PPC970_First = 0; 107 bits<1> PPC970_Single = 0; 108 bits<1> PPC970_Cracked = 0; 109 bits<3> PPC970_Unit = 0; 110 111 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 112 /// these must be reflected there! See comments there for what these are. 113 let TSFlags{0} = PPC970_First; 114 let TSFlags{1} = PPC970_Single; 115 let TSFlags{2} = PPC970_Cracked; 116 let TSFlags{5-3} = PPC970_Unit; 117 118 // Fields used for relation models. 119 string BaseName = ""; 120 bit Interpretation64Bit = 0; 121} 122 123// Base class for all X-Form memory instructions 124class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 125 InstrItinClass itin> 126 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 127 128// 1.7.1 I-Form 129class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 130 InstrItinClass itin, list<dag> pattern> 131 : I<opcode, OOL, IOL, asmstr, itin> { 132 let Pattern = pattern; 133 bits<24> LI; 134 135 let Inst{6-29} = LI; 136 let Inst{30} = aa; 137 let Inst{31} = lk; 138} 139 140// 1.7.2 B-Form 141class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 144 bits<3> CR; 145 bits<14> BD; 146 147 bits<5> BI; 148 let BI{0-1} = BIBO{5-6}; 149 let BI{2-4} = CR{0-2}; 150 151 let Inst{6-10} = BIBO{4-0}; 152 let Inst{11-15} = BI; 153 let Inst{16-29} = BD; 154 let Inst{30} = aa; 155 let Inst{31} = lk; 156} 157 158class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 159 string asmstr> 160 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 161 let BIBO{4-0} = bo; 162 let BIBO{6-5} = 0; 163 let CR = 0; 164} 165 166class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<14> BD; 170 171 let Inst{6-10} = bo; 172 let Inst{11-15} = bi; 173 let Inst{16-29} = BD; 174 let Inst{30} = aa; 175 let Inst{31} = lk; 176} 177 178class BForm_3<bits<6> opcode, bit aa, bit lk, 179 dag OOL, dag IOL, string asmstr> 180 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 181 bits<5> BO; 182 bits<5> BI; 183 bits<14> BD; 184 185 let Inst{6-10} = BO; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_3_at<bits<6> opcode, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BO; 196 bits<2> at; 197 bits<5> BI; 198 bits<14> BD; 199 200 let Inst{6-8} = BO{4-2}; 201 let Inst{9-10} = at; 202 let Inst{11-15} = BI; 203 let Inst{16-29} = BD; 204 let Inst{30} = aa; 205 let Inst{31} = lk; 206} 207 208class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 209 dag OOL, dag IOL, string asmstr> 210 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 211 bits<5> BI; 212 bits<14> BD; 213 214 let Inst{6-10} = bo; 215 let Inst{11-15} = BI; 216 let Inst{16-29} = BD; 217 let Inst{30} = aa; 218 let Inst{31} = lk; 219} 220 221// 1.7.3 SC-Form 222class SCForm<bits<6> opcode, bits<1> xo, 223 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 224 list<dag> pattern> 225 : I<opcode, OOL, IOL, asmstr, itin> { 226 bits<7> LEV; 227 228 let Pattern = pattern; 229 230 let Inst{20-26} = LEV; 231 let Inst{30} = xo; 232} 233 234// 1.7.4 D-Form 235class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : I<opcode, OOL, IOL, asmstr, itin> { 238 bits<5> A; 239 bits<5> B; 240 bits<16> C; 241 242 let Pattern = pattern; 243 244 let Inst{6-10} = A; 245 let Inst{11-15} = B; 246 let Inst{16-31} = C; 247} 248 249class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 250 InstrItinClass itin, list<dag> pattern> 251 : I<opcode, OOL, IOL, asmstr, itin> { 252 bits<5> A; 253 bits<21> Addr; 254 255 let Pattern = pattern; 256 257 let Inst{6-10} = A; 258 let Inst{11-15} = Addr{20-16}; // Base Reg 259 let Inst{16-31} = Addr{15-0}; // Displacement 260} 261 262class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 263 InstrItinClass itin, list<dag> pattern> 264 : I<opcode, OOL, IOL, asmstr, itin> { 265 bits<5> A; 266 bits<16> C; 267 bits<5> B; 268 269 let Pattern = pattern; 270 271 let Inst{6-10} = A; 272 let Inst{11-15} = B; 273 let Inst{16-31} = C; 274} 275 276 277class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 278 InstrItinClass itin, list<dag> pattern> 279 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 280 281 // Even though ADDIC_rec does not really have an RC bit, provide 282 // the declaration of one here so that isRecordForm has something to set. 283 bit RC = 0; 284} 285 286class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 287 InstrItinClass itin, list<dag> pattern> 288 : I<opcode, OOL, IOL, asmstr, itin> { 289 bits<5> A; 290 bits<16> B; 291 292 let Pattern = pattern; 293 294 let Inst{6-10} = A; 295 let Inst{11-15} = 0; 296 let Inst{16-31} = B; 297} 298 299class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 300 InstrItinClass itin, list<dag> pattern> 301 : I<opcode, OOL, IOL, asmstr, itin> { 302 bits<5> B; 303 bits<5> A; 304 bits<16> C; 305 306 let Pattern = pattern; 307 308 let Inst{6-10} = A; 309 let Inst{11-15} = B; 310 let Inst{16-31} = C; 311} 312 313class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 314 InstrItinClass itin, list<dag> pattern> 315 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 316 let A = 0; 317 let Addr = 0; 318} 319 320class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 321 string asmstr, InstrItinClass itin, 322 list<dag> pattern> 323 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 324 let A = R; 325 let B = R; 326 let C = 0; 327} 328 329class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 330 dag OOL, dag IOL, string asmstr, 331 InstrItinClass itin, list<dag> pattern> 332 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 333 bits<5> A; 334 bits<21> Addr; 335 336 let Pattern = pattern; 337 bits<24> LI; 338 339 let Inst{6-29} = LI; 340 let Inst{30} = aa; 341 let Inst{31} = lk; 342 343 let Inst{38-42} = A; 344 let Inst{43-47} = Addr{20-16}; // Base Reg 345 let Inst{48-63} = Addr{15-0}; // Displacement 346} 347 348// This is used to emit BL8+NOP. 349class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 350 dag OOL, dag IOL, string asmstr, 351 InstrItinClass itin, list<dag> pattern> 352 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 353 OOL, IOL, asmstr, itin, pattern> { 354 let A = 0; 355 let Addr = 0; 356} 357 358class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 359 InstrItinClass itin> 360 : I<opcode, OOL, IOL, asmstr, itin> { 361 bits<3> BF; 362 bits<1> L; 363 bits<5> RA; 364 bits<16> I; 365 366 let Inst{6-8} = BF; 367 let Inst{9} = 0; 368 let Inst{10} = L; 369 let Inst{11-15} = RA; 370 let Inst{16-31} = I; 371} 372 373class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 374 InstrItinClass itin> 375 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 376 let L = PPC64; 377} 378 379class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 380 InstrItinClass itin> 381 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 382 383class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 384 InstrItinClass itin> 385 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 386 let L = PPC64; 387} 388 389 390// 1.7.5 DS-Form 391class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 392 InstrItinClass itin, list<dag> pattern> 393 : I<opcode, OOL, IOL, asmstr, itin> { 394 bits<5> RST; 395 bits<19> DS_RA; 396 397 let Pattern = pattern; 398 399 let Inst{6-10} = RST; 400 let Inst{11-15} = DS_RA{18-14}; // Register # 401 let Inst{16-29} = DS_RA{13-0}; // Displacement. 402 let Inst{30-31} = xo; 403} 404 405// ISA V3.0B 1.6.6 DX-Form 406class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 407 InstrItinClass itin, list<dag> pattern> 408 : I<opcode, OOL, IOL, asmstr, itin> { 409 bits<5> RT; 410 bits<16> D; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = RT; 415 let Inst{11-15} = D{5-1}; // d1 416 let Inst{16-25} = D{15-6}; // d0 417 let Inst{26-30} = xo; 418 let Inst{31} = D{0}; // d2 419} 420 421// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 422class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 423 string asmstr, InstrItinClass itin, list<dag> pattern> 424 : I<opcode, OOL, IOL, asmstr, itin> { 425 bits<6> XT; 426 bits<17> DS_RA; 427 428 let Pattern = pattern; 429 430 let Inst{6-10} = XT{4-0}; 431 let Inst{11-15} = DS_RA{16-12}; // Register # 432 let Inst{16-27} = DS_RA{11-0}; // Displacement. 433 let Inst{28} = XT{5}; 434 let Inst{29-31} = xo; 435} 436 437class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 438 string asmstr, InstrItinClass itin, 439 list<dag> pattern> 440 : I<opcode, OOL, IOL, asmstr, itin> { 441 bits<5> RTp; 442 bits<17> DQ_RA; 443 let Pattern = pattern; 444 445 let Inst{6-10} = RTp{4-0}; 446 let Inst{11-15} = DQ_RA{16-12}; // Register # 447 let Inst{16-27} = DQ_RA{11-0}; // Displacement. 448 let Inst{28-31} = xo; 449} 450 451// 1.7.6 X-Form 452class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 453 InstrItinClass itin, list<dag> pattern> 454 : I<opcode, OOL, IOL, asmstr, itin> { 455 bits<5> RST; 456 bits<5> A; 457 bits<5> B; 458 459 let Pattern = pattern; 460 461 bit RC = 0; // set by isRecordForm 462 463 let Inst{6-10} = RST; 464 let Inst{11-15} = A; 465 let Inst{16-20} = B; 466 let Inst{21-30} = xo; 467 let Inst{31} = RC; 468} 469 470class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 471 string asmstr, InstrItinClass itin, 472 list<dag> pattern> 473 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 474 475class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 476 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 477 let RST = 0; 478} 479 480class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 481 InstrItinClass itin> 482 : I<opcode, OOL, IOL, asmstr, itin> { 483 let Inst{21-30} = xo; 484} 485 486// This is the same as XForm_base_r3xo, but the first two operands are swapped 487// when code is emitted. 488class XForm_base_r3xo_swapped 489 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 490 InstrItinClass itin> 491 : I<opcode, OOL, IOL, asmstr, itin> { 492 bits<5> A; 493 bits<5> RST; 494 bits<5> B; 495 496 bit RC = 0; // set by isRecordForm 497 498 let Inst{6-10} = RST; 499 let Inst{11-15} = A; 500 let Inst{16-20} = B; 501 let Inst{21-30} = xo; 502 let Inst{31} = RC; 503} 504 505 506class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 507 InstrItinClass itin, list<dag> pattern> 508 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 509 510class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 511 InstrItinClass itin, list<dag> pattern> 512 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 513 514class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 515 InstrItinClass itin, list<dag> pattern> 516 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 517 let RST = 0; 518} 519 520class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 521 InstrItinClass itin, list<dag> pattern> 522 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 523 let A = 0; 524 let B = 0; 525} 526 527class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin, list<dag> pattern> 529 : I<opcode, OOL, IOL, asmstr, itin> { 530 bits<5> RST; 531 bits<5> A; 532 bits<1> WS; 533 534 let Pattern = pattern; 535 536 let Inst{6-10} = RST; 537 let Inst{11-15} = A; 538 let Inst{20} = WS; 539 let Inst{21-30} = xo; 540 let Inst{31} = 0; 541} 542 543class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 544 InstrItinClass itin, list<dag> pattern> 545 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 546 let Pattern = pattern; 547} 548 549class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 550 InstrItinClass itin, list<dag> pattern> 551 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 552 553class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 554 InstrItinClass itin, list<dag> pattern> 555 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 556 557class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 558 InstrItinClass itin, list<dag> pattern> 559 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 560 let Pattern = pattern; 561} 562 563class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 564 InstrItinClass itin, list<dag> pattern> 565 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 566 let B = 0; 567 let Pattern = pattern; 568} 569 570class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 571 InstrItinClass itin> 572 : I<opcode, OOL, IOL, asmstr, itin> { 573 bits<3> BF; 574 bits<1> L; 575 bits<5> RA; 576 bits<5> RB; 577 578 let Inst{6-8} = BF; 579 let Inst{9} = 0; 580 let Inst{10} = L; 581 let Inst{11-15} = RA; 582 let Inst{16-20} = RB; 583 let Inst{21-30} = xo; 584 let Inst{31} = 0; 585} 586 587class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 588 InstrItinClass itin> 589 : I<opcode, OOL, IOL, asmstr, itin> { 590 bits<4> CT; 591 bits<5> RA; 592 bits<5> RB; 593 594 let Inst{6} = 0; 595 let Inst{7-10} = CT; 596 let Inst{11-15} = RA; 597 let Inst{16-20} = RB; 598 let Inst{21-30} = xo; 599 let Inst{31} = 0; 600} 601 602class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 603 InstrItinClass itin> 604 : I<opcode, OOL, IOL, asmstr, itin> { 605 bits<5> RS; 606 bits<4> SR; 607 608 let Inst{6-10} = RS; 609 let Inst{12-15} = SR; 610 let Inst{21-30} = xo; 611} 612 613class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 614 InstrItinClass itin> 615 : I<opcode, OOL, IOL, asmstr, itin> { 616 bits<5> MO; 617 618 let Inst{6-10} = MO; 619 let Inst{21-30} = xo; 620} 621 622class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 623 InstrItinClass itin> 624 : I<opcode, OOL, IOL, asmstr, itin> { 625 bits<5> RS; 626 bits<5> RB; 627 628 let Inst{6-10} = RS; 629 let Inst{16-20} = RB; 630 let Inst{21-30} = xo; 631} 632 633class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 634 InstrItinClass itin> 635 : I<opcode, OOL, IOL, asmstr, itin> { 636 bits<5> RS; 637 bits<1> L; 638 639 let Inst{6-10} = RS; 640 let Inst{15} = L; 641 let Inst{21-30} = xo; 642} 643 644class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 645 InstrItinClass itin> 646 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 647 let L = PPC64; 648} 649 650class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 651 InstrItinClass itin> 652 : I<opcode, OOL, IOL, asmstr, itin> { 653 bits<3> BF; 654 bits<5> FRA; 655 bits<5> FRB; 656 657 let Inst{6-8} = BF; 658 let Inst{9-10} = 0; 659 let Inst{11-15} = FRA; 660 let Inst{16-20} = FRB; 661 let Inst{21-30} = xo; 662 let Inst{31} = 0; 663} 664 665class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 666 InstrItinClass itin, list<dag> pattern> 667 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 668 let FRA = 0; 669 let Pattern = pattern; 670} 671 672class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 673 InstrItinClass itin, list<dag> pattern> 674 : I<opcode, OOL, IOL, asmstr, itin> { 675 bits<5> FRT; 676 bits<5> FRA; 677 bits<5> FRB; 678 679 let Pattern = pattern; 680 681 let Inst{6-10} = FRT; 682 let Inst{11-15} = FRA; 683 let Inst{16-20} = FRB; 684 let Inst{21-30} = xo; 685 let Inst{31} = 0; 686} 687 688class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 689 InstrItinClass itin, list<dag> pattern> 690 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 691 let FRA = 0; 692} 693 694class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 695 InstrItinClass itin, list<dag> pattern> 696 : I<opcode, OOL, IOL, asmstr, itin> { 697 bits<5> FRT; 698 bits<5> FRA; 699 bits<5> FRB; 700 bits<4> tttt; 701 702 let Pattern = pattern; 703 704 let Inst{6-10} = FRT; 705 let Inst{11-15} = FRA; 706 let Inst{16-20} = FRB; 707 let Inst{21-24} = tttt; 708 let Inst{25-30} = xo; 709 let Inst{31} = 0; 710} 711 712class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 713 InstrItinClass itin, list<dag> pattern> 714 : I<opcode, OOL, IOL, asmstr, itin> { 715 let Pattern = pattern; 716 let Inst{6-10} = 31; 717 let Inst{11-15} = 0; 718 let Inst{16-20} = 0; 719 let Inst{21-30} = xo; 720 let Inst{31} = 0; 721} 722 723class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 724 string asmstr, InstrItinClass itin, list<dag> pattern> 725 : I<opcode, OOL, IOL, asmstr, itin> { 726 bits<2> L; 727 728 let Pattern = pattern; 729 let Inst{6-8} = 0; 730 let Inst{9-10} = L; 731 let Inst{11-15} = 0; 732 let Inst{16-20} = 0; 733 let Inst{21-30} = xo; 734 let Inst{31} = 0; 735} 736 737class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 738 string asmstr, InstrItinClass itin, list<dag> pattern> 739 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 740 let L = 0; 741} 742 743class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 744 InstrItinClass itin, list<dag> pattern> 745 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 746} 747 748class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 749 string asmstr, InstrItinClass itin, list<dag> pattern> 750 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 751} 752 753// [PO RT /// RB XO RC] 754class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 755 InstrItinClass itin, list<dag> pattern> 756 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 757 let A = 0; 758} 759 760class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 761 string asmstr, InstrItinClass itin, list<dag> pattern> 762 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 763} 764 765class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 766 InstrItinClass itin, list<dag> pattern> 767 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 768} 769 770// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 771// numbers presumably relates to some document, but I haven't found it. 772class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 773 InstrItinClass itin, list<dag> pattern> 774 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 775 let Pattern = pattern; 776 777 bit RC = 0; // set by isRecordForm 778 779 let Inst{6-10} = RST; 780 let Inst{11-20} = 0; 781 let Inst{21-30} = xo; 782 let Inst{31} = RC; 783} 784class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 785 InstrItinClass itin, list<dag> pattern> 786 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 787 let Pattern = pattern; 788 bits<5> FM; 789 790 bit RC = 0; // set by isRecordForm 791 792 let Inst{6-10} = FM; 793 let Inst{11-20} = 0; 794 let Inst{21-30} = xo; 795 let Inst{31} = RC; 796} 797 798class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 799 InstrItinClass itin> 800 : I<opcode, OOL, IOL, asmstr, itin> { 801 bits<5> RT; 802 bits<3> BFA; 803 804 let Inst{6-10} = RT; 805 let Inst{11-13} = BFA; 806 let Inst{14-15} = 0; 807 let Inst{16-20} = 0; 808 let Inst{21-30} = xo; 809 let Inst{31} = 0; 810} 811 812class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 813 InstrItinClass itin> 814 : I<opcode, OOL, IOL, asmstr, itin> { 815 bits<5> RT; 816 bits<2> L; 817 818 let Inst{6-10} = RT; 819 let Inst{11-13} = 0; 820 let Inst{14-15} = L; 821 let Inst{16-20} = 0; 822 let Inst{21-30} = xo; 823 let Inst{31} = 0; 824} 825 826class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 827 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 828 list<dag> pattern> 829 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 830 let Pattern = pattern; 831 832 let Inst{6-10} = RST; 833 let Inst{11-12} = xo1; 834 let Inst{13-15} = xo2; 835 let Inst{16-20} = 0; 836 let Inst{21-30} = xo; 837 let Inst{31} = 0; 838} 839 840class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 841 bits<10> xo, dag OOL, dag IOL, string asmstr, 842 InstrItinClass itin, list<dag> pattern> 843 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 844 let Pattern = pattern; 845 bits<5> FRB; 846 847 let Inst{6-10} = RST; 848 let Inst{11-12} = xo1; 849 let Inst{13-15} = xo2; 850 let Inst{16-20} = FRB; 851 let Inst{21-30} = xo; 852 let Inst{31} = 0; 853} 854 855class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 856 bits<10> xo, dag OOL, dag IOL, string asmstr, 857 InstrItinClass itin, list<dag> pattern> 858 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 859 let Pattern = pattern; 860 bits<3> DRM; 861 862 let Inst{6-10} = RST; 863 let Inst{11-12} = xo1; 864 let Inst{13-15} = xo2; 865 let Inst{16-17} = 0; 866 let Inst{18-20} = DRM; 867 let Inst{21-30} = xo; 868 let Inst{31} = 0; 869} 870 871class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 872 bits<10> xo, dag OOL, dag IOL, string asmstr, 873 InstrItinClass itin, list<dag> pattern> 874 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 875 let Pattern = pattern; 876 bits<2> RM; 877 878 let Inst{6-10} = RST; 879 let Inst{11-12} = xo1; 880 let Inst{13-15} = xo2; 881 let Inst{16-18} = 0; 882 let Inst{19-20} = RM; 883 let Inst{21-30} = xo; 884 let Inst{31} = 0; 885} 886 887 888class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 889 InstrItinClass itin, list<dag> pattern> 890 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 891 let RST = 0; 892 let A = 0; 893 let B = 0; 894} 895 896class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 897 InstrItinClass itin, list<dag> pattern> 898 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 899 let RST = 0; 900 let A = 0; 901} 902 903class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 904 string asmstr, InstrItinClass itin> 905 : I<opcode, OOL, IOL, asmstr, itin> { 906 bit R; 907 908 bit RC = 1; 909 910 let Inst{6-9} = 0; 911 let Inst{10} = R; 912 let Inst{11-20} = 0; 913 let Inst{21-30} = xo; 914 let Inst{31} = RC; 915} 916 917class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 918 string asmstr, InstrItinClass itin> 919 : I<opcode, OOL, IOL, asmstr, itin> { 920 bit A; 921 922 bit RC = 1; 923 924 let Inst{6} = A; 925 let Inst{7-20} = 0; 926 let Inst{21-30} = xo; 927 let Inst{31} = RC; 928} 929 930class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 931 InstrItinClass itin> 932 : I<opcode, OOL, IOL, asmstr, itin> { 933 bit L; 934 935 bit RC = 0; // set by isRecordForm 936 937 let Inst{7-9} = 0; 938 let Inst{10} = L; 939 let Inst{11-20} = 0; 940 let Inst{21-30} = xo; 941 let Inst{31} = RC; 942} 943 944class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 945 InstrItinClass itin> 946 : I<opcode, OOL, IOL, asmstr, itin> { 947 bits<3> BF; 948 949 bit RC = 0; 950 951 let Inst{6-8} = BF; 952 let Inst{9-20} = 0; 953 let Inst{21-30} = xo; 954 let Inst{31} = RC; 955} 956 957// [PO RT RA RB XO /] 958class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 959 string asmstr, InstrItinClass itin, list<dag> pattern> 960 : I<opcode, OOL, IOL, asmstr, itin> { 961 bits<3> BF; 962 bits<1> L; 963 bits<5> RA; 964 bits<5> RB; 965 966 let Pattern = pattern; 967 968 let Inst{6-8} = BF; 969 let Inst{9} = 0; 970 let Inst{10} = L; 971 let Inst{11-15} = RA; 972 let Inst{16-20} = RB; 973 let Inst{21-30} = xo; 974 let Inst{31} = 0; 975} 976 977// Same as XForm_17 but with GPR's and new naming convention 978class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 979 string asmstr, InstrItinClass itin, list<dag> pattern> 980 : I<opcode, OOL, IOL, asmstr, itin> { 981 bits<3> BF; 982 bits<5> RA; 983 bits<5> RB; 984 985 let Pattern = pattern; 986 987 let Inst{6-8} = BF; 988 let Inst{9-10} = 0; 989 let Inst{11-15} = RA; 990 let Inst{16-20} = RB; 991 let Inst{21-30} = xo; 992 let Inst{31} = 0; 993} 994 995// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 996class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 997 string asmstr, InstrItinClass itin, list<dag> pattern> 998 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 999 let A = xo2; 1000} 1001 1002class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1003 string asmstr, InstrItinClass itin, list<dag> pattern> 1004 : I<opcode, OOL, IOL, asmstr, itin> { 1005 bits<3> BF; 1006 bits<7> DCMX; 1007 bits<5> VB; 1008 1009 let Pattern = pattern; 1010 1011 let Inst{6-8} = BF; 1012 let Inst{9-15} = DCMX; 1013 let Inst{16-20} = VB; 1014 let Inst{21-30} = xo; 1015 let Inst{31} = 0; 1016} 1017 1018class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1019 string asmstr, InstrItinClass itin, list<dag> pattern> 1020 : I<opcode, OOL, IOL, asmstr, itin> { 1021 bits<6> XT; 1022 bits<8> IMM8; 1023 1024 let Pattern = pattern; 1025 1026 let Inst{6-10} = XT{4-0}; 1027 let Inst{11-12} = 0; 1028 let Inst{13-20} = IMM8; 1029 let Inst{21-30} = xo; 1030 let Inst{31} = XT{5}; 1031} 1032 1033// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1034// to specify an SDAG pattern for matching. 1035class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1036 string asmstr, InstrItinClass itin> 1037 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1038} 1039 1040class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1041 InstrItinClass itin> 1042 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1043 let FRA = 0; 1044 let FRB = 0; 1045} 1046 1047// [PO /// L RA RB XO /] 1048class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1049 string asmstr, InstrItinClass itin, list<dag> pattern> 1050 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1051 let BF = 0; 1052 let Pattern = pattern; 1053 1054 bit RC = 0; 1055 let Inst{31} = RC; 1056} 1057 1058// XX*-Form (VSX) 1059class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1060 InstrItinClass itin, list<dag> pattern> 1061 : I<opcode, OOL, IOL, asmstr, itin> { 1062 bits<6> XT; 1063 bits<5> A; 1064 bits<5> B; 1065 1066 let Pattern = pattern; 1067 1068 let Inst{6-10} = XT{4-0}; 1069 let Inst{11-15} = A; 1070 let Inst{16-20} = B; 1071 let Inst{21-30} = xo; 1072 let Inst{31} = XT{5}; 1073} 1074 1075class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1076 string asmstr, InstrItinClass itin, list<dag> pattern> 1077 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1078 1079class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1080 string asmstr, InstrItinClass itin, list<dag> pattern> 1081 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1082 let B = 0; 1083} 1084 1085class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1086 InstrItinClass itin, list<dag> pattern> 1087 : I<opcode, OOL, IOL, asmstr, itin> { 1088 bits<6> XT; 1089 bits<6> XB; 1090 1091 let Pattern = pattern; 1092 1093 let Inst{6-10} = XT{4-0}; 1094 let Inst{11-15} = 0; 1095 let Inst{16-20} = XB{4-0}; 1096 let Inst{21-29} = xo; 1097 let Inst{30} = XB{5}; 1098 let Inst{31} = XT{5}; 1099} 1100 1101class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1102 InstrItinClass itin, list<dag> pattern> 1103 : I<opcode, OOL, IOL, asmstr, itin> { 1104 bits<3> CR; 1105 bits<6> XB; 1106 1107 let Pattern = pattern; 1108 1109 let Inst{6-8} = CR; 1110 let Inst{9-15} = 0; 1111 let Inst{16-20} = XB{4-0}; 1112 let Inst{21-29} = xo; 1113 let Inst{30} = XB{5}; 1114 let Inst{31} = 0; 1115} 1116 1117class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1118 InstrItinClass itin, list<dag> pattern> 1119 : I<opcode, OOL, IOL, asmstr, itin> { 1120 bits<6> XT; 1121 bits<6> XB; 1122 bits<2> D; 1123 1124 let Pattern = pattern; 1125 1126 let Inst{6-10} = XT{4-0}; 1127 let Inst{11-13} = 0; 1128 let Inst{14-15} = D; 1129 let Inst{16-20} = XB{4-0}; 1130 let Inst{21-29} = xo; 1131 let Inst{30} = XB{5}; 1132 let Inst{31} = XT{5}; 1133} 1134 1135class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1136 string asmstr, InstrItinClass itin, list<dag> pattern> 1137 : I<opcode, OOL, IOL, asmstr, itin> { 1138 bits<6> XT; 1139 bits<6> XB; 1140 bits<5> UIM5; 1141 1142 let Pattern = pattern; 1143 1144 let Inst{6-10} = XT{4-0}; 1145 let Inst{11-15} = UIM5; 1146 let Inst{16-20} = XB{4-0}; 1147 let Inst{21-29} = xo; 1148 let Inst{30} = XB{5}; 1149 let Inst{31} = XT{5}; 1150} 1151 1152// [PO T XO B XO BX /] 1153class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1154 string asmstr, InstrItinClass itin, list<dag> pattern> 1155 : I<opcode, OOL, IOL, asmstr, itin> { 1156 bits<5> RT; 1157 bits<6> XB; 1158 1159 let Pattern = pattern; 1160 1161 let Inst{6-10} = RT; 1162 let Inst{11-15} = xo2; 1163 let Inst{16-20} = XB{4-0}; 1164 let Inst{21-29} = xo; 1165 let Inst{30} = XB{5}; 1166 let Inst{31} = 0; 1167} 1168 1169// [PO T XO B XO BX TX] 1170class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1171 string asmstr, InstrItinClass itin, list<dag> pattern> 1172 : I<opcode, OOL, IOL, asmstr, itin> { 1173 bits<6> XT; 1174 bits<6> XB; 1175 1176 let Pattern = pattern; 1177 1178 let Inst{6-10} = XT{4-0}; 1179 let Inst{11-15} = xo2; 1180 let Inst{16-20} = XB{4-0}; 1181 let Inst{21-29} = xo; 1182 let Inst{30} = XB{5}; 1183 let Inst{31} = XT{5}; 1184} 1185 1186class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1187 string asmstr, InstrItinClass itin, list<dag> pattern> 1188 : I<opcode, OOL, IOL, asmstr, itin> { 1189 bits<3> BF; 1190 bits<7> DCMX; 1191 bits<6> XB; 1192 1193 let Pattern = pattern; 1194 1195 let Inst{6-8} = BF; 1196 let Inst{9-15} = DCMX; 1197 let Inst{16-20} = XB{4-0}; 1198 let Inst{21-29} = xo; 1199 let Inst{30} = XB{5}; 1200 let Inst{31} = 0; 1201} 1202 1203class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1204 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1205 list<dag> pattern> 1206 : I<opcode, OOL, IOL, asmstr, itin> { 1207 bits<6> XT; 1208 bits<7> DCMX; 1209 bits<6> XB; 1210 1211 let Pattern = pattern; 1212 1213 let Inst{6-10} = XT{4-0}; 1214 let Inst{11-15} = DCMX{4-0}; 1215 let Inst{16-20} = XB{4-0}; 1216 let Inst{21-24} = xo1; 1217 let Inst{25} = DCMX{6}; 1218 let Inst{26-28} = xo2; 1219 let Inst{29} = DCMX{5}; 1220 let Inst{30} = XB{5}; 1221 let Inst{31} = XT{5}; 1222} 1223 1224class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1225 string asmstr, InstrItinClass itin, list<dag> pattern> 1226 : I<opcode, OOL, IOL, asmstr, itin> { 1227 bits<11> D_RA_XD; 1228 bits<5> RB; 1229 1230 let Pattern = pattern; 1231 1232 let Inst{6-10} = D_RA_XD{4-0}; // D 1233 let Inst{11-15} = D_RA_XD{10-6}; // RA 1234 let Inst{16-20} = RB; 1235 let Inst{21-30} = xo; 1236 let Inst{31} = D_RA_XD{5}; // DX 1237} 1238 1239class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1240 InstrItinClass itin, list<dag> pattern> 1241 : I<opcode, OOL, IOL, asmstr, itin> { 1242 bits<6> XT; 1243 bits<6> XA; 1244 bits<6> XB; 1245 1246 let Pattern = pattern; 1247 1248 let Inst{6-10} = XT{4-0}; 1249 let Inst{11-15} = XA{4-0}; 1250 let Inst{16-20} = XB{4-0}; 1251 let Inst{21-28} = xo; 1252 let Inst{29} = XA{5}; 1253 let Inst{30} = XB{5}; 1254 let Inst{31} = XT{5}; 1255} 1256 1257class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1258 InstrItinClass itin, list<dag> pattern> 1259 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1260 let XA = XT; 1261 let XB = XT; 1262} 1263 1264class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1265 InstrItinClass itin, list<dag> pattern> 1266 : I<opcode, OOL, IOL, asmstr, itin> { 1267 bits<3> CR; 1268 bits<6> XA; 1269 bits<6> XB; 1270 1271 let Pattern = pattern; 1272 1273 let Inst{6-8} = CR; 1274 let Inst{9-10} = 0; 1275 let Inst{11-15} = XA{4-0}; 1276 let Inst{16-20} = XB{4-0}; 1277 let Inst{21-28} = xo; 1278 let Inst{29} = XA{5}; 1279 let Inst{30} = XB{5}; 1280 let Inst{31} = 0; 1281} 1282 1283class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1284 InstrItinClass itin, list<dag> pattern> 1285 : I<opcode, OOL, IOL, asmstr, itin> { 1286 bits<6> XT; 1287 bits<6> XA; 1288 bits<6> XB; 1289 bits<2> D; 1290 1291 let Pattern = pattern; 1292 1293 let Inst{6-10} = XT{4-0}; 1294 let Inst{11-15} = XA{4-0}; 1295 let Inst{16-20} = XB{4-0}; 1296 let Inst{21} = 0; 1297 let Inst{22-23} = D; 1298 let Inst{24-28} = xo; 1299 let Inst{29} = XA{5}; 1300 let Inst{30} = XB{5}; 1301 let Inst{31} = XT{5}; 1302} 1303 1304class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1305 InstrItinClass itin, list<dag> pattern> 1306 : I<opcode, OOL, IOL, asmstr, itin> { 1307 bits<6> XT; 1308 bits<6> XA; 1309 bits<6> XB; 1310 1311 let Pattern = pattern; 1312 1313 bit RC = 0; // set by isRecordForm 1314 1315 let Inst{6-10} = XT{4-0}; 1316 let Inst{11-15} = XA{4-0}; 1317 let Inst{16-20} = XB{4-0}; 1318 let Inst{21} = RC; 1319 let Inst{22-28} = xo; 1320 let Inst{29} = XA{5}; 1321 let Inst{30} = XB{5}; 1322 let Inst{31} = XT{5}; 1323} 1324 1325class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1326 InstrItinClass itin, list<dag> pattern> 1327 : I<opcode, OOL, IOL, asmstr, itin> { 1328 bits<6> XT; 1329 bits<6> XA; 1330 bits<6> XB; 1331 bits<6> XC; 1332 1333 let Pattern = pattern; 1334 1335 let Inst{6-10} = XT{4-0}; 1336 let Inst{11-15} = XA{4-0}; 1337 let Inst{16-20} = XB{4-0}; 1338 let Inst{21-25} = XC{4-0}; 1339 let Inst{26-27} = xo; 1340 let Inst{28} = XC{5}; 1341 let Inst{29} = XA{5}; 1342 let Inst{30} = XB{5}; 1343 let Inst{31} = XT{5}; 1344} 1345 1346// DCB_Form - Form X instruction, used for dcb* instructions. 1347class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1348 InstrItinClass itin, list<dag> pattern> 1349 : I<31, OOL, IOL, asmstr, itin> { 1350 bits<5> A; 1351 bits<5> B; 1352 1353 let Pattern = pattern; 1354 1355 let Inst{6-10} = immfield; 1356 let Inst{11-15} = A; 1357 let Inst{16-20} = B; 1358 let Inst{21-30} = xo; 1359 let Inst{31} = 0; 1360} 1361 1362class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1363 InstrItinClass itin, list<dag> pattern> 1364 : I<31, OOL, IOL, asmstr, itin> { 1365 bits<5> TH; 1366 bits<5> A; 1367 bits<5> B; 1368 1369 let Pattern = pattern; 1370 1371 let Inst{6-10} = TH; 1372 let Inst{11-15} = A; 1373 let Inst{16-20} = B; 1374 let Inst{21-30} = xo; 1375 let Inst{31} = 0; 1376} 1377 1378// DSS_Form - Form X instruction, used for altivec dss* instructions. 1379class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1380 InstrItinClass itin, list<dag> pattern> 1381 : I<31, OOL, IOL, asmstr, itin> { 1382 bits<2> STRM; 1383 bits<5> A; 1384 bits<5> B; 1385 1386 let Pattern = pattern; 1387 1388 let Inst{6} = T; 1389 let Inst{7-8} = 0; 1390 let Inst{9-10} = STRM; 1391 let Inst{11-15} = A; 1392 let Inst{16-20} = B; 1393 let Inst{21-30} = xo; 1394 let Inst{31} = 0; 1395} 1396 1397// 1.7.7 XL-Form 1398class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1399 InstrItinClass itin, list<dag> pattern> 1400 : I<opcode, OOL, IOL, asmstr, itin> { 1401 bits<5> CRD; 1402 bits<5> CRA; 1403 bits<5> CRB; 1404 1405 let Pattern = pattern; 1406 1407 let Inst{6-10} = CRD; 1408 let Inst{11-15} = CRA; 1409 let Inst{16-20} = CRB; 1410 let Inst{21-30} = xo; 1411 let Inst{31} = 0; 1412} 1413 1414// XL-Form for unary alias for CRNOR (CRNOT) 1415class XLForm_1s<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1416 InstrItinClass itin, list<dag> pattern> 1417 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1418 let CRB = CRA; 1419} 1420 1421class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1422 InstrItinClass itin, list<dag> pattern> 1423 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1424 let CRD = 0; 1425 let CRA = 0; 1426 let CRB = 0; 1427} 1428 1429class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1430 InstrItinClass itin, list<dag> pattern> 1431 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1432 bits<5> RT; 1433 bits<5> RB; 1434 1435 let CRD = RT; 1436 let CRA = 0; 1437 let CRB = RB; 1438} 1439 1440class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1441 InstrItinClass itin, list<dag> pattern> 1442 : I<opcode, OOL, IOL, asmstr, itin> { 1443 bits<5> CRD; 1444 1445 let Pattern = pattern; 1446 1447 let Inst{6-10} = CRD; 1448 let Inst{11-15} = CRD; 1449 let Inst{16-20} = CRD; 1450 let Inst{21-30} = xo; 1451 let Inst{31} = 0; 1452} 1453 1454class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1455 InstrItinClass itin, list<dag> pattern> 1456 : I<opcode, OOL, IOL, asmstr, itin> { 1457 bits<5> BO; 1458 bits<5> BI; 1459 bits<2> BH; 1460 1461 let Pattern = pattern; 1462 1463 let Inst{6-10} = BO; 1464 let Inst{11-15} = BI; 1465 let Inst{16-18} = 0; 1466 let Inst{19-20} = BH; 1467 let Inst{21-30} = xo; 1468 let Inst{31} = lk; 1469} 1470 1471class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1472 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1473 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1474 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1475 bits<3> CR; 1476 1477 let BO = BIBO{4-0}; 1478 let BI{0-1} = BIBO{5-6}; 1479 let BI{2-4} = CR{0-2}; 1480 let BH = 0; 1481} 1482 1483class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1484 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1485 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1486 let BO = bo; 1487 let BH = 0; 1488} 1489 1490class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1491 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1492 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1493 let BO = bo; 1494 let BI = bi; 1495 let BH = 0; 1496} 1497 1498class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1499 InstrItinClass itin> 1500 : I<opcode, OOL, IOL, asmstr, itin> { 1501 bits<3> BF; 1502 bits<3> BFA; 1503 1504 let Inst{6-8} = BF; 1505 let Inst{9-10} = 0; 1506 let Inst{11-13} = BFA; 1507 let Inst{14-15} = 0; 1508 let Inst{16-20} = 0; 1509 let Inst{21-30} = xo; 1510 let Inst{31} = 0; 1511} 1512 1513class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1514 InstrItinClass itin> 1515 : I<opcode, OOL, IOL, asmstr, itin> { 1516 bits<3> BF; 1517 bit W; 1518 bits<4> U; 1519 1520 bit RC = 0; 1521 1522 let Inst{6-8} = BF; 1523 let Inst{9-10} = 0; 1524 let Inst{11-14} = 0; 1525 let Inst{15} = W; 1526 let Inst{16-19} = U; 1527 let Inst{20} = 0; 1528 let Inst{21-30} = xo; 1529 let Inst{31} = RC; 1530} 1531 1532class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1533 InstrItinClass itin, list<dag> pattern> 1534 : I<opcode, OOL, IOL, asmstr, itin> { 1535 bits<1> S; 1536 1537 let Pattern = pattern; 1538 1539 let Inst{6-19} = 0; 1540 let Inst{20} = S; 1541 let Inst{21-30} = xo; 1542 let Inst{31} = 0; 1543} 1544 1545class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1546 bits<6> opcode2, bits<2> xo2, 1547 dag OOL, dag IOL, string asmstr, 1548 InstrItinClass itin, list<dag> pattern> 1549 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1550 bits<5> BO; 1551 bits<5> BI; 1552 bits<2> BH; 1553 1554 bits<5> RST; 1555 bits<19> DS_RA; 1556 1557 let Pattern = pattern; 1558 1559 let Inst{6-10} = BO; 1560 let Inst{11-15} = BI; 1561 let Inst{16-18} = 0; 1562 let Inst{19-20} = BH; 1563 let Inst{21-30} = xo1; 1564 let Inst{31} = lk; 1565 1566 let Inst{38-42} = RST; 1567 let Inst{43-47} = DS_RA{18-14}; // Register # 1568 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1569 let Inst{62-63} = xo2; 1570} 1571 1572class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1573 bits<5> bo, bits<5> bi, bit lk, 1574 bits<6> opcode2, bits<2> xo2, 1575 dag OOL, dag IOL, string asmstr, 1576 InstrItinClass itin, list<dag> pattern> 1577 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1578 OOL, IOL, asmstr, itin, pattern> { 1579 let BO = bo; 1580 let BI = bi; 1581 let BH = 0; 1582} 1583 1584class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1585 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1586 dag IOL, string asmstr, InstrItinClass itin, 1587 list<dag> pattern> 1588 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1589 1590 bits<5> RST; 1591 bits<21> D_RA; 1592 1593 let Pattern = pattern; 1594 1595 let Inst{6-10} = bo; 1596 let Inst{11-15} = bi; 1597 let Inst{16-18} = 0; 1598 let Inst{19-20} = 0; // Unused (BH) 1599 let Inst{21-30} = xo1; 1600 let Inst{31} = lk; 1601 1602 let Inst{38-42} = RST; 1603 let Inst{43-47} = D_RA{20-16}; // Base Register 1604 let Inst{48-63} = D_RA{15-0}; // Displacement 1605} 1606 1607// 1.7.8 XFX-Form 1608class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1609 InstrItinClass itin> 1610 : I<opcode, OOL, IOL, asmstr, itin> { 1611 bits<5> RT; 1612 bits<10> SPR; 1613 1614 let Inst{6-10} = RT; 1615 let Inst{11} = SPR{4}; 1616 let Inst{12} = SPR{3}; 1617 let Inst{13} = SPR{2}; 1618 let Inst{14} = SPR{1}; 1619 let Inst{15} = SPR{0}; 1620 let Inst{16} = SPR{9}; 1621 let Inst{17} = SPR{8}; 1622 let Inst{18} = SPR{7}; 1623 let Inst{19} = SPR{6}; 1624 let Inst{20} = SPR{5}; 1625 let Inst{21-30} = xo; 1626 let Inst{31} = 0; 1627} 1628 1629class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1630 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1631 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1632 let SPR = spr; 1633} 1634 1635class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1636 InstrItinClass itin> 1637 : I<opcode, OOL, IOL, asmstr, itin> { 1638 bits<5> RT; 1639 1640 let Inst{6-10} = RT; 1641 let Inst{11-20} = 0; 1642 let Inst{21-30} = xo; 1643 let Inst{31} = 0; 1644} 1645 1646class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1647 InstrItinClass itin, list<dag> pattern> 1648 : I<opcode, OOL, IOL, asmstr, itin> { 1649 bits<5> RT; 1650 bits<10> Entry; 1651 let Pattern = pattern; 1652 1653 let Inst{6-10} = RT; 1654 let Inst{11-20} = Entry; 1655 let Inst{21-30} = xo; 1656 let Inst{31} = 0; 1657} 1658 1659class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1660 InstrItinClass itin> 1661 : I<opcode, OOL, IOL, asmstr, itin> { 1662 bits<8> FXM; 1663 bits<5> rS; 1664 1665 let Inst{6-10} = rS; 1666 let Inst{11} = 0; 1667 let Inst{12-19} = FXM; 1668 let Inst{20} = 0; 1669 let Inst{21-30} = xo; 1670 let Inst{31} = 0; 1671} 1672 1673class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1674 InstrItinClass itin> 1675 : I<opcode, OOL, IOL, asmstr, itin> { 1676 bits<5> ST; 1677 bits<8> FXM; 1678 1679 let Inst{6-10} = ST; 1680 let Inst{11} = 1; 1681 let Inst{12-19} = FXM; 1682 let Inst{20} = 0; 1683 let Inst{21-30} = xo; 1684 let Inst{31} = 0; 1685} 1686 1687class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1688 InstrItinClass itin> 1689 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1690 1691class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1692 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1693 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1694 let SPR = spr; 1695} 1696 1697// XFL-Form - MTFSF 1698// This is probably 1.7.9, but I don't have the reference that uses this 1699// numbering scheme... 1700class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1701 InstrItinClass itin, list<dag>pattern> 1702 : I<opcode, OOL, IOL, asmstr, itin> { 1703 bits<8> FM; 1704 bits<5> rT; 1705 1706 bit RC = 0; // set by isRecordForm 1707 let Pattern = pattern; 1708 1709 let Inst{6} = 0; 1710 let Inst{7-14} = FM; 1711 let Inst{15} = 0; 1712 let Inst{16-20} = rT; 1713 let Inst{21-30} = xo; 1714 let Inst{31} = RC; 1715} 1716 1717class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1718 InstrItinClass itin, list<dag>pattern> 1719 : I<opcode, OOL, IOL, asmstr, itin> { 1720 bit L; 1721 bits<8> FLM; 1722 bit W; 1723 bits<5> FRB; 1724 1725 bit RC = 0; // set by isRecordForm 1726 let Pattern = pattern; 1727 1728 let Inst{6} = L; 1729 let Inst{7-14} = FLM; 1730 let Inst{15} = W; 1731 let Inst{16-20} = FRB; 1732 let Inst{21-30} = xo; 1733 let Inst{31} = RC; 1734} 1735 1736// 1.7.10 XS-Form - SRADI. 1737class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1738 InstrItinClass itin, list<dag> pattern> 1739 : I<opcode, OOL, IOL, asmstr, itin> { 1740 bits<5> A; 1741 bits<5> RS; 1742 bits<6> SH; 1743 1744 bit RC = 0; // set by isRecordForm 1745 let Pattern = pattern; 1746 1747 let Inst{6-10} = RS; 1748 let Inst{11-15} = A; 1749 let Inst{16-20} = SH{4,3,2,1,0}; 1750 let Inst{21-29} = xo; 1751 let Inst{30} = SH{5}; 1752 let Inst{31} = RC; 1753} 1754 1755// 1.7.11 XO-Form 1756class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1757 InstrItinClass itin, list<dag> pattern> 1758 : I<opcode, OOL, IOL, asmstr, itin> { 1759 bits<5> RT; 1760 bits<5> RA; 1761 bits<5> RB; 1762 1763 let Pattern = pattern; 1764 1765 bit RC = 0; // set by isRecordForm 1766 1767 let Inst{6-10} = RT; 1768 let Inst{11-15} = RA; 1769 let Inst{16-20} = RB; 1770 let Inst{21} = oe; 1771 let Inst{22-30} = xo; 1772 let Inst{31} = RC; 1773} 1774 1775class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1776 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1777 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1778 let RB = 0; 1779} 1780 1781// 1.7.12 A-Form 1782class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1783 InstrItinClass itin, list<dag> pattern> 1784 : I<opcode, OOL, IOL, asmstr, itin> { 1785 bits<5> FRT; 1786 bits<5> FRA; 1787 bits<5> FRC; 1788 bits<5> FRB; 1789 1790 let Pattern = pattern; 1791 1792 bit RC = 0; // set by isRecordForm 1793 1794 let Inst{6-10} = FRT; 1795 let Inst{11-15} = FRA; 1796 let Inst{16-20} = FRB; 1797 let Inst{21-25} = FRC; 1798 let Inst{26-30} = xo; 1799 let Inst{31} = RC; 1800} 1801 1802class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1803 InstrItinClass itin, list<dag> pattern> 1804 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1805 let FRC = 0; 1806} 1807 1808class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1809 InstrItinClass itin, list<dag> pattern> 1810 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1811 let FRB = 0; 1812} 1813 1814class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1815 InstrItinClass itin, list<dag> pattern> 1816 : I<opcode, OOL, IOL, asmstr, itin> { 1817 bits<5> RT; 1818 bits<5> RA; 1819 bits<5> RB; 1820 bits<5> COND; 1821 1822 let Pattern = pattern; 1823 1824 let Inst{6-10} = RT; 1825 let Inst{11-15} = RA; 1826 let Inst{16-20} = RB; 1827 let Inst{21-25} = COND; 1828 let Inst{26-30} = xo; 1829 let Inst{31} = 0; 1830} 1831 1832// 1.7.13 M-Form 1833class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1834 InstrItinClass itin, list<dag> pattern> 1835 : I<opcode, OOL, IOL, asmstr, itin> { 1836 bits<5> RA; 1837 bits<5> RS; 1838 bits<5> RB; 1839 bits<5> MB; 1840 bits<5> ME; 1841 1842 let Pattern = pattern; 1843 1844 bit RC = 0; // set by isRecordForm 1845 1846 let Inst{6-10} = RS; 1847 let Inst{11-15} = RA; 1848 let Inst{16-20} = RB; 1849 let Inst{21-25} = MB; 1850 let Inst{26-30} = ME; 1851 let Inst{31} = RC; 1852} 1853 1854class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1855 InstrItinClass itin, list<dag> pattern> 1856 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1857} 1858 1859// 1.7.14 MD-Form 1860class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1861 InstrItinClass itin, list<dag> pattern> 1862 : I<opcode, OOL, IOL, asmstr, itin> { 1863 bits<5> RA; 1864 bits<5> RS; 1865 bits<6> SH; 1866 bits<6> MBE; 1867 1868 let Pattern = pattern; 1869 1870 bit RC = 0; // set by isRecordForm 1871 1872 let Inst{6-10} = RS; 1873 let Inst{11-15} = RA; 1874 let Inst{16-20} = SH{4,3,2,1,0}; 1875 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1876 let Inst{27-29} = xo; 1877 let Inst{30} = SH{5}; 1878 let Inst{31} = RC; 1879} 1880 1881class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1882 InstrItinClass itin, list<dag> pattern> 1883 : I<opcode, OOL, IOL, asmstr, itin> { 1884 bits<5> RA; 1885 bits<5> RS; 1886 bits<5> RB; 1887 bits<6> MBE; 1888 1889 let Pattern = pattern; 1890 1891 bit RC = 0; // set by isRecordForm 1892 1893 let Inst{6-10} = RS; 1894 let Inst{11-15} = RA; 1895 let Inst{16-20} = RB; 1896 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1897 let Inst{27-30} = xo; 1898 let Inst{31} = RC; 1899} 1900 1901 1902// E-1 VA-Form 1903 1904// VAForm_1 - DACB ordering. 1905class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1906 InstrItinClass itin, list<dag> pattern> 1907 : I<4, OOL, IOL, asmstr, itin> { 1908 bits<5> VD; 1909 bits<5> VA; 1910 bits<5> VC; 1911 bits<5> VB; 1912 1913 let Pattern = pattern; 1914 1915 let Inst{6-10} = VD; 1916 let Inst{11-15} = VA; 1917 let Inst{16-20} = VB; 1918 let Inst{21-25} = VC; 1919 let Inst{26-31} = xo; 1920} 1921 1922// VAForm_1a - DABC ordering. 1923class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1924 InstrItinClass itin, list<dag> pattern> 1925 : I<4, OOL, IOL, asmstr, itin> { 1926 bits<5> VD; 1927 bits<5> VA; 1928 bits<5> VB; 1929 bits<5> VC; 1930 1931 let Pattern = pattern; 1932 1933 let Inst{6-10} = VD; 1934 let Inst{11-15} = VA; 1935 let Inst{16-20} = VB; 1936 let Inst{21-25} = VC; 1937 let Inst{26-31} = xo; 1938} 1939 1940class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1941 InstrItinClass itin, list<dag> pattern> 1942 : I<4, OOL, IOL, asmstr, itin> { 1943 bits<5> VD; 1944 bits<5> VA; 1945 bits<5> VB; 1946 bits<4> SH; 1947 1948 let Pattern = pattern; 1949 1950 let Inst{6-10} = VD; 1951 let Inst{11-15} = VA; 1952 let Inst{16-20} = VB; 1953 let Inst{21} = 0; 1954 let Inst{22-25} = SH; 1955 let Inst{26-31} = xo; 1956} 1957 1958// E-2 VX-Form 1959class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1960 InstrItinClass itin, list<dag> pattern> 1961 : I<4, OOL, IOL, asmstr, itin> { 1962 bits<5> VD; 1963 bits<5> VA; 1964 bits<5> VB; 1965 1966 let Pattern = pattern; 1967 1968 let Inst{6-10} = VD; 1969 let Inst{11-15} = VA; 1970 let Inst{16-20} = VB; 1971 let Inst{21-31} = xo; 1972} 1973 1974class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1975 InstrItinClass itin, list<dag> pattern> 1976 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1977 let VA = VD; 1978 let VB = VD; 1979} 1980 1981 1982class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1983 InstrItinClass itin, list<dag> pattern> 1984 : I<4, OOL, IOL, asmstr, itin> { 1985 bits<5> VD; 1986 bits<5> VB; 1987 1988 let Pattern = pattern; 1989 1990 let Inst{6-10} = VD; 1991 let Inst{11-15} = 0; 1992 let Inst{16-20} = VB; 1993 let Inst{21-31} = xo; 1994} 1995 1996class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1997 InstrItinClass itin, list<dag> pattern> 1998 : I<4, OOL, IOL, asmstr, itin> { 1999 bits<5> VD; 2000 bits<5> IMM; 2001 2002 let Pattern = pattern; 2003 2004 let Inst{6-10} = VD; 2005 let Inst{11-15} = IMM; 2006 let Inst{16-20} = 0; 2007 let Inst{21-31} = xo; 2008} 2009 2010/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 2011class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 2012 InstrItinClass itin, list<dag> pattern> 2013 : I<4, OOL, IOL, asmstr, itin> { 2014 bits<5> VD; 2015 2016 let Pattern = pattern; 2017 2018 let Inst{6-10} = VD; 2019 let Inst{11-15} = 0; 2020 let Inst{16-20} = 0; 2021 let Inst{21-31} = xo; 2022} 2023 2024/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 2025class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 2026 InstrItinClass itin, list<dag> pattern> 2027 : I<4, OOL, IOL, asmstr, itin> { 2028 bits<5> VB; 2029 2030 let Pattern = pattern; 2031 2032 let Inst{6-10} = 0; 2033 let Inst{11-15} = 0; 2034 let Inst{16-20} = VB; 2035 let Inst{21-31} = xo; 2036} 2037 2038// e.g. [PO VRT EO VRB XO] 2039class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 2040 string asmstr, InstrItinClass itin, list<dag> pattern> 2041 : I<4, OOL, IOL, asmstr, itin> { 2042 bits<5> RD; 2043 bits<5> VB; 2044 2045 let Pattern = pattern; 2046 2047 let Inst{6-10} = RD; 2048 let Inst{11-15} = eo; 2049 let Inst{16-20} = VB; 2050 let Inst{21-31} = xo; 2051} 2052 2053/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2054class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2055 InstrItinClass itin, list<dag> pattern> 2056 : I<4, OOL, IOL, asmstr, itin> { 2057 bits<5> VD; 2058 bits<5> VA; 2059 bits<1> ST; 2060 bits<4> SIX; 2061 2062 let Pattern = pattern; 2063 2064 let Inst{6-10} = VD; 2065 let Inst{11-15} = VA; 2066 let Inst{16} = ST; 2067 let Inst{17-20} = SIX; 2068 let Inst{21-31} = xo; 2069} 2070 2071/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2072class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2073 InstrItinClass itin, list<dag> pattern> 2074 : I<4, OOL, IOL, asmstr, itin> { 2075 bits<5> VD; 2076 bits<5> VA; 2077 2078 let Pattern = pattern; 2079 2080 let Inst{6-10} = VD; 2081 let Inst{11-15} = VA; 2082 let Inst{16-20} = 0; 2083 let Inst{21-31} = xo; 2084} 2085 2086// E-4 VXR-Form 2087class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2088 InstrItinClass itin, list<dag> pattern> 2089 : I<4, OOL, IOL, asmstr, itin> { 2090 bits<5> VD; 2091 bits<5> VA; 2092 bits<5> VB; 2093 bit RC = 0; 2094 2095 let Pattern = pattern; 2096 2097 let Inst{6-10} = VD; 2098 let Inst{11-15} = VA; 2099 let Inst{16-20} = VB; 2100 let Inst{21} = RC; 2101 let Inst{22-31} = xo; 2102} 2103 2104// VX-Form: [PO VRT EO VRB 1 PS XO] 2105class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2106 dag OOL, dag IOL, string asmstr, 2107 InstrItinClass itin, list<dag> pattern> 2108 : I<4, OOL, IOL, asmstr, itin> { 2109 bits<5> VD; 2110 bits<5> VB; 2111 bit PS; 2112 2113 let Pattern = pattern; 2114 2115 let Inst{6-10} = VD; 2116 let Inst{11-15} = eo; 2117 let Inst{16-20} = VB; 2118 let Inst{21} = 1; 2119 let Inst{22} = PS; 2120 let Inst{23-31} = xo; 2121} 2122 2123// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2124class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2125 InstrItinClass itin, list<dag> pattern> 2126 : I<4, OOL, IOL, asmstr, itin> { 2127 bits<5> VD; 2128 bits<5> VA; 2129 bits<5> VB; 2130 bit PS; 2131 2132 let Pattern = pattern; 2133 2134 let Inst{6-10} = VD; 2135 let Inst{11-15} = VA; 2136 let Inst{16-20} = VB; 2137 let Inst{21} = 1; 2138 let Inst{22} = PS; 2139 let Inst{23-31} = xo; 2140} 2141 2142class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2143 InstrItinClass itin, list<dag> pattern> 2144 : I<opcode, OOL, IOL, asmstr, itin> { 2145 bits<5> VRT; 2146 bit R; 2147 bits<5> VRB; 2148 bits<2> idx; 2149 2150 let Pattern = pattern; 2151 2152 bit RC = 0; // set by isRecordForm 2153 2154 let Inst{6-10} = VRT; 2155 let Inst{11-14} = 0; 2156 let Inst{15} = R; 2157 let Inst{16-20} = VRB; 2158 let Inst{21-22} = idx; 2159 let Inst{23-30} = xo; 2160 let Inst{31} = RC; 2161} 2162 2163class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2164 string asmstr, InstrItinClass itin, list<dag> pattern> 2165 : I<opcode, OOL, IOL, asmstr, itin> { 2166 bits<5> RT; 2167 bits<5> RA; 2168 bits<5> RB; 2169 bits<2> CY; 2170 2171 let Pattern = pattern; 2172 2173 let Inst{6-10} = RT; 2174 let Inst{11-15} = RA; 2175 let Inst{16-20} = RB; 2176 let Inst{21-22} = CY; 2177 let Inst{23-30} = xo; 2178 let Inst{31} = 0; 2179} 2180 2181//===----------------------------------------------------------------------===// 2182// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2183// stuff 2184class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2185 : I<0, OOL, IOL, asmstr, NoItinerary> { 2186 let isCodeGenOnly = 1; 2187 let PPC64 = 0; 2188 let Pattern = pattern; 2189 let Inst{31-0} = 0; 2190 let hasNoSchedulingInfo = 1; 2191} 2192 2193// Instruction that require custom insertion support 2194// a.k.a. ISelPseudos, however, these won't have isPseudo set 2195class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2196 list<dag> pattern> 2197 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2198 let usesCustomInserter = 1; 2199} 2200 2201// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2202// files is set only for PostRAPseudo 2203class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2204 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2205 let isPseudo = 1; 2206} 2207 2208class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2209 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2210 2211