1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Indicate that this instruction produces a result that is sign extended from 49 // 32 bits to 64 bits. 50 bits<1> SExt32To64 = 0; 51 let TSFlags{8} = SExt32To64; 52 53 // Indicate that this instruction produces a result that is zero extended from 54 // 32 bits to 64 bits. 55 bits<1> ZExt32To64 = 0; 56 let TSFlags{9} = ZExt32To64; 57 58 // Fields used for relation models. 59 string BaseName = ""; 60 61 // For cases where multiple instruction definitions really represent the 62 // same underlying instruction but with one definition for 64-bit arguments 63 // and one for 32-bit arguments, this bit breaks the degeneracy between 64 // the two forms and allows TableGen to generate mapping tables. 65 bit Interpretation64Bit = 0; 66} 67 68class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 69class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 70class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 71class PPC970_MicroCode; 72 73class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 74class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 75class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 76class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 77class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 78class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 79class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 80class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 81 82class XFormMemOp { bits<1> XFormMemOp = 1; } 83class SExt32To64 { bits<1> SExt32To64 = 1; } 84class ZExt32To64 { bits<1> ZExt32To64 = 1; } 85 86// Two joined instructions; used to emit two adjacent instructions as one. 87// The itinerary from the first instruction is used for scheduling and 88// classification. 89class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 90 InstrItinClass itin> 91 : Instruction { 92 field bits<64> Inst; 93 field bits<64> SoftFail = 0; 94 let Size = 8; 95 96 bit PPC64 = 0; // Default value, override with isPPC64 97 98 let Namespace = "PPC"; 99 let Inst{0-5} = opcode1; 100 let Inst{32-37} = opcode2; 101 let OutOperandList = OOL; 102 let InOperandList = IOL; 103 let AsmString = asmstr; 104 let Itinerary = itin; 105 106 bits<1> PPC970_First = 0; 107 bits<1> PPC970_Single = 0; 108 bits<1> PPC970_Cracked = 0; 109 bits<3> PPC970_Unit = 0; 110 111 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 112 /// these must be reflected there! See comments there for what these are. 113 let TSFlags{0} = PPC970_First; 114 let TSFlags{1} = PPC970_Single; 115 let TSFlags{2} = PPC970_Cracked; 116 let TSFlags{5-3} = PPC970_Unit; 117 118 // Fields used for relation models. 119 string BaseName = ""; 120 bit Interpretation64Bit = 0; 121} 122 123// Base class for all X-Form memory instructions 124class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 125 InstrItinClass itin> 126 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 127 128// 1.7.1 I-Form 129class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 130 InstrItinClass itin, list<dag> pattern> 131 : I<opcode, OOL, IOL, asmstr, itin> { 132 let Pattern = pattern; 133 bits<24> LI; 134 135 let Inst{6-29} = LI; 136 let Inst{30} = aa; 137 let Inst{31} = lk; 138} 139 140// 1.7.2 B-Form 141class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 144 bits<3> CR; 145 bits<14> BD; 146 147 bits<5> BI; 148 let BI{0-1} = BIBO{5-6}; 149 let BI{2-4} = CR{0-2}; 150 151 let Inst{6-10} = BIBO{4-0}; 152 let Inst{11-15} = BI; 153 let Inst{16-29} = BD; 154 let Inst{30} = aa; 155 let Inst{31} = lk; 156} 157 158class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 159 string asmstr> 160 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 161 let BIBO{4-0} = bo; 162 let BIBO{6-5} = 0; 163 let CR = 0; 164} 165 166class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<14> BD; 170 171 let Inst{6-10} = bo; 172 let Inst{11-15} = bi; 173 let Inst{16-29} = BD; 174 let Inst{30} = aa; 175 let Inst{31} = lk; 176} 177 178class BForm_3<bits<6> opcode, bit aa, bit lk, 179 dag OOL, dag IOL, string asmstr> 180 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 181 bits<5> BO; 182 bits<5> BI; 183 bits<14> BD; 184 185 let Inst{6-10} = BO; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_3_at<bits<6> opcode, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BO; 196 bits<2> at; 197 bits<5> BI; 198 bits<14> BD; 199 200 let Inst{6-8} = BO{4-2}; 201 let Inst{9-10} = at; 202 let Inst{11-15} = BI; 203 let Inst{16-29} = BD; 204 let Inst{30} = aa; 205 let Inst{31} = lk; 206} 207 208class 209BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 210 dag OOL, dag IOL, string asmstr> 211 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 212 bits<5> BI; 213 bits<14> BD; 214 215 let Inst{6-10} = bo; 216 let Inst{11-15} = BI; 217 let Inst{16-29} = BD; 218 let Inst{30} = aa; 219 let Inst{31} = lk; 220} 221 222// 1.7.3 SC-Form 223class SCForm<bits<6> opcode, bits<1> xo1, bits<1> xo2, 224 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 225 list<dag> pattern> 226 : I<opcode, OOL, IOL, asmstr, itin> { 227 bits<7> LEV; 228 229 let Pattern = pattern; 230 231 let Inst{20-26} = LEV; 232 let Inst{30} = xo1; 233 let Inst{31} = xo2; 234} 235 236// 1.7.4 D-Form 237class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 238 InstrItinClass itin, list<dag> pattern> 239 : I<opcode, OOL, IOL, asmstr, itin> { 240 bits<5> RST; 241 bits<5> RA; 242 bits<16> D; 243 244 let Pattern = pattern; 245 246 let Inst{6-10} = RST; 247 let Inst{11-15} = RA; 248 let Inst{16-31} = D; 249} 250 251class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 252 InstrItinClass itin, list<dag> pattern> 253 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 254} 255 256class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 257 InstrItinClass itin, list<dag> pattern> 258 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 259 260 // Even though ADDIC_rec does not really have an RC bit, provide 261 // the declaration of one here so that isRecordForm has something to set. 262 bit RC = 0; 263} 264 265class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 266 InstrItinClass itin, list<dag> pattern> 267 : I<opcode, OOL, IOL, asmstr, itin> { 268 bits<5> RST; 269 bits<16> D; 270 271 let Pattern = pattern; 272 273 let Inst{6-10} = RST; 274 let Inst{11-15} = 0; 275 let Inst{16-31} = D; 276} 277 278class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 279 InstrItinClass itin, list<dag> pattern> 280 : I<opcode, OOL, IOL, asmstr, itin> { 281 bits<5> RA; 282 bits<5> RST; 283 bits<16> D; 284 285 let Pattern = pattern; 286 287 let Inst{6-10} = RST; 288 let Inst{11-15} = RA; 289 let Inst{16-31} = D; 290} 291 292class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 293 InstrItinClass itin, list<dag> pattern> 294 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 295 let RST = 0; 296 let RA = 0; 297 let D = 0; 298} 299 300class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 301 string asmstr, InstrItinClass itin, 302 list<dag> pattern> 303 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 304 let RST = R; 305 let RA = R; 306 let D = 0; 307} 308 309class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 310 dag OOL, dag IOL, string asmstr, 311 InstrItinClass itin, list<dag> pattern> 312 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 313 bits<5> RST; 314 bits<5> RA; 315 bits<16> D; 316 317 let Pattern = pattern; 318 bits<24> LI; 319 320 let Inst{6-29} = LI; 321 let Inst{30} = aa; 322 let Inst{31} = lk; 323 324 let Inst{38-42} = RST; 325 let Inst{43-47} = RA; 326 let Inst{48-63} = D; 327} 328 329// This is used to emit BL8+NOP. 330class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 331 dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin, list<dag> pattern> 333 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 334 OOL, IOL, asmstr, itin, pattern> { 335 let RST = 0; 336 let RA = 0; 337 let D = 0; 338} 339 340class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 341 InstrItinClass itin> 342 : I<opcode, OOL, IOL, asmstr, itin> { 343 bits<3> BF; 344 bits<1> L; 345 bits<5> RA; 346 bits<16> D; 347 348 let Inst{6-8} = BF; 349 let Inst{9} = 0; 350 let Inst{10} = L; 351 let Inst{11-15} = RA; 352 let Inst{16-31} = D; 353} 354 355class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 356 InstrItinClass itin> 357 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 358 let L = PPC64; 359} 360 361class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 362 InstrItinClass itin> 363 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 364 365class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 366 InstrItinClass itin> 367 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 368 let L = PPC64; 369} 370 371 372// 1.7.5 DS-Form 373class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 374 InstrItinClass itin, list<dag> pattern> 375 : I<opcode, OOL, IOL, asmstr, itin> { 376 bits<5> RST; 377 bits<5> RA; 378 bits<14> D; 379 380 let Pattern = pattern; 381 382 let Inst{6-10} = RST; 383 let Inst{11-15} = RA; 384 let Inst{16-29} = D; 385 let Inst{30-31} = xo; 386} 387 388// ISA V3.0B 1.6.6 DX-Form 389class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 390 InstrItinClass itin, list<dag> pattern> 391 : I<opcode, OOL, IOL, asmstr, itin> { 392 bits<5> RT; 393 bits<16> D; 394 395 let Pattern = pattern; 396 397 let Inst{6-10} = RT; 398 let Inst{11-15} = D{5-1}; // d1 399 let Inst{16-25} = D{15-6}; // d0 400 let Inst{26-30} = xo; 401 let Inst{31} = D{0}; // d2 402} 403 404// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 405class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 406 string asmstr, InstrItinClass itin, list<dag> pattern> 407 : I<opcode, OOL, IOL, asmstr, itin> { 408 bits<6> XT; 409 bits<5> RA; 410 bits<12> DQ; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = XT{4-0}; 415 let Inst{11-15} = RA; 416 let Inst{16-27} = DQ; 417 let Inst{28} = XT{5}; 418 let Inst{29-31} = xo; 419} 420 421class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 422 string asmstr, InstrItinClass itin, 423 list<dag> pattern> 424 : I<opcode, OOL, IOL, asmstr, itin> { 425 bits<5> RTp; 426 bits<5> RA; 427 bits<12> DQ; 428 let Pattern = pattern; 429 430 let Inst{6-10} = RTp{4-0}; 431 let Inst{11-15} = RA; 432 let Inst{16-27} = DQ; 433 let Inst{28-31} = xo; 434} 435 436// 1.7.6 X-Form 437class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 438 InstrItinClass itin, list<dag> pattern> 439 : I<opcode, OOL, IOL, asmstr, itin> { 440 bits<5> RST; 441 bits<5> RA; 442 bits<5> RB; 443 444 let Pattern = pattern; 445 446 bit RC = 0; // set by isRecordForm 447 448 let Inst{6-10} = RST; 449 let Inst{11-15} = RA; 450 let Inst{16-20} = RB; 451 let Inst{21-30} = xo; 452 let Inst{31} = RC; 453} 454 455class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 456 string asmstr, InstrItinClass itin, 457 list<dag> pattern> 458 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 459 460class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 461 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 462 let RST = 0; 463} 464 465class XForm_tlbilx<bits<10> xo, dag OOL, dag IOL, string asmstr, 466 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 467 bits<5> T; 468 let RST = T; 469} 470 471class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 472 InstrItinClass itin> 473 : I<opcode, OOL, IOL, asmstr, itin> { 474 let Inst{21-30} = xo; 475} 476 477// This is the same as XForm_base_r3xo, but the first two operands are swapped 478// when code is emitted. 479class XForm_base_r3xo_swapped 480 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 481 InstrItinClass itin> 482 : I<opcode, OOL, IOL, asmstr, itin> { 483 bits<5> RA; 484 bits<5> RST; 485 bits<5> RB; 486 487 bit RC = 0; // set by isRecordForm 488 489 let Inst{6-10} = RST; 490 let Inst{11-15} = RA; 491 let Inst{16-20} = RB; 492 let Inst{21-30} = xo; 493 let Inst{31} = RC; 494} 495 496 497class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 498 InstrItinClass itin, list<dag> pattern> 499 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 500 501class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 502 InstrItinClass itin, list<dag> pattern> 503 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 504 505class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 506 InstrItinClass itin, list<dag> pattern> 507 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 508 let RST = 0; 509} 510 511class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 512 InstrItinClass itin, list<dag> pattern> 513 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 514 let RA = 0; 515 let RB = 0; 516} 517 518class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 519 InstrItinClass itin, list<dag> pattern> 520 : I<opcode, OOL, IOL, asmstr, itin> { 521 bits<5> RST; 522 bits<5> RA; 523 bits<1> WS; 524 525 let Pattern = pattern; 526 527 let Inst{6-10} = RST; 528 let Inst{11-15} = RA; 529 let Inst{20} = WS; 530 let Inst{21-30} = xo; 531 let Inst{31} = 0; 532} 533 534class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 535 InstrItinClass itin, list<dag> pattern> 536 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 537 let Pattern = pattern; 538} 539 540class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 541 InstrItinClass itin, list<dag> pattern> 542 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 543 544class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin, list<dag> pattern> 546 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 547 548class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 549 InstrItinClass itin, list<dag> pattern> 550 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 551 let Pattern = pattern; 552} 553 554class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 555 InstrItinClass itin, list<dag> pattern> 556 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 557 let RB = 0; 558 let Pattern = pattern; 559} 560 561class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 562 InstrItinClass itin> 563 : I<opcode, OOL, IOL, asmstr, itin> { 564 bits<3> BF; 565 bits<1> L; 566 bits<5> RA; 567 bits<5> RB; 568 569 let Inst{6-8} = BF; 570 let Inst{9} = 0; 571 let Inst{10} = L; 572 let Inst{11-15} = RA; 573 let Inst{16-20} = RB; 574 let Inst{21-30} = xo; 575 let Inst{31} = 0; 576} 577 578class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 579 InstrItinClass itin> 580 : I<opcode, OOL, IOL, asmstr, itin> { 581 bits<4> CT; 582 bits<5> RA; 583 bits<5> RB; 584 585 let Inst{6} = 0; 586 let Inst{7-10} = CT; 587 let Inst{11-15} = RA; 588 let Inst{16-20} = RB; 589 let Inst{21-30} = xo; 590 let Inst{31} = 0; 591} 592 593class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 594 InstrItinClass itin> 595 : I<opcode, OOL, IOL, asmstr, itin> { 596 bits<5> RS; 597 bits<4> SR; 598 599 let Inst{6-10} = RS; 600 let Inst{12-15} = SR; 601 let Inst{21-30} = xo; 602} 603 604class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 605 InstrItinClass itin> 606 : I<opcode, OOL, IOL, asmstr, itin> { 607 bits<5> MO; 608 609 let Inst{6-10} = MO; 610 let Inst{21-30} = xo; 611} 612 613class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 614 InstrItinClass itin> 615 : I<opcode, OOL, IOL, asmstr, itin> { 616 bits<5> RS; 617 bits<5> RB; 618 619 let Inst{6-10} = RS; 620 let Inst{16-20} = RB; 621 let Inst{21-30} = xo; 622} 623 624class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 625 InstrItinClass itin> 626 : I<opcode, OOL, IOL, asmstr, itin> { 627 bits<5> RS; 628 bits<1> L; 629 630 let Inst{6-10} = RS; 631 let Inst{15} = L; 632 let Inst{21-30} = xo; 633} 634 635class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 636 InstrItinClass itin> 637 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 638 let L = PPC64; 639} 640 641class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 642 InstrItinClass itin> 643 : I<opcode, OOL, IOL, asmstr, itin> { 644 bits<3> BF; 645 bits<5> RA; 646 bits<5> RB; 647 648 let Inst{6-8} = BF; 649 let Inst{9-10} = 0; 650 let Inst{11-15} = RA; 651 let Inst{16-20} = RB; 652 let Inst{21-30} = xo; 653 let Inst{31} = 0; 654} 655 656class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 657 InstrItinClass itin, list<dag> pattern> 658 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 659 let RA = 0; 660 let Pattern = pattern; 661} 662 663class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 664 InstrItinClass itin, list<dag> pattern> 665 : I<opcode, OOL, IOL, asmstr, itin> { 666 bits<5> FRT; 667 bits<5> FRA; 668 bits<5> FRB; 669 670 let Pattern = pattern; 671 672 let Inst{6-10} = FRT; 673 let Inst{11-15} = FRA; 674 let Inst{16-20} = FRB; 675 let Inst{21-30} = xo; 676 let Inst{31} = 0; 677} 678 679class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 680 InstrItinClass itin, list<dag> pattern> 681 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 682 let FRA = 0; 683} 684 685class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 686 InstrItinClass itin, list<dag> pattern> 687 : I<opcode, OOL, IOL, asmstr, itin> { 688 bits<5> FRT; 689 bits<5> FRA; 690 bits<5> FRB; 691 bits<4> tttt; 692 693 let Pattern = pattern; 694 695 let Inst{6-10} = FRT; 696 let Inst{11-15} = FRA; 697 let Inst{16-20} = FRB; 698 let Inst{21-24} = tttt; 699 let Inst{25-30} = xo; 700 let Inst{31} = 0; 701} 702 703class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 704 InstrItinClass itin, list<dag> pattern> 705 : I<opcode, OOL, IOL, asmstr, itin> { 706 let Pattern = pattern; 707 let Inst{6-10} = 31; 708 let Inst{11-15} = 0; 709 let Inst{16-20} = 0; 710 let Inst{21-30} = xo; 711 let Inst{31} = 0; 712} 713 714class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 715 string asmstr, InstrItinClass itin, list<dag> pattern> 716 : I<opcode, OOL, IOL, asmstr, itin> { 717 bits<2> L; 718 719 let Pattern = pattern; 720 let Inst{6-8} = 0; 721 let Inst{9-10} = L; 722 let Inst{11-15} = 0; 723 let Inst{16-20} = 0; 724 let Inst{21-30} = xo; 725 let Inst{31} = 0; 726} 727 728class XForm_IMM2_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 729 string asmstr, InstrItinClass itin, list<dag> pattern> 730 : I<opcode, OOL, IOL, asmstr, itin> { 731 bits<2> L; 732 bits<2> PL; 733 734 let Pattern = pattern; 735 let Inst{6-8} = 0; 736 let Inst{9-10} = L; 737 let Inst{11-13} = 0; 738 let Inst{14-15} = PL; 739 let Inst{16-20} = 0; 740 let Inst{21-30} = xo; 741 let Inst{31} = 0; 742} 743 744class XForm_IMM3_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 745 string asmstr, InstrItinClass itin, list<dag> pattern> 746 : I<opcode, OOL, IOL, asmstr, itin> { 747 bits<3> L; 748 bits<2> SC; 749 750 let Pattern = pattern; 751 let Inst{6-7} = 0; 752 let Inst{8-10} = L; 753 let Inst{11-13} = 0; 754 let Inst{14-15} = SC; 755 let Inst{16-20} = 0; 756 let Inst{21-30} = xo; 757 let Inst{31} = 0; 758} 759 760class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 761 string asmstr, InstrItinClass itin, list<dag> pattern> 762 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 763 let L = 0; 764} 765 766class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 767 InstrItinClass itin, list<dag> pattern> 768 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 769} 770 771class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 772 string asmstr, InstrItinClass itin, list<dag> pattern> 773 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 774} 775 776// [PO RT /// RB XO RC] 777class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 778 InstrItinClass itin, list<dag> pattern> 779 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 780 let RA = 0; 781} 782 783class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 784 string asmstr, InstrItinClass itin, list<dag> pattern> 785 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 786} 787 788class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 789 InstrItinClass itin, list<dag> pattern> 790 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 791} 792 793// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 794// numbers presumably relates to some document, but I haven't found it. 795class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 796 InstrItinClass itin, list<dag> pattern> 797 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 798 let Pattern = pattern; 799 800 bit RC = 0; // set by isRecordForm 801 802 let Inst{6-10} = RST; 803 let Inst{11-20} = 0; 804 let Inst{21-30} = xo; 805 let Inst{31} = RC; 806} 807class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 808 InstrItinClass itin, list<dag> pattern> 809 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 810 let Pattern = pattern; 811 bits<5> FM; 812 813 bit RC = 0; // set by isRecordForm 814 815 let Inst{6-10} = FM; 816 let Inst{11-20} = 0; 817 let Inst{21-30} = xo; 818 let Inst{31} = RC; 819} 820 821class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 822 InstrItinClass itin> 823 : I<opcode, OOL, IOL, asmstr, itin> { 824 bits<5> RT; 825 bits<3> BFA; 826 827 let Inst{6-10} = RT; 828 let Inst{11-13} = BFA; 829 let Inst{14-15} = 0; 830 let Inst{16-20} = 0; 831 let Inst{21-30} = xo; 832 let Inst{31} = 0; 833} 834 835class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 836 InstrItinClass itin> 837 : I<opcode, OOL, IOL, asmstr, itin> { 838 bits<5> RT; 839 bits<2> L; 840 841 let Inst{6-10} = RT; 842 let Inst{11-13} = 0; 843 let Inst{14-15} = L; 844 let Inst{16-20} = 0; 845 let Inst{21-30} = xo; 846 let Inst{31} = 0; 847} 848 849class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 850 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 851 list<dag> pattern> 852 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 853 let Pattern = pattern; 854 855 let Inst{6-10} = RST; 856 let Inst{11-12} = xo1; 857 let Inst{13-15} = xo2; 858 let Inst{16-20} = 0; 859 let Inst{21-30} = xo; 860 let Inst{31} = 0; 861} 862 863class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 864 bits<10> xo, dag OOL, dag IOL, string asmstr, 865 InstrItinClass itin, list<dag> pattern> 866 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 867 let Pattern = pattern; 868 bits<5> FRB; 869 870 let Inst{6-10} = RST; 871 let Inst{11-12} = xo1; 872 let Inst{13-15} = xo2; 873 let Inst{16-20} = FRB; 874 let Inst{21-30} = xo; 875 let Inst{31} = 0; 876} 877 878class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 879 bits<10> xo, dag OOL, dag IOL, string asmstr, 880 InstrItinClass itin, list<dag> pattern> 881 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 882 let Pattern = pattern; 883 bits<3> DRM; 884 885 let Inst{6-10} = RST; 886 let Inst{11-12} = xo1; 887 let Inst{13-15} = xo2; 888 let Inst{16-17} = 0; 889 let Inst{18-20} = DRM; 890 let Inst{21-30} = xo; 891 let Inst{31} = 0; 892} 893 894class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 895 bits<10> xo, dag OOL, dag IOL, string asmstr, 896 InstrItinClass itin, list<dag> pattern> 897 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 898 let Pattern = pattern; 899 bits<2> RM; 900 901 let Inst{6-10} = RST; 902 let Inst{11-12} = xo1; 903 let Inst{13-15} = xo2; 904 let Inst{16-18} = 0; 905 let Inst{19-20} = RM; 906 let Inst{21-30} = xo; 907 let Inst{31} = 0; 908} 909 910 911class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 912 InstrItinClass itin, list<dag> pattern> 913 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 914 let RST = 0; 915 let RA = 0; 916 let RB = 0; 917} 918 919class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 920 InstrItinClass itin, list<dag> pattern> 921 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 922 let RST = 0; 923 let RA = 0; 924} 925 926class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 927 string asmstr, InstrItinClass itin> 928 : I<opcode, OOL, IOL, asmstr, itin> { 929 bit R; 930 931 bit RC = 1; 932 933 let Inst{6-9} = 0; 934 let Inst{10} = R; 935 let Inst{11-20} = 0; 936 let Inst{21-30} = xo; 937 let Inst{31} = RC; 938} 939 940class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 941 string asmstr, InstrItinClass itin> 942 : I<opcode, OOL, IOL, asmstr, itin> { 943 bit A; 944 945 bit RC = 1; 946 947 let Inst{6} = A; 948 let Inst{7-20} = 0; 949 let Inst{21-30} = xo; 950 let Inst{31} = RC; 951} 952 953class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 954 InstrItinClass itin> 955 : I<opcode, OOL, IOL, asmstr, itin> { 956 bit L; 957 958 bit RC = 0; // set by isRecordForm 959 960 let Inst{7-9} = 0; 961 let Inst{10} = L; 962 let Inst{11-20} = 0; 963 let Inst{21-30} = xo; 964 let Inst{31} = RC; 965} 966 967class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 968 InstrItinClass itin> 969 : I<opcode, OOL, IOL, asmstr, itin> { 970 bits<3> BF; 971 972 bit RC = 0; 973 974 let Inst{6-8} = BF; 975 let Inst{9-20} = 0; 976 let Inst{21-30} = xo; 977 let Inst{31} = RC; 978} 979 980// [PO RT RA RB XO /] 981class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 982 string asmstr, InstrItinClass itin, list<dag> pattern> 983 : I<opcode, OOL, IOL, asmstr, itin> { 984 bits<3> BF; 985 bits<1> L; 986 bits<5> RA; 987 bits<5> RB; 988 989 let Pattern = pattern; 990 991 let Inst{6-8} = BF; 992 let Inst{9} = 0; 993 let Inst{10} = L; 994 let Inst{11-15} = RA; 995 let Inst{16-20} = RB; 996 let Inst{21-30} = xo; 997 let Inst{31} = 0; 998} 999 1000// Same as XForm_17 but with GPR's and new naming convention 1001class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1002 string asmstr, InstrItinClass itin, list<dag> pattern> 1003 : I<opcode, OOL, IOL, asmstr, itin> { 1004 bits<3> BF; 1005 bits<5> RA; 1006 bits<5> RB; 1007 1008 let Pattern = pattern; 1009 1010 let Inst{6-8} = BF; 1011 let Inst{9-10} = 0; 1012 let Inst{11-15} = RA; 1013 let Inst{16-20} = RB; 1014 let Inst{21-30} = xo; 1015 let Inst{31} = 0; 1016} 1017 1018// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 1019class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 1020 string asmstr, InstrItinClass itin, list<dag> pattern> 1021 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1022 let RA = xo2; 1023} 1024 1025class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1026 string asmstr, InstrItinClass itin, list<dag> pattern> 1027 : I<opcode, OOL, IOL, asmstr, itin> { 1028 bits<3> BF; 1029 bits<7> DCMX; 1030 bits<5> VB; 1031 1032 let Pattern = pattern; 1033 1034 let Inst{6-8} = BF; 1035 let Inst{9-15} = DCMX; 1036 let Inst{16-20} = VB; 1037 let Inst{21-30} = xo; 1038 let Inst{31} = 0; 1039} 1040 1041class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1042 string asmstr, InstrItinClass itin, list<dag> pattern> 1043 : I<opcode, OOL, IOL, asmstr, itin> { 1044 bits<6> XT; 1045 bits<8> IMM8; 1046 1047 let Pattern = pattern; 1048 1049 let Inst{6-10} = XT{4-0}; 1050 let Inst{11-12} = 0; 1051 let Inst{13-20} = IMM8; 1052 let Inst{21-30} = xo; 1053 let Inst{31} = XT{5}; 1054} 1055 1056// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1057// to specify an SDAG pattern for matching. 1058class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1059 string asmstr, InstrItinClass itin> 1060 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1061} 1062 1063class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1064 InstrItinClass itin> 1065 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1066 let RA = 0; 1067 let RB = 0; 1068} 1069 1070// [PO /// L RA RB XO /] 1071class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1072 string asmstr, InstrItinClass itin, list<dag> pattern> 1073 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1074 let BF = 0; 1075 let Pattern = pattern; 1076 1077 bit RC = 0; 1078 let Inst{31} = RC; 1079} 1080 1081// XX*-Form (VSX) 1082class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1083 InstrItinClass itin, list<dag> pattern> 1084 : I<opcode, OOL, IOL, asmstr, itin> { 1085 bits<6> XT; 1086 bits<5> RA; 1087 bits<5> RB; 1088 1089 let Pattern = pattern; 1090 1091 let Inst{6-10} = XT{4-0}; 1092 let Inst{11-15} = RA; 1093 let Inst{16-20} = RB; 1094 let Inst{21-30} = xo; 1095 let Inst{31} = XT{5}; 1096} 1097 1098class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1099 string asmstr, InstrItinClass itin, list<dag> pattern> 1100 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1101 1102class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1103 string asmstr, InstrItinClass itin, list<dag> pattern> 1104 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1105 let RB = 0; 1106} 1107 1108class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1109 InstrItinClass itin, list<dag> pattern> 1110 : I<opcode, OOL, IOL, asmstr, itin> { 1111 bits<6> XT; 1112 bits<6> XB; 1113 1114 let Pattern = pattern; 1115 1116 let Inst{6-10} = XT{4-0}; 1117 let Inst{11-15} = 0; 1118 let Inst{16-20} = XB{4-0}; 1119 let Inst{21-29} = xo; 1120 let Inst{30} = XB{5}; 1121 let Inst{31} = XT{5}; 1122} 1123 1124class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1125 InstrItinClass itin, list<dag> pattern> 1126 : I<opcode, OOL, IOL, asmstr, itin> { 1127 bits<3> CR; 1128 bits<6> XB; 1129 1130 let Pattern = pattern; 1131 1132 let Inst{6-8} = CR; 1133 let Inst{9-15} = 0; 1134 let Inst{16-20} = XB{4-0}; 1135 let Inst{21-29} = xo; 1136 let Inst{30} = XB{5}; 1137 let Inst{31} = 0; 1138} 1139 1140class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1141 InstrItinClass itin, list<dag> pattern> 1142 : I<opcode, OOL, IOL, asmstr, itin> { 1143 bits<6> XT; 1144 bits<6> XB; 1145 bits<2> D; 1146 1147 let Pattern = pattern; 1148 1149 let Inst{6-10} = XT{4-0}; 1150 let Inst{11-13} = 0; 1151 let Inst{14-15} = D; 1152 let Inst{16-20} = XB{4-0}; 1153 let Inst{21-29} = xo; 1154 let Inst{30} = XB{5}; 1155 let Inst{31} = XT{5}; 1156} 1157 1158class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1159 string asmstr, InstrItinClass itin, list<dag> pattern> 1160 : I<opcode, OOL, IOL, asmstr, itin> { 1161 bits<6> XT; 1162 bits<6> XB; 1163 bits<5> UIM5; 1164 1165 let Pattern = pattern; 1166 1167 let Inst{6-10} = XT{4-0}; 1168 let Inst{11-15} = UIM5; 1169 let Inst{16-20} = XB{4-0}; 1170 let Inst{21-29} = xo; 1171 let Inst{30} = XB{5}; 1172 let Inst{31} = XT{5}; 1173} 1174 1175// [PO T XO B XO BX /] 1176class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1177 string asmstr, InstrItinClass itin, list<dag> pattern> 1178 : I<opcode, OOL, IOL, asmstr, itin> { 1179 bits<5> RT; 1180 bits<6> XB; 1181 1182 let Pattern = pattern; 1183 1184 let Inst{6-10} = RT; 1185 let Inst{11-15} = xo2; 1186 let Inst{16-20} = XB{4-0}; 1187 let Inst{21-29} = xo; 1188 let Inst{30} = XB{5}; 1189 let Inst{31} = 0; 1190} 1191 1192// [PO T XO B XO BX TX] 1193class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1194 string asmstr, InstrItinClass itin, list<dag> pattern> 1195 : I<opcode, OOL, IOL, asmstr, itin> { 1196 bits<6> XT; 1197 bits<6> XB; 1198 1199 let Pattern = pattern; 1200 1201 let Inst{6-10} = XT{4-0}; 1202 let Inst{11-15} = xo2; 1203 let Inst{16-20} = XB{4-0}; 1204 let Inst{21-29} = xo; 1205 let Inst{30} = XB{5}; 1206 let Inst{31} = XT{5}; 1207} 1208 1209class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1210 string asmstr, InstrItinClass itin, list<dag> pattern> 1211 : I<opcode, OOL, IOL, asmstr, itin> { 1212 bits<3> BF; 1213 bits<7> DCMX; 1214 bits<6> XB; 1215 1216 let Pattern = pattern; 1217 1218 let Inst{6-8} = BF; 1219 let Inst{9-15} = DCMX; 1220 let Inst{16-20} = XB{4-0}; 1221 let Inst{21-29} = xo; 1222 let Inst{30} = XB{5}; 1223 let Inst{31} = 0; 1224} 1225 1226class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1227 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1228 list<dag> pattern> 1229 : I<opcode, OOL, IOL, asmstr, itin> { 1230 bits<6> XT; 1231 bits<7> DCMX; 1232 bits<6> XB; 1233 1234 let Pattern = pattern; 1235 1236 let Inst{6-10} = XT{4-0}; 1237 let Inst{11-15} = DCMX{4-0}; 1238 let Inst{16-20} = XB{4-0}; 1239 let Inst{21-24} = xo1; 1240 let Inst{25} = DCMX{6}; 1241 let Inst{26-28} = xo2; 1242 let Inst{29} = DCMX{5}; 1243 let Inst{30} = XB{5}; 1244 let Inst{31} = XT{5}; 1245} 1246 1247class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1248 string asmstr, InstrItinClass itin, list<dag> pattern> 1249 : I<opcode, OOL, IOL, asmstr, itin> { 1250 bits<5> RA; 1251 bits<6> D; 1252 bits<5> RB; 1253 1254 let Pattern = pattern; 1255 1256 let Inst{6-10} = D{4-0}; // D 1257 let Inst{11-15} = RA; 1258 let Inst{16-20} = RB; 1259 let Inst{21-30} = xo; 1260 let Inst{31} = D{5}; // DX 1261} 1262 1263class XForm_BF3_UIM6_FRB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1264 string asmstr, InstrItinClass itin, list<dag> pattern> 1265 : I<opcode, OOL, IOL, asmstr, itin> { 1266 bits<3> BF; 1267 bits<6> UIM; 1268 bits<5> FRB; 1269 1270 let Pattern = pattern; 1271 1272 let Inst{6-8} = BF; 1273 let Inst{9} = 0; 1274 let Inst{10-15} = UIM; 1275 let Inst{16-20} = FRB; 1276 let Inst{21-30} = xo; 1277 let Inst{31} = 0; 1278} 1279 1280class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1281 list<dag> pattern, InstrItinClass itin> 1282 : I<opcode, OOL, IOL, asmstr, itin> { 1283 bits<2> SP; 1284 bits<5> FRT; 1285 bits<5> FRB; 1286 1287 let Pattern = pattern; 1288 1289 bit RC = 0; // set by isRecordForm 1290 1291 let Inst{6 - 10} = FRT; 1292 let Inst{11 - 12} = SP; 1293 let Inst{13 - 15} = 0; 1294 let Inst{16 - 20} = FRB; 1295 let Inst{21 - 30} = xo; 1296 let Inst{31} = RC; 1297} 1298 1299class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1300 string asmstr, list<dag> pattern, InstrItinClass itin> 1301 : I<opcode, OOL, IOL, asmstr, itin> { 1302 bit S; 1303 bits<5> FRT; 1304 bits<5> FRB; 1305 1306 let Pattern = pattern; 1307 1308 bit RC = 0; // set by isRecordForm 1309 1310 let Inst{6 - 10} = FRT; 1311 let Inst{11} = S; 1312 let Inst{12 - 15} = 0; 1313 let Inst{16 - 20} = FRB; 1314 let Inst{21 - 30} = xo; 1315 let Inst{31} = RC; 1316} 1317 1318class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1319 InstrItinClass itin, list<dag> pattern> 1320 : I<opcode, OOL, IOL, asmstr, itin> { 1321 bits<6> XT; 1322 bits<6> XA; 1323 bits<6> XB; 1324 1325 let Pattern = pattern; 1326 1327 let Inst{6-10} = XT{4-0}; 1328 let Inst{11-15} = XA{4-0}; 1329 let Inst{16-20} = XB{4-0}; 1330 let Inst{21-28} = xo; 1331 let Inst{29} = XA{5}; 1332 let Inst{30} = XB{5}; 1333 let Inst{31} = XT{5}; 1334} 1335 1336class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1337 InstrItinClass itin, list<dag> pattern> 1338 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1339 let XA = XT; 1340 let XB = XT; 1341} 1342 1343class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1344 InstrItinClass itin, list<dag> pattern> 1345 : I<opcode, OOL, IOL, asmstr, itin> { 1346 bits<3> CR; 1347 bits<6> XA; 1348 bits<6> XB; 1349 1350 let Pattern = pattern; 1351 1352 let Inst{6-8} = CR; 1353 let Inst{9-10} = 0; 1354 let Inst{11-15} = XA{4-0}; 1355 let Inst{16-20} = XB{4-0}; 1356 let Inst{21-28} = xo; 1357 let Inst{29} = XA{5}; 1358 let Inst{30} = XB{5}; 1359 let Inst{31} = 0; 1360} 1361 1362class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1363 InstrItinClass itin, list<dag> pattern> 1364 : I<opcode, OOL, IOL, asmstr, itin> { 1365 bits<6> XT; 1366 bits<6> XA; 1367 bits<6> XB; 1368 bits<2> D; 1369 1370 let Pattern = pattern; 1371 1372 let Inst{6-10} = XT{4-0}; 1373 let Inst{11-15} = XA{4-0}; 1374 let Inst{16-20} = XB{4-0}; 1375 let Inst{21} = 0; 1376 let Inst{22-23} = D; 1377 let Inst{24-28} = xo; 1378 let Inst{29} = XA{5}; 1379 let Inst{30} = XB{5}; 1380 let Inst{31} = XT{5}; 1381} 1382 1383class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1384 InstrItinClass itin, list<dag> pattern> 1385 : I<opcode, OOL, IOL, asmstr, itin> { 1386 bits<6> XT; 1387 bits<6> XA; 1388 bits<6> XB; 1389 1390 let Pattern = pattern; 1391 1392 bit RC = 0; // set by isRecordForm 1393 1394 let Inst{6-10} = XT{4-0}; 1395 let Inst{11-15} = XA{4-0}; 1396 let Inst{16-20} = XB{4-0}; 1397 let Inst{21} = RC; 1398 let Inst{22-28} = xo; 1399 let Inst{29} = XA{5}; 1400 let Inst{30} = XB{5}; 1401 let Inst{31} = XT{5}; 1402} 1403 1404class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1405 InstrItinClass itin, list<dag> pattern> 1406 : I<opcode, OOL, IOL, asmstr, itin> { 1407 bits<6> XT; 1408 bits<6> XA; 1409 bits<6> XB; 1410 bits<6> XC; 1411 1412 let Pattern = pattern; 1413 1414 let Inst{6-10} = XT{4-0}; 1415 let Inst{11-15} = XA{4-0}; 1416 let Inst{16-20} = XB{4-0}; 1417 let Inst{21-25} = XC{4-0}; 1418 let Inst{26-27} = xo; 1419 let Inst{28} = XC{5}; 1420 let Inst{29} = XA{5}; 1421 let Inst{30} = XB{5}; 1422 let Inst{31} = XT{5}; 1423} 1424 1425// DCB_Form - Form X instruction, used for dcb* instructions. 1426class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1427 InstrItinClass itin, list<dag> pattern> 1428 : I<31, OOL, IOL, asmstr, itin> { 1429 bits<5> RA; 1430 bits<5> RB; 1431 1432 let Pattern = pattern; 1433 1434 let Inst{6-10} = immfield; 1435 let Inst{11-15} = RA; 1436 let Inst{16-20} = RB; 1437 let Inst{21-30} = xo; 1438 let Inst{31} = 0; 1439} 1440 1441class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1442 InstrItinClass itin, list<dag> pattern> 1443 : I<31, OOL, IOL, asmstr, itin> { 1444 bits<5> TH; 1445 bits<5> RA; 1446 bits<5> RB; 1447 1448 let Pattern = pattern; 1449 1450 let Inst{6-10} = TH; 1451 let Inst{11-15} = RA; 1452 let Inst{16-20} = RB; 1453 let Inst{21-30} = xo; 1454 let Inst{31} = 0; 1455} 1456 1457// DSS_Form - Form X instruction, used for altivec dss* instructions. 1458class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1459 InstrItinClass itin, list<dag> pattern> 1460 : I<31, OOL, IOL, asmstr, itin> { 1461 bits<2> STRM; 1462 bits<5> RA; 1463 bits<5> RB; 1464 1465 let Pattern = pattern; 1466 1467 let Inst{6} = T; 1468 let Inst{7-8} = 0; 1469 let Inst{9-10} = STRM; 1470 let Inst{11-15} = RA; 1471 let Inst{16-20} = RB; 1472 let Inst{21-30} = xo; 1473 let Inst{31} = 0; 1474} 1475 1476// 1.7.7 XL-Form 1477class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1478 InstrItinClass itin, list<dag> pattern> 1479 : I<opcode, OOL, IOL, asmstr, itin> { 1480 bits<5> CRD; 1481 bits<5> CRA; 1482 bits<5> CRB; 1483 1484 let Pattern = pattern; 1485 1486 let Inst{6-10} = CRD; 1487 let Inst{11-15} = CRA; 1488 let Inst{16-20} = CRB; 1489 let Inst{21-30} = xo; 1490 let Inst{31} = 0; 1491} 1492 1493// XL-Form for unary alias for CRNOR (CRNOT) 1494class XLForm_1s<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1495 InstrItinClass itin, list<dag> pattern> 1496 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1497 let CRB = CRA; 1498} 1499 1500class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1501 InstrItinClass itin, list<dag> pattern> 1502 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1503 let CRD = 0; 1504 let CRA = 0; 1505 let CRB = 0; 1506} 1507 1508class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1509 InstrItinClass itin, list<dag> pattern> 1510 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1511 bits<5> RT; 1512 bits<5> RB; 1513 1514 let CRD = RT; 1515 let CRA = 0; 1516 let CRB = RB; 1517} 1518 1519class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1520 InstrItinClass itin, list<dag> pattern> 1521 : I<opcode, OOL, IOL, asmstr, itin> { 1522 bits<5> CRD; 1523 1524 let Pattern = pattern; 1525 1526 let Inst{6-10} = CRD; 1527 let Inst{11-15} = CRD; 1528 let Inst{16-20} = CRD; 1529 let Inst{21-30} = xo; 1530 let Inst{31} = 0; 1531} 1532 1533class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1534 InstrItinClass itin, list<dag> pattern> 1535 : I<opcode, OOL, IOL, asmstr, itin> { 1536 bits<5> BO; 1537 bits<5> BI; 1538 bits<2> BH; 1539 1540 let Pattern = pattern; 1541 1542 let Inst{6-10} = BO; 1543 let Inst{11-15} = BI; 1544 let Inst{16-18} = 0; 1545 let Inst{19-20} = BH; 1546 let Inst{21-30} = xo; 1547 let Inst{31} = lk; 1548} 1549 1550class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1551 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1552 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1553 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1554 bits<3> CR; 1555 1556 let BO = BIBO{4-0}; 1557 let BI{0-1} = BIBO{5-6}; 1558 let BI{2-4} = CR{0-2}; 1559 let BH = 0; 1560} 1561 1562class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1563 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1564 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1565 let BO = bo; 1566 let BH = 0; 1567} 1568 1569class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1570 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1571 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1572 let BO = bo; 1573 let BI = bi; 1574 let BH = 0; 1575} 1576 1577class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1578 InstrItinClass itin> 1579 : I<opcode, OOL, IOL, asmstr, itin> { 1580 bits<3> BF; 1581 bits<3> BFA; 1582 1583 let Inst{6-8} = BF; 1584 let Inst{9-10} = 0; 1585 let Inst{11-13} = BFA; 1586 let Inst{14-15} = 0; 1587 let Inst{16-20} = 0; 1588 let Inst{21-30} = xo; 1589 let Inst{31} = 0; 1590} 1591 1592class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1593 InstrItinClass itin> 1594 : I<opcode, OOL, IOL, asmstr, itin> { 1595 bits<3> BF; 1596 bit W; 1597 bits<4> U; 1598 1599 bit RC = 0; 1600 1601 let Inst{6-8} = BF; 1602 let Inst{9-10} = 0; 1603 let Inst{11-14} = 0; 1604 let Inst{15} = W; 1605 let Inst{16-19} = U; 1606 let Inst{20} = 0; 1607 let Inst{21-30} = xo; 1608 let Inst{31} = RC; 1609} 1610 1611class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1612 InstrItinClass itin, list<dag> pattern> 1613 : I<opcode, OOL, IOL, asmstr, itin> { 1614 bits<1> S; 1615 1616 let Pattern = pattern; 1617 1618 let Inst{6-19} = 0; 1619 let Inst{20} = S; 1620 let Inst{21-30} = xo; 1621 let Inst{31} = 0; 1622} 1623 1624class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1625 bits<6> opcode2, bits<2> xo2, 1626 dag OOL, dag IOL, string asmstr, 1627 InstrItinClass itin, list<dag> pattern> 1628 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1629 bits<5> BO; 1630 bits<5> BI; 1631 bits<2> BH; 1632 1633 bits<5> RST; 1634 bits<5> RA; 1635 bits<14> D; 1636 1637 let Pattern = pattern; 1638 1639 let Inst{6-10} = BO; 1640 let Inst{11-15} = BI; 1641 let Inst{16-18} = 0; 1642 let Inst{19-20} = BH; 1643 let Inst{21-30} = xo1; 1644 let Inst{31} = lk; 1645 1646 let Inst{38-42} = RST; 1647 let Inst{43-47} = RA; 1648 let Inst{48-61} = D; 1649 let Inst{62-63} = xo2; 1650} 1651 1652class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1653 bits<5> bo, bits<5> bi, bit lk, 1654 bits<6> opcode2, bits<2> xo2, 1655 dag OOL, dag IOL, string asmstr, 1656 InstrItinClass itin, list<dag> pattern> 1657 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1658 OOL, IOL, asmstr, itin, pattern> { 1659 let BO = bo; 1660 let BI = bi; 1661 let BH = 0; 1662} 1663 1664class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1665 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1666 dag IOL, string asmstr, InstrItinClass itin, 1667 list<dag> pattern> 1668 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1669 1670 bits<5> RST; 1671 bits<5> RA; 1672 bits<16> D; 1673 1674 let Pattern = pattern; 1675 1676 let Inst{6-10} = bo; 1677 let Inst{11-15} = bi; 1678 let Inst{16-18} = 0; 1679 let Inst{19-20} = 0; // Unused (BH) 1680 let Inst{21-30} = xo1; 1681 let Inst{31} = lk; 1682 1683 let Inst{38-42} = RST; 1684 let Inst{43-47} = RA; 1685 let Inst{48-63} = D; 1686} 1687 1688// 1.7.8 XFX-Form 1689class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1690 InstrItinClass itin> 1691 : I<opcode, OOL, IOL, asmstr, itin> { 1692 bits<5> RST; 1693 bits<10> SPR; 1694 1695 let Inst{6-10} = RST; 1696 let Inst{11} = SPR{4}; 1697 let Inst{12} = SPR{3}; 1698 let Inst{13} = SPR{2}; 1699 let Inst{14} = SPR{1}; 1700 let Inst{15} = SPR{0}; 1701 let Inst{16} = SPR{9}; 1702 let Inst{17} = SPR{8}; 1703 let Inst{18} = SPR{7}; 1704 let Inst{19} = SPR{6}; 1705 let Inst{20} = SPR{5}; 1706 let Inst{21-30} = xo; 1707 let Inst{31} = 0; 1708} 1709 1710class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1711 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1712 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1713 let SPR = spr; 1714} 1715 1716class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1717 InstrItinClass itin> 1718 : I<opcode, OOL, IOL, asmstr, itin> { 1719 bits<5> RT; 1720 1721 let Inst{6-10} = RT; 1722 let Inst{11-20} = 0; 1723 let Inst{21-30} = xo; 1724 let Inst{31} = 0; 1725} 1726 1727class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1728 InstrItinClass itin, list<dag> pattern> 1729 : I<opcode, OOL, IOL, asmstr, itin> { 1730 bits<5> RT; 1731 bits<10> imm; 1732 let Pattern = pattern; 1733 1734 let Inst{6-10} = RT; 1735 let Inst{11-20} = imm; 1736 let Inst{21-30} = xo; 1737 let Inst{31} = 0; 1738} 1739 1740class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1741 InstrItinClass itin> 1742 : I<opcode, OOL, IOL, asmstr, itin> { 1743 bits<8> FXM; 1744 bits<5> RST; 1745 1746 let Inst{6-10} = RST; 1747 let Inst{11} = 0; 1748 let Inst{12-19} = FXM; 1749 let Inst{20} = 0; 1750 let Inst{21-30} = xo; 1751 let Inst{31} = 0; 1752} 1753 1754class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1755 InstrItinClass itin> 1756 : I<opcode, OOL, IOL, asmstr, itin> { 1757 bits<5> RST; 1758 bits<8> FXM; 1759 1760 let Inst{6-10} = RST; 1761 let Inst{11} = 1; 1762 let Inst{12-19} = FXM; 1763 let Inst{20} = 0; 1764 let Inst{21-30} = xo; 1765 let Inst{31} = 0; 1766} 1767 1768// XFL-Form - MTFSF 1769// This is probably 1.7.9, but I don't have the reference that uses this 1770// numbering scheme... 1771class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1772 InstrItinClass itin, list<dag>pattern> 1773 : I<opcode, OOL, IOL, asmstr, itin> { 1774 bits<8> FM; 1775 bits<5> RT; 1776 1777 bit RC = 0; // set by isRecordForm 1778 let Pattern = pattern; 1779 1780 let Inst{6} = 0; 1781 let Inst{7-14} = FM; 1782 let Inst{15} = 0; 1783 let Inst{16-20} = RT; 1784 let Inst{21-30} = xo; 1785 let Inst{31} = RC; 1786} 1787 1788class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1789 InstrItinClass itin, list<dag>pattern> 1790 : I<opcode, OOL, IOL, asmstr, itin> { 1791 bit L; 1792 bits<8> FLM; 1793 bit W; 1794 bits<5> FRB; 1795 1796 bit RC = 0; // set by isRecordForm 1797 let Pattern = pattern; 1798 1799 let Inst{6} = L; 1800 let Inst{7-14} = FLM; 1801 let Inst{15} = W; 1802 let Inst{16-20} = FRB; 1803 let Inst{21-30} = xo; 1804 let Inst{31} = RC; 1805} 1806 1807// 1.7.10 XS-Form - SRADI. 1808class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1809 InstrItinClass itin, list<dag> pattern> 1810 : I<opcode, OOL, IOL, asmstr, itin> { 1811 bits<5> RA; 1812 bits<5> RS; 1813 bits<6> SH; 1814 1815 bit RC = 0; // set by isRecordForm 1816 let Pattern = pattern; 1817 1818 let Inst{6-10} = RS; 1819 let Inst{11-15} = RA; 1820 let Inst{16-20} = SH{4,3,2,1,0}; 1821 let Inst{21-29} = xo; 1822 let Inst{30} = SH{5}; 1823 let Inst{31} = RC; 1824} 1825 1826// 1.7.11 XO-Form 1827class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1828 InstrItinClass itin, list<dag> pattern> 1829 : I<opcode, OOL, IOL, asmstr, itin> { 1830 bits<5> RT; 1831 bits<5> RA; 1832 bits<5> RB; 1833 1834 let Pattern = pattern; 1835 1836 bit RC = 0; // set by isRecordForm 1837 1838 let Inst{6-10} = RT; 1839 let Inst{11-15} = RA; 1840 let Inst{16-20} = RB; 1841 let Inst{21} = oe; 1842 let Inst{22-30} = xo; 1843 let Inst{31} = RC; 1844} 1845 1846class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1847 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1848 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1849 let RB = 0; 1850} 1851 1852// 1.7.12 A-Form 1853class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1854 InstrItinClass itin, list<dag> pattern> 1855 : I<opcode, OOL, IOL, asmstr, itin> { 1856 bits<5> FRT; 1857 bits<5> FRA; 1858 bits<5> FRC; 1859 bits<5> FRB; 1860 1861 let Pattern = pattern; 1862 1863 bit RC = 0; // set by isRecordForm 1864 1865 let Inst{6-10} = FRT; 1866 let Inst{11-15} = FRA; 1867 let Inst{16-20} = FRB; 1868 let Inst{21-25} = FRC; 1869 let Inst{26-30} = xo; 1870 let Inst{31} = RC; 1871} 1872 1873class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1874 InstrItinClass itin, list<dag> pattern> 1875 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1876 let FRC = 0; 1877} 1878 1879class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1880 InstrItinClass itin, list<dag> pattern> 1881 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1882 let FRB = 0; 1883} 1884 1885class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1886 InstrItinClass itin, list<dag> pattern> 1887 : I<opcode, OOL, IOL, asmstr, itin> { 1888 bits<5> RT; 1889 bits<5> RA; 1890 bits<5> RB; 1891 bits<5> COND; 1892 1893 let Pattern = pattern; 1894 1895 let Inst{6-10} = RT; 1896 let Inst{11-15} = RA; 1897 let Inst{16-20} = RB; 1898 let Inst{21-25} = COND; 1899 let Inst{26-30} = xo; 1900 let Inst{31} = 0; 1901} 1902 1903// 1.7.13 M-Form 1904class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1905 InstrItinClass itin, list<dag> pattern> 1906 : I<opcode, OOL, IOL, asmstr, itin> { 1907 bits<5> RA; 1908 bits<5> RS; 1909 bits<5> RB; 1910 bits<5> MB; 1911 bits<5> ME; 1912 1913 let Pattern = pattern; 1914 1915 bit RC = 0; // set by isRecordForm 1916 1917 let Inst{6-10} = RS; 1918 let Inst{11-15} = RA; 1919 let Inst{16-20} = RB; 1920 let Inst{21-25} = MB; 1921 let Inst{26-30} = ME; 1922 let Inst{31} = RC; 1923} 1924 1925class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1926 InstrItinClass itin, list<dag> pattern> 1927 : I<opcode, OOL, IOL, asmstr, itin> { 1928 bits<5> RA; 1929 bits<5> RS; 1930 bits<5> SH; 1931 bits<5> MB; 1932 bits<5> ME; 1933 1934 let Pattern = pattern; 1935 1936 bit RC = 0; // set by isRecordForm 1937 1938 let Inst{6-10} = RS; 1939 let Inst{11-15} = RA; 1940 let Inst{16-20} = SH; 1941 let Inst{21-25} = MB; 1942 let Inst{26-30} = ME; 1943 let Inst{31} = RC; 1944} 1945 1946// 1.7.14 MD-Form 1947class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1948 InstrItinClass itin, list<dag> pattern> 1949 : I<opcode, OOL, IOL, asmstr, itin> { 1950 bits<5> RA; 1951 bits<5> RS; 1952 bits<6> SH; 1953 bits<6> MBE; 1954 1955 let Pattern = pattern; 1956 1957 bit RC = 0; // set by isRecordForm 1958 1959 let Inst{6-10} = RS; 1960 let Inst{11-15} = RA; 1961 let Inst{16-20} = SH{4,3,2,1,0}; 1962 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1963 let Inst{27-29} = xo; 1964 let Inst{30} = SH{5}; 1965 let Inst{31} = RC; 1966} 1967 1968class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1969 InstrItinClass itin, list<dag> pattern> 1970 : I<opcode, OOL, IOL, asmstr, itin> { 1971 bits<5> RA; 1972 bits<5> RS; 1973 bits<5> RB; 1974 bits<6> MBE; 1975 1976 let Pattern = pattern; 1977 1978 bit RC = 0; // set by isRecordForm 1979 1980 let Inst{6-10} = RS; 1981 let Inst{11-15} = RA; 1982 let Inst{16-20} = RB; 1983 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1984 let Inst{27-30} = xo; 1985 let Inst{31} = RC; 1986} 1987 1988 1989// E-1 VA-Form 1990 1991// VAForm_1 - DACB ordering. 1992class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1993 InstrItinClass itin, list<dag> pattern> 1994 : I<4, OOL, IOL, asmstr, itin> { 1995 bits<5> RT; 1996 bits<5> RA; 1997 bits<5> RC; 1998 bits<5> RB; 1999 2000 let Pattern = pattern; 2001 2002 let Inst{6-10} = RT; 2003 let Inst{11-15} = RA; 2004 let Inst{16-20} = RB; 2005 let Inst{21-25} = RC; 2006 let Inst{26-31} = xo; 2007} 2008 2009// VAForm_1a - DABC ordering. 2010class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 2011 InstrItinClass itin, list<dag> pattern> 2012 : I<4, OOL, IOL, asmstr, itin> { 2013 bits<5> RT; 2014 bits<5> RA; 2015 bits<5> RB; 2016 bits<5> RC; 2017 2018 let Pattern = pattern; 2019 2020 let Inst{6-10} = RT; 2021 let Inst{11-15} = RA; 2022 let Inst{16-20} = RB; 2023 let Inst{21-25} = RC; 2024 let Inst{26-31} = xo; 2025} 2026 2027class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 2028 InstrItinClass itin, list<dag> pattern> 2029 : I<4, OOL, IOL, asmstr, itin> { 2030 bits<5> RT; 2031 bits<5> RA; 2032 bits<5> RB; 2033 bits<4> SH; 2034 2035 let Pattern = pattern; 2036 2037 let Inst{6-10} = RT; 2038 let Inst{11-15} = RA; 2039 let Inst{16-20} = RB; 2040 let Inst{21} = 0; 2041 let Inst{22-25} = SH; 2042 let Inst{26-31} = xo; 2043} 2044 2045// E-2 VX-Form 2046class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 2047 InstrItinClass itin, list<dag> pattern> 2048 : I<4, OOL, IOL, asmstr, itin> { 2049 bits<5> VD; 2050 bits<5> VA; 2051 bits<5> VB; 2052 2053 let Pattern = pattern; 2054 2055 let Inst{6-10} = VD; 2056 let Inst{11-15} = VA; 2057 let Inst{16-20} = VB; 2058 let Inst{21-31} = xo; 2059} 2060 2061class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 2062 InstrItinClass itin, list<dag> pattern> 2063 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 2064 let VA = VD; 2065 let VB = VD; 2066} 2067 2068 2069class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 2070 InstrItinClass itin, list<dag> pattern> 2071 : I<4, OOL, IOL, asmstr, itin> { 2072 bits<5> VD; 2073 bits<5> VB; 2074 2075 let Pattern = pattern; 2076 2077 let Inst{6-10} = VD; 2078 let Inst{11-15} = 0; 2079 let Inst{16-20} = VB; 2080 let Inst{21-31} = xo; 2081} 2082 2083class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 2084 InstrItinClass itin, list<dag> pattern> 2085 : I<4, OOL, IOL, asmstr, itin> { 2086 bits<5> VD; 2087 bits<5> IMM; 2088 2089 let Pattern = pattern; 2090 2091 let Inst{6-10} = VD; 2092 let Inst{11-15} = IMM; 2093 let Inst{16-20} = 0; 2094 let Inst{21-31} = xo; 2095} 2096 2097/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 2098class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 2099 InstrItinClass itin, list<dag> pattern> 2100 : I<4, OOL, IOL, asmstr, itin> { 2101 bits<5> VD; 2102 2103 let Pattern = pattern; 2104 2105 let Inst{6-10} = VD; 2106 let Inst{11-15} = 0; 2107 let Inst{16-20} = 0; 2108 let Inst{21-31} = xo; 2109} 2110 2111/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 2112class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 2113 InstrItinClass itin, list<dag> pattern> 2114 : I<4, OOL, IOL, asmstr, itin> { 2115 bits<5> VB; 2116 2117 let Pattern = pattern; 2118 2119 let Inst{6-10} = 0; 2120 let Inst{11-15} = 0; 2121 let Inst{16-20} = VB; 2122 let Inst{21-31} = xo; 2123} 2124 2125// e.g. [PO VRT EO VRB XO] 2126class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 2127 string asmstr, InstrItinClass itin, list<dag> pattern> 2128 : I<4, OOL, IOL, asmstr, itin> { 2129 bits<5> VD; 2130 bits<5> VB; 2131 2132 let Pattern = pattern; 2133 2134 let Inst{6-10} = VD; 2135 let Inst{11-15} = eo; 2136 let Inst{16-20} = VB; 2137 let Inst{21-31} = xo; 2138} 2139 2140/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2141class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2142 InstrItinClass itin, list<dag> pattern> 2143 : I<4, OOL, IOL, asmstr, itin> { 2144 bits<5> VD; 2145 bits<5> VA; 2146 bits<1> ST; 2147 bits<4> SIX; 2148 2149 let Pattern = pattern; 2150 2151 let Inst{6-10} = VD; 2152 let Inst{11-15} = VA; 2153 let Inst{16} = ST; 2154 let Inst{17-20} = SIX; 2155 let Inst{21-31} = xo; 2156} 2157 2158/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2159class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2160 InstrItinClass itin, list<dag> pattern> 2161 : I<4, OOL, IOL, asmstr, itin> { 2162 bits<5> VD; 2163 bits<5> VA; 2164 2165 let Pattern = pattern; 2166 2167 let Inst{6-10} = VD; 2168 let Inst{11-15} = VA; 2169 let Inst{16-20} = 0; 2170 let Inst{21-31} = xo; 2171} 2172 2173// E-4 VXR-Form 2174class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2175 InstrItinClass itin, list<dag> pattern> 2176 : I<4, OOL, IOL, asmstr, itin> { 2177 bits<5> VD; 2178 bits<5> VA; 2179 bits<5> VB; 2180 bit RC = 0; 2181 2182 let Pattern = pattern; 2183 2184 let Inst{6-10} = VD; 2185 let Inst{11-15} = VA; 2186 let Inst{16-20} = VB; 2187 let Inst{21} = RC; 2188 let Inst{22-31} = xo; 2189} 2190 2191// VX-Form: [PO VRT EO VRB 1 PS XO] 2192class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2193 dag OOL, dag IOL, string asmstr, 2194 InstrItinClass itin, list<dag> pattern> 2195 : I<4, OOL, IOL, asmstr, itin> { 2196 bits<5> VD; 2197 bits<5> VB; 2198 bit PS; 2199 2200 let Pattern = pattern; 2201 2202 let Inst{6-10} = VD; 2203 let Inst{11-15} = eo; 2204 let Inst{16-20} = VB; 2205 let Inst{21} = 1; 2206 let Inst{22} = PS; 2207 let Inst{23-31} = xo; 2208} 2209 2210// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2211class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2212 InstrItinClass itin, list<dag> pattern> 2213 : I<4, OOL, IOL, asmstr, itin> { 2214 bits<5> VD; 2215 bits<5> VA; 2216 bits<5> VB; 2217 bit PS; 2218 2219 let Pattern = pattern; 2220 2221 let Inst{6-10} = VD; 2222 let Inst{11-15} = VA; 2223 let Inst{16-20} = VB; 2224 let Inst{21} = 1; 2225 let Inst{22} = PS; 2226 let Inst{23-31} = xo; 2227} 2228 2229class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 2230 string asmstr, InstrItinClass itin, 2231 list<dag> pattern> 2232 : I<opcode, OOL, IOL, asmstr, itin> { 2233 bits<3> BF; 2234 bits<5> FRA; 2235 bits<6> DCM; 2236 2237 let Pattern = pattern; 2238 2239 let Inst{6-8} = BF; 2240 let Inst{9-10} = 0; 2241 let Inst{11-15} = FRA; 2242 let Inst{16-21} = DCM; 2243 let Inst{22-30} = xo; 2244 let Inst{31} = 0; 2245} 2246 2247class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 2248 string asmstr, list<dag> pattern, InstrItinClass itin> 2249 : I<opcode, OOL, IOL, asmstr, itin> { 2250 2251 bits<5> FRT; 2252 bits<5> FRA; 2253 bits<6> SH; 2254 2255 let Pattern = pattern; 2256 2257 bit RC = 0; // set by isRecordForm 2258 2259 let Inst{6 - 10} = FRT; 2260 let Inst{11 - 15} = FRA; 2261 let Inst{16 - 21} = SH; 2262 let Inst{22 - 30} = xo; 2263 let Inst{31} = RC; 2264} 2265 2266class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2267 InstrItinClass itin, list<dag> pattern> 2268 : I<opcode, OOL, IOL, asmstr, itin> { 2269 bits<5> VRT; 2270 bit R; 2271 bits<5> VRB; 2272 bits<2> idx; 2273 2274 let Pattern = pattern; 2275 2276 bit RC = 0; // set by isRecordForm 2277 2278 let Inst{6-10} = VRT; 2279 let Inst{11-14} = 0; 2280 let Inst{15} = R; 2281 let Inst{16-20} = VRB; 2282 let Inst{21-22} = idx; 2283 let Inst{23-30} = xo; 2284 let Inst{31} = RC; 2285} 2286 2287class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2288 string asmstr, InstrItinClass itin, list<dag> pattern> 2289 : I<opcode, OOL, IOL, asmstr, itin> { 2290 bits<5> RT; 2291 bits<5> RA; 2292 bits<5> RB; 2293 bits<2> CY; 2294 2295 let Pattern = pattern; 2296 2297 let Inst{6-10} = RT; 2298 let Inst{11-15} = RA; 2299 let Inst{16-20} = RB; 2300 let Inst{21-22} = CY; 2301 let Inst{23-30} = xo; 2302 let Inst{31} = 0; 2303} 2304 2305class Z23Form_FRTAB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2306 string asmstr, list<dag> pattern> 2307 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 2308 bits<5> FRT; 2309 bits<5> FRA; 2310 bits<5> FRB; 2311 bits<2> RMC; 2312 2313 let Pattern = pattern; 2314 2315 bit RC = 0; // set by isRecordForm 2316 2317 let Inst{6 - 10} = FRT; 2318 let Inst{11 - 15} = FRA; 2319 let Inst{16 - 20} = FRB; 2320 let Inst{21 - 22} = RMC; 2321 let Inst{23 - 30} = xo; 2322 let Inst{31} = RC; 2323} 2324 2325class Z23Form_TE5_FRTB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2326 string asmstr, list<dag> pattern> 2327 : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, asmstr, pattern> { 2328 bits<5> TE; 2329 let FRA = TE; 2330} 2331 2332class Z23Form_FRTB5_R1_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 2333 string asmstr, list<dag> pattern> 2334 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 2335 bits<5> FRT; 2336 bits<1> R; 2337 bits<5> FRB; 2338 bits<2> RMC; 2339 2340 let Pattern = pattern; 2341 2342 bit RC = 0; // set by isRecordForm 2343 2344 let Inst{6 - 10} = FRT; 2345 let Inst{11 - 14} = 0; 2346 let Inst{15} = R; 2347 let Inst{16 - 20} = FRB; 2348 let Inst{21 - 22} = RMC; 2349 let Inst{23 - 30} = xo; 2350 let Inst{31} = RC; 2351} 2352 2353//===----------------------------------------------------------------------===// 2354// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2355// stuff 2356class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2357 : I<0, OOL, IOL, asmstr, NoItinerary> { 2358 let isCodeGenOnly = 1; 2359 let PPC64 = 0; 2360 let Pattern = pattern; 2361 let Inst{31-0} = 0; 2362 let hasNoSchedulingInfo = 1; 2363} 2364 2365// Instruction that require custom insertion support 2366// a.k.a. ISelPseudos, however, these won't have isPseudo set 2367class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2368 list<dag> pattern> 2369 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2370 let usesCustomInserter = 1; 2371} 2372 2373// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2374// files is set only for PostRAPseudo 2375class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2376 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2377 let isPseudo = 1; 2378} 2379 2380class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2381 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2382 2383