1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Altivec extension to the PowerPC instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// *********************************** NOTE *********************************** 14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 15// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 16// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 17// ** whether lanes are numbered from left to right. An instruction like ** 18// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 19// ** relies only on the corresponding lane of the source vectors. However, ** 20// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 21// ** "odd" lanes are different for big-endian and little-endian numbering. ** 22// ** ** 23// ** When adding new VMX and VSX instructions, please consider whether they ** 24// ** are lane-sensitive. If so, they must be added to a switch statement ** 25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 26// **************************************************************************** 27 28 29//===----------------------------------------------------------------------===// 30// Altivec transformation functions and pattern fragments. 31// 32 33// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 34// of that type. 35def vnot_ppc : PatFrag<(ops node:$in), 36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 37 38def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 39 (vector_shuffle node:$lhs, node:$rhs), [{ 40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 41}]>; 42def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 43 (vector_shuffle node:$lhs, node:$rhs), [{ 44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 45}]>; 46def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 47 (vector_shuffle node:$lhs, node:$rhs), [{ 48 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 49}]>; 50def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 51 (vector_shuffle node:$lhs, node:$rhs), [{ 52 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 53}]>; 54def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 55 (vector_shuffle node:$lhs, node:$rhs), [{ 56 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 57}]>; 58def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 59 (vector_shuffle node:$lhs, node:$rhs), [{ 60 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 61}]>; 62 63// These fragments are provided for little-endian, where the inputs must be 64// swapped for correct semantics. 65def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 66 (vector_shuffle node:$lhs, node:$rhs), [{ 67 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 68}]>; 69def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 70 (vector_shuffle node:$lhs, node:$rhs), [{ 71 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 72}]>; 73def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 74 (vector_shuffle node:$lhs, node:$rhs), [{ 75 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 76}]>; 77 78def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 80 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 81}]>; 82def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 84 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 85}]>; 86def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 88 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 89}]>; 90def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 92 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 93}]>; 94def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 96 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 97}]>; 98def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 100 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 101}]>; 102 103 104def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 106 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 107}]>; 108def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 109 (vector_shuffle node:$lhs, node:$rhs), [{ 110 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 111}]>; 112def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 113 (vector_shuffle node:$lhs, node:$rhs), [{ 114 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 115}]>; 116def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 117 (vector_shuffle node:$lhs, node:$rhs), [{ 118 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 119}]>; 120def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 121 (vector_shuffle node:$lhs, node:$rhs), [{ 122 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 123}]>; 124def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 127}]>; 128 129 130// These fragments are provided for little-endian, where the inputs must be 131// swapped for correct semantics. 132def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 134 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 135}]>; 136def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 137 (vector_shuffle node:$lhs, node:$rhs), [{ 138 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 139}]>; 140def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 141 (vector_shuffle node:$lhs, node:$rhs), [{ 142 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 143}]>; 144def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 145 (vector_shuffle node:$lhs, node:$rhs), [{ 146 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 147}]>; 148def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 149 (vector_shuffle node:$lhs, node:$rhs), [{ 150 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 151}]>; 152def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 153 (vector_shuffle node:$lhs, node:$rhs), [{ 154 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 155}]>; 156 157 158def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 159 (vector_shuffle node:$lhs, node:$rhs), [{ 160 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG); 161}]>; 162def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 163 (vector_shuffle node:$lhs, node:$rhs), [{ 164 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG); 165}]>; 166def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 167 (vector_shuffle node:$lhs, node:$rhs), [{ 168 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG); 169}]>; 170def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 171 (vector_shuffle node:$lhs, node:$rhs), [{ 172 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG); 173}]>; 174def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 175 (vector_shuffle node:$lhs, node:$rhs), [{ 176 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG); 177}]>; 178def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 179 (vector_shuffle node:$lhs, node:$rhs), [{ 180 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG); 181}]>; 182 183 184 185def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 186 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); 187}]>; 188def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 189 (vector_shuffle node:$lhs, node:$rhs), [{ 190 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 191}], VSLDOI_get_imm>; 192 193 194/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 195/// vector_shuffle(X,undef,mask) by the dag combiner. 196def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 197 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); 198}]>; 199def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 200 (vector_shuffle node:$lhs, node:$rhs), [{ 201 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 202}], VSLDOI_unary_get_imm>; 203 204 205/// VSLDOI_swapped* - These fragments are provided for little-endian, where 206/// the inputs must be swapped for correct semantics. 207def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 208 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); 209}]>; 210def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 211 (vector_shuffle node:$lhs, node:$rhs), [{ 212 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 213}], VSLDOI_get_imm>; 214 215 216// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 217def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 218 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N)); 219}]>; 220def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 221 (vector_shuffle node:$lhs, node:$rhs), [{ 222 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 223}], VSPLTB_get_imm>; 224def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 225 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N)); 226}]>; 227def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 228 (vector_shuffle node:$lhs, node:$rhs), [{ 229 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 230}], VSPLTH_get_imm>; 231def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 232 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N)); 233}]>; 234def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 235 (vector_shuffle node:$lhs, node:$rhs), [{ 236 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 237}], VSPLTW_get_imm>; 238 239 240// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 241def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 242 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 243}]>; 244def vecspltisb : PatLeaf<(build_vector), [{ 245 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr; 246}], VSPLTISB_get_imm>; 247 248// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 249def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 250 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 251}]>; 252def vecspltish : PatLeaf<(build_vector), [{ 253 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr; 254}], VSPLTISH_get_imm>; 255 256// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 257def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 258 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 259}]>; 260def vecspltisw : PatLeaf<(build_vector), [{ 261 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr; 262}], VSPLTISW_get_imm>; 263 264//===----------------------------------------------------------------------===// 265// Helpers for defining instructions that directly correspond to intrinsics. 266 267// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 268class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 269 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 270 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 271 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 272 273// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 274// inputs doesn't match the type of the output. 275class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 276 ValueType InTy> 277 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 278 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 279 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 280 281// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 282// input types and an output type. 283class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 284 ValueType In1Ty, ValueType In2Ty> 285 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 286 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 287 [(set OutTy:$vD, 288 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 289 290// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 291class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 292 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 293 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 294 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 295 296// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 297// inputs doesn't match the type of the output. 298class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 299 ValueType InTy> 300 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 301 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 302 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 303 304// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 305// input types and an output type. 306class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 307 ValueType In1Ty, ValueType In2Ty> 308 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 309 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 310 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 311 312// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 313class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 314 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 315 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 316 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 317 318// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 319// inputs doesn't match the type of the output. 320class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 321 ValueType InTy> 322 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 323 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 324 [(set OutTy:$vD, (IntID InTy:$vB))]>; 325 326class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 327 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), 328 !strconcat(opc, " $vD, $vA"), IIC_VecFP, 329 [(set Ty:$vD, (IntID Ty:$vA))]>; 330 331class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 332 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), 333 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, 334 [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>; 335 336//===----------------------------------------------------------------------===// 337// Instruction Definitions. 338 339def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; 340let Predicates = [HasAltivec] in { 341 342def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 343 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 344 Deprecated<DeprecatedDST> { 345 let A = 0; 346 let B = 0; 347} 348 349def DSSALL : DSS_Form<1, 822, (outs), (ins), 350 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, 351 Deprecated<DeprecatedDST> { 352 let STRM = 0; 353 let A = 0; 354 let B = 0; 355} 356 357def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 358 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 359 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 360 Deprecated<DeprecatedDST>; 361 362def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 363 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 364 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 365 Deprecated<DeprecatedDST>; 366 367def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 368 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 369 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 370 Deprecated<DeprecatedDST>; 371 372def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 373 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 374 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 375 Deprecated<DeprecatedDST>; 376 377let isCodeGenOnly = 1 in { 378 // The very same instructions as above, but formally matching 64bit registers. 379 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 380 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 381 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 382 Deprecated<DeprecatedDST>; 383 384 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 385 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 386 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 387 Deprecated<DeprecatedDST>; 388 389 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 390 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 391 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 392 imm:$STRM)]>, 393 Deprecated<DeprecatedDST>; 394 395 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 396 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 397 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 398 imm:$STRM)]>, 399 Deprecated<DeprecatedDST>; 400} 401 402def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 403 "mfvscr $vD", IIC_LdStStore, 404 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 405def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 406 "mtvscr $vB", IIC_LdStLoad, 407 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 408 409let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. 410def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), 411 "lvebx $vD, $src", IIC_LdStLoad, 412 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 413def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), 414 "lvehx $vD, $src", IIC_LdStLoad, 415 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 416def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), 417 "lvewx $vD, $src", IIC_LdStLoad, 418 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 419def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), 420 "lvx $vD, $src", IIC_LdStLoad, 421 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 422def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), 423 "lvxl $vD, $src", IIC_LdStLoad, 424 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 425} 426 427def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), 428 "lvsl $vD, $src", IIC_LdStLoad, 429 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 430 PPC970_Unit_LSU; 431def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), 432 "lvsr $vD, $src", IIC_LdStLoad, 433 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 434 PPC970_Unit_LSU; 435 436let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. 437def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 438 "stvebx $rS, $dst", IIC_LdStStore, 439 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 440def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 441 "stvehx $rS, $dst", IIC_LdStStore, 442 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 443def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 444 "stvewx $rS, $dst", IIC_LdStStore, 445 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 446def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 447 "stvx $rS, $dst", IIC_LdStStore, 448 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 449def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 450 "stvxl $rS, $dst", IIC_LdStStore, 451 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 452} 453 454let PPC970_Unit = 5 in { // VALU Operations. 455// VA-Form instructions. 3-input AltiVec ops. 456let isCommutable = 1 in { 457def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 458 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 459 [(set v4f32:$vD, 460 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 461 462// FIXME: The fma+fneg pattern won't match because fneg is not legal. 463def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 464 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 465 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 466 (fneg v4f32:$vB))))]>; 467 468def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 469def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 470 v8i16>; 471def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 472} // isCommutable 473 474def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 475 v4i32, v4i32, v16i8>; 476def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 477 478// Shuffles. 479def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), 480 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 481 [(set v16i8:$vD, 482 (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; 483 484// VX-Form instructions. AltiVec arithmetic ops. 485let isCommutable = 1 in { 486def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 487 "vaddfp $vD, $vA, $vB", IIC_VecFP, 488 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 489 490def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 491 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 492 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 493def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 494 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 495 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 496def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 497 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 498 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 499 500def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 501def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 502def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 503def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 504def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 505def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 506def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 507} // isCommutable 508 509let isCommutable = 1 in 510def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 511 "vand $vD, $vA, $vB", IIC_VecFP, 512 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 513def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 514 "vandc $vD, $vA, $vB", IIC_VecFP, 515 [(set v4i32:$vD, (and v4i32:$vA, 516 (vnot_ppc v4i32:$vB)))]>; 517 518def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 519 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 520 [(set v4f32:$vD, 521 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 522def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 523 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 524 [(set v4f32:$vD, 525 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 526def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 527 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 528 [(set v4i32:$vD, 529 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 530def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 531 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 532 [(set v4i32:$vD, 533 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 534 535// Defines with the UIM field set to 0 for floating-point 536// to integer (fp_to_sint/fp_to_uint) conversions and integer 537// to floating-point (sint_to_fp/uint_to_fp) conversions. 538let isCodeGenOnly = 1, VA = 0 in { 539def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 540 "vcfsx $vD, $vB, 0", IIC_VecFP, 541 [(set v4f32:$vD, 542 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 543def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 544 "vctuxs $vD, $vB, 0", IIC_VecFP, 545 [(set v4i32:$vD, 546 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 547def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 548 "vcfux $vD, $vB, 0", IIC_VecFP, 549 [(set v4f32:$vD, 550 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 551def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 552 "vctsxs $vD, $vB, 0", IIC_VecFP, 553 [(set v4i32:$vD, 554 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 555} 556def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 557def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 558 559let isCommutable = 1 in { 560def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 561def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 562def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 563def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 564def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 565def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 566 567def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 568def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 569def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 570def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 571def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 572def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 573def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 574def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 575def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 576def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 577def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 578def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 579def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 580def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 581} // isCommutable 582 583def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 584 "vmrghb $vD, $vA, $vB", IIC_VecFP, 585 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 586def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 587 "vmrghh $vD, $vA, $vB", IIC_VecFP, 588 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 589def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 590 "vmrghw $vD, $vA, $vB", IIC_VecFP, 591 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 592def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 593 "vmrglb $vD, $vA, $vB", IIC_VecFP, 594 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 595def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 596 "vmrglh $vD, $vA, $vB", IIC_VecFP, 597 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 598def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 599 "vmrglw $vD, $vA, $vB", IIC_VecFP, 600 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 601 602def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 603 v4i32, v16i8, v4i32>; 604def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 605 v4i32, v8i16, v4i32>; 606def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 607 v4i32, v8i16, v4i32>; 608def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 609 v4i32, v16i8, v4i32>; 610def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 611 v4i32, v8i16, v4i32>; 612def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 613 v4i32, v8i16, v4i32>; 614 615let isCommutable = 1 in { 616def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 617 v8i16, v16i8>; 618def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 619 v4i32, v8i16>; 620def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 621 v8i16, v16i8>; 622def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 623 v4i32, v8i16>; 624def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 625 v8i16, v16i8>; 626def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 627 v4i32, v8i16>; 628def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 629 v8i16, v16i8>; 630def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 631 v4i32, v8i16>; 632} // isCommutable 633 634def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 635def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 636def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 637def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 638def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 639def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 640 641def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 642 643def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 644 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 645 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 646def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 647 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 648 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 649def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 650 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 651 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 652def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 653 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 654 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 655 656def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 657def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 658def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 659def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 660def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 661def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 662 663def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 664def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 665 666def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 667 v4i32, v16i8, v4i32>; 668def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 669 v4i32, v8i16, v4i32>; 670def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 671 v4i32, v16i8, v4i32>; 672 673def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 674 "vnor $vD, $vA, $vB", IIC_VecFP, 675 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 676 v4i32:$vB)))]>; 677let isCommutable = 1 in { 678def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 679 "vor $vD, $vA, $vB", IIC_VecFP, 680 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 681def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 682 "vxor $vD, $vA, $vB", IIC_VecFP, 683 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 684} // isCommutable 685 686def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 687def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 688def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 689 690def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 691def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 692 693def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 694def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 695def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 696 697def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 698 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 699 [(set v16i8:$vD, 700 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 701def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 702 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 703 [(set v16i8:$vD, 704 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 705def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 706 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 707 [(set v16i8:$vD, 708 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 709let isCodeGenOnly = 1 in { 710 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 711 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; 712 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 713 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; 714} 715 716def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 717def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 718 719def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 720def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 721def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 722def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 723def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 724def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 725 726 727def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 728 "vspltisb $vD, $SIMM", IIC_VecPerm, 729 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 730def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 731 "vspltish $vD, $SIMM", IIC_VecPerm, 732 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 733def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 734 "vspltisw $vD, $SIMM", IIC_VecPerm, 735 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 736 737// Vector Pack. 738def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 739 v8i16, v4i32>; 740def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 741 v16i8, v8i16>; 742def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 743 v16i8, v8i16>; 744def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 745 v8i16, v4i32>; 746def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 747 v8i16, v4i32>; 748def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 749 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 750 [(set v16i8:$vD, 751 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 752def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 753 v16i8, v8i16>; 754def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 755 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 756 [(set v16i8:$vD, 757 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 758def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 759 v8i16, v4i32>; 760 761// Vector Unpack. 762def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 763 v4i32, v8i16>; 764def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 765 v8i16, v16i8>; 766def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 767 v4i32, v8i16>; 768def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 769 v4i32, v8i16>; 770def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 771 v8i16, v16i8>; 772def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 773 v4i32, v8i16>; 774 775 776// Altivec Comparisons. 777 778class VCMP<bits<10> xo, string asmstr, ValueType Ty> 779 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 780 IIC_VecFPCompare, 781 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 782class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 783 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 784 IIC_VecFPCompare, 785 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 786 let Defs = [CR6]; 787 let RC = 1; 788} 789 790// f32 element comparisons.0 791def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 792def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 793def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 794def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 795def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 796def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 797def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 798def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 799 800// i8 element comparisons. 801def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 802def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 803def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 804def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 805def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 806def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 807 808// i16 element comparisons. 809def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 810def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 811def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 812def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 813def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 814def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 815 816// i32 element comparisons. 817def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 818def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 819def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 820def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 821def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 822def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 823 824let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 825 isReMaterializable = 1 in { 826 827def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 828 "vxor $vD, $vD, $vD", IIC_VecFP, 829 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 830def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 831 "vxor $vD, $vD, $vD", IIC_VecFP, 832 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 833def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 834 "vxor $vD, $vD, $vD", IIC_VecFP, 835 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 836 837let IMM=-1 in { 838def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 839 "vspltisw $vD, -1", IIC_VecFP, 840 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 841def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 842 "vspltisw $vD, -1", IIC_VecFP, 843 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 844def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 845 "vspltisw $vD, -1", IIC_VecFP, 846 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 847} 848} 849} // VALU Operations. 850 851//===----------------------------------------------------------------------===// 852// Additional Altivec Patterns 853// 854 855// Extended mnemonics 856def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 857def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 858 859// Loads. 860def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 861 862// Stores. 863def : Pat<(store v4i32:$rS, xoaddr:$dst), 864 (STVX $rS, xoaddr:$dst)>; 865 866// Bit conversions. 867def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 868def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 869def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 870def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 871def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>; 872 873def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 874def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 875def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 876def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 877def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>; 878 879def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 880def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 881def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 882def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 883def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>; 884 885def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 886def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 887def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 888def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 889def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>; 890 891def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 892def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 893def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 894def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 895def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>; 896 897def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>; 898def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>; 899def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; 900def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; 901def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; 902 903// Max/Min 904def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)), 905 (v16i8 (VMAXUB $src1, $src2))>; 906def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)), 907 (v16i8 (VMAXSB $src1, $src2))>; 908def : Pat<(v8i16 (umax v8i16:$src1, v8i16:$src2)), 909 (v8i16 (VMAXUH $src1, $src2))>; 910def : Pat<(v8i16 (smax v8i16:$src1, v8i16:$src2)), 911 (v8i16 (VMAXSH $src1, $src2))>; 912def : Pat<(v4i32 (umax v4i32:$src1, v4i32:$src2)), 913 (v4i32 (VMAXUW $src1, $src2))>; 914def : Pat<(v4i32 (smax v4i32:$src1, v4i32:$src2)), 915 (v4i32 (VMAXSW $src1, $src2))>; 916def : Pat<(v16i8 (umin v16i8:$src1, v16i8:$src2)), 917 (v16i8 (VMINUB $src1, $src2))>; 918def : Pat<(v16i8 (smin v16i8:$src1, v16i8:$src2)), 919 (v16i8 (VMINSB $src1, $src2))>; 920def : Pat<(v8i16 (umin v8i16:$src1, v8i16:$src2)), 921 (v8i16 (VMINUH $src1, $src2))>; 922def : Pat<(v8i16 (smin v8i16:$src1, v8i16:$src2)), 923 (v8i16 (VMINSH $src1, $src2))>; 924def : Pat<(v4i32 (umin v4i32:$src1, v4i32:$src2)), 925 (v4i32 (VMINUW $src1, $src2))>; 926def : Pat<(v4i32 (smin v4i32:$src1, v4i32:$src2)), 927 (v4i32 (VMINSW $src1, $src2))>; 928 929// Shuffles. 930 931// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 932def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 933 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 934def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 935 (VPKUWUM $vA, $vA)>; 936def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 937 (VPKUHUM $vA, $vA)>; 938def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB), 939 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>; 940 941 942// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 943// These fragments are matched for little-endian, where the inputs must 944// be swapped for correct semantics. 945def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 946 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 947def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 948 (VPKUWUM $vB, $vA)>; 949def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 950 (VPKUHUM $vB, $vA)>; 951 952// Match vmrg*(x,x) 953def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 954 (VMRGLB $vA, $vA)>; 955def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 956 (VMRGLH $vA, $vA)>; 957def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 958 (VMRGLW $vA, $vA)>; 959def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 960 (VMRGHB $vA, $vA)>; 961def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 962 (VMRGHH $vA, $vA)>; 963def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 964 (VMRGHW $vA, $vA)>; 965 966// Match vmrg*(y,x), i.e., swapped operands. These fragments 967// are matched for little-endian, where the inputs must be 968// swapped for correct semantics. 969def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 970 (VMRGLB $vB, $vA)>; 971def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 972 (VMRGLH $vB, $vA)>; 973def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 974 (VMRGLW $vB, $vA)>; 975def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 976 (VMRGHB $vB, $vA)>; 977def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 978 (VMRGHH $vB, $vA)>; 979def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 980 (VMRGHW $vB, $vA)>; 981 982// Logical Operations 983def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 984 985def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 986 (VNOR $A, $B)>; 987def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 988 (VANDC $A, $B)>; 989 990def : Pat<(fmul v4f32:$vA, v4f32:$vB), 991 (VMADDFP $vA, $vB, 992 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 993 994// Fused multiply add and multiply sub for packed float. These are represented 995// separately from the real instructions above, for operations that must have 996// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 997def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 998 (VMADDFP $A, $B, $C)>; 999def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 1000 (VNMSUBFP $A, $B, $C)>; 1001 1002def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 1003 (VMADDFP $A, $B, $C)>; 1004def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 1005 (VNMSUBFP $A, $B, $C)>; 1006 1007def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 1008 (VPERM $vA, $vB, $vC)>; 1009 1010def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 1011def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 1012 1013// Vector shifts 1014def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 1015 (v16i8 (VSLB $vA, $vB))>; 1016def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 1017 (v8i16 (VSLH $vA, $vB))>; 1018def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 1019 (v4i32 (VSLW $vA, $vB))>; 1020def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)), 1021 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1022def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)), 1023 (v16i8 (VSLB $vA, $vB))>; 1024def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)), 1025 (v8i16 (VSLH $vA, $vB))>; 1026def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)), 1027 (v4i32 (VSLW $vA, $vB))>; 1028def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)), 1029 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1030 1031def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 1032 (v16i8 (VSRB $vA, $vB))>; 1033def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 1034 (v8i16 (VSRH $vA, $vB))>; 1035def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 1036 (v4i32 (VSRW $vA, $vB))>; 1037def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)), 1038 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1039def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)), 1040 (v16i8 (VSRB $vA, $vB))>; 1041def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)), 1042 (v8i16 (VSRH $vA, $vB))>; 1043def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)), 1044 (v4i32 (VSRW $vA, $vB))>; 1045def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)), 1046 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1047 1048def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 1049 (v16i8 (VSRAB $vA, $vB))>; 1050def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 1051 (v8i16 (VSRAH $vA, $vB))>; 1052def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 1053 (v4i32 (VSRAW $vA, $vB))>; 1054def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)), 1055 (v16i8 (VSRAB $vA, $vB))>; 1056def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)), 1057 (v8i16 (VSRAH $vA, $vB))>; 1058def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)), 1059 (v4i32 (VSRAW $vA, $vB))>; 1060 1061// Float to integer and integer to float conversions 1062def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 1063 (VCTSXS_0 $vA)>; 1064def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 1065 (VCTUXS_0 $vA)>; 1066def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 1067 (VCFSX_0 $vA)>; 1068def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 1069 (VCFUX_0 $vA)>; 1070 1071// Floating-point rounding 1072def : Pat<(v4f32 (ffloor v4f32:$vA)), 1073 (VRFIM $vA)>; 1074def : Pat<(v4f32 (fceil v4f32:$vA)), 1075 (VRFIP $vA)>; 1076def : Pat<(v4f32 (ftrunc v4f32:$vA)), 1077 (VRFIZ $vA)>; 1078def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 1079 (VRFIN $vA)>; 1080 1081// Vector selection 1082def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 1083 (VSEL $vC, $vB, $vA)>; 1084def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 1085 (VSEL $vC, $vB, $vA)>; 1086def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)), 1087 (VSEL $vC, $vB, $vA)>; 1088def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)), 1089 (VSEL $vC, $vB, $vA)>; 1090def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)), 1091 (VSEL $vC, $vB, $vA)>; 1092def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)), 1093 (VSEL $vC, $vB, $vA)>; 1094 1095} // end HasAltivec 1096 1097def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; 1098def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">; 1099let Predicates = [HasP8Altivec] in { 1100 1101let isCommutable = 1 in { 1102def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 1103 v2i64, v4i32>; 1104def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 1105 v2i64, v4i32>; 1106def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 1107 v2i64, v4i32>; 1108def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 1109 v2i64, v4i32>; 1110def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1111 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, 1112 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; 1113def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 1114def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 1115def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 1116def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 1117} // isCommutable 1118 1119// Vector merge 1120def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1121 "vmrgew $vD, $vA, $vB", IIC_VecFP, 1122 [(set v16i8:$vD, 1123 (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; 1124def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1125 "vmrgow $vD, $vA, $vB", IIC_VecFP, 1126 [(set v16i8:$vD, 1127 (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; 1128 1129// Match vmrgew(x,x) and vmrgow(x,x) 1130def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), 1131 (VMRGEW $vA, $vA)>; 1132def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef), 1133 (VMRGOW $vA, $vA)>; 1134 1135// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments 1136// are matched for little-endian, where the inputs must be swapped for correct 1137// semantics.w 1138def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB), 1139 (VMRGEW $vB, $vA)>; 1140def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB), 1141 (VMRGOW $vB, $vA)>; 1142 1143 1144// Vector shifts 1145def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 1146def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1147 "vsld $vD, $vA, $vB", IIC_VecGeneral, []>; 1148def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1149 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; 1150def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1151 "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; 1152 1153def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), 1154 (v2i64 (VSLD $vA, $vB))>; 1155def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)), 1156 (v2i64 (VSLD $vA, $vB))>; 1157def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)), 1158 (v2i64 (VSRD $vA, $vB))>; 1159def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)), 1160 (v2i64 (VSRD $vA, $vB))>; 1161def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)), 1162 (v2i64 (VSRAD $vA, $vB))>; 1163def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)), 1164 (v2i64 (VSRAD $vA, $vB))>; 1165 1166// Vector Integer Arithmetic Instructions 1167let isCommutable = 1 in { 1168def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1169 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 1170 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 1171def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1172 "vadduqm $vD, $vA, $vB", IIC_VecGeneral, 1173 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; 1174} // isCommutable 1175 1176// Vector Quadword Add 1177def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>; 1178def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>; 1179def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; 1180 1181// Vector Doubleword Subtract 1182def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1183 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 1184 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 1185 1186// Vector Quadword Subtract 1187def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1188 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, 1189 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; 1190def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; 1191def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; 1192def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; 1193 1194// Count Leading Zeros 1195def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 1196 "vclzb $vD, $vB", IIC_VecGeneral, 1197 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 1198def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 1199 "vclzh $vD, $vB", IIC_VecGeneral, 1200 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 1201def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 1202 "vclzw $vD, $vB", IIC_VecGeneral, 1203 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 1204def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 1205 "vclzd $vD, $vB", IIC_VecGeneral, 1206 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 1207 1208// Population Count 1209def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 1210 "vpopcntb $vD, $vB", IIC_VecGeneral, 1211 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 1212def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 1213 "vpopcnth $vD, $vB", IIC_VecGeneral, 1214 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 1215def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1216 "vpopcntw $vD, $vB", IIC_VecGeneral, 1217 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1218def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1219 "vpopcntd $vD, $vB", IIC_VecGeneral, 1220 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1221 1222let isCommutable = 1 in { 1223// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1224// VSX equivalents. We need to fix this up at some point. Two possible 1225// solutions for this problem: 1226// 1. Disable Altivec patterns that compete with VSX patterns using the 1227// !HasVSX predicate. This essentially favours VSX over Altivec, in 1228// hopes of reducing register pressure (larger register set using VSX 1229// instructions than VMX instructions) 1230// 2. Employ a more disciplined use of AddedComplexity, which would provide 1231// more fine-grained control than option 1. This would be beneficial 1232// if we find situations where Altivec is really preferred over VSX. 1233def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1234 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1235 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; 1236def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1237 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1238 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; 1239} // isCommutable 1240 1241def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1242 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1243 [(set v4i32:$vD, (or v4i32:$vA, 1244 (vnot_ppc v4i32:$vB)))]>; 1245 1246// i64 element comparisons. 1247def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1248def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1249def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1250def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1251def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1252def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1253 1254// The cryptography instructions that do not require Category:Vector.Crypto 1255def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", 1256 int_ppc_altivec_crypto_vpmsumb, v16i8>; 1257def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", 1258 int_ppc_altivec_crypto_vpmsumh, v8i16>; 1259def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", 1260 int_ppc_altivec_crypto_vpmsumw, v4i32>; 1261def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", 1262 int_ppc_altivec_crypto_vpmsumd, v2i64>; 1263def VPERMXOR : VA1a_Int_Ty<45, "vpermxor", 1264 int_ppc_altivec_crypto_vpermxor, v16i8>; 1265 1266// Vector doubleword integer pack and unpack. 1267def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss, 1268 v4i32, v2i64>; 1269def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus, 1270 v4i32, v2i64>; 1271def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1272 "vpkudum $vD, $vA, $vB", IIC_VecFP, 1273 [(set v16i8:$vD, 1274 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; 1275def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, 1276 v4i32, v2i64>; 1277def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, 1278 v2i64, v4i32>; 1279def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, 1280 v2i64, v4i32>; 1281 1282// Shuffle patterns for unary and swapped (LE) vector pack modulo. 1283def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef), 1284 (VPKUDUM $vA, $vA)>; 1285def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1286 (VPKUDUM $vB, $vA)>; 1287 1288def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>; 1289def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq, 1290 v2i64, v16i8>; 1291} // end HasP8Altivec 1292 1293// Crypto instructions (from builtins) 1294let Predicates = [HasP8Crypto] in { 1295def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw", 1296 int_ppc_altivec_crypto_vshasigmaw, v4i32>; 1297def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad", 1298 int_ppc_altivec_crypto_vshasigmad, v2i64>; 1299def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher, 1300 v2i64>; 1301def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast", 1302 int_ppc_altivec_crypto_vcipherlast, v2i64>; 1303def VNCIPHER : VX1_Int_Ty<1352, "vncipher", 1304 int_ppc_altivec_crypto_vncipher, v2i64>; 1305def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast", 1306 int_ppc_altivec_crypto_vncipherlast, v2i64>; 1307def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; 1308} // HasP8Crypto 1309 1310// The following altivec instructions were introduced in Power ISA 3.0 1311def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">; 1312let Predicates = [HasP9Altivec] in { 1313 1314// i8 element comparisons. 1315def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; 1316def VCMPNEBo : VCMPo < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; 1317def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; 1318def VCMPNEZBo : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; 1319 1320// i16 element comparisons. 1321def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; 1322def VCMPNEHo : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; 1323def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; 1324def VCMPNEZHo : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; 1325 1326// i32 element comparisons. 1327def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; 1328def VCMPNEWo : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; 1329def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; 1330def VCMPNEZWo : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; 1331 1332// VX-Form: [PO VRT / UIM VRB XO]. 1333// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent 1334// "/ UIM" (1 + 4 bit) 1335class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern> 1336 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB), 1337 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>; 1338 1339class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1340 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB), 1341 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>; 1342 1343// Vector Extract Unsigned 1344def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; 1345def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>; 1346def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; 1347def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; 1348 1349// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed 1350def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>; 1351def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>; 1352def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>; 1353def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>; 1354def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>; 1355def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>; 1356 1357// Vector Insert Element Instructions 1358def VINSERTB : VXForm_1<781, (outs vrrc:$vD), 1359 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1360 "vinsertb $vD, $vB, $UIM", IIC_VecGeneral, 1361 [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, 1362 imm32SExt16:$UIM))]>, 1363 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1364def VINSERTH : VXForm_1<845, (outs vrrc:$vD), 1365 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1366 "vinserth $vD, $vB, $UIM", IIC_VecGeneral, 1367 [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, 1368 imm32SExt16:$UIM))]>, 1369 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1370def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; 1371def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; 1372 1373class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1374 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB), 1375 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1376class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1377 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB), 1378 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1379 1380// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] 1381def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), 1382 "vclzlsbb $rD, $vB", IIC_VecGeneral, 1383 [(set i32:$rD, (int_ppc_altivec_vclzlsbb 1384 v16i8:$vB))]>; 1385def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), 1386 "vctzlsbb $rD, $vB", IIC_VecGeneral, 1387 [(set i32:$rD, (int_ppc_altivec_vctzlsbb 1388 v16i8:$vB))]>; 1389// Vector Count Trailing Zeros 1390def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", 1391 [(set v16i8:$vD, (cttz v16i8:$vB))]>; 1392def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", 1393 [(set v8i16:$vD, (cttz v8i16:$vB))]>; 1394def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", 1395 [(set v4i32:$vD, (cttz v4i32:$vB))]>; 1396def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", 1397 [(set v2i64:$vD, (cttz v2i64:$vB))]>; 1398 1399// Vector Extend Sign 1400def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>; 1401def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>; 1402def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>; 1403def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>; 1404def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>; 1405let isCodeGenOnly = 1 in { 1406 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; 1407 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; 1408 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>; 1409 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>; 1410 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>; 1411} 1412 1413// Vector Integer Negate 1414def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", 1415 [(set v4i32:$vD, 1416 (sub (v4i32 immAllZerosV), v4i32:$vB))]>; 1417 1418def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", 1419 [(set v2i64:$vD, 1420 (sub (v2i64 (bitconvert (v4i32 immAllZerosV))), 1421 v2i64:$vB))]>; 1422 1423// Vector Parity Byte 1424def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, 1425 (int_ppc_altivec_vprtybw v4i32:$vB))]>; 1426def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, 1427 (int_ppc_altivec_vprtybd v2i64:$vB))]>; 1428def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, 1429 (int_ppc_altivec_vprtybq v1i128:$vB))]>; 1430 1431// Vector (Bit) Permute (Right-indexed) 1432def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1433 "vbpermd $vD, $vA, $vB", IIC_VecFP, []>; 1434def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1435 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; 1436 1437class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1438 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1439 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; 1440 1441// Vector Rotate Left Mask/Mask-Insert 1442def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", 1443 [(set v4i32:$vD, 1444 (int_ppc_altivec_vrlwnm v4i32:$vA, 1445 v4i32:$vB))]>; 1446def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1447 "vrlwmi $vD, $vA, $vB", IIC_VecFP, 1448 [(set v4i32:$vD, 1449 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, 1450 v4i32:$vDi))]>, 1451 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1452def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", 1453 [(set v2i64:$vD, 1454 (int_ppc_altivec_vrldnm v2i64:$vA, 1455 v2i64:$vB))]>; 1456def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1457 "vrldmi $vD, $vA, $vB", IIC_VecFP, 1458 [(set v2i64:$vD, 1459 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, 1460 v2i64:$vDi))]>, 1461 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1462 1463// Vector Shift Left/Right 1464def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", 1465 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; 1466def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", 1467 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; 1468 1469// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword 1470def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), 1471 "vmul10uq $vD, $vA", IIC_VecFP, []>; 1472def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), 1473 "vmul10cuq $vD, $vA", IIC_VecFP, []>; 1474 1475// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword 1476def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; 1477def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; 1478 1479// Decimal Integer Format Conversion Instructions 1480 1481// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. 1482class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc, 1483 list<dag> pattern> 1484 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS), 1485 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> { 1486 let Defs = [CR6]; 1487} 1488 1489// [PO VRT EO VRB 1 / XO] 1490class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc, 1491 list<dag> pattern> 1492 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB), 1493 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> { 1494 let Defs = [CR6]; 1495 let PS = 0; 1496} 1497 1498// Decimal Convert From/to National/Zoned/Signed-QWord 1499def BCDCFNo : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; 1500def BCDCFZo : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; 1501def BCDCTNo : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; 1502def BCDCTZo : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>; 1503def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>; 1504def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; 1505 1506// Decimal Copy-Sign/Set-Sign 1507let Defs = [CR6] in 1508def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; 1509 1510def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; 1511 1512// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. 1513class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1514 : VX_RD5_RSp5_PS1_XO9<xo, 1515 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS), 1516 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> { 1517 let Defs = [CR6]; 1518} 1519 1520// [PO VRT VRA VRB 1 / XO] 1521class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1522 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1523 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> { 1524 let Defs = [CR6]; 1525 let PS = 0; 1526} 1527 1528// Decimal Shift/Unsigned-Shift/Shift-and-Round 1529def BCDSo : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; 1530def BCDUSo : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; 1531def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; 1532 1533// Decimal (Unsigned) Truncate 1534def BCDTRUNCo : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; 1535def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; 1536 1537// Absolute Difference 1538def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1539 "vabsdub $vD, $vA, $vB", IIC_VecGeneral, 1540 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; 1541def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1542 "vabsduh $vD, $vA, $vB", IIC_VecGeneral, 1543 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; 1544def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1545 "vabsduw $vD, $vA, $vB", IIC_VecGeneral, 1546 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; 1547 1548} // end HasP9Altivec 1549