1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Altivec extension to the PowerPC instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// *********************************** NOTE *********************************** 14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 15// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 16// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 17// ** whether lanes are numbered from left to right. An instruction like ** 18// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 19// ** relies only on the corresponding lane of the source vectors. However, ** 20// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 21// ** "odd" lanes are different for big-endian and little-endian numbering. ** 22// ** ** 23// ** When adding new VMX and VSX instructions, please consider whether they ** 24// ** are lane-sensitive. If so, they must be added to a switch statement ** 25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 26// **************************************************************************** 27 28 29//===----------------------------------------------------------------------===// 30// Altivec transformation functions and pattern fragments. 31// 32 33// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 34// of that type. 35def vnot_ppc : PatFrag<(ops node:$in), 36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 37 38def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 39 (vector_shuffle node:$lhs, node:$rhs), [{ 40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 41}]>; 42def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 43 (vector_shuffle node:$lhs, node:$rhs), [{ 44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 45}]>; 46def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 47 (vector_shuffle node:$lhs, node:$rhs), [{ 48 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 49}]>; 50def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 51 (vector_shuffle node:$lhs, node:$rhs), [{ 52 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 53}]>; 54def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 55 (vector_shuffle node:$lhs, node:$rhs), [{ 56 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 57}]>; 58def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 59 (vector_shuffle node:$lhs, node:$rhs), [{ 60 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 61}]>; 62 63// These fragments are provided for little-endian, where the inputs must be 64// swapped for correct semantics. 65def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 66 (vector_shuffle node:$lhs, node:$rhs), [{ 67 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 68}]>; 69def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 70 (vector_shuffle node:$lhs, node:$rhs), [{ 71 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 72}]>; 73def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 74 (vector_shuffle node:$lhs, node:$rhs), [{ 75 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 76}]>; 77 78def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 80 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 81}]>; 82def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 84 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 85}]>; 86def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 88 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 89}]>; 90def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 92 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 93}]>; 94def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 96 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 97}]>; 98def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 100 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 101}]>; 102 103 104def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 106 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 107}]>; 108def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 109 (vector_shuffle node:$lhs, node:$rhs), [{ 110 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 111}]>; 112def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 113 (vector_shuffle node:$lhs, node:$rhs), [{ 114 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 115}]>; 116def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 117 (vector_shuffle node:$lhs, node:$rhs), [{ 118 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 119}]>; 120def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 121 (vector_shuffle node:$lhs, node:$rhs), [{ 122 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 123}]>; 124def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 127}]>; 128 129 130// These fragments are provided for little-endian, where the inputs must be 131// swapped for correct semantics. 132def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 134 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 135}]>; 136def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 137 (vector_shuffle node:$lhs, node:$rhs), [{ 138 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 139}]>; 140def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 141 (vector_shuffle node:$lhs, node:$rhs), [{ 142 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 143}]>; 144def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 145 (vector_shuffle node:$lhs, node:$rhs), [{ 146 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 147}]>; 148def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 149 (vector_shuffle node:$lhs, node:$rhs), [{ 150 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 151}]>; 152def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 153 (vector_shuffle node:$lhs, node:$rhs), [{ 154 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 155}]>; 156 157 158def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 159 (vector_shuffle node:$lhs, node:$rhs), [{ 160 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG); 161}]>; 162def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 163 (vector_shuffle node:$lhs, node:$rhs), [{ 164 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG); 165}]>; 166def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 167 (vector_shuffle node:$lhs, node:$rhs), [{ 168 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG); 169}]>; 170def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 171 (vector_shuffle node:$lhs, node:$rhs), [{ 172 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG); 173}]>; 174def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 175 (vector_shuffle node:$lhs, node:$rhs), [{ 176 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG); 177}]>; 178def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 179 (vector_shuffle node:$lhs, node:$rhs), [{ 180 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG); 181}]>; 182 183 184 185def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 186 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); 187}]>; 188def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 189 (vector_shuffle node:$lhs, node:$rhs), [{ 190 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 191}], VSLDOI_get_imm>; 192 193 194/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 195/// vector_shuffle(X,undef,mask) by the dag combiner. 196def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 197 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); 198}]>; 199def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 200 (vector_shuffle node:$lhs, node:$rhs), [{ 201 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 202}], VSLDOI_unary_get_imm>; 203 204 205/// VSLDOI_swapped* - These fragments are provided for little-endian, where 206/// the inputs must be swapped for correct semantics. 207def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 208 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); 209}]>; 210def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 211 (vector_shuffle node:$lhs, node:$rhs), [{ 212 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 213}], VSLDOI_get_imm>; 214 215 216// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 217def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 218 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 1, *CurDAG), SDLoc(N)); 219}]>; 220def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 221 (vector_shuffle node:$lhs, node:$rhs), [{ 222 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 223}], VSPLTB_get_imm>; 224def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 225 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 2, *CurDAG), SDLoc(N)); 226}]>; 227def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 228 (vector_shuffle node:$lhs, node:$rhs), [{ 229 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 230}], VSPLTH_get_imm>; 231def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 232 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 4, *CurDAG), SDLoc(N)); 233}]>; 234def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 235 (vector_shuffle node:$lhs, node:$rhs), [{ 236 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 237}], VSPLTW_get_imm>; 238 239 240// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 241def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 242 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 243}]>; 244def vecspltisb : PatLeaf<(build_vector), [{ 245 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr; 246}], VSPLTISB_get_imm>; 247 248// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 249def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 250 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 251}]>; 252def vecspltish : PatLeaf<(build_vector), [{ 253 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr; 254}], VSPLTISH_get_imm>; 255 256// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 257def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 258 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 259}]>; 260def vecspltisw : PatLeaf<(build_vector), [{ 261 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr; 262}], VSPLTISW_get_imm>; 263 264def immEQOneV : PatLeaf<(build_vector), [{ 265 if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode()) 266 return C->isOne(); 267 return false; 268}]>; 269//===----------------------------------------------------------------------===// 270// Helpers for defining instructions that directly correspond to intrinsics. 271 272// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 273class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 274 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 275 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 276 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 277 278// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 279// inputs doesn't match the type of the output. 280class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 281 ValueType InTy> 282 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 283 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 284 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 285 286// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 287// input types and an output type. 288class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 289 ValueType In1Ty, ValueType In2Ty> 290 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 291 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 292 [(set OutTy:$vD, 293 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 294 295// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 296class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 297 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 298 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 299 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 300 301// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 302// inputs doesn't match the type of the output. 303class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 304 ValueType InTy> 305 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 306 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 307 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 308 309// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 310// input types and an output type. 311class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 312 ValueType In1Ty, ValueType In2Ty> 313 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 314 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 315 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 316 317// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 318class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 319 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 320 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 321 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 322 323// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 324// inputs doesn't match the type of the output. 325class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 326 ValueType InTy> 327 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 328 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 329 [(set OutTy:$vD, (IntID InTy:$vB))]>; 330 331class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 332 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), 333 !strconcat(opc, " $vD, $vA"), IIC_VecFP, 334 [(set Ty:$vD, (IntID Ty:$vA))]>; 335 336class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 337 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), 338 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, 339 [(set Ty:$vD, (IntID Ty:$vA, timm:$ST, timm:$SIX))]>; 340 341//===----------------------------------------------------------------------===// 342// Instruction Definitions. 343 344def HasAltivec : Predicate<"Subtarget->hasAltivec()">; 345let Predicates = [HasAltivec] in { 346 347def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 348 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 349 Deprecated<DeprecatedDST> { 350 let A = 0; 351 let B = 0; 352} 353 354def DSSALL : DSS_Form<1, 822, (outs), (ins), 355 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, 356 Deprecated<DeprecatedDST> { 357 let STRM = 0; 358 let A = 0; 359 let B = 0; 360} 361 362def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 363 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 364 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 365 Deprecated<DeprecatedDST>; 366 367def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 368 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 369 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 370 Deprecated<DeprecatedDST>; 371 372def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 373 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 374 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 375 Deprecated<DeprecatedDST>; 376 377def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 378 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 379 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 380 Deprecated<DeprecatedDST>; 381 382let isCodeGenOnly = 1 in { 383 // The very same instructions as above, but formally matching 64bit registers. 384 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 385 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 386 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 387 Deprecated<DeprecatedDST>; 388 389 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 390 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 391 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 392 Deprecated<DeprecatedDST>; 393 394 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 395 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 396 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 397 imm:$STRM)]>, 398 Deprecated<DeprecatedDST>; 399 400 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 401 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 402 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 403 imm:$STRM)]>, 404 Deprecated<DeprecatedDST>; 405} 406 407let hasSideEffects = 1 in { 408 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 409 "mfvscr $vD", IIC_LdStStore, 410 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 411 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 412 "mtvscr $vB", IIC_LdStLoad, 413 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 414} 415 416let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. 417def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), 418 "lvebx $vD, $src", IIC_LdStLoad, 419 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 420def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), 421 "lvehx $vD, $src", IIC_LdStLoad, 422 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 423def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), 424 "lvewx $vD, $src", IIC_LdStLoad, 425 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 426def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), 427 "lvx $vD, $src", IIC_LdStLoad, 428 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 429def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), 430 "lvxl $vD, $src", IIC_LdStLoad, 431 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 432} 433 434def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), 435 "lvsl $vD, $src", IIC_LdStLoad, 436 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 437 PPC970_Unit_LSU; 438def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), 439 "lvsr $vD, $src", IIC_LdStLoad, 440 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 441 PPC970_Unit_LSU; 442 443let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. 444def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 445 "stvebx $rS, $dst", IIC_LdStStore, 446 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 447def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 448 "stvehx $rS, $dst", IIC_LdStStore, 449 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 450def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 451 "stvewx $rS, $dst", IIC_LdStStore, 452 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 453def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 454 "stvx $rS, $dst", IIC_LdStStore, 455 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 456def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 457 "stvxl $rS, $dst", IIC_LdStStore, 458 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 459} 460 461let PPC970_Unit = 5 in { // VALU Operations. 462// VA-Form instructions. 3-input AltiVec ops. 463let isCommutable = 1 in { 464def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 465 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 466 [(set v4f32:$vD, 467 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 468 469// FIXME: The fma+fneg pattern won't match because fneg is not legal. 470def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 471 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 472 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 473 (fneg v4f32:$vB))))]>; 474let hasSideEffects = 1 in { 475 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 476 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 477 v8i16>; 478} 479def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 480} // isCommutable 481 482def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 483 v4i32, v4i32, v16i8>; 484def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 485 486// Shuffles. 487def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), 488 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 489 [(set v16i8:$vD, 490 (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; 491 492// VX-Form instructions. AltiVec arithmetic ops. 493let isCommutable = 1 in { 494def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 495 "vaddfp $vD, $vA, $vB", IIC_VecFP, 496 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 497 498def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 499 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 500 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 501def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 502 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 503 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 504def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 505 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 506 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 507 508def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 509def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 510def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 511def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 512def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 513def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 514def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 515} // isCommutable 516 517let isCommutable = 1 in 518def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 519 "vand $vD, $vA, $vB", IIC_VecFP, 520 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 521def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 522 "vandc $vD, $vA, $vB", IIC_VecFP, 523 [(set v4i32:$vD, (and v4i32:$vA, 524 (vnot_ppc v4i32:$vB)))]>; 525 526def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 527 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 528 [(set v4f32:$vD, 529 (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>; 530def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 531 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 532 [(set v4f32:$vD, 533 (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>; 534def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 535 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 536 [(set v4i32:$vD, 537 (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>; 538def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 539 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 540 [(set v4i32:$vD, 541 (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>; 542 543// Defines with the UIM field set to 0 for floating-point 544// to integer (fp_to_sint/fp_to_uint) conversions and integer 545// to floating-point (sint_to_fp/uint_to_fp) conversions. 546let isCodeGenOnly = 1, VA = 0 in { 547def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 548 "vcfsx $vD, $vB, 0", IIC_VecFP, 549 [(set v4f32:$vD, 550 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 551def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 552 "vctuxs $vD, $vB, 0", IIC_VecFP, 553 [(set v4i32:$vD, 554 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 555def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 556 "vcfux $vD, $vB, 0", IIC_VecFP, 557 [(set v4f32:$vD, 558 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 559def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 560 "vctsxs $vD, $vB, 0", IIC_VecFP, 561 [(set v4i32:$vD, 562 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 563} 564def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 565def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 566 567let isCommutable = 1 in { 568def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 569def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 570def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 571def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 572def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 573def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 574 575def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 576def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 577def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 578def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 579def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 580def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 581def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 582def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 583def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 584def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 585def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 586def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 587def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 588def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 589} // isCommutable 590 591def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 592 "vmrghb $vD, $vA, $vB", IIC_VecFP, 593 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 594def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 595 "vmrghh $vD, $vA, $vB", IIC_VecFP, 596 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 597def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 598 "vmrghw $vD, $vA, $vB", IIC_VecFP, 599 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 600def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 601 "vmrglb $vD, $vA, $vB", IIC_VecFP, 602 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 603def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 604 "vmrglh $vD, $vA, $vB", IIC_VecFP, 605 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 606def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 607 "vmrglw $vD, $vA, $vB", IIC_VecFP, 608 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 609 610def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 611 v4i32, v16i8, v4i32>; 612def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 613 v4i32, v8i16, v4i32>; 614def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 615 v4i32, v16i8, v4i32>; 616def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 617 v4i32, v8i16, v4i32>; 618let hasSideEffects = 1 in { 619 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 620 v4i32, v8i16, v4i32>; 621 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 622 v4i32, v8i16, v4i32>; 623} 624 625let isCommutable = 1 in { 626def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 627 v8i16, v16i8>; 628def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 629 v4i32, v8i16>; 630def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 631 v8i16, v16i8>; 632def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 633 v4i32, v8i16>; 634def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 635 v8i16, v16i8>; 636def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 637 v4i32, v8i16>; 638def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 639 v8i16, v16i8>; 640def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 641 v4i32, v8i16>; 642} // isCommutable 643 644def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 645def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 646def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 647def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 648def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 649def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 650 651def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 652 653def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 654 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 655 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 656def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 657 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 658 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 659def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 660 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 661 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 662def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 663 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 664 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 665 666def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 667def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 668def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 669def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 670def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 671def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 672 673let hasSideEffects = 1 in { 674 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 675 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 676 677 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 678 v4i32, v16i8, v4i32>; 679 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 680 v4i32, v8i16, v4i32>; 681 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 682 v4i32, v16i8, v4i32>; 683} 684 685def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 686 "vnor $vD, $vA, $vB", IIC_VecFP, 687 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 688 v4i32:$vB)))]>; 689let isCommutable = 1 in { 690def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 691 "vor $vD, $vA, $vB", IIC_VecFP, 692 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 693def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 694 "vxor $vD, $vA, $vB", IIC_VecFP, 695 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 696} // isCommutable 697 698def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 699def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 700def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 701 702def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 703def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 704 705def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 706def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 707def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 708 709def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 710 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 711 [(set v16i8:$vD, 712 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 713def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 714 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 715 [(set v16i8:$vD, 716 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 717def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 718 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 719 [(set v16i8:$vD, 720 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 721let isCodeGenOnly = 1, hasSideEffects = 0 in { 722 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 723 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; 724 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 725 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; 726} 727 728def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 729def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 730 731def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 732def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 733def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 734def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 735def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 736def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 737 738 739def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 740 "vspltisb $vD, $SIMM", IIC_VecPerm, 741 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 742def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 743 "vspltish $vD, $SIMM", IIC_VecPerm, 744 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 745def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 746 "vspltisw $vD, $SIMM", IIC_VecPerm, 747 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 748 749// Vector Pack. 750def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 751 v8i16, v4i32>; 752let hasSideEffects = 1 in { 753 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 754 v16i8, v8i16>; 755 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 756 v16i8, v8i16>; 757 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 758 v8i16, v4i32>; 759 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 760 v8i16, v4i32>; 761 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 762 v16i8, v8i16>; 763 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 764 v8i16, v4i32>; 765} 766def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 767 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 768 [(set v16i8:$vD, 769 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 770def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 771 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 772 [(set v16i8:$vD, 773 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 774 775// Vector Unpack. 776def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 777 v4i32, v8i16>; 778def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 779 v8i16, v16i8>; 780def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 781 v4i32, v8i16>; 782def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 783 v4i32, v8i16>; 784def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 785 v8i16, v16i8>; 786def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 787 v4i32, v8i16>; 788 789 790// Altivec Comparisons. 791 792class VCMP<bits<10> xo, string asmstr, ValueType Ty> 793 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 794 IIC_VecFPCompare, 795 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 796class VCMP_rec<bits<10> xo, string asmstr, ValueType Ty> 797 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 798 IIC_VecFPCompare, 799 [(set Ty:$vD, (Ty (PPCvcmp_rec Ty:$vA, Ty:$vB, xo)))]> { 800 let Defs = [CR6]; 801 let RC = 1; 802} 803 804// f32 element comparisons.0 805def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 806def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 807def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 808def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 809def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 810def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 811def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 812def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 813 814// i8 element comparisons. 815def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 816def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 817def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 818def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 819def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 820def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 821 822// i16 element comparisons. 823def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 824def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 825def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 826def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 827def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 828def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 829 830// i32 element comparisons. 831def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 832def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 833def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 834def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 835def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 836def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 837 838let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 839 isReMaterializable = 1 in { 840 841def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 842 "vxor $vD, $vD, $vD", IIC_VecFP, 843 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 844def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 845 "vxor $vD, $vD, $vD", IIC_VecFP, 846 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 847def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 848 "vxor $vD, $vD, $vD", IIC_VecFP, 849 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 850 851let IMM=-1 in { 852def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 853 "vspltisw $vD, -1", IIC_VecFP, 854 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 855def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 856 "vspltisw $vD, -1", IIC_VecFP, 857 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 858def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 859 "vspltisw $vD, -1", IIC_VecFP, 860 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 861} 862} 863} // VALU Operations. 864 865//===----------------------------------------------------------------------===// 866// Additional Altivec Patterns 867// 868 869// Extended mnemonics 870def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 871def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 872 873// Rotates. 874def : Pat<(v16i8 (rotl v16i8:$vA, v16i8:$vB)), 875 (v16i8 (VRLB v16i8:$vA, v16i8:$vB))>; 876def : Pat<(v8i16 (rotl v8i16:$vA, v8i16:$vB)), 877 (v8i16 (VRLH v8i16:$vA, v8i16:$vB))>; 878def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)), 879 (v4i32 (VRLW v4i32:$vA, v4i32:$vB))>; 880 881// Multiply 882def : Pat<(mul v8i16:$vA, v8i16:$vB), (VMLADDUHM $vA, $vB, (v8i16(V_SET0H)))>; 883 884// Add 885def : Pat<(add (mul v8i16:$vA, v8i16:$vB), v8i16:$vC), (VMLADDUHM $vA, $vB, $vC)>; 886 887// Saturating adds/subtracts. 888def : Pat<(v16i8 (saddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDSBS $vA, $vB))>; 889def : Pat<(v16i8 (uaddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDUBS $vA, $vB))>; 890def : Pat<(v8i16 (saddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDSHS $vA, $vB))>; 891def : Pat<(v8i16 (uaddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDUHS $vA, $vB))>; 892def : Pat<(v4i32 (saddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDSWS $vA, $vB))>; 893def : Pat<(v4i32 (uaddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDUWS $vA, $vB))>; 894def : Pat<(v16i8 (ssubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBSBS $vA, $vB))>; 895def : Pat<(v16i8 (usubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBUBS $vA, $vB))>; 896def : Pat<(v8i16 (ssubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBSHS $vA, $vB))>; 897def : Pat<(v8i16 (usubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBUHS $vA, $vB))>; 898def : Pat<(v4i32 (ssubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBSWS $vA, $vB))>; 899def : Pat<(v4i32 (usubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBUWS $vA, $vB))>; 900 901// Loads. 902def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 903 904// Stores. 905def : Pat<(store v4i32:$rS, xoaddr:$dst), 906 (STVX $rS, xoaddr:$dst)>; 907 908// Bit conversions. 909def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 910def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 911def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 912def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 913def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>; 914 915def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 916def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 917def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 918def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 919def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>; 920 921def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 922def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 923def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 924def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 925def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>; 926 927def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 928def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 929def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 930def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 931def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>; 932 933def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 934def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 935def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 936def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 937def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>; 938 939def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>; 940def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>; 941def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; 942def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; 943def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; 944 945def : Pat<(f128 (bitconvert (v16i8 VRRC:$src))), (f128 VRRC:$src)>; 946def : Pat<(f128 (bitconvert (v8i16 VRRC:$src))), (f128 VRRC:$src)>; 947def : Pat<(f128 (bitconvert (v4i32 VRRC:$src))), (f128 VRRC:$src)>; 948def : Pat<(f128 (bitconvert (v4f32 VRRC:$src))), (f128 VRRC:$src)>; 949def : Pat<(f128 (bitconvert (v2f64 VRRC:$src))), (f128 VRRC:$src)>; 950 951def : Pat<(v16i8 (bitconvert (f128 VRRC:$src))), (v16i8 VRRC:$src)>; 952def : Pat<(v8i16 (bitconvert (f128 VRRC:$src))), (v8i16 VRRC:$src)>; 953def : Pat<(v4i32 (bitconvert (f128 VRRC:$src))), (v4i32 VRRC:$src)>; 954def : Pat<(v4f32 (bitconvert (f128 VRRC:$src))), (v4f32 VRRC:$src)>; 955def : Pat<(v2f64 (bitconvert (f128 VRRC:$src))), (v2f64 VRRC:$src)>; 956 957// Max/Min 958def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)), 959 (v16i8 (VMAXUB $src1, $src2))>; 960def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)), 961 (v16i8 (VMAXSB $src1, $src2))>; 962def : Pat<(v8i16 (umax v8i16:$src1, v8i16:$src2)), 963 (v8i16 (VMAXUH $src1, $src2))>; 964def : Pat<(v8i16 (smax v8i16:$src1, v8i16:$src2)), 965 (v8i16 (VMAXSH $src1, $src2))>; 966def : Pat<(v4i32 (umax v4i32:$src1, v4i32:$src2)), 967 (v4i32 (VMAXUW $src1, $src2))>; 968def : Pat<(v4i32 (smax v4i32:$src1, v4i32:$src2)), 969 (v4i32 (VMAXSW $src1, $src2))>; 970def : Pat<(v16i8 (umin v16i8:$src1, v16i8:$src2)), 971 (v16i8 (VMINUB $src1, $src2))>; 972def : Pat<(v16i8 (smin v16i8:$src1, v16i8:$src2)), 973 (v16i8 (VMINSB $src1, $src2))>; 974def : Pat<(v8i16 (umin v8i16:$src1, v8i16:$src2)), 975 (v8i16 (VMINUH $src1, $src2))>; 976def : Pat<(v8i16 (smin v8i16:$src1, v8i16:$src2)), 977 (v8i16 (VMINSH $src1, $src2))>; 978def : Pat<(v4i32 (umin v4i32:$src1, v4i32:$src2)), 979 (v4i32 (VMINUW $src1, $src2))>; 980def : Pat<(v4i32 (smin v4i32:$src1, v4i32:$src2)), 981 (v4i32 (VMINSW $src1, $src2))>; 982 983// Shuffles. 984 985// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 986def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 987 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 988def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 989 (VPKUWUM $vA, $vA)>; 990def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 991 (VPKUHUM $vA, $vA)>; 992def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB), 993 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>; 994 995 996// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 997// These fragments are matched for little-endian, where the inputs must 998// be swapped for correct semantics. 999def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 1000 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 1001def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1002 (VPKUWUM $vB, $vA)>; 1003def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1004 (VPKUHUM $vB, $vA)>; 1005 1006// Match vmrg*(x,x) 1007def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 1008 (VMRGLB $vA, $vA)>; 1009def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 1010 (VMRGLH $vA, $vA)>; 1011def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 1012 (VMRGLW $vA, $vA)>; 1013def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 1014 (VMRGHB $vA, $vA)>; 1015def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 1016 (VMRGHH $vA, $vA)>; 1017def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 1018 (VMRGHW $vA, $vA)>; 1019 1020// Match vmrg*(y,x), i.e., swapped operands. These fragments 1021// are matched for little-endian, where the inputs must be 1022// swapped for correct semantics. 1023def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 1024 (VMRGLB $vB, $vA)>; 1025def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 1026 (VMRGLH $vB, $vA)>; 1027def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 1028 (VMRGLW $vB, $vA)>; 1029def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 1030 (VMRGHB $vB, $vA)>; 1031def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 1032 (VMRGHH $vB, $vA)>; 1033def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 1034 (VMRGHW $vB, $vA)>; 1035 1036// Logical Operations 1037def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 1038 1039def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 1040 (VNOR $A, $B)>; 1041def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 1042 (VANDC $A, $B)>; 1043 1044def : Pat<(fmul v4f32:$vA, v4f32:$vB), 1045 (VMADDFP $vA, $vB, 1046 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 1047 1048def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), 1049 (VNMSUBFP $A, $B, $C)>; 1050 1051def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 1052 (VMADDFP $A, $B, $C)>; 1053def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 1054 (VNMSUBFP $A, $B, $C)>; 1055 1056def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 1057 (VPERM $vA, $vB, $vC)>; 1058 1059def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 1060def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 1061 1062// Vector shifts 1063def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 1064 (v16i8 (VSLB $vA, $vB))>; 1065def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 1066 (v8i16 (VSLH $vA, $vB))>; 1067def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 1068 (v4i32 (VSLW $vA, $vB))>; 1069def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)), 1070 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1071def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)), 1072 (v16i8 (VSLB $vA, $vB))>; 1073def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)), 1074 (v8i16 (VSLH $vA, $vB))>; 1075def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)), 1076 (v4i32 (VSLW $vA, $vB))>; 1077def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)), 1078 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1079 1080def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 1081 (v16i8 (VSRB $vA, $vB))>; 1082def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 1083 (v8i16 (VSRH $vA, $vB))>; 1084def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 1085 (v4i32 (VSRW $vA, $vB))>; 1086def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)), 1087 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1088def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)), 1089 (v16i8 (VSRB $vA, $vB))>; 1090def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)), 1091 (v8i16 (VSRH $vA, $vB))>; 1092def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)), 1093 (v4i32 (VSRW $vA, $vB))>; 1094def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)), 1095 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1096 1097def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 1098 (v16i8 (VSRAB $vA, $vB))>; 1099def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 1100 (v8i16 (VSRAH $vA, $vB))>; 1101def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 1102 (v4i32 (VSRAW $vA, $vB))>; 1103def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)), 1104 (v16i8 (VSRAB $vA, $vB))>; 1105def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)), 1106 (v8i16 (VSRAH $vA, $vB))>; 1107def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)), 1108 (v4i32 (VSRAW $vA, $vB))>; 1109 1110// Float to integer and integer to float conversions 1111def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 1112 (VCTSXS_0 $vA)>; 1113def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 1114 (VCTUXS_0 $vA)>; 1115def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 1116 (VCFSX_0 $vA)>; 1117def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 1118 (VCFUX_0 $vA)>; 1119 1120// Floating-point rounding 1121def : Pat<(v4f32 (ffloor v4f32:$vA)), 1122 (VRFIM $vA)>; 1123def : Pat<(v4f32 (fceil v4f32:$vA)), 1124 (VRFIP $vA)>; 1125def : Pat<(v4f32 (ftrunc v4f32:$vA)), 1126 (VRFIZ $vA)>; 1127def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 1128 (VRFIN $vA)>; 1129 1130// Vector selection 1131def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 1132 (VSEL $vC, $vB, $vA)>; 1133def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 1134 (VSEL $vC, $vB, $vA)>; 1135def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)), 1136 (VSEL $vC, $vB, $vA)>; 1137def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)), 1138 (VSEL $vC, $vB, $vA)>; 1139def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)), 1140 (VSEL $vC, $vB, $vA)>; 1141def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)), 1142 (VSEL $vC, $vB, $vA)>; 1143 1144// Vector Integer Average Instructions 1145def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), 1146 (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>; 1147def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), 1148 (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>; 1149def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), 1150 (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>; 1151def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), 1152 (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>; 1153def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), 1154 (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>; 1155def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), 1156 (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>; 1157 1158} // end HasAltivec 1159 1160def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; 1161def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; 1162let Predicates = [HasP8Altivec] in { 1163 1164let isCommutable = 1 in { 1165def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 1166 v2i64, v4i32>; 1167def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 1168 v2i64, v4i32>; 1169def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 1170 v2i64, v4i32>; 1171def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 1172 v2i64, v4i32>; 1173def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1174 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, 1175 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; 1176def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 1177def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 1178def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 1179def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 1180} // isCommutable 1181 1182// Vector merge 1183def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1184 "vmrgew $vD, $vA, $vB", IIC_VecFP, 1185 [(set v16i8:$vD, 1186 (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; 1187def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1188 "vmrgow $vD, $vA, $vB", IIC_VecFP, 1189 [(set v16i8:$vD, 1190 (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; 1191 1192// Match vmrgew(x,x) and vmrgow(x,x) 1193def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), 1194 (VMRGEW $vA, $vA)>; 1195def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef), 1196 (VMRGOW $vA, $vA)>; 1197 1198// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments 1199// are matched for little-endian, where the inputs must be swapped for correct 1200// semantics.w 1201def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB), 1202 (VMRGEW $vB, $vA)>; 1203def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB), 1204 (VMRGOW $vB, $vA)>; 1205 1206// Vector rotates. 1207def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 1208 1209def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)), 1210 (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>; 1211 1212// Vector shifts 1213def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1214 "vsld $vD, $vA, $vB", IIC_VecGeneral, []>; 1215def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1216 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; 1217def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1218 "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; 1219 1220def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), 1221 (v2i64 (VSLD $vA, $vB))>; 1222def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)), 1223 (v2i64 (VSLD $vA, $vB))>; 1224def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)), 1225 (v2i64 (VSRD $vA, $vB))>; 1226def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)), 1227 (v2i64 (VSRD $vA, $vB))>; 1228def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)), 1229 (v2i64 (VSRAD $vA, $vB))>; 1230def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)), 1231 (v2i64 (VSRAD $vA, $vB))>; 1232 1233// Vector Integer Arithmetic Instructions 1234let isCommutable = 1 in { 1235def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1236 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 1237 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 1238def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1239 "vadduqm $vD, $vA, $vB", IIC_VecGeneral, 1240 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; 1241} // isCommutable 1242 1243// Vector Quadword Add 1244def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>; 1245def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>; 1246def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; 1247 1248// Vector Doubleword Subtract 1249def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1250 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 1251 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 1252 1253// Vector Quadword Subtract 1254def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1255 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, 1256 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; 1257def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; 1258def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; 1259def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; 1260 1261// Count Leading Zeros 1262def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 1263 "vclzb $vD, $vB", IIC_VecGeneral, 1264 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 1265def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 1266 "vclzh $vD, $vB", IIC_VecGeneral, 1267 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 1268def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 1269 "vclzw $vD, $vB", IIC_VecGeneral, 1270 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 1271def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 1272 "vclzd $vD, $vB", IIC_VecGeneral, 1273 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 1274 1275// Population Count 1276def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 1277 "vpopcntb $vD, $vB", IIC_VecGeneral, 1278 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 1279def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 1280 "vpopcnth $vD, $vB", IIC_VecGeneral, 1281 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 1282def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1283 "vpopcntw $vD, $vB", IIC_VecGeneral, 1284 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1285def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1286 "vpopcntd $vD, $vB", IIC_VecGeneral, 1287 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1288 1289let isCommutable = 1 in { 1290// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1291// VSX equivalents. We need to fix this up at some point. Two possible 1292// solutions for this problem: 1293// 1. Disable Altivec patterns that compete with VSX patterns using the 1294// !HasVSX predicate. This essentially favours VSX over Altivec, in 1295// hopes of reducing register pressure (larger register set using VSX 1296// instructions than VMX instructions) 1297// 2. Employ a more disciplined use of AddedComplexity, which would provide 1298// more fine-grained control than option 1. This would be beneficial 1299// if we find situations where Altivec is really preferred over VSX. 1300def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1301 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1302 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; 1303def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1304 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1305 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; 1306} // isCommutable 1307 1308def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1309 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1310 [(set v4i32:$vD, (or v4i32:$vA, 1311 (vnot_ppc v4i32:$vB)))]>; 1312 1313// i64 element comparisons. 1314def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1315def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1316def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1317def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1318def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1319def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1320 1321// The cryptography instructions that do not require Category:Vector.Crypto 1322def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", 1323 int_ppc_altivec_crypto_vpmsumb, v16i8>; 1324def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", 1325 int_ppc_altivec_crypto_vpmsumh, v8i16>; 1326def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", 1327 int_ppc_altivec_crypto_vpmsumw, v4i32>; 1328def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", 1329 int_ppc_altivec_crypto_vpmsumd, v2i64>; 1330def VPERMXOR : VAForm_1<45, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VC), 1331 "vpermxor $VD, $VA, $VB, $VC", IIC_VecFP, []>; 1332 1333// Vector doubleword integer pack and unpack. 1334let hasSideEffects = 1 in { 1335 def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss, 1336 v4i32, v2i64>; 1337 def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus, 1338 v4i32, v2i64>; 1339 def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, 1340 v4i32, v2i64>; 1341} 1342def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1343 "vpkudum $vD, $vA, $vB", IIC_VecFP, 1344 [(set v16i8:$vD, 1345 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; 1346def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, 1347 v2i64, v4i32>; 1348def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, 1349 v2i64, v4i32>; 1350 1351// Shuffle patterns for unary and swapped (LE) vector pack modulo. 1352def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef), 1353 (VPKUDUM $vA, $vA)>; 1354def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1355 (VPKUDUM $vB, $vA)>; 1356 1357def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>; 1358def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq, 1359 v2i64, v16i8>; 1360} // end HasP8Altivec 1361 1362// Crypto instructions (from builtins) 1363let Predicates = [HasP8Crypto] in { 1364def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw", 1365 int_ppc_altivec_crypto_vshasigmaw, v4i32>; 1366def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad", 1367 int_ppc_altivec_crypto_vshasigmad, v2i64>; 1368def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher, 1369 v2i64>; 1370def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast", 1371 int_ppc_altivec_crypto_vcipherlast, v2i64>; 1372def VNCIPHER : VX1_Int_Ty<1352, "vncipher", 1373 int_ppc_altivec_crypto_vncipher, v2i64>; 1374def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast", 1375 int_ppc_altivec_crypto_vncipherlast, v2i64>; 1376def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; 1377} // HasP8Crypto 1378 1379// The following altivec instructions were introduced in Power ISA 3.0 1380def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; 1381let Predicates = [HasP9Altivec] in { 1382 1383// Vector Multiply-Sum 1384def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm, 1385 v1i128, v2i64, v1i128>; 1386 1387// i8 element comparisons. 1388def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; 1389def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; 1390def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; 1391def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; 1392 1393// i16 element comparisons. 1394def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; 1395def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; 1396def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; 1397def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; 1398 1399// i32 element comparisons. 1400def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; 1401def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; 1402def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; 1403def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; 1404 1405// VX-Form: [PO VRT / UIM VRB XO]. 1406// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent 1407// "/ UIM" (1 + 4 bit) 1408class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern> 1409 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB), 1410 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>; 1411 1412class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1413 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB), 1414 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>; 1415 1416// Vector Extract Unsigned 1417def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; 1418def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>; 1419def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; 1420def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; 1421 1422// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed 1423let hasSideEffects = 0 in { 1424def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>; 1425def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>; 1426def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>; 1427def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>; 1428def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>; 1429def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>; 1430} 1431 1432// Vector Insert Element Instructions 1433def VINSERTB : VXForm_1<781, (outs vrrc:$vD), 1434 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1435 "vinsertb $vD, $vB, $UIM", IIC_VecGeneral, 1436 [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, 1437 imm32SExt16:$UIM))]>, 1438 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1439def VINSERTH : VXForm_1<845, (outs vrrc:$vD), 1440 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1441 "vinserth $vD, $vB, $UIM", IIC_VecGeneral, 1442 [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, 1443 imm32SExt16:$UIM))]>, 1444 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1445def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; 1446def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; 1447 1448class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1449 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB), 1450 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1451class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1452 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB), 1453 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1454 1455// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] 1456def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), 1457 "vclzlsbb $rD, $vB", IIC_VecGeneral, 1458 [(set i32:$rD, (int_ppc_altivec_vclzlsbb 1459 v16i8:$vB))]>; 1460def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), 1461 "vctzlsbb $rD, $vB", IIC_VecGeneral, 1462 [(set i32:$rD, (int_ppc_altivec_vctzlsbb 1463 v16i8:$vB))]>; 1464// Vector Count Trailing Zeros 1465def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", 1466 [(set v16i8:$vD, (cttz v16i8:$vB))]>; 1467def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", 1468 [(set v8i16:$vD, (cttz v8i16:$vB))]>; 1469def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", 1470 [(set v4i32:$vD, (cttz v4i32:$vB))]>; 1471def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", 1472 [(set v2i64:$vD, (cttz v2i64:$vB))]>; 1473 1474// Vector Extend Sign 1475def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", 1476 [(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>; 1477def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", 1478 [(set v4i32:$vD, (int_ppc_altivec_vextsh2w v8i16:$vB))]>; 1479def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", 1480 [(set v2i64:$vD, (int_ppc_altivec_vextsb2d v16i8:$vB))]>; 1481def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", 1482 [(set v2i64:$vD, (int_ppc_altivec_vextsh2d v8i16:$vB))]>; 1483def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", 1484 [(set v2i64:$vD, (int_ppc_altivec_vextsw2d v4i32:$vB))]>; 1485let isCodeGenOnly = 1 in { 1486 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; 1487 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; 1488 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>; 1489 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>; 1490 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>; 1491} 1492 1493def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>; 1494def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>; 1495def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>; 1496def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>; 1497def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>; 1498 1499// Vector Integer Negate 1500def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", 1501 [(set v4i32:$vD, 1502 (sub (v4i32 immAllZerosV), v4i32:$vB))]>; 1503 1504def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", 1505 [(set v2i64:$vD, 1506 (sub (v2i64 (bitconvert (v4i32 immAllZerosV))), 1507 v2i64:$vB))]>; 1508 1509// Vector Parity Byte 1510def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, 1511 (int_ppc_altivec_vprtybw v4i32:$vB))]>; 1512def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, 1513 (int_ppc_altivec_vprtybd v2i64:$vB))]>; 1514def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, 1515 (int_ppc_altivec_vprtybq v1i128:$vB))]>; 1516 1517// Vector (Bit) Permute (Right-indexed) 1518def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1519 "vbpermd $vD, $vA, $vB", IIC_VecFP, []>; 1520def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1521 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; 1522 1523class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1524 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1525 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; 1526 1527// Vector Rotate Left Mask/Mask-Insert 1528def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", 1529 [(set v4i32:$vD, 1530 (int_ppc_altivec_vrlwnm v4i32:$vA, 1531 v4i32:$vB))]>; 1532def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1533 "vrlwmi $vD, $vA, $vB", IIC_VecFP, 1534 [(set v4i32:$vD, 1535 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, 1536 v4i32:$vDi))]>, 1537 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1538def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", 1539 [(set v2i64:$vD, 1540 (int_ppc_altivec_vrldnm v2i64:$vA, 1541 v2i64:$vB))]>; 1542def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1543 "vrldmi $vD, $vA, $vB", IIC_VecFP, 1544 [(set v2i64:$vD, 1545 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, 1546 v2i64:$vDi))]>, 1547 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1548 1549// Vector Shift Left/Right 1550def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", 1551 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; 1552def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", 1553 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; 1554 1555// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword 1556def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), 1557 "vmul10uq $vD, $vA", IIC_VecFP, []>; 1558def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), 1559 "vmul10cuq $vD, $vA", IIC_VecFP, []>; 1560 1561// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword 1562def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; 1563def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; 1564 1565// Decimal Integer Format Conversion Instructions 1566 1567// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. 1568class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc, 1569 list<dag> pattern> 1570 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS), 1571 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> { 1572 let Defs = [CR6]; 1573} 1574 1575// [PO VRT EO VRB 1 / XO] 1576class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc, 1577 list<dag> pattern> 1578 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB), 1579 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> { 1580 let Defs = [CR6]; 1581 let PS = 0; 1582} 1583 1584// Decimal Convert From/to National/Zoned/Signed-QWord 1585def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; 1586def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; 1587def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; 1588def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>; 1589def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>; 1590def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; 1591 1592// Decimal Copy-Sign/Set-Sign 1593let Defs = [CR6] in 1594def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; 1595 1596def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; 1597 1598// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. 1599class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1600 : VX_RD5_RSp5_PS1_XO9<xo, 1601 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS), 1602 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> { 1603 let Defs = [CR6]; 1604} 1605 1606// [PO VRT VRA VRB 1 / XO] 1607class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1608 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1609 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> { 1610 let Defs = [CR6]; 1611 let PS = 0; 1612} 1613 1614// Decimal Shift/Unsigned-Shift/Shift-and-Round 1615def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; 1616def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; 1617def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; 1618 1619// Decimal (Unsigned) Truncate 1620def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; 1621def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; 1622 1623// Absolute Difference 1624def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1625 "vabsdub $vD, $vA, $vB", IIC_VecGeneral, 1626 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; 1627def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1628 "vabsduh $vD, $vA, $vB", IIC_VecGeneral, 1629 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; 1630def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1631 "vabsduw $vD, $vA, $vB", IIC_VecGeneral, 1632 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; 1633 1634} // end HasP9Altivec 1635