1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Altivec extension to the PowerPC instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// *********************************** NOTE *********************************** 14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 15// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 16// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 17// ** whether lanes are numbered from left to right. An instruction like ** 18// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 19// ** relies only on the corresponding lane of the source vectors. However, ** 20// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 21// ** "odd" lanes are different for big-endian and little-endian numbering. ** 22// ** ** 23// ** When adding new VMX and VSX instructions, please consider whether they ** 24// ** are lane-sensitive. If so, they must be added to a switch statement ** 25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 26// **************************************************************************** 27 28 29//===----------------------------------------------------------------------===// 30// Altivec transformation functions and pattern fragments. 31// 32 33// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 34// of that type. 35def vnot_ppc : PatFrag<(ops node:$in), 36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 37 38def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 39 (vector_shuffle node:$lhs, node:$rhs), [{ 40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 41}]>; 42def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 43 (vector_shuffle node:$lhs, node:$rhs), [{ 44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 45}]>; 46def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 47 (vector_shuffle node:$lhs, node:$rhs), [{ 48 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 49}]>; 50def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 51 (vector_shuffle node:$lhs, node:$rhs), [{ 52 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 53}]>; 54def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 55 (vector_shuffle node:$lhs, node:$rhs), [{ 56 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 57}]>; 58def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 59 (vector_shuffle node:$lhs, node:$rhs), [{ 60 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 61}]>; 62 63// These fragments are provided for little-endian, where the inputs must be 64// swapped for correct semantics. 65def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 66 (vector_shuffle node:$lhs, node:$rhs), [{ 67 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 68}]>; 69def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 70 (vector_shuffle node:$lhs, node:$rhs), [{ 71 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 72}]>; 73def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 74 (vector_shuffle node:$lhs, node:$rhs), [{ 75 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 76}]>; 77 78def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 80 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 81}]>; 82def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 84 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 85}]>; 86def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 88 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 89}]>; 90def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 92 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 93}]>; 94def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 96 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 97}]>; 98def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 100 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 101}]>; 102 103 104def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 106 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 107}]>; 108def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 109 (vector_shuffle node:$lhs, node:$rhs), [{ 110 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 111}]>; 112def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 113 (vector_shuffle node:$lhs, node:$rhs), [{ 114 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 115}]>; 116def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 117 (vector_shuffle node:$lhs, node:$rhs), [{ 118 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 119}]>; 120def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 121 (vector_shuffle node:$lhs, node:$rhs), [{ 122 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 123}]>; 124def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 127}]>; 128 129 130// These fragments are provided for little-endian, where the inputs must be 131// swapped for correct semantics. 132def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 134 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 135}]>; 136def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 137 (vector_shuffle node:$lhs, node:$rhs), [{ 138 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 139}]>; 140def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 141 (vector_shuffle node:$lhs, node:$rhs), [{ 142 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 143}]>; 144def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 145 (vector_shuffle node:$lhs, node:$rhs), [{ 146 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 147}]>; 148def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 149 (vector_shuffle node:$lhs, node:$rhs), [{ 150 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 151}]>; 152def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 153 (vector_shuffle node:$lhs, node:$rhs), [{ 154 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 155}]>; 156 157 158def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 159 (vector_shuffle node:$lhs, node:$rhs), [{ 160 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG); 161}]>; 162def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 163 (vector_shuffle node:$lhs, node:$rhs), [{ 164 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG); 165}]>; 166def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 167 (vector_shuffle node:$lhs, node:$rhs), [{ 168 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG); 169}]>; 170def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 171 (vector_shuffle node:$lhs, node:$rhs), [{ 172 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG); 173}]>; 174def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 175 (vector_shuffle node:$lhs, node:$rhs), [{ 176 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG); 177}]>; 178def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 179 (vector_shuffle node:$lhs, node:$rhs), [{ 180 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG); 181}]>; 182 183 184 185def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 186 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); 187}]>; 188def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 189 (vector_shuffle node:$lhs, node:$rhs), [{ 190 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 191}], VSLDOI_get_imm>; 192 193 194/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 195/// vector_shuffle(X,undef,mask) by the dag combiner. 196def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 197 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); 198}]>; 199def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 200 (vector_shuffle node:$lhs, node:$rhs), [{ 201 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 202}], VSLDOI_unary_get_imm>; 203 204 205/// VSLDOI_swapped* - These fragments are provided for little-endian, where 206/// the inputs must be swapped for correct semantics. 207def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 208 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); 209}]>; 210def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 211 (vector_shuffle node:$lhs, node:$rhs), [{ 212 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 213}], VSLDOI_get_imm>; 214 215 216// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 217def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 218 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 1, *CurDAG), SDLoc(N)); 219}]>; 220def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 221 (vector_shuffle node:$lhs, node:$rhs), [{ 222 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 223}], VSPLTB_get_imm>; 224def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 225 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 2, *CurDAG), SDLoc(N)); 226}]>; 227def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 228 (vector_shuffle node:$lhs, node:$rhs), [{ 229 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 230}], VSPLTH_get_imm>; 231def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 232 return getI32Imm(PPC::getSplatIdxForPPCMnemonics(N, 4, *CurDAG), SDLoc(N)); 233}]>; 234def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 235 (vector_shuffle node:$lhs, node:$rhs), [{ 236 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 237}], VSPLTW_get_imm>; 238 239 240// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 241def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 242 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 243}]>; 244def vecspltisb : PatLeaf<(build_vector), [{ 245 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr; 246}], VSPLTISB_get_imm>; 247 248// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 249def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 250 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 251}]>; 252def vecspltish : PatLeaf<(build_vector), [{ 253 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr; 254}], VSPLTISH_get_imm>; 255 256// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 257def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 258 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 259}]>; 260def vecspltisw : PatLeaf<(build_vector), [{ 261 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr; 262}], VSPLTISW_get_imm>; 263 264def immEQOneV : PatLeaf<(build_vector), [{ 265 if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode()) 266 return C->isOne(); 267 return false; 268}]>; 269//===----------------------------------------------------------------------===// 270// Helpers for defining instructions that directly correspond to intrinsics. 271 272// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 273class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 274 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 275 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 276 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 277 278// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 279// inputs doesn't match the type of the output. 280class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 281 ValueType InTy> 282 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 283 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 284 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 285 286// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 287// input types and an output type. 288class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 289 ValueType In1Ty, ValueType In2Ty> 290 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 291 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 292 [(set OutTy:$vD, 293 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 294 295// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 296class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 297 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 298 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 299 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 300 301// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 302// inputs doesn't match the type of the output. 303class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 304 ValueType InTy> 305 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 306 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 307 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 308 309// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 310// input types and an output type. 311class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 312 ValueType In1Ty, ValueType In2Ty> 313 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 314 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 315 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 316 317// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 318class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 319 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 320 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 321 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 322 323// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 324// inputs doesn't match the type of the output. 325class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 326 ValueType InTy> 327 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 328 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 329 [(set OutTy:$vD, (IntID InTy:$vB))]>; 330 331class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 332 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), 333 !strconcat(opc, " $vD, $vA"), IIC_VecFP, 334 [(set Ty:$vD, (IntID Ty:$vA))]>; 335 336class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 337 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), 338 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, 339 [(set Ty:$vD, (IntID Ty:$vA, timm:$ST, timm:$SIX))]>; 340 341//===----------------------------------------------------------------------===// 342// Instruction Definitions. 343 344def HasAltivec : Predicate<"Subtarget->hasAltivec()">; 345let Predicates = [HasAltivec] in { 346 347def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 348 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 349 Deprecated<DeprecatedDST> { 350 let A = 0; 351 let B = 0; 352} 353 354def DSSALL : DSS_Form<1, 822, (outs), (ins), 355 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, 356 Deprecated<DeprecatedDST> { 357 let STRM = 0; 358 let A = 0; 359 let B = 0; 360} 361 362def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 363 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 364 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 365 Deprecated<DeprecatedDST>; 366 367def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 368 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 369 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 370 Deprecated<DeprecatedDST>; 371 372def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 373 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 374 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 375 Deprecated<DeprecatedDST>; 376 377def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 378 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 379 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 380 Deprecated<DeprecatedDST>; 381 382let isCodeGenOnly = 1 in { 383 // The very same instructions as above, but formally matching 64bit registers. 384 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 385 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 386 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 387 Deprecated<DeprecatedDST>; 388 389 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 390 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 391 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 392 Deprecated<DeprecatedDST>; 393 394 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 395 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 396 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 397 imm:$STRM)]>, 398 Deprecated<DeprecatedDST>; 399 400 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 401 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 402 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 403 imm:$STRM)]>, 404 Deprecated<DeprecatedDST>; 405} 406 407def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 408 "mfvscr $vD", IIC_LdStStore, 409 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 410def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 411 "mtvscr $vB", IIC_LdStLoad, 412 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 413 414let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. 415def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), 416 "lvebx $vD, $src", IIC_LdStLoad, 417 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 418def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), 419 "lvehx $vD, $src", IIC_LdStLoad, 420 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 421def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), 422 "lvewx $vD, $src", IIC_LdStLoad, 423 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 424def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), 425 "lvx $vD, $src", IIC_LdStLoad, 426 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 427def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), 428 "lvxl $vD, $src", IIC_LdStLoad, 429 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 430} 431 432def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), 433 "lvsl $vD, $src", IIC_LdStLoad, 434 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 435 PPC970_Unit_LSU; 436def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), 437 "lvsr $vD, $src", IIC_LdStLoad, 438 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 439 PPC970_Unit_LSU; 440 441let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. 442def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 443 "stvebx $rS, $dst", IIC_LdStStore, 444 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 445def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 446 "stvehx $rS, $dst", IIC_LdStStore, 447 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 448def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 449 "stvewx $rS, $dst", IIC_LdStStore, 450 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 451def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 452 "stvx $rS, $dst", IIC_LdStStore, 453 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 454def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 455 "stvxl $rS, $dst", IIC_LdStStore, 456 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 457} 458 459let PPC970_Unit = 5 in { // VALU Operations. 460// VA-Form instructions. 3-input AltiVec ops. 461let isCommutable = 1 in { 462def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 463 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 464 [(set v4f32:$vD, 465 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 466 467// FIXME: The fma+fneg pattern won't match because fneg is not legal. 468def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 469 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 470 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 471 (fneg v4f32:$vB))))]>; 472 473def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 474def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 475 v8i16>; 476def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 477} // isCommutable 478 479def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 480 v4i32, v4i32, v16i8>; 481def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 482 483// Shuffles. 484def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), 485 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 486 [(set v16i8:$vD, 487 (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; 488 489// VX-Form instructions. AltiVec arithmetic ops. 490let isCommutable = 1 in { 491def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 492 "vaddfp $vD, $vA, $vB", IIC_VecFP, 493 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 494 495def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 496 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 497 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 498def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 499 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 500 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 501def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 502 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 503 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 504 505def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 506def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 507def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 508def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 509def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 510def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 511def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 512} // isCommutable 513 514let isCommutable = 1 in 515def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 516 "vand $vD, $vA, $vB", IIC_VecFP, 517 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 518def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 519 "vandc $vD, $vA, $vB", IIC_VecFP, 520 [(set v4i32:$vD, (and v4i32:$vA, 521 (vnot_ppc v4i32:$vB)))]>; 522 523def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 524 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 525 [(set v4f32:$vD, 526 (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>; 527def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 528 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 529 [(set v4f32:$vD, 530 (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>; 531def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 532 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 533 [(set v4i32:$vD, 534 (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>; 535def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 536 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 537 [(set v4i32:$vD, 538 (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>; 539 540// Defines with the UIM field set to 0 for floating-point 541// to integer (fp_to_sint/fp_to_uint) conversions and integer 542// to floating-point (sint_to_fp/uint_to_fp) conversions. 543let isCodeGenOnly = 1, VA = 0 in { 544def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 545 "vcfsx $vD, $vB, 0", IIC_VecFP, 546 [(set v4f32:$vD, 547 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 548def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 549 "vctuxs $vD, $vB, 0", IIC_VecFP, 550 [(set v4i32:$vD, 551 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 552def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 553 "vcfux $vD, $vB, 0", IIC_VecFP, 554 [(set v4f32:$vD, 555 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 556def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 557 "vctsxs $vD, $vB, 0", IIC_VecFP, 558 [(set v4i32:$vD, 559 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 560} 561def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 562def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 563 564let isCommutable = 1 in { 565def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 566def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 567def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 568def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 569def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 570def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 571 572def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 573def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 574def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 575def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 576def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 577def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 578def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 579def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 580def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 581def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 582def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 583def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 584def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 585def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 586} // isCommutable 587 588def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 589 "vmrghb $vD, $vA, $vB", IIC_VecFP, 590 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 591def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 592 "vmrghh $vD, $vA, $vB", IIC_VecFP, 593 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 594def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 595 "vmrghw $vD, $vA, $vB", IIC_VecFP, 596 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 597def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 598 "vmrglb $vD, $vA, $vB", IIC_VecFP, 599 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 600def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 601 "vmrglh $vD, $vA, $vB", IIC_VecFP, 602 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 603def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 604 "vmrglw $vD, $vA, $vB", IIC_VecFP, 605 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 606 607def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 608 v4i32, v16i8, v4i32>; 609def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 610 v4i32, v8i16, v4i32>; 611def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 612 v4i32, v8i16, v4i32>; 613def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 614 v4i32, v16i8, v4i32>; 615def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 616 v4i32, v8i16, v4i32>; 617def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 618 v4i32, v8i16, v4i32>; 619 620let isCommutable = 1 in { 621def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 622 v8i16, v16i8>; 623def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 624 v4i32, v8i16>; 625def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 626 v8i16, v16i8>; 627def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 628 v4i32, v8i16>; 629def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 630 v8i16, v16i8>; 631def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 632 v4i32, v8i16>; 633def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 634 v8i16, v16i8>; 635def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 636 v4i32, v8i16>; 637} // isCommutable 638 639def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 640def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 641def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 642def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 643def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 644def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 645 646def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 647 648def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 649 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 650 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 651def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 652 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 653 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 654def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 655 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 656 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 657def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 658 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 659 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 660 661def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 662def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 663def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 664def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 665def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 666def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 667 668def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 669def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 670 671def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 672 v4i32, v16i8, v4i32>; 673def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 674 v4i32, v8i16, v4i32>; 675def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 676 v4i32, v16i8, v4i32>; 677 678def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 679 "vnor $vD, $vA, $vB", IIC_VecFP, 680 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 681 v4i32:$vB)))]>; 682let isCommutable = 1 in { 683def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 684 "vor $vD, $vA, $vB", IIC_VecFP, 685 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 686def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 687 "vxor $vD, $vA, $vB", IIC_VecFP, 688 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 689} // isCommutable 690 691def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 692def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 693def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 694 695def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 696def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 697 698def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 699def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 700def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 701 702def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 703 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 704 [(set v16i8:$vD, 705 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 706def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 707 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 708 [(set v16i8:$vD, 709 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 710def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 711 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 712 [(set v16i8:$vD, 713 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 714let isCodeGenOnly = 1, hasSideEffects = 0 in { 715 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 716 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; 717 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 718 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; 719} 720 721def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 722def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 723 724def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 725def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 726def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 727def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 728def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 729def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 730 731 732def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 733 "vspltisb $vD, $SIMM", IIC_VecPerm, 734 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 735def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 736 "vspltish $vD, $SIMM", IIC_VecPerm, 737 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 738def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 739 "vspltisw $vD, $SIMM", IIC_VecPerm, 740 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 741 742// Vector Pack. 743def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 744 v8i16, v4i32>; 745def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 746 v16i8, v8i16>; 747def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 748 v16i8, v8i16>; 749def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 750 v8i16, v4i32>; 751def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 752 v8i16, v4i32>; 753def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 754 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 755 [(set v16i8:$vD, 756 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 757def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 758 v16i8, v8i16>; 759def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 760 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 761 [(set v16i8:$vD, 762 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 763def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 764 v8i16, v4i32>; 765 766// Vector Unpack. 767def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 768 v4i32, v8i16>; 769def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 770 v8i16, v16i8>; 771def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 772 v4i32, v8i16>; 773def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 774 v4i32, v8i16>; 775def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 776 v8i16, v16i8>; 777def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 778 v4i32, v8i16>; 779 780 781// Altivec Comparisons. 782 783class VCMP<bits<10> xo, string asmstr, ValueType Ty> 784 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 785 IIC_VecFPCompare, 786 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 787class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 788 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 789 IIC_VecFPCompare, 790 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 791 let Defs = [CR6]; 792 let RC = 1; 793} 794 795// f32 element comparisons.0 796def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 797def VCMPBFP_rec : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 798def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 799def VCMPEQFP_rec : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 800def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 801def VCMPGEFP_rec : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 802def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 803def VCMPGTFP_rec : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 804 805// i8 element comparisons. 806def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 807def VCMPEQUB_rec : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 808def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 809def VCMPGTSB_rec : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 810def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 811def VCMPGTUB_rec : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 812 813// i16 element comparisons. 814def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 815def VCMPEQUH_rec : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 816def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 817def VCMPGTSH_rec : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 818def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 819def VCMPGTUH_rec : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 820 821// i32 element comparisons. 822def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 823def VCMPEQUW_rec : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 824def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 825def VCMPGTSW_rec : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 826def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 827def VCMPGTUW_rec : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 828 829let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 830 isReMaterializable = 1 in { 831 832def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 833 "vxor $vD, $vD, $vD", IIC_VecFP, 834 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 835def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 836 "vxor $vD, $vD, $vD", IIC_VecFP, 837 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 838def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 839 "vxor $vD, $vD, $vD", IIC_VecFP, 840 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 841 842let IMM=-1 in { 843def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 844 "vspltisw $vD, -1", IIC_VecFP, 845 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 846def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 847 "vspltisw $vD, -1", IIC_VecFP, 848 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 849def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 850 "vspltisw $vD, -1", IIC_VecFP, 851 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 852} 853} 854} // VALU Operations. 855 856//===----------------------------------------------------------------------===// 857// Additional Altivec Patterns 858// 859 860// Extended mnemonics 861def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 862def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 863 864// Rotates. 865def : Pat<(v16i8 (rotl v16i8:$vA, v16i8:$vB)), 866 (v16i8 (VRLB v16i8:$vA, v16i8:$vB))>; 867def : Pat<(v8i16 (rotl v8i16:$vA, v8i16:$vB)), 868 (v8i16 (VRLH v8i16:$vA, v8i16:$vB))>; 869def : Pat<(v4i32 (rotl v4i32:$vA, v4i32:$vB)), 870 (v4i32 (VRLW v4i32:$vA, v4i32:$vB))>; 871 872// Multiply 873def : Pat<(mul v8i16:$vA, v8i16:$vB), (VMLADDUHM $vA, $vB, (v8i16(V_SET0H)))>; 874 875// Add 876def : Pat<(add (mul v8i16:$vA, v8i16:$vB), v8i16:$vC), (VMLADDUHM $vA, $vB, $vC)>; 877 878// Saturating adds/subtracts. 879def : Pat<(v16i8 (saddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDSBS $vA, $vB))>; 880def : Pat<(v16i8 (uaddsat v16i8:$vA, v16i8:$vB)), (v16i8 (VADDUBS $vA, $vB))>; 881def : Pat<(v8i16 (saddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDSHS $vA, $vB))>; 882def : Pat<(v8i16 (uaddsat v8i16:$vA, v8i16:$vB)), (v8i16 (VADDUHS $vA, $vB))>; 883def : Pat<(v4i32 (saddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDSWS $vA, $vB))>; 884def : Pat<(v4i32 (uaddsat v4i32:$vA, v4i32:$vB)), (v4i32 (VADDUWS $vA, $vB))>; 885def : Pat<(v16i8 (ssubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBSBS $vA, $vB))>; 886def : Pat<(v16i8 (usubsat v16i8:$vA, v16i8:$vB)), (v16i8 (VSUBUBS $vA, $vB))>; 887def : Pat<(v8i16 (ssubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBSHS $vA, $vB))>; 888def : Pat<(v8i16 (usubsat v8i16:$vA, v8i16:$vB)), (v8i16 (VSUBUHS $vA, $vB))>; 889def : Pat<(v4i32 (ssubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBSWS $vA, $vB))>; 890def : Pat<(v4i32 (usubsat v4i32:$vA, v4i32:$vB)), (v4i32 (VSUBUWS $vA, $vB))>; 891 892// Loads. 893def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 894 895// Stores. 896def : Pat<(store v4i32:$rS, xoaddr:$dst), 897 (STVX $rS, xoaddr:$dst)>; 898 899// Bit conversions. 900def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 901def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 902def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 903def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 904def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>; 905 906def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 907def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 908def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 909def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 910def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>; 911 912def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 913def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 914def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 915def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 916def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>; 917 918def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 919def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 920def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 921def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 922def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>; 923 924def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 925def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 926def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 927def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 928def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>; 929 930def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>; 931def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>; 932def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; 933def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; 934def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; 935 936// Max/Min 937def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)), 938 (v16i8 (VMAXUB $src1, $src2))>; 939def : Pat<(v16i8 (smax v16i8:$src1, v16i8:$src2)), 940 (v16i8 (VMAXSB $src1, $src2))>; 941def : Pat<(v8i16 (umax v8i16:$src1, v8i16:$src2)), 942 (v8i16 (VMAXUH $src1, $src2))>; 943def : Pat<(v8i16 (smax v8i16:$src1, v8i16:$src2)), 944 (v8i16 (VMAXSH $src1, $src2))>; 945def : Pat<(v4i32 (umax v4i32:$src1, v4i32:$src2)), 946 (v4i32 (VMAXUW $src1, $src2))>; 947def : Pat<(v4i32 (smax v4i32:$src1, v4i32:$src2)), 948 (v4i32 (VMAXSW $src1, $src2))>; 949def : Pat<(v16i8 (umin v16i8:$src1, v16i8:$src2)), 950 (v16i8 (VMINUB $src1, $src2))>; 951def : Pat<(v16i8 (smin v16i8:$src1, v16i8:$src2)), 952 (v16i8 (VMINSB $src1, $src2))>; 953def : Pat<(v8i16 (umin v8i16:$src1, v8i16:$src2)), 954 (v8i16 (VMINUH $src1, $src2))>; 955def : Pat<(v8i16 (smin v8i16:$src1, v8i16:$src2)), 956 (v8i16 (VMINSH $src1, $src2))>; 957def : Pat<(v4i32 (umin v4i32:$src1, v4i32:$src2)), 958 (v4i32 (VMINUW $src1, $src2))>; 959def : Pat<(v4i32 (smin v4i32:$src1, v4i32:$src2)), 960 (v4i32 (VMINSW $src1, $src2))>; 961 962// Shuffles. 963 964// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 965def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 966 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 967def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 968 (VPKUWUM $vA, $vA)>; 969def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 970 (VPKUHUM $vA, $vA)>; 971def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB), 972 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>; 973 974 975// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 976// These fragments are matched for little-endian, where the inputs must 977// be swapped for correct semantics. 978def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 979 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 980def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 981 (VPKUWUM $vB, $vA)>; 982def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 983 (VPKUHUM $vB, $vA)>; 984 985// Match vmrg*(x,x) 986def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 987 (VMRGLB $vA, $vA)>; 988def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 989 (VMRGLH $vA, $vA)>; 990def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 991 (VMRGLW $vA, $vA)>; 992def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 993 (VMRGHB $vA, $vA)>; 994def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 995 (VMRGHH $vA, $vA)>; 996def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 997 (VMRGHW $vA, $vA)>; 998 999// Match vmrg*(y,x), i.e., swapped operands. These fragments 1000// are matched for little-endian, where the inputs must be 1001// swapped for correct semantics. 1002def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 1003 (VMRGLB $vB, $vA)>; 1004def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 1005 (VMRGLH $vB, $vA)>; 1006def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 1007 (VMRGLW $vB, $vA)>; 1008def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 1009 (VMRGHB $vB, $vA)>; 1010def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 1011 (VMRGHH $vB, $vA)>; 1012def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 1013 (VMRGHW $vB, $vA)>; 1014 1015// Logical Operations 1016def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 1017 1018def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 1019 (VNOR $A, $B)>; 1020def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 1021 (VANDC $A, $B)>; 1022 1023def : Pat<(fmul v4f32:$vA, v4f32:$vB), 1024 (VMADDFP $vA, $vB, 1025 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 1026 1027def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), 1028 (VNMSUBFP $A, $B, $C)>; 1029 1030def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 1031 (VMADDFP $A, $B, $C)>; 1032def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 1033 (VNMSUBFP $A, $B, $C)>; 1034 1035def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 1036 (VPERM $vA, $vB, $vC)>; 1037 1038def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 1039def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 1040 1041// Vector shifts 1042def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 1043 (v16i8 (VSLB $vA, $vB))>; 1044def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 1045 (v8i16 (VSLH $vA, $vB))>; 1046def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 1047 (v4i32 (VSLW $vA, $vB))>; 1048def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)), 1049 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1050def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)), 1051 (v16i8 (VSLB $vA, $vB))>; 1052def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)), 1053 (v8i16 (VSLH $vA, $vB))>; 1054def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)), 1055 (v4i32 (VSLW $vA, $vB))>; 1056def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)), 1057 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1058 1059def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 1060 (v16i8 (VSRB $vA, $vB))>; 1061def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 1062 (v8i16 (VSRH $vA, $vB))>; 1063def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 1064 (v4i32 (VSRW $vA, $vB))>; 1065def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)), 1066 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1067def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)), 1068 (v16i8 (VSRB $vA, $vB))>; 1069def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)), 1070 (v8i16 (VSRH $vA, $vB))>; 1071def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)), 1072 (v4i32 (VSRW $vA, $vB))>; 1073def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)), 1074 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1075 1076def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 1077 (v16i8 (VSRAB $vA, $vB))>; 1078def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 1079 (v8i16 (VSRAH $vA, $vB))>; 1080def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 1081 (v4i32 (VSRAW $vA, $vB))>; 1082def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)), 1083 (v16i8 (VSRAB $vA, $vB))>; 1084def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)), 1085 (v8i16 (VSRAH $vA, $vB))>; 1086def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)), 1087 (v4i32 (VSRAW $vA, $vB))>; 1088 1089// Float to integer and integer to float conversions 1090def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 1091 (VCTSXS_0 $vA)>; 1092def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 1093 (VCTUXS_0 $vA)>; 1094def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 1095 (VCFSX_0 $vA)>; 1096def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 1097 (VCFUX_0 $vA)>; 1098 1099// Floating-point rounding 1100def : Pat<(v4f32 (ffloor v4f32:$vA)), 1101 (VRFIM $vA)>; 1102def : Pat<(v4f32 (fceil v4f32:$vA)), 1103 (VRFIP $vA)>; 1104def : Pat<(v4f32 (ftrunc v4f32:$vA)), 1105 (VRFIZ $vA)>; 1106def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 1107 (VRFIN $vA)>; 1108 1109// Vector selection 1110def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 1111 (VSEL $vC, $vB, $vA)>; 1112def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 1113 (VSEL $vC, $vB, $vA)>; 1114def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)), 1115 (VSEL $vC, $vB, $vA)>; 1116def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)), 1117 (VSEL $vC, $vB, $vA)>; 1118def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)), 1119 (VSEL $vC, $vB, $vA)>; 1120def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)), 1121 (VSEL $vC, $vB, $vA)>; 1122 1123// Vector Integer Average Instructions 1124def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), 1125 (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>; 1126def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), 1127 (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>; 1128def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), 1129 (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>; 1130def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), 1131 (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>; 1132def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), 1133 (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>; 1134def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), 1135 (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>; 1136 1137} // end HasAltivec 1138 1139def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; 1140def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; 1141let Predicates = [HasP8Altivec] in { 1142 1143let isCommutable = 1 in { 1144def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 1145 v2i64, v4i32>; 1146def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 1147 v2i64, v4i32>; 1148def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 1149 v2i64, v4i32>; 1150def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 1151 v2i64, v4i32>; 1152def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1153 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, 1154 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; 1155def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 1156def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 1157def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 1158def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 1159} // isCommutable 1160 1161// Vector merge 1162def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1163 "vmrgew $vD, $vA, $vB", IIC_VecFP, 1164 [(set v16i8:$vD, 1165 (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; 1166def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1167 "vmrgow $vD, $vA, $vB", IIC_VecFP, 1168 [(set v16i8:$vD, 1169 (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; 1170 1171// Match vmrgew(x,x) and vmrgow(x,x) 1172def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), 1173 (VMRGEW $vA, $vA)>; 1174def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef), 1175 (VMRGOW $vA, $vA)>; 1176 1177// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments 1178// are matched for little-endian, where the inputs must be swapped for correct 1179// semantics.w 1180def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB), 1181 (VMRGEW $vB, $vA)>; 1182def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB), 1183 (VMRGOW $vB, $vA)>; 1184 1185// Vector rotates. 1186def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 1187 1188def : Pat<(v2i64 (rotl v2i64:$vA, v2i64:$vB)), 1189 (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>; 1190 1191// Vector shifts 1192def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1193 "vsld $vD, $vA, $vB", IIC_VecGeneral, []>; 1194def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1195 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; 1196def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1197 "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; 1198 1199def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), 1200 (v2i64 (VSLD $vA, $vB))>; 1201def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)), 1202 (v2i64 (VSLD $vA, $vB))>; 1203def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)), 1204 (v2i64 (VSRD $vA, $vB))>; 1205def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)), 1206 (v2i64 (VSRD $vA, $vB))>; 1207def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)), 1208 (v2i64 (VSRAD $vA, $vB))>; 1209def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)), 1210 (v2i64 (VSRAD $vA, $vB))>; 1211 1212// Vector Integer Arithmetic Instructions 1213let isCommutable = 1 in { 1214def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1215 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 1216 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 1217def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1218 "vadduqm $vD, $vA, $vB", IIC_VecGeneral, 1219 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; 1220} // isCommutable 1221 1222// Vector Quadword Add 1223def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>; 1224def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>; 1225def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; 1226 1227// Vector Doubleword Subtract 1228def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1229 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 1230 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 1231 1232// Vector Quadword Subtract 1233def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1234 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, 1235 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; 1236def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; 1237def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; 1238def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; 1239 1240// Count Leading Zeros 1241def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 1242 "vclzb $vD, $vB", IIC_VecGeneral, 1243 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 1244def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 1245 "vclzh $vD, $vB", IIC_VecGeneral, 1246 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 1247def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 1248 "vclzw $vD, $vB", IIC_VecGeneral, 1249 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 1250def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 1251 "vclzd $vD, $vB", IIC_VecGeneral, 1252 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 1253 1254// Population Count 1255def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 1256 "vpopcntb $vD, $vB", IIC_VecGeneral, 1257 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 1258def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 1259 "vpopcnth $vD, $vB", IIC_VecGeneral, 1260 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 1261def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1262 "vpopcntw $vD, $vB", IIC_VecGeneral, 1263 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1264def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1265 "vpopcntd $vD, $vB", IIC_VecGeneral, 1266 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1267 1268let isCommutable = 1 in { 1269// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1270// VSX equivalents. We need to fix this up at some point. Two possible 1271// solutions for this problem: 1272// 1. Disable Altivec patterns that compete with VSX patterns using the 1273// !HasVSX predicate. This essentially favours VSX over Altivec, in 1274// hopes of reducing register pressure (larger register set using VSX 1275// instructions than VMX instructions) 1276// 2. Employ a more disciplined use of AddedComplexity, which would provide 1277// more fine-grained control than option 1. This would be beneficial 1278// if we find situations where Altivec is really preferred over VSX. 1279def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1280 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1281 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; 1282def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1283 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1284 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; 1285} // isCommutable 1286 1287def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1288 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1289 [(set v4i32:$vD, (or v4i32:$vA, 1290 (vnot_ppc v4i32:$vB)))]>; 1291 1292// i64 element comparisons. 1293def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1294def VCMPEQUD_rec : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1295def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1296def VCMPGTSD_rec : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1297def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1298def VCMPGTUD_rec : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1299 1300// The cryptography instructions that do not require Category:Vector.Crypto 1301def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", 1302 int_ppc_altivec_crypto_vpmsumb, v16i8>; 1303def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", 1304 int_ppc_altivec_crypto_vpmsumh, v8i16>; 1305def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", 1306 int_ppc_altivec_crypto_vpmsumw, v4i32>; 1307def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", 1308 int_ppc_altivec_crypto_vpmsumd, v2i64>; 1309def VPERMXOR : VA1a_Int_Ty<45, "vpermxor", 1310 int_ppc_altivec_crypto_vpermxor, v16i8>; 1311 1312// Vector doubleword integer pack and unpack. 1313def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss, 1314 v4i32, v2i64>; 1315def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus, 1316 v4i32, v2i64>; 1317def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1318 "vpkudum $vD, $vA, $vB", IIC_VecFP, 1319 [(set v16i8:$vD, 1320 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; 1321def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, 1322 v4i32, v2i64>; 1323def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, 1324 v2i64, v4i32>; 1325def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, 1326 v2i64, v4i32>; 1327 1328// Shuffle patterns for unary and swapped (LE) vector pack modulo. 1329def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef), 1330 (VPKUDUM $vA, $vA)>; 1331def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1332 (VPKUDUM $vB, $vA)>; 1333 1334def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>; 1335def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq, 1336 v2i64, v16i8>; 1337} // end HasP8Altivec 1338 1339// Crypto instructions (from builtins) 1340let Predicates = [HasP8Crypto] in { 1341def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw", 1342 int_ppc_altivec_crypto_vshasigmaw, v4i32>; 1343def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad", 1344 int_ppc_altivec_crypto_vshasigmad, v2i64>; 1345def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher, 1346 v2i64>; 1347def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast", 1348 int_ppc_altivec_crypto_vcipherlast, v2i64>; 1349def VNCIPHER : VX1_Int_Ty<1352, "vncipher", 1350 int_ppc_altivec_crypto_vncipher, v2i64>; 1351def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast", 1352 int_ppc_altivec_crypto_vncipherlast, v2i64>; 1353def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; 1354} // HasP8Crypto 1355 1356// The following altivec instructions were introduced in Power ISA 3.0 1357def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; 1358let Predicates = [HasP9Altivec] in { 1359 1360// Vector Multiply-Sum 1361def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm, 1362 v1i128, v2i64, v1i128>; 1363 1364// i8 element comparisons. 1365def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; 1366def VCMPNEB_rec : VCMPo < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; 1367def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; 1368def VCMPNEZB_rec : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; 1369 1370// i16 element comparisons. 1371def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; 1372def VCMPNEH_rec : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; 1373def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; 1374def VCMPNEZH_rec : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; 1375 1376// i32 element comparisons. 1377def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; 1378def VCMPNEW_rec : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; 1379def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; 1380def VCMPNEZW_rec : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; 1381 1382// VX-Form: [PO VRT / UIM VRB XO]. 1383// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent 1384// "/ UIM" (1 + 4 bit) 1385class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern> 1386 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB), 1387 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>; 1388 1389class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1390 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB), 1391 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>; 1392 1393// Vector Extract Unsigned 1394def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; 1395def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>; 1396def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; 1397def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; 1398 1399// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed 1400let hasSideEffects = 0 in { 1401def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>; 1402def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>; 1403def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>; 1404def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>; 1405def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>; 1406def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>; 1407} 1408 1409// Vector Insert Element Instructions 1410def VINSERTB : VXForm_1<781, (outs vrrc:$vD), 1411 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1412 "vinsertb $vD, $vB, $UIM", IIC_VecGeneral, 1413 [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, 1414 imm32SExt16:$UIM))]>, 1415 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1416def VINSERTH : VXForm_1<845, (outs vrrc:$vD), 1417 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1418 "vinserth $vD, $vB, $UIM", IIC_VecGeneral, 1419 [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, 1420 imm32SExt16:$UIM))]>, 1421 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1422def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; 1423def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; 1424 1425class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1426 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB), 1427 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1428class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1429 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB), 1430 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1431 1432// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] 1433def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), 1434 "vclzlsbb $rD, $vB", IIC_VecGeneral, 1435 [(set i32:$rD, (int_ppc_altivec_vclzlsbb 1436 v16i8:$vB))]>; 1437def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), 1438 "vctzlsbb $rD, $vB", IIC_VecGeneral, 1439 [(set i32:$rD, (int_ppc_altivec_vctzlsbb 1440 v16i8:$vB))]>; 1441// Vector Count Trailing Zeros 1442def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", 1443 [(set v16i8:$vD, (cttz v16i8:$vB))]>; 1444def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", 1445 [(set v8i16:$vD, (cttz v8i16:$vB))]>; 1446def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", 1447 [(set v4i32:$vD, (cttz v4i32:$vB))]>; 1448def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", 1449 [(set v2i64:$vD, (cttz v2i64:$vB))]>; 1450 1451// Vector Extend Sign 1452def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>; 1453def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>; 1454def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>; 1455def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>; 1456def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>; 1457let isCodeGenOnly = 1 in { 1458 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; 1459 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; 1460 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>; 1461 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>; 1462 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>; 1463} 1464 1465def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i8)), (v4i32 (VEXTSB2W $VRB))>; 1466def : Pat<(v4i32 (sext_inreg v4i32:$VRB, v4i16)), (v4i32 (VEXTSH2W $VRB))>; 1467def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i8)), (v2i64 (VEXTSB2D $VRB))>; 1468def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i16)), (v2i64 (VEXTSH2D $VRB))>; 1469def : Pat<(v2i64 (sext_inreg v2i64:$VRB, v2i32)), (v2i64 (VEXTSW2D $VRB))>; 1470 1471// Vector Integer Negate 1472def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", 1473 [(set v4i32:$vD, 1474 (sub (v4i32 immAllZerosV), v4i32:$vB))]>; 1475 1476def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", 1477 [(set v2i64:$vD, 1478 (sub (v2i64 (bitconvert (v4i32 immAllZerosV))), 1479 v2i64:$vB))]>; 1480 1481// Vector Parity Byte 1482def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, 1483 (int_ppc_altivec_vprtybw v4i32:$vB))]>; 1484def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, 1485 (int_ppc_altivec_vprtybd v2i64:$vB))]>; 1486def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, 1487 (int_ppc_altivec_vprtybq v1i128:$vB))]>; 1488 1489// Vector (Bit) Permute (Right-indexed) 1490def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1491 "vbpermd $vD, $vA, $vB", IIC_VecFP, []>; 1492def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1493 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; 1494 1495class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1496 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1497 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; 1498 1499// Vector Rotate Left Mask/Mask-Insert 1500def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", 1501 [(set v4i32:$vD, 1502 (int_ppc_altivec_vrlwnm v4i32:$vA, 1503 v4i32:$vB))]>; 1504def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1505 "vrlwmi $vD, $vA, $vB", IIC_VecFP, 1506 [(set v4i32:$vD, 1507 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, 1508 v4i32:$vDi))]>, 1509 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1510def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", 1511 [(set v2i64:$vD, 1512 (int_ppc_altivec_vrldnm v2i64:$vA, 1513 v2i64:$vB))]>; 1514def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1515 "vrldmi $vD, $vA, $vB", IIC_VecFP, 1516 [(set v2i64:$vD, 1517 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, 1518 v2i64:$vDi))]>, 1519 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1520 1521// Vector Shift Left/Right 1522def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", 1523 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; 1524def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", 1525 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; 1526 1527// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword 1528def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), 1529 "vmul10uq $vD, $vA", IIC_VecFP, []>; 1530def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), 1531 "vmul10cuq $vD, $vA", IIC_VecFP, []>; 1532 1533// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword 1534def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; 1535def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; 1536 1537// Decimal Integer Format Conversion Instructions 1538 1539// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. 1540class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc, 1541 list<dag> pattern> 1542 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS), 1543 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> { 1544 let Defs = [CR6]; 1545} 1546 1547// [PO VRT EO VRB 1 / XO] 1548class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc, 1549 list<dag> pattern> 1550 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB), 1551 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> { 1552 let Defs = [CR6]; 1553 let PS = 0; 1554} 1555 1556// Decimal Convert From/to National/Zoned/Signed-QWord 1557def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; 1558def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; 1559def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; 1560def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>; 1561def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>; 1562def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; 1563 1564// Decimal Copy-Sign/Set-Sign 1565let Defs = [CR6] in 1566def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; 1567 1568def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; 1569 1570// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. 1571class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1572 : VX_RD5_RSp5_PS1_XO9<xo, 1573 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS), 1574 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> { 1575 let Defs = [CR6]; 1576} 1577 1578// [PO VRT VRA VRB 1 / XO] 1579class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1580 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1581 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> { 1582 let Defs = [CR6]; 1583 let PS = 0; 1584} 1585 1586// Decimal Shift/Unsigned-Shift/Shift-and-Round 1587def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; 1588def BCDUS_rec : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; 1589def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; 1590 1591// Decimal (Unsigned) Truncate 1592def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; 1593def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; 1594 1595// Absolute Difference 1596def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1597 "vabsdub $vD, $vA, $vB", IIC_VecGeneral, 1598 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; 1599def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1600 "vabsduh $vD, $vA, $vB", IIC_VecGeneral, 1601 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; 1602def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1603 "vabsduw $vD, $vA, $vB", IIC_VecGeneral, 1604 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; 1605 1606} // end HasP9Altivec 1607