1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 let isPredicable = 1 in 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 let Predicates = [PCRelativeMemops] in { 144 // BL8_NOTOC means that the caller does not use the TOC pointer and if 145 // it does use R2 then it is just a caller saved register. Therefore it is 146 // safe to emit only the bl and not the nop for this instruction. The 147 // linker will not try to restore R2 after the call. 148 def BL8_NOTOC : IForm<18, 0, 1, (outs), 149 (ins calltarget:$func), 150 "bl $func", IIC_BrB, []>; 151 } 152 } 153 let Uses = [CTR8, RM] in { 154 let isPredicable = 1 in 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173} 174 175let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc iaddrX4:$src)]>, 182 Requires<[In64BitMode]>; 183} 184 185} // Interpretation64Bit 186 187// FIXME: Duplicating this for the asm parser should be unnecessary, but the 188// previous definition must be marked as CodeGen only to prevent decoding 189// conflicts. 190let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195// Calls 196def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 207 (BL8_NOTOC tglobaladdr:$dst)>; 208def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 209 (BL8_NOTOC texternalsym:$dst)>; 210 211// Calls for AIX 212def : Pat<(PPCcall (i64 mcsym:$dst)), 213 (BL8 mcsym:$dst)>; 214def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 215 (BL8_NOP mcsym:$dst)>; 216 217// Atomic operations 218// FIXME: some of these might be used with constant operands. This will result 219// in constant materialization instructions that may be redundant. We currently 220// clean this up in PPCMIPeephole with calls to 221// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 222// in the first place. 223let Defs = [CR0] in { 224 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 226 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 227 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 229 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 230 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 232 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 235 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 238 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 241 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 244 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 247 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 250 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 253 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 254 255 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 256 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 257 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 258 259 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 260 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 261 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 262} 263 264// Instructions to support atomic operations 265let mayLoad = 1, hasSideEffects = 0 in { 266def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 267 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 268 269// Instruction to support lock versions of atomics 270// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 271def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 272 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 273 274let hasExtraDefRegAllocReq = 1 in 275def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 276 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 277 Requires<[IsISA3_0]>; 278} 279 280let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 281def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 282 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 283 284let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 285def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 286 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 287 Requires<[IsISA3_0]>; 288 289let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 290let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 291def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 292 (ins calltarget:$dst, i32imm:$offset), 293 "#TC_RETURNd8 $dst $offset", 294 []>; 295 296let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 297def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 298 "#TC_RETURNa8 $func $offset", 299 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 300 301let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 302def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 303 "#TC_RETURNr8 $dst $offset", 304 []>; 305 306let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 307 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 308def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 309 []>, 310 Requires<[In64BitMode]>; 311 312let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 313 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 314def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 315 "b $dst", IIC_BrB, 316 []>; 317 318let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 319 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 320def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 321 "ba $dst", IIC_BrB, 322 []>; 323} // Interpretation64Bit 324 325def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 326 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 327 328def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 329 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 330 331def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 332 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 333 334 335// 64-bit CR instructions 336let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 337let hasSideEffects = 0 in { 338// mtocrf's input needs to be prepared by shifting by an amount dependent 339// on the cr register selected. Thus, post-ra anti-dep breaking must not 340// later change that register assignment. 341let hasExtraDefRegAllocReq = 1 in { 342def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 343 "mtocrf $FXM, $ST", IIC_BrMCRX>, 344 PPC970_DGroup_First, PPC970_Unit_CRU; 345 346// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 347// is dependent on the cr fields being set. 348def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 349 "mtcrf $FXM, $rS", IIC_BrMCRX>, 350 PPC970_MicroCode, PPC970_Unit_CRU; 351} // hasExtraDefRegAllocReq = 1 352 353// mfocrf's input needs to be prepared by shifting by an amount dependent 354// on the cr register selected. Thus, post-ra anti-dep breaking must not 355// later change that register assignment. 356let hasExtraSrcRegAllocReq = 1 in { 357def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 358 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 359 PPC970_DGroup_First, PPC970_Unit_CRU; 360 361// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 362// is dependent on the cr fields being copied. 363def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 364 "mfcr $rT", IIC_SprMFCR>, 365 PPC970_MicroCode, PPC970_Unit_CRU; 366} // hasExtraSrcRegAllocReq = 1 367} // hasSideEffects = 0 368 369// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 370// is not. 371let hasSideEffects = 1 in { 372 let Defs = [CTR8] in 373 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 374 "#EH_SJLJ_SETJMP64", 375 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 376 Requires<[In64BitMode]>; 377} 378 379let hasSideEffects = 1, isBarrier = 1 in { 380 let isTerminator = 1 in 381 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 382 "#EH_SJLJ_LONGJMP64", 383 [(PPCeh_sjlj_longjmp addr:$buf)]>, 384 Requires<[In64BitMode]>; 385} 386 387def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 388 "mfspr $RT, $SPR", IIC_SprMFSPR>; 389def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 390 "mtspr $SPR, $RT", IIC_SprMTSPR>; 391 392 393//===----------------------------------------------------------------------===// 394// 64-bit SPR manipulation instrs. 395 396let Uses = [CTR8] in { 397def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 398 "mfctr $rT", IIC_SprMFSPR>, 399 PPC970_DGroup_First, PPC970_Unit_FXU; 400} 401let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 402def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 403 "mtctr $rS", IIC_SprMTSPR>, 404 PPC970_DGroup_First, PPC970_Unit_FXU; 405} 406let hasSideEffects = 1, Defs = [CTR8] in { 407let Pattern = [(int_set_loop_iterations i64:$rS)] in 408def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 409 "mtctr $rS", IIC_SprMTSPR>, 410 PPC970_DGroup_First, PPC970_Unit_FXU; 411} 412 413let Pattern = [(set i64:$rT, readcyclecounter)] in 414def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 415 "mfspr $rT, 268", IIC_SprMFTB>, 416 PPC970_DGroup_First, PPC970_Unit_FXU; 417// Note that encoding mftb using mfspr is now the preferred form, 418// and has been since at least ISA v2.03. The mftb instruction has 419// now been phased out. Using mfspr, however, is known not to work on 420// the POWER3. 421 422let Defs = [X1], Uses = [X1] in 423def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 424 [(set i64:$result, 425 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 426def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 427 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 428// Probed alloca to support stack clash protection. 429let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 430def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 431 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 432 [(set i64:$result, 433 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 434def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 435 g8rc:$fp, g8rc:$actual_negsize), 436 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 437def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 438 g8rc:$fp, g8rc:$actual_negsize), 439 (ins g8rc:$negsize, memri:$fpsi), 440 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 441 RegConstraint<"$actual_negsize = $negsize">; 442def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 443 (ins i64imm:$stacksize), 444 "#PROBED_STACKALLOC_64", []>; 445} 446 447let hasSideEffects = 0 in { 448let Defs = [LR8] in { 449def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 450 "mtlr $rS", IIC_SprMTSPR>, 451 PPC970_DGroup_First, PPC970_Unit_FXU; 452} 453let Uses = [LR8] in { 454def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 455 "mflr $rT", IIC_SprMFSPR>, 456 PPC970_DGroup_First, PPC970_Unit_FXU; 457} 458} // Interpretation64Bit 459} 460 461//===----------------------------------------------------------------------===// 462// Fixed point instructions. 463// 464 465let PPC970_Unit = 1 in { // FXU Operations. 466let Interpretation64Bit = 1 in { 467let hasSideEffects = 0 in { 468let isCodeGenOnly = 1 in { 469 470let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 471def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 472 "li $rD, $imm", IIC_IntSimple, 473 [(set i64:$rD, imm64SExt16:$imm)]>; 474def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 475 "lis $rD, $imm", IIC_IntSimple, 476 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 477} 478 479// Logical ops. 480let isCommutable = 1 in { 481defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 482 "nand", "$rA, $rS, $rB", IIC_IntSimple, 483 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 484defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 485 "and", "$rA, $rS, $rB", IIC_IntSimple, 486 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 487} // isCommutable 488defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 489 "andc", "$rA, $rS, $rB", IIC_IntSimple, 490 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 491let isCommutable = 1 in { 492defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 493 "or", "$rA, $rS, $rB", IIC_IntSimple, 494 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 495defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 496 "nor", "$rA, $rS, $rB", IIC_IntSimple, 497 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 498} // isCommutable 499defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 500 "orc", "$rA, $rS, $rB", IIC_IntSimple, 501 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 502let isCommutable = 1 in { 503defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 504 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 505 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 506defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 507 "xor", "$rA, $rS, $rB", IIC_IntSimple, 508 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 509} // let isCommutable = 1 510 511// Logical ops with immediate. 512let Defs = [CR0] in { 513def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 514 "andi. $dst, $src1, $src2", IIC_IntGeneral, 515 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 516 isRecordForm; 517def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 518 "andis. $dst, $src1, $src2", IIC_IntGeneral, 519 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 520 isRecordForm; 521} 522def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 523 "ori $dst, $src1, $src2", IIC_IntSimple, 524 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 525def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 526 "oris $dst, $src1, $src2", IIC_IntSimple, 527 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 528def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 529 "xori $dst, $src1, $src2", IIC_IntSimple, 530 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 531def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 532 "xoris $dst, $src1, $src2", IIC_IntSimple, 533 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 534 535let isCommutable = 1 in 536defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 537 "add", "$rT, $rA, $rB", IIC_IntSimple, 538 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 539// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 540// initial-exec thread-local storage model. We need to forbid r0 here - 541// while it works for add just fine, the linker can relax this to local-exec 542// addi, which won't work for r0. 543def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 544 "add $rT, $rA, $rB", IIC_IntSimple, 545 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 546let mayLoad = 1 in { 547def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 548 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 549def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 550 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 551def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 552 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 553def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 554 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 555def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 556 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 557def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 558 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 559def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 560 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 561 562} 563 564let mayStore = 1 in { 565def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 566 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 567 PPC970_DGroup_Cracked; 568def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 569 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 570 PPC970_DGroup_Cracked; 571def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 572 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 573 PPC970_DGroup_Cracked; 574def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 575 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 576 PPC970_DGroup_Cracked; 577def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 578 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 579 PPC970_DGroup_Cracked; 580def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 581 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 582 PPC970_DGroup_Cracked; 583def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 584 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 585 PPC970_DGroup_Cracked; 586 587} 588 589let isCommutable = 1 in 590defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 591 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 592 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 593 PPC970_DGroup_Cracked; 594 595let Defs = [CARRY] in 596def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 597 "addic $rD, $rA, $imm", IIC_IntGeneral, 598 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 599def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 600 "addi $rD, $rA, $imm", IIC_IntSimple, 601 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 602def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 603 "addis $rD, $rA, $imm", IIC_IntSimple, 604 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 605 606let Defs = [CARRY] in { 607def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 608 "subfic $rD, $rA, $imm", IIC_IntGeneral, 609 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 610} 611defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 612 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 613 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 614 PPC970_DGroup_Cracked; 615defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 616 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 617 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 618defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 619 "neg", "$rT, $rA", IIC_IntSimple, 620 [(set i64:$rT, (ineg i64:$rA))]>; 621let Uses = [CARRY] in { 622let isCommutable = 1 in 623defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 624 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 625 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 626defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 627 "addme", "$rT, $rA", IIC_IntGeneral, 628 [(set i64:$rT, (adde i64:$rA, -1))]>; 629defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 630 "addze", "$rT, $rA", IIC_IntGeneral, 631 [(set i64:$rT, (adde i64:$rA, 0))]>; 632defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 633 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 634 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 635defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 636 "subfme", "$rT, $rA", IIC_IntGeneral, 637 [(set i64:$rT, (sube -1, i64:$rA))]>; 638defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 639 "subfze", "$rT, $rA", IIC_IntGeneral, 640 [(set i64:$rT, (sube 0, i64:$rA))]>; 641} 642} // isCodeGenOnly 643 644// FIXME: Duplicating this for the asm parser should be unnecessary, but the 645// previous definition must be marked as CodeGen only to prevent decoding 646// conflicts. 647let isAsmParserOnly = 1 in { 648def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 649 "add $rT, $rA, $rB", IIC_IntSimple, []>; 650 651let mayLoad = 1 in { 652def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 653 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 654def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 655 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 656def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 657 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 658def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 659 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 660} 661 662let mayStore = 1 in { 663def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 664 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 665 PPC970_DGroup_Cracked; 666def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 667 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 668 PPC970_DGroup_Cracked; 669def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 670 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 671 PPC970_DGroup_Cracked; 672def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 673 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 674 PPC970_DGroup_Cracked; 675} 676} 677 678let isCommutable = 1 in { 679defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 680 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 681 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 682defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 683 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 684 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 685} // isCommutable 686} 687} // Interpretation64Bit 688 689let isCompare = 1, hasSideEffects = 0 in { 690 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 691 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 692 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 693 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 694 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 695 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 696 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 697 "cmpldi $dst, $src1, $src2", 698 IIC_IntCompare>, isPPC64; 699 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 700 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 701 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 702 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 703 Requires<[IsISA3_0]>; 704 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 705 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 706 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 707} 708 709let hasSideEffects = 0 in { 710defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 711 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 712 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 713defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 714 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 715 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 716defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 717 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 718 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 719 720let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 721defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 722 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 723defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 724 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 725 Requires<[IsISA3_0]>; 726 727defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 728 "extsb", "$rA, $rS", IIC_IntSimple, 729 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 730defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 731 "extsh", "$rA, $rS", IIC_IntSimple, 732 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 733 734defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 735 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 736defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 737 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 738} // Interpretation64Bit 739 740// For fast-isel: 741let isCodeGenOnly = 1 in { 742def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 743 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 744def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 745 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 746} // isCodeGenOnly for fast-isel 747 748defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 749 "extsw", "$rA, $rS", IIC_IntSimple, 750 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 751let Interpretation64Bit = 1, isCodeGenOnly = 1 in 752defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 753 "extsw", "$rA, $rS", IIC_IntSimple, 754 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 755let isCodeGenOnly = 1 in 756def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 757 "extsw $rA, $rS", IIC_IntSimple, 758 []>, isPPC64; 759 760defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 761 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 762 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 763 764let Interpretation64Bit = 1, isCodeGenOnly = 1 in 765defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 766 (ins gprc:$rS, u6imm:$SH), 767 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 768 [(set i64:$rA, 769 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 770 isPPC64, Requires<[IsISA3_0]>; 771 772defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 773 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 774 []>, isPPC64, Requires<[IsISA3_0]>; 775 776// For fast-isel: 777let isCodeGenOnly = 1, Defs = [CARRY] in 778def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 779 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 780 781defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 782 "cntlzd", "$rA, $rS", IIC_IntGeneral, 783 [(set i64:$rA, (ctlz i64:$rS))]>; 784defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 785 "cnttzd", "$rA, $rS", IIC_IntGeneral, 786 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 787def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 788 "popcntd $rA, $rS", IIC_IntGeneral, 789 [(set i64:$rA, (ctpop i64:$rS))]>; 790def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 791 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 792 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 793 isPPC64, Requires<[HasBPERMD]>; 794 795let isCodeGenOnly = 1, isCommutable = 1 in 796def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 797 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 798 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 799 800// popcntw also does a population count on the high 32 bits (storing the 801// results in the high 32-bits of the output). We'll ignore that here (which is 802// safe because we never separately use the high part of the 64-bit registers). 803def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 804 "popcntw $rA, $rS", IIC_IntGeneral, 805 [(set i32:$rA, (ctpop i32:$rS))]>; 806 807def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 808 "popcntb $rA, $rS", IIC_IntGeneral, 809 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 810 811defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 812 "divd", "$rT, $rA, $rB", IIC_IntDivD, 813 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 814defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 815 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 816 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 817defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 818 "divde", "$rT, $rA, $rB", IIC_IntDivD, 819 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 820 isPPC64, Requires<[HasExtDiv]>; 821 822let Predicates = [IsISA3_0] in { 823def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 824 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 825def MADDHDU : VAForm_1a<49, 826 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 827 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 828def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 829 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 830 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 831 isPPC64; 832def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 833 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 834let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 835 def MADDLD8 : VAForm_1a<51, 836 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 837 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 838 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 839 isPPC64; 840 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 841 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 842} 843def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 844 "darn $RT, $L", IIC_LdStLD>, isPPC64; 845def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 846 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 847def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 848 "modsd $rT, $rA, $rB", IIC_IntDivW, 849 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 850def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 851 "modud $rT, $rA, $rB", IIC_IntDivW, 852 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 853} 854 855defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 856 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 857 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 858 isPPC64, Requires<[HasExtDiv]>; 859let isCommutable = 1 in 860defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 861 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 862 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 863let Interpretation64Bit = 1, isCodeGenOnly = 1 in 864def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 865 "mulli $rD, $rA, $imm", IIC_IntMulLI, 866 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 867} 868 869let hasSideEffects = 0 in { 870defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 871 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 872 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 873 []>, isPPC64, RegConstraint<"$rSi = $rA">, 874 NoEncode<"$rSi">; 875 876// Rotate instructions. 877defm RLDCL : MDSForm_1r<30, 8, 878 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 879 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 880 []>, isPPC64; 881defm RLDCR : MDSForm_1r<30, 9, 882 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 883 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 884 []>, isPPC64; 885defm RLDICL : MDForm_1r<30, 0, 886 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 887 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 888 []>, isPPC64; 889// For fast-isel: 890let isCodeGenOnly = 1 in 891def RLDICL_32_64 : MDForm_1<30, 0, 892 (outs g8rc:$rA), 893 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 894 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 895 []>, isPPC64; 896// End fast-isel. 897let Interpretation64Bit = 1, isCodeGenOnly = 1 in 898defm RLDICL_32 : MDForm_1r<30, 0, 899 (outs gprc:$rA), 900 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 901 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 902 []>, isPPC64; 903defm RLDICR : MDForm_1r<30, 1, 904 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 905 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 906 []>, isPPC64; 907let isCodeGenOnly = 1 in 908def RLDICR_32 : MDForm_1<30, 1, 909 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 910 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 911 []>, isPPC64; 912defm RLDIC : MDForm_1r<30, 2, 913 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 914 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 915 []>, isPPC64; 916 917let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 918defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 919 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 920 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 921 []>; 922 923defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 924 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 925 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 926 []>; 927 928// RLWIMI can be commuted if the rotate amount is zero. 929let Interpretation64Bit = 1, isCodeGenOnly = 1 in 930defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 931 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 932 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 933 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 934 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 935 936let isSelect = 1 in 937def ISEL8 : AForm_4<31, 15, 938 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 939 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 940 []>; 941} // Interpretation64Bit 942} // hasSideEffects = 0 943} // End FXU Operations. 944 945def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 946def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 947 948def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 949def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 950 951def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 952def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 953 954def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 955 956def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 957def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 958def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 959def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 960 961def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 962def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 963def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 964def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 965def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 966def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 967 968def : InstAlias<"isellt $rT, $rA, $rB", 969 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 970def : InstAlias<"iselgt $rT, $rA, $rB", 971 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 972def : InstAlias<"iseleq $rT, $rA, $rB", 973 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 974 975def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 976def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 977 978def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 979def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 980 981def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 982def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 983 984def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 985def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 986 987def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 988def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 989 990def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 991def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 992 993def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 994def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 995 996def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 997def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 998 999def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1000def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1001 1002def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1003def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1004 1005def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1006def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1007 1008def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1009def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1010 1011def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1012def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1013 1014def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1015def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1016 1017def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1018def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1019 1020def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1021def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1022 1023def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1024def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1025 1026foreach SPRG = 0-3 in { 1027 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1028 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1029 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1030 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1031} 1032 1033def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1034def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1035 1036def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1037def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1038 1039def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1040 1041def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1042def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1043 1044//===----------------------------------------------------------------------===// 1045// Load/Store instructions. 1046// 1047 1048 1049// Sign extending loads. 1050let PPC970_Unit = 2 in { 1051let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1052def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1053 "lha $rD, $src", IIC_LdStLHA, 1054 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 1055 PPC970_DGroup_Cracked; 1056def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1057 "lwa $rD, $src", IIC_LdStLWA, 1058 [(set i64:$rD, 1059 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 1060 PPC970_DGroup_Cracked; 1061let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1062def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1063 "lhax $rD, $src", IIC_LdStLHA, 1064 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 1065 PPC970_DGroup_Cracked; 1066def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1067 "lwax $rD, $src", IIC_LdStLHA, 1068 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 1069 PPC970_DGroup_Cracked; 1070// For fast-isel: 1071let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1072def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1073 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1074 PPC970_DGroup_Cracked; 1075def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1076 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1077 PPC970_DGroup_Cracked; 1078} // end fast-isel isCodeGenOnly 1079 1080// Update forms. 1081let mayLoad = 1, hasSideEffects = 0 in { 1082let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1083def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1084 (ins memri:$addr), 1085 "lhau $rD, $addr", IIC_LdStLHAU, 1086 []>, RegConstraint<"$addr.reg = $ea_result">, 1087 NoEncode<"$ea_result">; 1088// NO LWAU! 1089 1090let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1091def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1092 (ins memrr:$addr), 1093 "lhaux $rD, $addr", IIC_LdStLHAUX, 1094 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1095 NoEncode<"$ea_result">; 1096def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1097 (ins memrr:$addr), 1098 "lwaux $rD, $addr", IIC_LdStLHAUX, 1099 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1100 NoEncode<"$ea_result">, isPPC64; 1101} 1102} 1103 1104let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1105// Zero extending loads. 1106let PPC970_Unit = 2 in { 1107def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1108 "lbz $rD, $src", IIC_LdStLoad, 1109 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 1110def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1111 "lhz $rD, $src", IIC_LdStLoad, 1112 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 1113def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1114 "lwz $rD, $src", IIC_LdStLoad, 1115 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 1116 1117def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1118 "lbzx $rD, $src", IIC_LdStLoad, 1119 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 1120def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1121 "lhzx $rD, $src", IIC_LdStLoad, 1122 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 1123def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1124 "lwzx $rD, $src", IIC_LdStLoad, 1125 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 1126 1127 1128// Update forms. 1129let mayLoad = 1, hasSideEffects = 0 in { 1130def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1131 (ins memri:$addr), 1132 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1133 []>, RegConstraint<"$addr.reg = $ea_result">, 1134 NoEncode<"$ea_result">; 1135def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1136 (ins memri:$addr), 1137 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1138 []>, RegConstraint<"$addr.reg = $ea_result">, 1139 NoEncode<"$ea_result">; 1140def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1141 (ins memri:$addr), 1142 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1143 []>, RegConstraint<"$addr.reg = $ea_result">, 1144 NoEncode<"$ea_result">; 1145 1146def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1147 (ins memrr:$addr), 1148 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1149 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1150 NoEncode<"$ea_result">; 1151def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1152 (ins memrr:$addr), 1153 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1154 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1155 NoEncode<"$ea_result">; 1156def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1157 (ins memrr:$addr), 1158 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1159 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1160 NoEncode<"$ea_result">; 1161} 1162} 1163} // Interpretation64Bit 1164 1165 1166// Full 8-byte loads. 1167let PPC970_Unit = 2 in { 1168def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1169 "ld $rD, $src", IIC_LdStLD, 1170 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1171// The following four definitions are selected for small code model only. 1172// Otherwise, we need to create two instructions to form a 32-bit offset, 1173// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1174def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1175 "#LDtoc", 1176 [(set i64:$rD, 1177 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1178def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1179 "#LDtocJTI", 1180 [(set i64:$rD, 1181 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1182def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1183 "#LDtocCPT", 1184 [(set i64:$rD, 1185 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1186def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1187 "#LDtocCPT", 1188 [(set i64:$rD, 1189 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1190 1191def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1192 "ldx $rD, $src", IIC_LdStLD, 1193 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1194def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1195 "ldbrx $rD, $src", IIC_LdStLoad, 1196 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1197 1198let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1199def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1200 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1201def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1202 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1203} 1204 1205let mayLoad = 1, hasSideEffects = 0 in { 1206def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1207 (ins memrix:$addr), 1208 "ldu $rD, $addr", IIC_LdStLDU, 1209 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1210 NoEncode<"$ea_result">; 1211 1212def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1213 (ins memrr:$addr), 1214 "ldux $rD, $addr", IIC_LdStLDUX, 1215 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1216 NoEncode<"$ea_result">, isPPC64; 1217 1218def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1219 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1220 Requires<[IsISA3_0]>; 1221} 1222} 1223 1224// Support for medium and large code model. 1225let hasSideEffects = 0 in { 1226let isReMaterializable = 1 in { 1227def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1228 "#ADDIStocHA8", []>, isPPC64; 1229def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1230 "#ADDItocL", []>, isPPC64; 1231} 1232let mayLoad = 1 in 1233def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1234 "#LDtocL", []>, isPPC64; 1235} 1236 1237// Support for thread-local storage. 1238def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1239 "#ADDISgotTprelHA", 1240 [(set i64:$rD, 1241 (PPCaddisGotTprelHA i64:$reg, 1242 tglobaltlsaddr:$disp))]>, 1243 isPPC64; 1244def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1245 "#LDgotTprelL", 1246 [(set i64:$rD, 1247 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1248 isPPC64; 1249 1250let Defs = [CR7], Itinerary = IIC_LdStSync in 1251def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1252 1253def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1254 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1255def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1256 "#ADDIStlsgdHA", 1257 [(set i64:$rD, 1258 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1259 isPPC64; 1260def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1261 "#ADDItlsgdL", 1262 [(set i64:$rD, 1263 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1264 isPPC64; 1265// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1266// explicitly defined when this op is created, so not mentioned here. 1267// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1268// correct because the branch select pass is relying on it. 1269let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1270 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1271def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1272 "#GETtlsADDR", 1273 [(set i64:$rD, 1274 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1275 isPPC64; 1276// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1277// are true defines while the rest of the Defs are clobbers. 1278let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1279 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1280 in 1281def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1282 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1283 "#ADDItlsgdLADDR", 1284 [(set i64:$rD, 1285 (PPCaddiTlsgdLAddr i64:$reg, 1286 tglobaltlsaddr:$disp, 1287 tglobaltlsaddr:$sym))]>, 1288 isPPC64; 1289def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1290 "#ADDIStlsldHA", 1291 [(set i64:$rD, 1292 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1293 isPPC64; 1294def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1295 "#ADDItlsldL", 1296 [(set i64:$rD, 1297 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1298 isPPC64; 1299// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1300// explicitly defined when this op is created, so not mentioned here. 1301let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1302 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1303def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1304 "#GETtlsldADDR", 1305 [(set i64:$rD, 1306 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1307 isPPC64; 1308// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1309// are true defines, while the rest of the Defs are clobbers. 1310let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1311 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1312 in 1313def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1314 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1315 "#ADDItlsldLADDR", 1316 [(set i64:$rD, 1317 (PPCaddiTlsldLAddr i64:$reg, 1318 tglobaltlsaddr:$disp, 1319 tglobaltlsaddr:$sym))]>, 1320 isPPC64; 1321def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1322 "#ADDISdtprelHA", 1323 [(set i64:$rD, 1324 (PPCaddisDtprelHA i64:$reg, 1325 tglobaltlsaddr:$disp))]>, 1326 isPPC64; 1327def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1328 "#ADDIdtprelL", 1329 [(set i64:$rD, 1330 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1331 isPPC64; 1332 1333let PPC970_Unit = 2 in { 1334let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1335// Truncating stores. 1336def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1337 "stb $rS, $src", IIC_LdStStore, 1338 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1339def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1340 "sth $rS, $src", IIC_LdStStore, 1341 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1342def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1343 "stw $rS, $src", IIC_LdStStore, 1344 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1345def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1346 "stbx $rS, $dst", IIC_LdStStore, 1347 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1348 PPC970_DGroup_Cracked; 1349def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1350 "sthx $rS, $dst", IIC_LdStStore, 1351 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1352 PPC970_DGroup_Cracked; 1353def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1354 "stwx $rS, $dst", IIC_LdStStore, 1355 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1356 PPC970_DGroup_Cracked; 1357} // Interpretation64Bit 1358 1359// Normal 8-byte stores. 1360def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1361 "std $rS, $dst", IIC_LdStSTD, 1362 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1363def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1364 "stdx $rS, $dst", IIC_LdStSTD, 1365 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1366 PPC970_DGroup_Cracked; 1367def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1368 "stdbrx $rS, $dst", IIC_LdStStore, 1369 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1370 PPC970_DGroup_Cracked; 1371} 1372 1373// Stores with Update (pre-inc). 1374let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1375let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1376def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1377 "stbu $rS, $dst", IIC_LdStSTU, []>, 1378 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1379def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1380 "sthu $rS, $dst", IIC_LdStSTU, []>, 1381 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1382def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1383 "stwu $rS, $dst", IIC_LdStSTU, []>, 1384 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1385 1386def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1387 (ins g8rc:$rS, memrr:$dst), 1388 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1389 RegConstraint<"$dst.ptrreg = $ea_res">, 1390 NoEncode<"$ea_res">, 1391 PPC970_DGroup_Cracked; 1392def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1393 (ins g8rc:$rS, memrr:$dst), 1394 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1395 RegConstraint<"$dst.ptrreg = $ea_res">, 1396 NoEncode<"$ea_res">, 1397 PPC970_DGroup_Cracked; 1398def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1399 (ins g8rc:$rS, memrr:$dst), 1400 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1401 RegConstraint<"$dst.ptrreg = $ea_res">, 1402 NoEncode<"$ea_res">, 1403 PPC970_DGroup_Cracked; 1404} // Interpretation64Bit 1405 1406def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1407 (ins g8rc:$rS, memrix:$dst), 1408 "stdu $rS, $dst", IIC_LdStSTU, []>, 1409 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1410 isPPC64; 1411 1412def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1413 (ins g8rc:$rS, memrr:$dst), 1414 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1415 RegConstraint<"$dst.ptrreg = $ea_res">, 1416 NoEncode<"$ea_res">, 1417 PPC970_DGroup_Cracked, isPPC64; 1418} 1419 1420// Patterns to match the pre-inc stores. We can't put the patterns on 1421// the instruction definitions directly as ISel wants the address base 1422// and offset to be separate operands, not a single complex operand. 1423def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1424 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1425def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1426 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1427def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1428 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1429def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1430 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1431 1432def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1433 (STBUX8 $rS, $ptrreg, $ptroff)>; 1434def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1435 (STHUX8 $rS, $ptrreg, $ptroff)>; 1436def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1437 (STWUX8 $rS, $ptrreg, $ptroff)>; 1438def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1439 (STDUX $rS, $ptrreg, $ptroff)>; 1440 1441 1442//===----------------------------------------------------------------------===// 1443// Floating point instructions. 1444// 1445 1446 1447let PPC970_Unit = 3, hasSideEffects = 0, 1448 Uses = [RM] in { // FPU Operations. 1449defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1450 "fcfid", "$frD, $frB", IIC_FPGeneral, 1451 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1452defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1453 "fctid", "$frD, $frB", IIC_FPGeneral, 1454 []>, isPPC64; 1455defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1456 "fctidu", "$frD, $frB", IIC_FPGeneral, 1457 []>, isPPC64; 1458defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1459 "fctidz", "$frD, $frB", IIC_FPGeneral, 1460 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1461 1462defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1463 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1464 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1465defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1466 "fcfids", "$frD, $frB", IIC_FPGeneral, 1467 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1468defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1469 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1470 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1471defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1472 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1473 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1474defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1475 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1476 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1477} 1478 1479 1480//===----------------------------------------------------------------------===// 1481// Instruction Patterns 1482// 1483 1484// Extensions and truncates to/from 32-bit regs. 1485def : Pat<(i64 (zext i32:$in)), 1486 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1487 0, 32)>; 1488def : Pat<(i64 (anyext i32:$in)), 1489 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1490def : Pat<(i32 (trunc i64:$in)), 1491 (EXTRACT_SUBREG $in, sub_32)>; 1492 1493// Implement the 'not' operation with the NOR instruction. 1494// (we could use the default xori pattern, but nor has lower latency on some 1495// cores (such as the A2)). 1496def i64not : OutPatFrag<(ops node:$in), 1497 (NOR8 $in, $in)>; 1498def : Pat<(not i64:$in), 1499 (i64not $in)>; 1500 1501// Extending loads with i64 targets. 1502def : Pat<(zextloadi1 iaddr:$src), 1503 (LBZ8 iaddr:$src)>; 1504def : Pat<(zextloadi1 xaddr:$src), 1505 (LBZX8 xaddr:$src)>; 1506def : Pat<(extloadi1 iaddr:$src), 1507 (LBZ8 iaddr:$src)>; 1508def : Pat<(extloadi1 xaddr:$src), 1509 (LBZX8 xaddr:$src)>; 1510def : Pat<(extloadi8 iaddr:$src), 1511 (LBZ8 iaddr:$src)>; 1512def : Pat<(extloadi8 xaddr:$src), 1513 (LBZX8 xaddr:$src)>; 1514def : Pat<(extloadi16 iaddr:$src), 1515 (LHZ8 iaddr:$src)>; 1516def : Pat<(extloadi16 xaddr:$src), 1517 (LHZX8 xaddr:$src)>; 1518def : Pat<(extloadi32 iaddr:$src), 1519 (LWZ8 iaddr:$src)>; 1520def : Pat<(extloadi32 xaddr:$src), 1521 (LWZX8 xaddr:$src)>; 1522 1523// Standard shifts. These are represented separately from the real shifts above 1524// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1525// amounts. 1526def : Pat<(sra i64:$rS, i32:$rB), 1527 (SRAD $rS, $rB)>; 1528def : Pat<(srl i64:$rS, i32:$rB), 1529 (SRD $rS, $rB)>; 1530def : Pat<(shl i64:$rS, i32:$rB), 1531 (SLD $rS, $rB)>; 1532 1533// SUBFIC 1534def : Pat<(sub imm64SExt16:$imm, i64:$in), 1535 (SUBFIC8 $in, imm:$imm)>; 1536 1537// SHL/SRL 1538def : Pat<(shl i64:$in, (i32 imm:$imm)), 1539 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1540def : Pat<(srl i64:$in, (i32 imm:$imm)), 1541 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1542 1543// ROTL 1544def : Pat<(rotl i64:$in, i32:$sh), 1545 (RLDCL $in, $sh, 0)>; 1546def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1547 (RLDICL $in, imm:$imm, 0)>; 1548 1549// Hi and Lo for Darwin Global Addresses. 1550def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1551def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1552def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1553def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1554def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1555def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1556def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1557def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1558def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1559 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1560def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1561 (ADDI8 $in, tglobaltlsaddr:$g)>; 1562def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1563 (ADDIS8 $in, tglobaladdr:$g)>; 1564def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1565 (ADDIS8 $in, tconstpool:$g)>; 1566def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1567 (ADDIS8 $in, tjumptable:$g)>; 1568def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1569 (ADDIS8 $in, tblockaddress:$g)>; 1570 1571// Patterns to match r+r indexed loads and stores for 1572// addresses without at least 4-byte alignment. 1573def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1574 (LWAX xoaddr:$src)>; 1575def : Pat<(i64 (unaligned4load xoaddr:$src)), 1576 (LDX xoaddr:$src)>; 1577def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1578 (STDX $rS, xoaddr:$dst)>; 1579 1580// 64-bits atomic loads and stores 1581def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1582def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1583 1584def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1585def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1586 1587let Predicates = [IsISA3_0] in { 1588 1589class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1590 InstrItinClass itin, list<dag> pattern> 1591 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1592 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1593 1594let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1595def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1596def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1597def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1598} 1599 1600// SLB Invalidate Entry Global 1601def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1602 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1603// SLB Synchronize 1604def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1605 1606} // IsISA3_0 1607