1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retglue)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 91 "bcctr 12, $BI, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 94 "bcctr 4, $BI, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 106 "bdz $BD">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 108 "bdnz $BD">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 125 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$LI), 128 "bl $LI", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 131 "bla $LI", IIC_BrB, [(PPCcall (i64 imm:$LI))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$LI), 136 "bl $LI\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$LI), 140 "bl $LI\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$LI), 144 "bla $LI\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$LI))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$LI), 153 "bl $LI", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$LI), 156 "bl $LI", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 172 "bcctrl 12, $BI, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 175 "bcctrl 4, $BI, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, 182 isCodeGenOnly = 1, Uses = [RM] in { 183 // Convenient aliases for call instructions 184 def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 185 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 186 187 def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 188 "bla $LI", IIC_BrB, [(PPCcall_rm (i64 imm:$LI))]>; 189 def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 190 (outs), (ins calltarget:$LI), 191 "bl $LI\n\tnop", IIC_BrB, []>; 192 193 def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, 194 (outs), (ins abscalltarget:$LI), 195 "bla $LI\n\tnop", IIC_BrB, 196 [(PPCcall_nop_rm (i64 imm:$LI))]>; 197 let Predicates = [PCRelativeMemops] in { 198 // BL8_NOTOC means that the caller does not use the TOC pointer and if 199 // it does use R2 then it is just a caller saved register. Therefore it is 200 // safe to emit only the bl and not the nop for this instruction. The 201 // linker will not try to restore R2 after the call. 202 def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), 203 (ins calltarget:$LI), 204 "bl $LI", IIC_BrB, []>; 205 } 206 let Uses = [CTR8, RM] in { 207 let isPredicable = 1 in 208 def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 209 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 210 Requires<[In64BitMode]>; 211 } 212} 213 214let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 215 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 216 def BCTRL8_LDinto_toc : 217 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 218 (ins (memrix $D, $RA):$src), 219 "bctrl\n\tld 2, $src", IIC_BrB, 220 [(PPCbctrl_load_toc iaddrX4:$src)]>, 221 Requires<[In64BitMode]>; 222} 223 224let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 225 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in { 226 def BCTRL8_LDinto_toc_RM : 227 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 228 (ins (memrix $D, $RA):$src), 229 "bctrl\n\tld 2, $src", IIC_BrB, 230 [(PPCbctrl_load_toc_rm iaddrX4:$src)]>, 231 Requires<[In64BitMode]>; 232} 233 234} // Interpretation64Bit 235 236// FIXME: Duplicating this for the asm parser should be unnecessary, but the 237// previous definition must be marked as CodeGen only to prevent decoding 238// conflicts. 239let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in 240let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 241def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$LI), 242 "bl $LI", IIC_BrB, []>; 243 244// Calls 245def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 246 (BL8 tglobaladdr:$dst)>; 247def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 248 (BL8_NOP tglobaladdr:$dst)>; 249 250def : Pat<(PPCcall (i64 texternalsym:$dst)), 251 (BL8 texternalsym:$dst)>; 252def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 253 (BL8_NOP texternalsym:$dst)>; 254 255def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 256 (BL8_NOTOC tglobaladdr:$dst)>; 257def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 258 (BL8_NOTOC texternalsym:$dst)>; 259 260def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)), 261 (BL8_RM tglobaladdr:$dst)>; 262def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)), 263 (BL8_NOP_RM tglobaladdr:$dst)>; 264 265def : Pat<(PPCcall_rm (i64 texternalsym:$dst)), 266 (BL8_RM texternalsym:$dst)>; 267def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)), 268 (BL8_NOP_RM texternalsym:$dst)>; 269 270def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)), 271 (BL8_NOTOC_RM tglobaladdr:$dst)>; 272def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)), 273 (BL8_NOTOC_RM texternalsym:$dst)>; 274 275// Calls for AIX 276def : Pat<(PPCcall (i64 mcsym:$dst)), 277 (BL8 mcsym:$dst)>; 278def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 279 (BL8_NOP mcsym:$dst)>; 280 281def : Pat<(PPCcall_rm (i64 mcsym:$dst)), 282 (BL8_RM mcsym:$dst)>; 283def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)), 284 (BL8_NOP_RM mcsym:$dst)>; 285 286// Atomic operations 287// FIXME: some of these might be used with constant operands. This will result 288// in constant materialization instructions that may be redundant. We currently 289// clean this up in PPCMIPeephole with calls to 290// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 291// in the first place. 292let Defs = [CR0] in { 293 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 294 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 295 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 296 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 297 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 298 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 299 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 300 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 301 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 302 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 303 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 304 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 305 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 306 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 307 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 308 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 309 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 310 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 311 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 312 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 313 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 314 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 315 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 316 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 317 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 318 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 319 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 320 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 321 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 322 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 323 324 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 325 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 326 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 327 328 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 329 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 330 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 331} 332 333// Instructions to support atomic operations 334let mayLoad = 1, hasSideEffects = 0 in { 335def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 336 "ldarx $RST, $addr", IIC_LdStLDARX, []>; 337// TODO: Add scheduling info. 338let hasNoSchedulingInfo = 1 in 339def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr), 340 "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64; 341 342// Instruction to support lock versions of atomics 343// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 344def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 345 "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm; 346// TODO: Add scheduling info. 347let hasNoSchedulingInfo = 1 in 348// FIXME: We have to seek a way to remove isRecordForm since 349// LQARXL is not really altering CR0. 350def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr), 351 "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>, 352 isPPC64, isRecordForm; 353 354let hasExtraDefRegAllocReq = 1 in 355def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB), 356 "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64, 357 Requires<[IsISA3_0]>; 358} 359 360let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 361def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 362 "stdcx. $RST, $addr", IIC_LdStSTDCX, []>, isRecordForm; 363// TODO: Add scheduling info. 364let hasNoSchedulingInfo = 1 in 365def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr), 366 "stqcx. $RST, $addr", IIC_LdStSTQCX, []>, 367 isPPC64, isRecordForm; 368} 369 370def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 371 (ins g8prc:$src), 372 "#SPLIT_QUADWORD", []>; 373class AtomicRMW128<string asmstr> 374 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 375 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 376 asmstr, []>; 377// We have to keep values in MI's uses during LL/SC looping as they are, 378// so set both $RTp and $scratch earlyclobber. 379let mayStore = 1, mayLoad = 1, 380 Defs = [CR0], 381 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 382// Atomic pseudo instructions expanded post-ra. 383def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 384def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 385def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 386def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 387def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 388def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 389def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 390 391def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 392 (outs g8prc:$RTp, g8prc:$scratch), 393 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 394 g8rc:$new_lo, g8rc:$new_hi), 395 "#ATOMIC_CMP_SWAP_I128", []>; 396} 397 398class PatAtomicRMWI128<SDPatternOperator OpNode, AtomicRMW128 Inst> : 399 Pat<(OpNode ForceXForm:$ptr, 400 i64:$incr_lo, 401 i64:$incr_hi), 402 (SPLIT_QUADWORD (Inst memrr:$ptr, 403 g8rc:$incr_lo, 404 g8rc:$incr_hi))>; 405 406def : PatAtomicRMWI128<int_ppc_atomicrmw_add_i128, ATOMIC_LOAD_ADD_I128>; 407def : PatAtomicRMWI128<int_ppc_atomicrmw_sub_i128, ATOMIC_LOAD_SUB_I128>; 408def : PatAtomicRMWI128<int_ppc_atomicrmw_xor_i128, ATOMIC_LOAD_XOR_I128>; 409def : PatAtomicRMWI128<int_ppc_atomicrmw_and_i128, ATOMIC_LOAD_AND_I128>; 410def : PatAtomicRMWI128<int_ppc_atomicrmw_nand_i128, ATOMIC_LOAD_NAND_I128>; 411def : PatAtomicRMWI128<int_ppc_atomicrmw_or_i128, ATOMIC_LOAD_OR_I128>; 412def : PatAtomicRMWI128<int_ppc_atomicrmw_xchg_i128, ATOMIC_SWAP_I128>; 413def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 414 i64:$cmp_lo, 415 i64:$cmp_hi, 416 i64:$new_lo, 417 i64:$new_hi), 418 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 419 memrr:$ptr, 420 g8rc:$cmp_lo, 421 g8rc:$cmp_hi, 422 g8rc:$new_lo, 423 g8rc:$new_hi))>; 424 425let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 426def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB), 427 "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64, 428 Requires<[IsISA3_0]>; 429 430let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 431let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 432def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 433 (ins calltarget:$dst, i32imm:$offset), 434 "#TC_RETURNd8 $dst $offset", 435 []>; 436 437let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 438def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 439 "#TC_RETURNa8 $func $offset", 440 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 441 442let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 443def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 444 "#TC_RETURNr8 $dst $offset", 445 []>; 446 447let hasSideEffects = 0 in { 448let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 449 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 450def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 451 []>, 452 Requires<[In64BitMode]>; 453 454let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 455 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 456def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 457 "b $LI", IIC_BrB, 458 []>; 459 460let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 461 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 462def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 463 "ba $LI", IIC_BrB, 464 []>; 465} 466} // Interpretation64Bit 467 468def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 469 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 470 471def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 472 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 473 474def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 475 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 476 477 478// 64-bit CR instructions 479let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 480let hasSideEffects = 0 in { 481// mtocrf's input needs to be prepared by shifting by an amount dependent 482// on the cr register selected. Thus, post-ra anti-dep breaking must not 483// later change that register assignment. 484let hasExtraDefRegAllocReq = 1 in { 485def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$RST), 486 "mtocrf $FXM, $RST", IIC_BrMCRX>, 487 PPC970_DGroup_First, PPC970_Unit_CRU; 488 489// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 490// is dependent on the cr fields being set. 491def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$RST), 492 "mtcrf $FXM, $RST", IIC_BrMCRX>, 493 PPC970_MicroCode, PPC970_Unit_CRU; 494} // hasExtraDefRegAllocReq = 1 495 496// mfocrf's input needs to be prepared by shifting by an amount dependent 497// on the cr register selected. Thus, post-ra anti-dep breaking must not 498// later change that register assignment. 499let hasExtraSrcRegAllocReq = 1 in { 500def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$RST), (ins crbitm:$FXM), 501 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 502 PPC970_DGroup_First, PPC970_Unit_CRU; 503 504// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 505// is dependent on the cr fields being copied. 506def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$RT), (ins), 507 "mfcr $RT", IIC_SprMFCR>, 508 PPC970_MicroCode, PPC970_Unit_CRU; 509} // hasExtraSrcRegAllocReq = 1 510} // hasSideEffects = 0 511 512// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 513// is not. 514let hasSideEffects = 1 in { 515 let Defs = [CTR8] in 516 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 517 "#EH_SJLJ_SETJMP64", 518 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 519 Requires<[In64BitMode]>; 520} 521 522let hasSideEffects = 1, isBarrier = 1 in { 523 let isTerminator = 1 in 524 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 525 "#EH_SJLJ_LONGJMP64", 526 [(PPCeh_sjlj_longjmp addr:$buf)]>, 527 Requires<[In64BitMode]>; 528} 529 530def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR), 531 "mfspr $RST, $SPR", IIC_SprMFSPR>; 532def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST), 533 "mtspr $SPR, $RST", IIC_SprMTSPR>; 534 535 536//===----------------------------------------------------------------------===// 537// 64-bit SPR manipulation instrs. 538 539let Uses = [CTR8] in { 540def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$RST), (ins), 541 "mfctr $RST", IIC_SprMFSPR>, 542 PPC970_DGroup_First, PPC970_Unit_FXU; 543} 544let Pattern = [(PPCmtctr i64:$RST)], Defs = [CTR8] in { 545def MTCTR8 : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST), 546 "mtctr $RST", IIC_SprMTSPR>, 547 PPC970_DGroup_First, PPC970_Unit_FXU; 548} 549// MTCTR[8|]loop must be inside a loop-preheader, duplicating 550// the loop-preheader block will break this assumption. 551let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in { 552let Pattern = [(int_set_loop_iterations i64:$RST)] in 553def MTCTR8loop : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST), 554 "mtctr $RST", IIC_SprMTSPR>, 555 PPC970_DGroup_First, PPC970_Unit_FXU; 556} 557 558let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in 559def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), 560 "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>; 561 562let Pattern = [(set i64:$RST, readcyclecounter)] in 563def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$RST), (ins), 564 "mfspr $RST, 268", IIC_SprMFTB>, 565 PPC970_DGroup_First, PPC970_Unit_FXU; 566// Note that encoding mftb using mfspr is now the preferred form, 567// and has been since at least ISA v2.03. The mftb instruction has 568// now been phased out. Using mfspr, however, is known not to work on 569// the POWER3. 570 571let Defs = [X1], Uses = [X1] in 572def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 573 [(set i64:$result, 574 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 575def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 576 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 577// Probed alloca to support stack clash protection. 578let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 579def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 580 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 581 [(set i64:$result, 582 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 583def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 584 g8rc:$fp, g8rc:$actual_negsize), 585 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 586def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 587 g8rc:$fp, g8rc:$actual_negsize), 588 (ins g8rc:$negsize, memri:$fpsi), 589 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 590 RegConstraint<"$actual_negsize = $negsize">; 591def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 592 (ins i64imm:$stacksize), 593 "#PROBED_STACKALLOC_64", []>; 594} 595 596let hasSideEffects = 0 in { 597let Defs = [LR8] in { 598def MTLR8 : XFXForm_1_ext<31, 467, 8, (outs), (ins g8rc:$RST), 599 "mtlr $RST", IIC_SprMTSPR>, 600 PPC970_DGroup_First, PPC970_Unit_FXU; 601} 602let Uses = [LR8] in { 603def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$RST), (ins), 604 "mflr $RST", IIC_SprMFSPR>, 605 PPC970_DGroup_First, PPC970_Unit_FXU; 606} 607} // Interpretation64Bit 608} 609 610//===----------------------------------------------------------------------===// 611// Fixed point instructions. 612// 613 614let PPC970_Unit = 1 in { // FXU Operations. 615let Interpretation64Bit = 1 in { 616let hasSideEffects = 0 in { 617let isCodeGenOnly = 1 in { 618 619let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 620def LI8 : DForm_2_r0<14, (outs g8rc:$RST), (ins s16imm64:$D), 621 "li $RST, $D", IIC_IntSimple, 622 [(set i64:$RST, imm64SExt16:$D)]>, SExt32To64; 623def LIS8 : DForm_2_r0<15, (outs g8rc:$RST), (ins s17imm64:$D), 624 "lis $RST, $D", IIC_IntSimple, 625 [(set i64:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 626} 627 628// Logical ops. 629let isCommutable = 1 in { 630defm NAND8: XForm_6r<31, 476, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 631 "nand", "$RA, $RST, $RB", IIC_IntSimple, 632 [(set i64:$RA, (not (and i64:$RST, i64:$RB)))]>; 633defm AND8 : XForm_6r<31, 28, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 634 "and", "$RA, $RST, $RB", IIC_IntSimple, 635 [(set i64:$RA, (and i64:$RST, i64:$RB))]>; 636} // isCommutable 637defm ANDC8: XForm_6r<31, 60, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 638 "andc", "$RA, $RST, $RB", IIC_IntSimple, 639 [(set i64:$RA, (and i64:$RST, (not i64:$RB)))]>; 640let isCommutable = 1 in { 641defm OR8 : XForm_6r<31, 444, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 642 "or", "$RA, $RST, $RB", IIC_IntSimple, 643 [(set i64:$RA, (or i64:$RST, i64:$RB))]>; 644defm NOR8 : XForm_6r<31, 124, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 645 "nor", "$RA, $RST, $RB", IIC_IntSimple, 646 [(set i64:$RA, (not (or i64:$RST, i64:$RB)))]>; 647} // isCommutable 648defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 649 "orc", "$RA, $RST, $RB", IIC_IntSimple, 650 [(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>; 651let isCommutable = 1 in { 652defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 653 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 654 [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>; 655defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 656 "xor", "$RA, $RST, $RB", IIC_IntSimple, 657 [(set i64:$RA, (xor i64:$RST, i64:$RB))]>; 658} // let isCommutable = 1 659 660// Logical ops with immediate. 661let Defs = [CR0] in { 662def ANDI8_rec : DForm_4<28, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 663 "andi. $RA, $RST, $D", IIC_IntGeneral, 664 [(set i64:$RA, (and i64:$RST, immZExt16:$D))]>, 665 isRecordForm, SExt32To64, ZExt32To64; 666def ANDIS8_rec : DForm_4<29, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 667 "andis. $RA, $RST, $D", IIC_IntGeneral, 668 [(set i64:$RA, (and i64:$RST, imm16ShiftedZExt:$D))]>, 669 isRecordForm, ZExt32To64; 670} 671def ORI8 : DForm_4<24, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 672 "ori $RA, $RST, $D", IIC_IntSimple, 673 [(set i64:$RA, (or i64:$RST, immZExt16:$D))]>; 674def ORIS8 : DForm_4<25, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 675 "oris $RA, $RST, $D", IIC_IntSimple, 676 [(set i64:$RA, (or i64:$RST, imm16ShiftedZExt:$D))]>; 677def XORI8 : DForm_4<26, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 678 "xori $RA, $RST, $D", IIC_IntSimple, 679 [(set i64:$RA, (xor i64:$RST, immZExt16:$D))]>; 680def XORIS8 : DForm_4<27, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), 681 "xoris $RA, $RST, $D", IIC_IntSimple, 682 [(set i64:$RA, (xor i64:$RST, imm16ShiftedZExt:$D))]>; 683 684let isCommutable = 1 in 685defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 686 "add", "$RT, $RA, $RB", IIC_IntSimple, 687 [(set i64:$RT, (add i64:$RA, i64:$RB))]>; 688// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 689// initial-exec thread-local storage model. We need to forbid r0 here - 690// while it works for add just fine, the linker can relax this to local-exec 691// addi, which won't work for r0. 692def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB), 693 "add $RT, $RA, $RB", IIC_IntSimple, 694 [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>; 695let mayLoad = 1 in { 696def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 697 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; 698def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 699 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; 700def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 701 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; 702def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 703 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; 704def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 705 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; 706def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 707 "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; 708def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 709 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; 710def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 711 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; 712def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 713 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; 714def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 715 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; 716def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 717 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; 718 719} 720let mayLoad = 1, Predicates = [HasFPU] in { 721def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 722 "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; 723def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 724 "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; 725} 726 727let mayStore = 1 in { 728def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 729 "stbx $RST, $RA, $RB", IIC_LdStStore, []>, 730 PPC970_DGroup_Cracked; 731def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 732 "sthx $RST, $RA, $RB", IIC_LdStStore, []>, 733 PPC970_DGroup_Cracked; 734def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 735 "stwx $RST, $RA, $RB", IIC_LdStStore, []>, 736 PPC970_DGroup_Cracked; 737def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 738 "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, 739 PPC970_DGroup_Cracked; 740def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 741 "stbx $RST, $RA, $RB", IIC_LdStStore, []>, 742 PPC970_DGroup_Cracked; 743def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 744 "sthx $RST, $RA, $RB", IIC_LdStStore, []>, 745 PPC970_DGroup_Cracked; 746def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 747 "stwx $RST, $RA, $RB", IIC_LdStStore, []>, 748 PPC970_DGroup_Cracked; 749 750} 751let mayStore = 1, Predicates = [HasFPU] in { 752def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 753 "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, 754 PPC970_DGroup_Cracked; 755def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 756 "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, 757 PPC970_DGroup_Cracked; 758} 759 760let isCommutable = 1 in 761defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 762 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 763 [(set i64:$RT, (addc i64:$RA, i64:$RB))]>, 764 PPC970_DGroup_Cracked; 765 766let Defs = [CARRY] in 767def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), 768 "addic $RST, $RA, $D", IIC_IntGeneral, 769 [(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>; 770def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D), 771 "addi $RST, $RA, $D", IIC_IntSimple, 772 [(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>; 773def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D), 774 "addis $RST, $RA, $D", IIC_IntSimple, 775 [(set i64:$RST, (add i64:$RA, imm16ShiftedSExt:$D))]>; 776 777def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D), 778 "la $RST, $D($RA)", IIC_IntGeneral, 779 [(set i64:$RST, (add i64:$RA, 780 (PPClo tglobaladdr:$D, 0)))]>; 781 782let Defs = [CARRY] in { 783def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), 784 "subfic $RST, $RA, $D", IIC_IntGeneral, 785 [(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>; 786} 787defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 788 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 789 [(set i64:$RT, (subc i64:$RB, i64:$RA))]>, 790 PPC970_DGroup_Cracked; 791defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 792 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 793 [(set i64:$RT, (sub i64:$RB, i64:$RA))]>; 794defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA), 795 "neg", "$RT, $RA", IIC_IntSimple, 796 [(set i64:$RT, (ineg i64:$RA))]>; 797let Uses = [CARRY] in { 798let isCommutable = 1 in 799defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 800 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 801 [(set i64:$RT, (adde i64:$RA, i64:$RB))]>; 802defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA), 803 "addme", "$RT, $RA", IIC_IntGeneral, 804 [(set i64:$RT, (adde i64:$RA, -1))]>; 805defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA), 806 "addze", "$RT, $RA", IIC_IntGeneral, 807 [(set i64:$RT, (adde i64:$RA, 0))]>; 808defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 809 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 810 [(set i64:$RT, (sube i64:$RB, i64:$RA))]>; 811defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA), 812 "subfme", "$RT, $RA", IIC_IntGeneral, 813 [(set i64:$RT, (sube -1, i64:$RA))]>; 814defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA), 815 "subfze", "$RT, $RA", IIC_IntGeneral, 816 [(set i64:$RT, (sube 0, i64:$RA))]>; 817} 818} // isCodeGenOnly 819 820// FIXME: Duplicating this for the asm parser should be unnecessary, but the 821// previous definition must be marked as CodeGen only to prevent decoding 822// conflicts. 823let isAsmParserOnly = 1 in { 824def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB), 825 "add $RT, $RA, $RB", IIC_IntSimple, []>; 826 827let mayLoad = 1 in { 828def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 829 "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; 830def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 831 "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; 832def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 833 "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; 834def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 835 "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; 836def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 837 "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; 838def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 839 "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; 840} 841 842let mayLoad = 1, Predicates = [HasFPU] in { 843def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 844 "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; 845def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), 846 "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; 847} 848 849let mayStore = 1 in { 850def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 851 "stbx $RST, $RA, $RB", IIC_LdStStore, []>, 852 PPC970_DGroup_Cracked; 853def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 854 "sthx $RST, $RA, $RB", IIC_LdStStore, []>, 855 PPC970_DGroup_Cracked; 856def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 857 "stwx $RST, $RA, $RB", IIC_LdStStore, []>, 858 PPC970_DGroup_Cracked; 859def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 860 "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, 861 PPC970_DGroup_Cracked; 862} 863 864let mayStore = 1, Predicates = [HasFPU] in { 865def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 866 "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, 867 PPC970_DGroup_Cracked; 868def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), 869 "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, 870 PPC970_DGroup_Cracked; 871} 872} 873 874let isCommutable = 1 in { 875defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 876 "mulhd", "$RT, $RA, $RB", IIC_IntMulHW, 877 [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>; 878defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 879 "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU, 880 [(set i64:$RT, (mulhu i64:$RA, i64:$RB))]>; 881} // isCommutable 882} 883} // Interpretation64Bit 884 885let isCompare = 1, hasSideEffects = 0 in { 886 def CMPD : XForm_16_ext<31, 0, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB), 887 "cmpd $BF, $RA, $RB", IIC_IntCompare>, isPPC64; 888 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB), 889 "cmpld $BF, $RA, $RB", IIC_IntCompare>, isPPC64; 890 def CMPDI : DForm_5_ext<11, (outs crrc:$BF), (ins g8rc:$RA, s16imm64:$D), 891 "cmpdi $BF, $RA, $D", IIC_IntCompare>, isPPC64; 892 def CMPLDI : DForm_6_ext<10, (outs crrc:$BF), (ins g8rc:$RA, u16imm64:$D), 893 "cmpldi $BF, $RA, $D", 894 IIC_IntCompare>, isPPC64; 895 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 896 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 897 (ins u1imm:$L, g8rc:$RA, g8rc:$RB), 898 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 899 Requires<[IsISA3_0]>; 900 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 901 (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB", 902 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 903} 904 905let hasSideEffects = 0 in { 906defm SLD : XForm_6r<31, 27, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), 907 "sld", "$RA, $RST, $RB", IIC_IntRotateD, 908 [(set i64:$RA, (PPCshl i64:$RST, i32:$RB))]>, isPPC64; 909defm SRD : XForm_6r<31, 539, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), 910 "srd", "$RA, $RST, $RB", IIC_IntRotateD, 911 [(set i64:$RA, (PPCsrl i64:$RST, i32:$RB))]>, isPPC64; 912defm SRAD : XForm_6rc<31, 794, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), 913 "srad", "$RA, $RST, $RB", IIC_IntRotateD, 914 [(set i64:$RA, (PPCsra i64:$RST, i32:$RB))]>, isPPC64; 915 916let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 917defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$RA), (ins g8rc:$RST), 918 "cntlzw", "$RA, $RST", IIC_IntGeneral, []>, 919 ZExt32To64, SExt32To64; 920defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$RA), (ins g8rc:$RST), 921 "cnttzw", "$RA, $RST", IIC_IntGeneral, []>, 922 Requires<[IsISA3_0]>, ZExt32To64, SExt32To64; 923 924defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$RA), (ins g8rc:$RST), 925 "extsb", "$RA, $RST", IIC_IntSimple, 926 [(set i64:$RA, (sext_inreg i64:$RST, i8))]>, SExt32To64; 927defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$RA), (ins g8rc:$RST), 928 "extsh", "$RA, $RST", IIC_IntSimple, 929 [(set i64:$RA, (sext_inreg i64:$RST, i16))]>, SExt32To64; 930 931defm SLW8 : XForm_6r<31, 24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 932 "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64; 933defm SRW8 : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 934 "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64; 935} // Interpretation64Bit 936 937// For fast-isel: 938let isCodeGenOnly = 1 in { 939def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$RA), (ins gprc:$RST), 940 "extsb $RA, $RST", IIC_IntSimple, []>, isPPC64, 941 SExt32To64; 942def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$RA), (ins gprc:$RST), 943 "extsh $RA, $RST", IIC_IntSimple, []>, isPPC64, 944 SExt32To64; 945} // isCodeGenOnly for fast-isel 946 947defm EXTSW : XForm_11r<31, 986, (outs g8rc:$RA), (ins g8rc:$RST), 948 "extsw", "$RA, $RST", IIC_IntSimple, 949 [(set i64:$RA, (sext_inreg i64:$RST, i32))]>, isPPC64, 950 SExt32To64; 951let Interpretation64Bit = 1, isCodeGenOnly = 1 in 952defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$RA), (ins gprc:$RST), 953 "extsw", "$RA, $RST", IIC_IntSimple, 954 [(set i64:$RA, (sext i32:$RST))]>, isPPC64, 955 SExt32To64; 956let isCodeGenOnly = 1 in 957def EXTSW_32 : XForm_11<31, 986, (outs gprc:$RA), (ins gprc:$RST), 958 "extsw $RA, $RST", IIC_IntSimple, 959 []>, isPPC64; 960 961defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH), 962 "sradi", "$RA, $RS, $SH", IIC_IntRotateDI, 963 [(set i64:$RA, (sra i64:$RS, (i32 imm:$SH)))]>, isPPC64; 964 965let Interpretation64Bit = 1, isCodeGenOnly = 1 in 966defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$RA), 967 (ins gprc:$RS, u6imm:$SH), 968 "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI, 969 [(set i64:$RA, 970 (PPCextswsli i32:$RS, (i32 imm:$SH)))]>, 971 isPPC64, Requires<[IsISA3_0]>; 972 973defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH), 974 "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI, 975 []>, isPPC64, Requires<[IsISA3_0]>; 976 977// For fast-isel: 978let isCodeGenOnly = 1, Defs = [CARRY] in 979def SRADI_32 : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH), 980 "sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64; 981 982defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$RA), (ins g8rc:$RST), 983 "cntlzd", "$RA, $RST", IIC_IntGeneral, 984 [(set i64:$RA, (ctlz i64:$RST))]>, 985 ZExt32To64, SExt32To64; 986defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$RA), (ins g8rc:$RST), 987 "cnttzd", "$RA, $RST", IIC_IntGeneral, 988 [(set i64:$RA, (cttz i64:$RST))]>, Requires<[IsISA3_0]>, 989 ZExt32To64, SExt32To64; 990def POPCNTD : XForm_11<31, 506, (outs g8rc:$RA), (ins g8rc:$RST), 991 "popcntd $RA, $RST", IIC_IntGeneral, 992 [(set i64:$RA, (ctpop i64:$RST))]>, 993 ZExt32To64, SExt32To64; 994def BPERMD : XForm_6<31, 252, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 995 "bpermd $RA, $RST, $RB", IIC_IntGeneral, 996 [(set i64:$RA, (int_ppc_bpermd g8rc:$RST, g8rc:$RB))]>, 997 isPPC64, Requires<[HasBPERMD]>; 998 999let isCodeGenOnly = 1, isCommutable = 1 in 1000def CMPB8 : XForm_6<31, 508, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), 1001 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 1002 [(set i64:$RA, (PPCcmpb i64:$RST, i64:$RB))]>; 1003 1004// popcntw also does a population count on the high 32 bits (storing the 1005// results in the high 32-bits of the output). We'll ignore that here (which is 1006// safe because we never separately use the high part of the 64-bit registers). 1007def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST), 1008 "popcntw $RA, $RST", IIC_IntGeneral, 1009 [(set i32:$RA, (ctpop i32:$RST))]>; 1010 1011let isCodeGenOnly = 1 in { 1012def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST), 1013 "popcntb $RA, $RST", IIC_IntGeneral, 1014 [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>; 1015 1016def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST), 1017 "cdtbcd $RA, $RST", IIC_IntGeneral, []>; 1018def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST), 1019 "cbcdtd $RA, $RST", IIC_IntGeneral, []>; 1020 1021def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1022 "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>; 1023} 1024 1025defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1026 "divd", "$RT, $RA, $RB", IIC_IntDivD, 1027 [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64; 1028defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1029 "divdu", "$RT, $RA, $RB", IIC_IntDivD, 1030 [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64; 1031defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1032 "divde", "$RT, $RA, $RB", IIC_IntDivD, 1033 [(set i64:$RT, (int_ppc_divde g8rc:$RA, g8rc:$RB))]>, 1034 isPPC64, Requires<[HasExtDiv]>; 1035 1036let Predicates = [IsISA3_0] in { 1037def MADDHD : VAForm_1a<48, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1038 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1039def MADDHDU : VAForm_1a<49, 1040 (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1041 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1042def MADDLD : VAForm_1a<51, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 1043 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1044 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 1045 isPPC64; 1046let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1047 def MADDLD8 : VAForm_1a<51, 1048 (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1049 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1050 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 1051 isPPC64; 1052 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 1053 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64; 1054} 1055def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 1056 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 1057def MODSD : XForm_8<31, 777, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB), 1058 "modsd $RST, $RA, $RB", IIC_IntDivW, 1059 [(set i64:$RST, (srem i64:$RA, i64:$RB))]>; 1060def MODUD : XForm_8<31, 265, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB), 1061 "modud $RST, $RA, $RB", IIC_IntDivW, 1062 [(set i64:$RST, (urem i64:$RA, i64:$RB))]>; 1063} 1064 1065defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1066 "divdeu", "$RT, $RA, $RB", IIC_IntDivD, 1067 [(set i64:$RT, (int_ppc_divdeu g8rc:$RA, g8rc:$RB))]>, 1068 isPPC64, Requires<[HasExtDiv]>; 1069let isCommutable = 1 in 1070defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), 1071 "mulld", "$RT, $RA, $RB", IIC_IntMulHD, 1072 [(set i64:$RT, (mul i64:$RA, i64:$RB))]>, isPPC64; 1073let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1074def MULLI8 : DForm_2<7, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), 1075 "mulli $RST, $RA, $D", IIC_IntMulLI, 1076 [(set i64:$RST, (mul i64:$RA, imm64SExt16:$D))]>; 1077} 1078 1079let hasSideEffects = 1 in { 1080def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 1081 "darn $RT, $L", IIC_LdStLD>, isPPC64; 1082} 1083 1084let hasSideEffects = 0 in { 1085defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA), 1086 (ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1087 "rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1088 []>, isPPC64, RegConstraint<"$RAi = $RA">, 1089 NoEncode<"$RAi">; 1090 1091// Rotate instructions. 1092defm RLDCL : MDSForm_1r<30, 8, 1093 (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE), 1094 "rldcl", "$RA, $RS, $RB, $MBE", IIC_IntRotateD, 1095 []>, isPPC64; 1096defm RLDCR : MDSForm_1r<30, 9, 1097 (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE), 1098 "rldcr", "$RA, $RS, $RB, $MBE", IIC_IntRotateD, 1099 []>, isPPC64; 1100defm RLDICL : MDForm_1r<30, 0, 1101 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1102 "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1103 []>, isPPC64; 1104// For fast-isel: 1105let isCodeGenOnly = 1 in 1106def RLDICL_32_64 : MDForm_1<30, 0, 1107 (outs g8rc:$RA), 1108 (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), 1109 "rldicl $RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1110 []>, isPPC64; 1111// End fast-isel. 1112let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1113defm RLDICL_32 : MDForm_1r<30, 0, 1114 (outs gprc:$RA), 1115 (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), 1116 "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1117 []>, isPPC64; 1118defm RLDICR : MDForm_1r<30, 1, 1119 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1120 "rldicr", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1121 []>, isPPC64; 1122let isCodeGenOnly = 1 in 1123def RLDICR_32 : MDForm_1<30, 1, 1124 (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), 1125 "rldicr $RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1126 []>, isPPC64; 1127defm RLDIC : MDForm_1r<30, 2, 1128 (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), 1129 "rldic", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, 1130 []>, isPPC64; 1131 1132let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1133defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA), 1134 (ins g8rc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1135 "rlwinm", "$RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 1136 []>; 1137 1138defm RLWNM8 : MForm_1r<23, (outs g8rc:$RA), 1139 (ins g8rc:$RS, g8rc:$RB, u5imm:$MB, u5imm:$ME), 1140 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 1141 []>; 1142 1143// RLWIMI can be commuted if the rotate amount is zero. 1144let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1145defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA), 1146 (ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB, 1147 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 1148 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1149 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 1150 1151let isSelect = 1 in 1152def ISEL8 : AForm_4<31, 15, 1153 (outs g8rc:$RT), (ins g8rc_nox0:$RA, g8rc:$RB, crbitrc:$COND), 1154 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 1155 []>; 1156} // Interpretation64Bit 1157} // hasSideEffects = 0 1158} // End FXU Operations. 1159 1160def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1161def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1162 1163def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1164def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1165 1166def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1167def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1168 1169def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1170 1171def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1172def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1173def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1174def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1175 1176def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1177def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1178def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1179def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1180def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1181def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1182 1183def : InstAlias<"isellt $rT, $rA, $rB", 1184 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1185def : InstAlias<"iselgt $rT, $rA, $rB", 1186 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1187def : InstAlias<"iseleq $rT, $rA, $rB", 1188 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1189 1190def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1191def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1192 1193def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1194def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1195 1196def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1197def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1198 1199//Disable this alias on AIX for now because as does not support them. 1200let Predicates = [ModernAs] in { 1201 1202def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1203def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1204 1205def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1206def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1207 1208def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1209def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1210 1211def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1212def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1213 1214def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1215def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1216 1217def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1218def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1219 1220def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1221def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1222 1223def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1224def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1225 1226def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1227def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1228 1229def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1230def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1231 1232def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1233def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1234 1235def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1236def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1237 1238def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1239def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1240 1241def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1242def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1243 1244foreach SPRG = 0-3 in { 1245 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1246 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1247 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1248 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1249} 1250 1251def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1252def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1253 1254def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1255def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1256 1257def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1258 1259def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1260def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1261 1262} 1263 1264//===----------------------------------------------------------------------===// 1265// Load/Store instructions. 1266// 1267 1268 1269// Sign extending loads. 1270let PPC970_Unit = 2 in { 1271let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1272def LHA8: DForm_1<42, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1273 "lha $RST, $addr", IIC_LdStLHA, 1274 [(set i64:$RST, (sextloadi16 DForm:$addr))]>, 1275 PPC970_DGroup_Cracked, SExt32To64; 1276def LWA : DSForm_1<58, 2, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr), 1277 "lwa $RST, $addr", IIC_LdStLWA, 1278 [(set i64:$RST, 1279 (sextloadi32 DSForm:$addr))]>, isPPC64, 1280 PPC970_DGroup_Cracked, SExt32To64; 1281let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1282def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1283 "lhax $RST, $addr", IIC_LdStLHA, 1284 [(set i64:$RST, (sextloadi16 XForm:$addr))]>, 1285 PPC970_DGroup_Cracked, SExt32To64; 1286def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1287 "lwax $RST, $addr", IIC_LdStLHA, 1288 [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64, 1289 PPC970_DGroup_Cracked, SExt32To64; 1290// For fast-isel: 1291let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1292def LWA_32 : DSForm_1<58, 2, (outs gprc:$RST), (ins (memrix $D, $RA):$addr), 1293 "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64, 1294 PPC970_DGroup_Cracked, SExt32To64; 1295def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1296 "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64, 1297 PPC970_DGroup_Cracked, SExt32To64; 1298} // end fast-isel isCodeGenOnly 1299 1300// Update forms. 1301let mayLoad = 1, hasSideEffects = 0 in { 1302let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1303def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1304 (ins (memri $D, $RA):$addr), 1305 "lhau $RST, $addr", IIC_LdStLHAU, 1306 []>, RegConstraint<"$addr.reg = $ea_result">, 1307 NoEncode<"$ea_result">; 1308// NO LWAU! 1309 1310let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1311def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1312 (ins (memrr $RA, $RB):$addr), 1313 "lhaux $RST, $addr", IIC_LdStLHAUX, 1314 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1315 NoEncode<"$ea_result">; 1316def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1317 (ins (memrr $RA, $RB):$addr), 1318 "lwaux $RST, $addr", IIC_LdStLHAUX, 1319 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1320 NoEncode<"$ea_result">, isPPC64; 1321} 1322} 1323 1324let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1325// Zero extending loads. 1326let PPC970_Unit = 2 in { 1327def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1328 "lbz $RST, $addr", IIC_LdStLoad, 1329 [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1330 SExt32To64; 1331def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1332 "lhz $RST, $addr", IIC_LdStLoad, 1333 [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1334 SExt32To64; 1335def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins (memri $D, $RA):$addr), 1336 "lwz $RST, $addr", IIC_LdStLoad, 1337 [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64, 1338 ZExt32To64; 1339 1340def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1341 "lbzx $RST, $addr", IIC_LdStLoad, 1342 [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 1343 SExt32To64; 1344def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1345 "lhzx $RST, $addr", IIC_LdStLoad, 1346 [(set i64:$RST, (zextloadi16 XForm:$addr))]>, 1347 ZExt32To64, SExt32To64; 1348def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1349 "lwzx $RST, $addr", IIC_LdStLoad, 1350 [(set i64:$RST, (zextloadi32 XForm:$addr))]>, 1351 ZExt32To64; 1352 1353 1354// Update forms. 1355let mayLoad = 1, hasSideEffects = 0 in { 1356def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1357 (ins (memri $D, $RA):$addr), 1358 "lbzu $RST, $addr", IIC_LdStLoadUpd, 1359 []>, RegConstraint<"$addr.reg = $ea_result">, 1360 NoEncode<"$ea_result">; 1361def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1362 (ins (memri $D, $RA):$addr), 1363 "lhzu $RST, $addr", IIC_LdStLoadUpd, 1364 []>, RegConstraint<"$addr.reg = $ea_result">, 1365 NoEncode<"$ea_result">; 1366def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1367 (ins (memri $D, $RA):$addr), 1368 "lwzu $RST, $addr", IIC_LdStLoadUpd, 1369 []>, RegConstraint<"$addr.reg = $ea_result">, 1370 NoEncode<"$ea_result">; 1371 1372def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1373 (ins (memrr $RA, $RB):$addr), 1374 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 1375 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1376 NoEncode<"$ea_result">; 1377def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1378 (ins (memrr $RA, $RB):$addr), 1379 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 1380 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1381 NoEncode<"$ea_result">; 1382def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1383 (ins (memrr $RA, $RB):$addr), 1384 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 1385 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1386 NoEncode<"$ea_result">; 1387} 1388} 1389} // Interpretation64Bit 1390 1391 1392// Full 8-byte loads. 1393let PPC970_Unit = 2 in { 1394def LD : DSForm_1<58, 0, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr), 1395 "ld $RST, $addr", IIC_LdStLD, 1396 [(set i64:$RST, (load DSForm:$addr))]>, isPPC64; 1397// The following four definitions are selected for small code model only. 1398// Otherwise, we need to create two instructions to form a 32-bit offset, 1399// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1400def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1401 "#LDtoc", 1402 [(set i64:$rD, 1403 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1404def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1405 "#LDtocJTI", 1406 [(set i64:$rD, 1407 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1408def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1409 "#LDtocCPT", 1410 [(set i64:$rD, 1411 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1412def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1413 "#LDtocCPT", 1414 [(set i64:$rD, 1415 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1416 1417def LDX : XForm_1_memOp<31, 21, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1418 "ldx $RST, $addr", IIC_LdStLD, 1419 [(set i64:$RST, (load XForm:$addr))]>, isPPC64; 1420 1421let Predicates = [IsISA2_06] in { 1422def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1423 "ldbrx $RST, $addr", IIC_LdStLoad, 1424 [(set i64:$RST, (PPClbrx ForceXForm:$addr, i64))]>, isPPC64; 1425} 1426 1427let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1428def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1429 "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64; 1430def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), 1431 "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64; 1432} 1433 1434let mayLoad = 1, hasSideEffects = 0 in { 1435def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1436 (ins (memrix $D, $RA):$addr), 1437 "ldu $RST, $addr", IIC_LdStLDU, 1438 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1439 NoEncode<"$ea_result">; 1440 1441def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), 1442 (ins (memrr $RA, $RB):$addr), 1443 "ldux $RST, $addr", IIC_LdStLDUX, 1444 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1445 NoEncode<"$ea_result">, isPPC64; 1446} 1447 1448let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1449// Full 16-byte load. 1450// Early clobber $RTp to avoid assigned to the same register as RA. 1451// TODO: Add scheduling info. 1452def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1453 (outs g8prc:$RTp), 1454 (ins (memrix16 $DQ, $RA):$addr), 1455 "lq $RTp, $addr", IIC_LdStLQ, 1456 []>, 1457 RegConstraint<"@earlyclobber $RTp">, 1458 isPPC64; 1459// We don't really have LQX in the ISA, make a pseudo one so that we can 1460// handle x-form during isel. Make it pre-ra may expose 1461// oppotunities to some opts(CSE, LICM and etc.) for the result of adding 1462// RA and RB. 1463def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), 1464 (ins memrr:$src), "#LQX_PSEUDO", []>; 1465 1466def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1467 "#RESTORE_QUADWORD", []>; 1468} 1469 1470} 1471 1472def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src), 1473 (SPLIT_QUADWORD (LQ memrix16:$src))>; 1474 1475def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src), 1476 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>; 1477 1478// Support for medium and large code model. 1479let hasSideEffects = 0 in { 1480let isReMaterializable = 1 in { 1481def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1482 "#ADDIStocHA8", []>, isPPC64; 1483def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1484 "#ADDItocL", []>, isPPC64; 1485} 1486 1487// Local Data Transform 1488def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1489 "#ADDItoc8", 1490 [(set i64:$rD, 1491 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1492 1493let mayLoad = 1 in 1494def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1495 "#LDtocL", []>, isPPC64; 1496} 1497 1498// Support for thread-local storage. 1499def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1500 "#ADDISgotTprelHA", 1501 [(set i64:$rD, 1502 (PPCaddisGotTprelHA i64:$reg, 1503 tglobaltlsaddr:$disp))]>, 1504 isPPC64; 1505def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1506 "#LDgotTprelL", 1507 [(set i64:$rD, 1508 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1509 isPPC64; 1510 1511let Defs = [CR7], Itinerary = IIC_LdStSync in 1512def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1513 1514def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1515 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1516def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1517 "#ADDIStlsgdHA", 1518 [(set i64:$rD, 1519 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1520 isPPC64; 1521def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1522 "#ADDItlsgdL", 1523 [(set i64:$rD, 1524 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1525 isPPC64; 1526 1527class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1528 asmstr, 1529 [(set i64:$rD, 1530 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1531 isPPC64; 1532class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1533 asmstr, 1534 [(set i64:$rD, 1535 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1536 isPPC64; 1537 1538let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1539// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1540// explicitly defined when this op is created, so not mentioned here. 1541// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1542// correct because the branch select pass is relying on it. 1543let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1544def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1545let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1546def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1547 1548// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1549// explicitly defined when this op is created, so not mentioned here. 1550let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1551def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1552let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1553def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1554 1555// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1556// offset and region handle respectively. The call is not followed by a nop 1557// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1558// manual mentions this exact set of registers as the clobbered set, others 1559// are guaranteed not to be clobbered. 1560let Defs = [X0,X4,X5,X11,LR8,CR0] in 1561def GETtlsADDR64AIX : 1562 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1563 "GETtlsADDR64AIX", 1564 [(set i64:$rD, 1565 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1566} 1567 1568// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1569// are true defines while the rest of the Defs are clobbers. 1570let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1571 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1572 in 1573def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1574 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1575 "#ADDItlsgdLADDR", 1576 [(set i64:$rD, 1577 (PPCaddiTlsgdLAddr i64:$reg, 1578 tglobaltlsaddr:$disp, 1579 tglobaltlsaddr:$sym))]>, 1580 isPPC64; 1581def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1582 "#ADDIStlsldHA", 1583 [(set i64:$rD, 1584 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1585 isPPC64; 1586def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1587 "#ADDItlsldL", 1588 [(set i64:$rD, 1589 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1590 isPPC64; 1591// This pseudo is expanded to two copies to put the variable offset in R4 and 1592// the region handle in R3 and GETtlsADDR64AIX. 1593def TLSGDAIX8 : 1594 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1595 "#TLSGDAIX8", 1596 [(set i64:$rD, 1597 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1598// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1599// are true defines, while the rest of the Defs are clobbers. 1600let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1601 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1602 in 1603def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1604 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1605 "#ADDItlsldLADDR", 1606 [(set i64:$rD, 1607 (PPCaddiTlsldLAddr i64:$reg, 1608 tglobaltlsaddr:$disp, 1609 tglobaltlsaddr:$sym))]>, 1610 isPPC64; 1611def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1612 "#ADDISdtprelHA", 1613 [(set i64:$rD, 1614 (PPCaddisDtprelHA i64:$reg, 1615 tglobaltlsaddr:$disp))]>, 1616 isPPC64; 1617def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1618 "#ADDIdtprelL", 1619 [(set i64:$rD, 1620 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1621 isPPC64; 1622def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1623 "#PADDIdtprel", 1624 [(set i64:$rD, 1625 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1626 isPPC64; 1627 1628let PPC970_Unit = 2 in { 1629let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1630// Truncating stores. 1631def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr), 1632 "stb $RST, $addr", IIC_LdStStore, 1633 [(truncstorei8 i64:$RST, DForm:$addr)]>; 1634def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr), 1635 "sth $RST, $addr", IIC_LdStStore, 1636 [(truncstorei16 i64:$RST, DForm:$addr)]>; 1637def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr), 1638 "stw $RST, $addr", IIC_LdStStore, 1639 [(truncstorei32 i64:$RST, DForm:$addr)]>; 1640def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1641 "stbx $RST, $addr", IIC_LdStStore, 1642 [(truncstorei8 i64:$RST, XForm:$addr)]>, 1643 PPC970_DGroup_Cracked; 1644def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1645 "sthx $RST, $addr", IIC_LdStStore, 1646 [(truncstorei16 i64:$RST, XForm:$addr)]>, 1647 PPC970_DGroup_Cracked; 1648def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1649 "stwx $RST, $addr", IIC_LdStStore, 1650 [(truncstorei32 i64:$RST, XForm:$addr)]>, 1651 PPC970_DGroup_Cracked; 1652} // Interpretation64Bit 1653 1654// Normal 8-byte stores. 1655def STD : DSForm_1<62, 0, (outs), (ins g8rc:$RST, (memrix $D, $RA):$addr), 1656 "std $RST, $addr", IIC_LdStSTD, 1657 [(store i64:$RST, DSForm:$addr)]>, isPPC64; 1658def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1659 "stdx $RST, $addr", IIC_LdStSTD, 1660 [(store i64:$RST, XForm:$addr)]>, isPPC64, 1661 PPC970_DGroup_Cracked; 1662 1663let Predicates = [IsISA2_06] in { 1664def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1665 "stdbrx $RST, $addr", IIC_LdStStore, 1666 [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64, 1667 PPC970_DGroup_Cracked; 1668} 1669 1670let mayStore = 1, hasNoSchedulingInfo = 1 in { 1671// Normal 16-byte stores. 1672// TODO: Add scheduling info. 1673def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, (memrix $D, $RA):$addr), 1674 "stq $RST, $addr", IIC_LdStSTQ, 1675 []>, isPPC64; 1676 1677def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), 1678 (ins g8prc:$RSp, memrr:$dst), 1679 "#STQX_PSEUDO", []>; 1680 1681def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1682 "#SPILL_QUADWORD", []>; 1683} 1684 1685} 1686 1687def BUILD_QUADWORD : PPCPostRAExpPseudo< 1688 (outs g8prc:$RTp), 1689 (ins g8rc:$lo, g8rc:$hi), 1690 "#BUILD_QUADWORD", []>; 1691 1692def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst), 1693 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; 1694 1695def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), 1696 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; 1697 1698// Stores with Update (pre-inc). 1699let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1700let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1701def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), 1702 "stbu $RST, $addr", IIC_LdStSTU, []>, 1703 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; 1704def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), 1705 "sthu $RST, $addr", IIC_LdStSTU, []>, 1706 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; 1707def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), 1708 "stwu $RST, $addr", IIC_LdStSTU, []>, 1709 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; 1710 1711def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1712 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1713 "stbux $RST, $addr", IIC_LdStSTUX, []>, 1714 RegConstraint<"$addr.ptrreg = $ea_res">, 1715 NoEncode<"$ea_res">, 1716 PPC970_DGroup_Cracked; 1717def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1718 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1719 "sthux $RST, $addr", IIC_LdStSTUX, []>, 1720 RegConstraint<"$addr.ptrreg = $ea_res">, 1721 NoEncode<"$ea_res">, 1722 PPC970_DGroup_Cracked; 1723def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1724 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1725 "stwux $RST, $addr", IIC_LdStSTUX, []>, 1726 RegConstraint<"$addr.ptrreg = $ea_res">, 1727 NoEncode<"$ea_res">, 1728 PPC970_DGroup_Cracked; 1729} // Interpretation64Bit 1730 1731def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1732 (ins g8rc:$RST, (memrix $D, $RA):$addr), 1733 "stdu $RST, $addr", IIC_LdStSTU, []>, 1734 RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">, 1735 isPPC64; 1736 1737def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1738 (ins g8rc:$RST, (memrr $RA, $RB):$addr), 1739 "stdux $RST, $addr", IIC_LdStSTUX, []>, 1740 RegConstraint<"$addr.ptrreg = $ea_res">, 1741 NoEncode<"$ea_res">, 1742 PPC970_DGroup_Cracked, isPPC64; 1743} 1744 1745// Patterns to match the pre-inc stores. We can't put the patterns on 1746// the instruction definitions directly as ISel wants the address base 1747// and offset to be separate operands, not a single complex operand. 1748def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1749 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1750def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1751 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1752def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1753 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1754def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1755 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1756 1757def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1758 (STBUX8 $rS, $ptrreg, $ptroff)>; 1759def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1760 (STHUX8 $rS, $ptrreg, $ptroff)>; 1761def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1762 (STWUX8 $rS, $ptrreg, $ptroff)>; 1763def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1764 (STDUX $rS, $ptrreg, $ptroff)>; 1765 1766 1767//===----------------------------------------------------------------------===// 1768// Floating point instructions. 1769// 1770 1771 1772let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1773 Uses = [RM] in { // FPU Operations. 1774defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB), 1775 "fcfid", "$RST, $RB", IIC_FPGeneral, 1776 [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64; 1777defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB), 1778 "fctid", "$RST, $RB", IIC_FPGeneral, 1779 []>, isPPC64; 1780defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB), 1781 "fctidu", "$RST, $RB", IIC_FPGeneral, 1782 []>, isPPC64; 1783defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB), 1784 "fctidz", "$RST, $RB", IIC_FPGeneral, 1785 [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64; 1786 1787defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB), 1788 "fcfidu", "$RST, $RB", IIC_FPGeneral, 1789 [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64; 1790defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB), 1791 "fcfids", "$RST, $RB", IIC_FPGeneral, 1792 [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64; 1793defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB), 1794 "fcfidus", "$RST, $RB", IIC_FPGeneral, 1795 [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64; 1796defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB), 1797 "fctiduz", "$RST, $RB", IIC_FPGeneral, 1798 [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64; 1799defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB), 1800 "fctiwuz", "$RST, $RB", IIC_FPGeneral, 1801 [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64; 1802} 1803 1804// These instructions store a hash computed from the value of the link register 1805// and the value of the stack pointer. 1806let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1807def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs), 1808 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1809 "hashst $RB, $addr", IIC_IntGeneral, []>; 1810def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs), 1811 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1812 "hashstp $RB, $addr", IIC_IntGeneral, []>; 1813} 1814 1815// These instructions check a hash computed from the value of the link register 1816// and the value of the stack pointer. The hasSideEffects flag is needed as the 1817// instruction may TRAP if the hash does not match the hash stored at the 1818// specified address. 1819let mayLoad = 1, hasSideEffects = 1, 1820 Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1821def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs), 1822 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1823 "hashchk $RB, $addr", IIC_IntGeneral, []>; 1824def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs), 1825 (ins g8rc:$RB, (memrihash $D, $RA):$addr), 1826 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 1827} 1828 1829let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in 1830def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT), 1831 (ins g8rc:$RA, g8rc:$RB, u2imm:$CY), 1832 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, 1833 [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB, 1834 timm:$CY))]>; 1835 1836//===----------------------------------------------------------------------===// 1837// Instruction Patterns 1838// 1839 1840// Extensions and truncates to/from 32-bit regs. 1841def : Pat<(i64 (zext i32:$in)), 1842 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1843 0, 32)>; 1844def : Pat<(i64 (anyext i32:$in)), 1845 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1846def : Pat<(i32 (trunc i64:$in)), 1847 (EXTRACT_SUBREG $in, sub_32)>; 1848 1849// Implement the 'not' operation with the NOR instruction. 1850// (we could use the default xori pattern, but nor has lower latency on some 1851// cores (such as the A2)). 1852def i64not : OutPatFrag<(ops node:$in), 1853 (NOR8 $in, $in)>; 1854def : Pat<(not i64:$in), 1855 (i64not $in)>; 1856 1857// Extending loads with i64 targets. 1858def : Pat<(zextloadi1 DForm:$src), 1859 (LBZ8 DForm:$src)>; 1860def : Pat<(zextloadi1 XForm:$src), 1861 (LBZX8 XForm:$src)>; 1862def : Pat<(extloadi1 DForm:$src), 1863 (LBZ8 DForm:$src)>; 1864def : Pat<(extloadi1 XForm:$src), 1865 (LBZX8 XForm:$src)>; 1866def : Pat<(extloadi8 DForm:$src), 1867 (LBZ8 DForm:$src)>; 1868def : Pat<(extloadi8 XForm:$src), 1869 (LBZX8 XForm:$src)>; 1870def : Pat<(extloadi16 DForm:$src), 1871 (LHZ8 DForm:$src)>; 1872def : Pat<(extloadi16 XForm:$src), 1873 (LHZX8 XForm:$src)>; 1874def : Pat<(extloadi32 DForm:$src), 1875 (LWZ8 DForm:$src)>; 1876def : Pat<(extloadi32 XForm:$src), 1877 (LWZX8 XForm:$src)>; 1878 1879// Standard shifts. These are represented separately from the real shifts above 1880// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1881// amounts. 1882def : Pat<(sra i64:$rS, i32:$rB), 1883 (SRAD $rS, $rB)>; 1884def : Pat<(srl i64:$rS, i32:$rB), 1885 (SRD $rS, $rB)>; 1886def : Pat<(shl i64:$rS, i32:$rB), 1887 (SLD $rS, $rB)>; 1888 1889// SUBFIC 1890def : Pat<(sub imm64SExt16:$imm, i64:$in), 1891 (SUBFIC8 $in, imm:$imm)>; 1892 1893// SHL/SRL 1894def : Pat<(shl i64:$in, (i32 imm:$imm)), 1895 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1896def : Pat<(srl i64:$in, (i32 imm:$imm)), 1897 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1898 1899// ROTL 1900def : Pat<(rotl i64:$in, i32:$sh), 1901 (RLDCL $in, $sh, 0)>; 1902def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1903 (RLDICL $in, imm:$imm, 0)>; 1904 1905// Hi and Lo for Darwin Global Addresses. 1906def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1907def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1908def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1909def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1910def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1911def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1912def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1913def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1914def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1915 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1916def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1917 (ADDI8 $in, tglobaltlsaddr:$g)>; 1918def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1919 (ADDIS8 $in, tglobaladdr:$g)>; 1920def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1921 (ADDIS8 $in, tconstpool:$g)>; 1922def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1923 (ADDIS8 $in, tjumptable:$g)>; 1924def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1925 (ADDIS8 $in, tblockaddress:$g)>; 1926 1927// AIX 64-bit small code model TLS access. 1928// This is used for global dynamic accesses when loading the region handle and 1929// variable offset, and also for local-exec accesses to load the offset of a 1930// TLS variable from the TOC, prior to adding it to r13. 1931def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1932 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1933 1934// The following pattern matches 64-bit local- and initial-exec TLS accesses on AIX. 1935// PPCaddTls is used in local- and initial-exec accesses in order to: 1936// - Get the address of a variable (adding the variable offset to the thread 1937// pointer in r13). 1938// - Create an opportunity to optimize the user of the loaded address. 1939def : Pat<(PPCaddTls i64:$in, i64:$addr), 1940 (ADD8TLS $in, $addr)>; 1941 1942// 64-bits atomic loads and stores 1943def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1944def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1945 1946def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>; 1947def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>; 1948 1949let Predicates = [IsISA3_0, In64BitMode] in { 1950def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1951 (i64 (SETB8 (CMPEQB $a, $b)))>; 1952def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1953 (i64 (SETB8 (CMPD $a, $b)))>; 1954def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1955 (i64 (MADDHD $a, $b, $c))>; 1956def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1957 (i64 (MADDHDU $a, $b, $c))>; 1958def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1959 (i64 (MADDLD8 $a, $b, $c))>; 1960} 1961 1962let Predicates = [In64BitMode] in { 1963def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1964 (i64 (MULHD $a, $b))>; 1965def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1966 (i64 (MULHDU $a, $b))>; 1967def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1968 (LDBRX ForceXForm:$ptr)>; 1969def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1970 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1971} 1972 1973def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1974 (i64 (CMPB8 $a, $b))>; 1975 1976let Predicates = [IsISA3_0] in { 1977// DARN (deliver random number) 1978// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1979def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1980def : Pat<(int_ppc_darn), (DARN 1)>; 1981def : Pat<(int_ppc_darnraw), (DARN 2)>; 1982 1983class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1984 InstrItinClass itin, list<dag> pattern> 1985 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L), 1986 !strconcat(opc, " $RA, $RB"), itin, pattern>{ 1987 let L = 1; 1988} 1989 1990class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1991 InstrItinClass itin, list<dag> pattern> 1992 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L), 1993 !strconcat(opc, " $RA, $RB, $L"), itin, pattern>; 1994 1995let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1996def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1997def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1998} 1999 2000// SLB Invalidate Entry Global 2001def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RST, gprc:$RB), 2002 "slbieg $RST, $RB", IIC_SprSLBIEG, []>; 2003// SLB Synchronize 2004def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 2005 2006} // IsISA3_0 2007 2008def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 2009 (STDCX g8rc:$A, ForceXForm:$dst)>; 2010def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8), 2011 (STDCX g8rc:$A, ForceXForm:$dst)>; 2012 2013def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 2014 (MFSPR8 $SPR)>; 2015def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 2016 (MTSPR8 $SPR, $RT)>; 2017