xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstr64Bit.td (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e)
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the PowerPC 64-bit instructions.  These patterns are used
10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// 64-bit operands.
16//
17def s16imm64 : Operand<i64> {
18  let PrintMethod = "printS16ImmOperand";
19  let EncoderMethod = "getImm16Encoding";
20  let ParserMatchClass = PPCS16ImmAsmOperand;
21  let DecoderMethod = "decodeSImmOperand<16>";
22  let OperandType = "OPERAND_IMMEDIATE";
23}
24def u16imm64 : Operand<i64> {
25  let PrintMethod = "printU16ImmOperand";
26  let EncoderMethod = "getImm16Encoding";
27  let ParserMatchClass = PPCU16ImmAsmOperand;
28  let DecoderMethod = "decodeUImmOperand<16>";
29  let OperandType = "OPERAND_IMMEDIATE";
30}
31def s17imm64 : Operand<i64> {
32  // This operand type is used for addis/lis to allow the assembler parser
33  // to accept immediates in the range -65536..65535 for compatibility with
34  // the GNU assembler.  The operand is treated as 16-bit otherwise.
35  let PrintMethod = "printS16ImmOperand";
36  let EncoderMethod = "getImm16Encoding";
37  let ParserMatchClass = PPCS17ImmAsmOperand;
38  let DecoderMethod = "decodeSImmOperand<16>";
39  let OperandType = "OPERAND_IMMEDIATE";
40}
41def tocentry : Operand<iPTR> {
42  let MIOperandInfo = (ops i64imm:$imm);
43}
44def tlsreg : Operand<i64> {
45  let EncoderMethod = "getTLSRegEncoding";
46  let ParserMatchClass = PPCTLSRegOperand;
47}
48def tlsgd : Operand<i64> {}
49def tlscall : Operand<i64> {
50  let PrintMethod = "printTLSCall";
51  let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
52  let EncoderMethod = "getTLSCallEncoding";
53}
54
55//===----------------------------------------------------------------------===//
56// 64-bit transformation functions.
57//
58
59def SHL64 : SDNodeXForm<imm, [{
60  // Transformation function: 63 - imm
61  return getI32Imm(63 - N->getZExtValue(), SDLoc(N));
62}]>;
63
64def SRL64 : SDNodeXForm<imm, [{
65  // Transformation function: 64 - imm
66  return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N))
67                           : getI32Imm(0, SDLoc(N));
68}]>;
69
70
71//===----------------------------------------------------------------------===//
72// Calls.
73//
74
75let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
77  let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in
78    def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
79                            [(retglue)]>, Requires<[In64BitMode]>;
80  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
81    let isPredicable = 1 in
82      def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
83                               []>,
84          Requires<[In64BitMode]>;
85    def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
86                              "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
87                              []>,
88        Requires<[In64BitMode]>;
89
90    def BCCTR8  : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
91                               "bcctr 12, $BI, 0", IIC_BrB, []>,
92        Requires<[In64BitMode]>;
93    def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
94                               "bcctr 4, $BI, 0", IIC_BrB, []>,
95        Requires<[In64BitMode]>;
96  }
97}
98
99let Defs = [LR8] in
100  def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
101                    PPC970_Unit_BRU;
102
103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
104  let Defs = [CTR8], Uses = [CTR8] in {
105    def BDZ8  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),
106                        "bdz $BD">;
107    def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),
108                        "bdnz $BD">;
109  }
110
111  let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
112    def BDZLR8  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
113                              "bdzlr", IIC_BrB, []>;
114    def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
115                              "bdnzlr", IIC_BrB, []>;
116  }
117}
118
119
120
121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
122  // Convenient aliases for call instructions
123  let Uses = [RM] in {
124    def BL8  : IForm<18, 0, 1, (outs), (ins calltarget:$LI),
125                     "bl $LI", IIC_BrB, []>;  // See Pat patterns below.
126
127    def BL8_TLS  : IForm<18, 0, 1, (outs), (ins tlscall:$LI),
128                         "bl $LI", IIC_BrB, []>;
129
130    def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),
131                     "bla $LI", IIC_BrB, [(PPCcall (i64 imm:$LI))]>;
132  }
133  let Uses = [RM], isCodeGenOnly = 1 in {
134    def BL8_NOP  : IForm_and_DForm_4_zero<18, 0, 1, 24,
135                             (outs), (ins calltarget:$LI),
136                             "bl $LI\n\tnop", IIC_BrB, []>;
137
138    def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
139                                  (outs), (ins tlscall:$LI),
140                                  "bl $LI\n\tnop", IIC_BrB, []>;
141
142    def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
143                             (outs), (ins abscalltarget:$LI),
144                             "bla $LI\n\tnop", IIC_BrB,
145                             [(PPCcall_nop (i64 imm:$LI))]>;
146    let Predicates = [PCRelativeMemops] in {
147      // BL8_NOTOC means that the caller does not use the TOC pointer and if
148      // it does use R2 then it is just a caller saved register. Therefore it is
149      // safe to emit only the bl and not the nop for this instruction. The
150      // linker will not try to restore R2 after the call.
151      def BL8_NOTOC : IForm<18, 0, 1, (outs),
152                            (ins calltarget:$LI),
153                            "bl $LI", IIC_BrB, []>;
154      def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs),
155                                (ins tlscall:$LI),
156                                "bl $LI", IIC_BrB, []>;
157    }
158  }
159  let Uses = [CTR8, RM] in {
160    let isPredicable = 1 in
161      def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
162                                "bctrl", IIC_BrB, [(PPCbctrl)]>,
163                   Requires<[In64BitMode]>;
164
165    let isCodeGenOnly = 1 in {
166      def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
167                                 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
168                                 []>,
169          Requires<[In64BitMode]>;
170
171      def BCCTRL8  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
172                                  "bcctrl 12, $BI, 0", IIC_BrB, []>,
173          Requires<[In64BitMode]>;
174      def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
175                                  "bcctrl 4, $BI, 0", IIC_BrB, []>,
176          Requires<[In64BitMode]>;
177    }
178  }
179}
180
181let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,
182    isCodeGenOnly = 1, Uses = [RM] in {
183  // Convenient aliases for call instructions
184  def BL8_RM  : IForm<18, 0, 1, (outs), (ins calltarget:$LI),
185                      "bl $LI", IIC_BrB, []>;  // See Pat patterns below.
186
187  def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI),
188                      "bla $LI", IIC_BrB, [(PPCcall_rm (i64 imm:$LI))]>;
189  def BL8_NOP_RM  : IForm_and_DForm_4_zero<18, 0, 1, 24,
190                           (outs), (ins calltarget:$LI),
191                           "bl $LI\n\tnop", IIC_BrB, []>;
192
193  def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24,
194                           (outs), (ins abscalltarget:$LI),
195                           "bla $LI\n\tnop", IIC_BrB,
196                           [(PPCcall_nop_rm (i64 imm:$LI))]>;
197  let Predicates = [PCRelativeMemops] in {
198    // BL8_NOTOC means that the caller does not use the TOC pointer and if
199    // it does use R2 then it is just a caller saved register. Therefore it is
200    // safe to emit only the bl and not the nop for this instruction. The
201    // linker will not try to restore R2 after the call.
202    def BL8_NOTOC_RM : IForm<18, 0, 1, (outs),
203                             (ins calltarget:$LI),
204                             "bl $LI", IIC_BrB, []>;
205  }
206  let Uses = [CTR8, RM] in {
207    let isPredicable = 1 in
208      def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
209                                   "bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
210                   Requires<[In64BitMode]>;
211  }
212}
213
214let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
215    Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
216  def BCTRL8_LDinto_toc :
217    XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
218                              (ins (memrix $D, $RA):$src),
219                              "bctrl\n\tld 2, $src", IIC_BrB,
220                              [(PPCbctrl_load_toc iaddrX4:$src)]>,
221    Requires<[In64BitMode]>;
222}
223
224let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
225    Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in {
226  def BCTRL8_LDinto_toc_RM :
227    XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
228                              (ins (memrix $D, $RA):$src),
229                              "bctrl\n\tld 2, $src", IIC_BrB,
230                              [(PPCbctrl_load_toc_rm iaddrX4:$src)]>,
231    Requires<[In64BitMode]>;
232}
233
234} // Interpretation64Bit
235
236// FIXME: Duplicating this for the asm parser should be unnecessary, but the
237// previous definition must be marked as CodeGen only to prevent decoding
238// conflicts.
239let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in
240let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
241def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$LI),
242                     "bl $LI", IIC_BrB, []>;
243
244// Calls
245def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
246          (BL8 tglobaladdr:$dst)>;
247def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
248          (BL8_NOP tglobaladdr:$dst)>;
249
250def : Pat<(PPCcall (i64 texternalsym:$dst)),
251          (BL8 texternalsym:$dst)>;
252def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
253          (BL8_NOP texternalsym:$dst)>;
254
255def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)),
256          (BL8_NOTOC tglobaladdr:$dst)>;
257def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)),
258          (BL8_NOTOC texternalsym:$dst)>;
259
260def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)),
261          (BL8_RM tglobaladdr:$dst)>;
262def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)),
263          (BL8_NOP_RM tglobaladdr:$dst)>;
264
265def : Pat<(PPCcall_rm (i64 texternalsym:$dst)),
266          (BL8_RM texternalsym:$dst)>;
267def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)),
268          (BL8_NOP_RM texternalsym:$dst)>;
269
270def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)),
271          (BL8_NOTOC_RM tglobaladdr:$dst)>;
272def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)),
273          (BL8_NOTOC_RM texternalsym:$dst)>;
274
275// Calls for AIX
276def : Pat<(PPCcall (i64 mcsym:$dst)),
277          (BL8 mcsym:$dst)>;
278def : Pat<(PPCcall_nop (i64 mcsym:$dst)),
279          (BL8_NOP mcsym:$dst)>;
280
281def : Pat<(PPCcall_rm (i64 mcsym:$dst)),
282          (BL8_RM mcsym:$dst)>;
283def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)),
284          (BL8_NOP_RM mcsym:$dst)>;
285
286// Atomic operations
287// FIXME: some of these might be used with constant operands. This will result
288// in constant materialization instructions that may be redundant. We currently
289// clean this up in PPCMIPeephole with calls to
290// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
291// in the first place.
292let Defs = [CR0] in {
293  def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo<
294    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
295    [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>;
296  def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo<
297    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
298    [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>;
299  def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo<
300    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
301    [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>;
302  def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo<
303    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
304    [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>;
305  def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo<
306    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
307    [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>;
308  def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo<
309    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
310    [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>;
311  def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo<
312    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",
313    [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>;
314  def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo<
315    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",
316    [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>;
317  def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo<
318    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",
319    [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>;
320  def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo<
321    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",
322    [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>;
323
324  def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo<
325    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
326    [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>;
327
328  def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo<
329    (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
330    [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>;
331}
332
333// Instructions to support atomic operations
334let mayLoad = 1, hasSideEffects = 0 in {
335def LDARX : XForm_1_memOp<31,  84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
336                          "ldarx $RST, $addr", IIC_LdStLDARX, []>;
337// TODO: Add scheduling info.
338let hasNoSchedulingInfo = 1 in
339def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
340                          "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64;
341
342// Instruction to support lock versions of atomics
343// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
344def LDARXL : XForm_1<31,  84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
345                     "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm;
346// TODO: Add scheduling info.
347let hasNoSchedulingInfo = 1 in
348// FIXME: We have to seek a way to remove isRecordForm since
349// LQARXL is not really altering CR0.
350def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
351                     "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>,
352                     isPPC64, isRecordForm;
353
354let hasExtraDefRegAllocReq = 1 in
355def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB),
356                         "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64,
357           Requires<[IsISA3_0]>;
358}
359
360let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
361def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
362                          "stdcx. $RST, $addr", IIC_LdStSTDCX, []>, isRecordForm;
363// TODO: Add scheduling info.
364let hasNoSchedulingInfo = 1 in
365def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr),
366                          "stqcx. $RST, $addr", IIC_LdStSTQCX, []>,
367                          isPPC64, isRecordForm;
368}
369
370def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi),
371                                             (ins g8prc:$src),
372                                             "#SPLIT_QUADWORD", []>;
373class AtomicRMW128<string asmstr>
374  : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch),
375                       (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi),
376                       asmstr, []>;
377// We have to keep values in MI's uses during LL/SC looping as they are,
378// so set both $RTp and $scratch earlyclobber.
379let mayStore = 1, mayLoad = 1,
380    Defs = [CR0],
381    Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in {
382// Atomic pseudo instructions expanded post-ra.
383def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">;
384def ATOMIC_LOAD_ADD_I128  : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">;
385def ATOMIC_LOAD_SUB_I128  : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">;
386def ATOMIC_LOAD_AND_I128  : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">;
387def ATOMIC_LOAD_XOR_I128  : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">;
388def ATOMIC_LOAD_OR_I128   : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">;
389def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">;
390
391def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo<
392                              (outs g8prc:$RTp, g8prc:$scratch),
393                              (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi,
394                                   g8rc:$new_lo, g8rc:$new_hi),
395                              "#ATOMIC_CMP_SWAP_I128", []>;
396}
397
398def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr,
399                                      i64:$incr_lo,
400                                      i64:$incr_hi),
401          (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr,
402                                                g8rc:$incr_lo,
403                                                g8rc:$incr_hi))>;
404def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr,
405                                      i64:$incr_lo,
406                                      i64:$incr_hi),
407          (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr,
408                                                g8rc:$incr_lo,
409                                                g8rc:$incr_hi))>;
410def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr,
411                                      i64:$incr_lo,
412                                      i64:$incr_hi),
413          (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr,
414                                                g8rc:$incr_lo,
415                                                g8rc:$incr_hi))>;
416def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr,
417                                      i64:$incr_lo,
418                                      i64:$incr_hi),
419          (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr,
420                                                g8rc:$incr_lo,
421                                                g8rc:$incr_hi))>;
422def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr,
423                                       i64:$incr_lo,
424                                       i64:$incr_hi),
425          (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr,
426                                                 g8rc:$incr_lo,
427                                                 g8rc:$incr_hi))>;
428def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr,
429                                     i64:$incr_lo,
430                                     i64:$incr_hi),
431          (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr,
432                                               g8rc:$incr_lo,
433                                               g8rc:$incr_hi))>;
434def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr,
435                                       i64:$incr_lo,
436                                       i64:$incr_hi),
437          (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr,
438                                            g8rc:$incr_lo,
439                                            g8rc:$incr_hi))>;
440def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr,
441                                i64:$cmp_lo,
442                                i64:$cmp_hi,
443                                i64:$new_lo,
444                                i64:$new_hi),
445          (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128
446                           memrr:$ptr,
447                           g8rc:$cmp_lo,
448                           g8rc:$cmp_hi,
449                           g8rc:$new_lo,
450                           g8rc:$new_hi))>;
451
452let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
453def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB),
454                          "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64,
455            Requires<[IsISA3_0]>;
456
457let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
458let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
459def TCRETURNdi8 :PPCEmitTimePseudo< (outs),
460                        (ins calltarget:$dst, i32imm:$offset),
461                 "#TC_RETURNd8 $dst $offset",
462                 []>;
463
464let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
465def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
466                 "#TC_RETURNa8 $func $offset",
467                 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
468
469let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
470def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
471                 "#TC_RETURNr8 $dst $offset",
472                 []>;
473
474let hasSideEffects = 0 in {
475let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
476    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
477def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
478                             []>,
479    Requires<[In64BitMode]>;
480
481let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
482    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
483def TAILB8   : IForm<18, 0, 0, (outs), (ins calltarget:$LI),
484                  "b $LI", IIC_BrB,
485                  []>;
486
487let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
488    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
489def TAILBA8   : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI),
490                  "ba $LI", IIC_BrB,
491                  []>;
492}
493} // Interpretation64Bit
494
495def : Pat<(PPCtc_return (i64 tglobaladdr:$dst),  imm:$imm),
496          (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
497
498def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
499          (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
500
501def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
502          (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
503
504
505// 64-bit CR instructions
506let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
507let hasSideEffects = 0 in {
508// mtocrf's input needs to be prepared by shifting by an amount dependent
509// on the cr register selected. Thus, post-ra anti-dep breaking must not
510// later change that register assignment.
511let hasExtraDefRegAllocReq = 1 in {
512def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$RST),
513                        "mtocrf $FXM, $RST", IIC_BrMCRX>,
514            PPC970_DGroup_First, PPC970_Unit_CRU;
515
516// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
517// is dependent on the cr fields being set.
518def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$RST),
519                      "mtcrf $FXM, $RST", IIC_BrMCRX>,
520            PPC970_MicroCode, PPC970_Unit_CRU;
521} // hasExtraDefRegAllocReq = 1
522
523// mfocrf's input needs to be prepared by shifting by an amount dependent
524// on the cr register selected. Thus, post-ra anti-dep breaking must not
525// later change that register assignment.
526let hasExtraSrcRegAllocReq = 1 in {
527def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$RST), (ins crbitm:$FXM),
528                        "mfocrf $RST, $FXM", IIC_SprMFCRF>,
529             PPC970_DGroup_First, PPC970_Unit_CRU;
530
531// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
532// is dependent on the cr fields being copied.
533def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$RT), (ins),
534                     "mfcr $RT", IIC_SprMFCR>,
535                     PPC970_MicroCode, PPC970_Unit_CRU;
536} // hasExtraSrcRegAllocReq = 1
537} // hasSideEffects = 0
538
539// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp
540// is not.
541let hasSideEffects = 1 in {
542  let Defs = [CTR8] in
543  def EH_SjLj_SetJmp64  : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
544                            "#EH_SJLJ_SETJMP64",
545                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
546                          Requires<[In64BitMode]>;
547}
548
549let hasSideEffects = 1, isBarrier = 1 in {
550  let isTerminator = 1 in
551  def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
552                            "#EH_SJLJ_LONGJMP64",
553                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
554                          Requires<[In64BitMode]>;
555}
556
557def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),
558                       "mfspr $RST, $SPR", IIC_SprMFSPR>;
559def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST),
560                       "mtspr $SPR, $RST", IIC_SprMTSPR>;
561
562
563//===----------------------------------------------------------------------===//
564// 64-bit SPR manipulation instrs.
565
566let Uses = [CTR8] in {
567def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$RST), (ins),
568                           "mfctr $RST", IIC_SprMFSPR>,
569             PPC970_DGroup_First, PPC970_Unit_FXU;
570}
571let Pattern = [(PPCmtctr i64:$RST)], Defs = [CTR8] in {
572def MTCTR8 : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST),
573                           "mtctr $RST", IIC_SprMTSPR>,
574             PPC970_DGroup_First, PPC970_Unit_FXU;
575}
576// MTCTR[8|]loop must be inside a loop-preheader, duplicating
577// the loop-preheader block will break this assumption.
578let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in {
579let Pattern = [(int_set_loop_iterations i64:$RST)] in
580def MTCTR8loop : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST),
581                               "mtctr $RST", IIC_SprMTSPR>,
582                 PPC970_DGroup_First, PPC970_Unit_FXU;
583}
584
585let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in
586def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride),
587                                        "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>;
588
589let Pattern = [(set i64:$RST, readcyclecounter)] in
590def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$RST), (ins),
591                          "mfspr $RST, 268", IIC_SprMFTB>,
592            PPC970_DGroup_First, PPC970_Unit_FXU;
593// Note that encoding mftb using mfspr is now the preferred form,
594// and has been since at least ISA v2.03. The mftb instruction has
595// now been phased out. Using mfspr, however, is known not to work on
596// the POWER3.
597
598let Defs = [X1], Uses = [X1] in
599def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
600                       [(set i64:$result,
601                             (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
602def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
603                       [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
604// Probed alloca to support stack clash protection.
605let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in {
606def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result),
607                         (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64",
608                           [(set i64:$result,
609                             (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>;
610def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs
611    g8rc:$fp, g8rc:$actual_negsize),
612    (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>;
613def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs
614    g8rc:$fp, g8rc:$actual_negsize),
615    (ins g8rc:$negsize, memri:$fpsi),
616    "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>,
617    RegConstraint<"$actual_negsize = $negsize">;
618def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp),
619    (ins i64imm:$stacksize),
620    "#PROBED_STACKALLOC_64", []>;
621}
622
623let hasSideEffects = 0 in {
624let Defs = [LR8] in {
625def MTLR8  : XFXForm_1_ext<31, 467, 8, (outs), (ins g8rc:$RST),
626                           "mtlr $RST", IIC_SprMTSPR>,
627             PPC970_DGroup_First, PPC970_Unit_FXU;
628}
629let Uses = [LR8] in {
630def MFLR8  : XFXForm_1_ext<31, 339, 8, (outs g8rc:$RST), (ins),
631                           "mflr $RST", IIC_SprMFSPR>,
632             PPC970_DGroup_First, PPC970_Unit_FXU;
633}
634} // Interpretation64Bit
635}
636
637//===----------------------------------------------------------------------===//
638// Fixed point instructions.
639//
640
641let PPC970_Unit = 1 in {  // FXU Operations.
642let Interpretation64Bit = 1 in {
643let hasSideEffects = 0 in {
644let isCodeGenOnly = 1 in {
645
646let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
647def LI8  : DForm_2_r0<14, (outs g8rc:$RST), (ins s16imm64:$D),
648                      "li $RST, $D", IIC_IntSimple,
649                      [(set i64:$RST, imm64SExt16:$D)]>, SExt32To64;
650def LIS8 : DForm_2_r0<15, (outs g8rc:$RST), (ins s17imm64:$D),
651                      "lis $RST, $D", IIC_IntSimple,
652                      [(set i64:$RST, imm16ShiftedSExt:$D)]>, SExt32To64;
653}
654
655// Logical ops.
656let isCommutable = 1 in {
657defm NAND8: XForm_6r<31, 476, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
658                     "nand", "$RA, $RST, $RB", IIC_IntSimple,
659                     [(set i64:$RA, (not (and i64:$RST, i64:$RB)))]>;
660defm AND8 : XForm_6r<31,  28, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
661                     "and", "$RA, $RST, $RB", IIC_IntSimple,
662                     [(set i64:$RA, (and i64:$RST, i64:$RB))]>;
663} // isCommutable
664defm ANDC8: XForm_6r<31,  60, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
665                     "andc", "$RA, $RST, $RB", IIC_IntSimple,
666                     [(set i64:$RA, (and i64:$RST, (not i64:$RB)))]>;
667let isCommutable = 1 in {
668defm OR8  : XForm_6r<31, 444, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
669                     "or", "$RA, $RST, $RB", IIC_IntSimple,
670                     [(set i64:$RA, (or i64:$RST, i64:$RB))]>;
671defm NOR8 : XForm_6r<31, 124, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
672                     "nor", "$RA, $RST, $RB", IIC_IntSimple,
673                     [(set i64:$RA, (not (or i64:$RST, i64:$RB)))]>;
674} // isCommutable
675defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
676                     "orc", "$RA, $RST, $RB", IIC_IntSimple,
677                     [(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>;
678let isCommutable = 1 in {
679defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
680                     "eqv", "$RA, $RST, $RB", IIC_IntSimple,
681                     [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>;
682defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
683                     "xor", "$RA, $RST, $RB", IIC_IntSimple,
684                     [(set i64:$RA, (xor i64:$RST, i64:$RB))]>;
685} // let isCommutable = 1
686
687// Logical ops with immediate.
688let Defs = [CR0] in {
689def ANDI8_rec  : DForm_4<28, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
690                      "andi. $RA, $RST, $D", IIC_IntGeneral,
691                      [(set i64:$RA, (and i64:$RST, immZExt16:$D))]>,
692                      isRecordForm, SExt32To64, ZExt32To64;
693def ANDIS8_rec : DForm_4<29, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
694                     "andis. $RA, $RST, $D", IIC_IntGeneral,
695                    [(set i64:$RA, (and i64:$RST, imm16ShiftedZExt:$D))]>,
696                     isRecordForm, ZExt32To64;
697}
698def ORI8    : DForm_4<24, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
699                      "ori $RA, $RST, $D", IIC_IntSimple,
700                      [(set i64:$RA, (or i64:$RST, immZExt16:$D))]>;
701def ORIS8   : DForm_4<25, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
702                      "oris $RA, $RST, $D", IIC_IntSimple,
703                    [(set i64:$RA, (or i64:$RST, imm16ShiftedZExt:$D))]>;
704def XORI8   : DForm_4<26, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
705                      "xori $RA, $RST, $D", IIC_IntSimple,
706                      [(set i64:$RA, (xor i64:$RST, immZExt16:$D))]>;
707def XORIS8  : DForm_4<27, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D),
708                      "xoris $RA, $RST, $D", IIC_IntSimple,
709                   [(set i64:$RA, (xor i64:$RST, imm16ShiftedZExt:$D))]>;
710
711let isCommutable = 1 in
712defm ADD8  : XOForm_1rx<31, 266, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
713                        "add", "$RT, $RA, $RB", IIC_IntSimple,
714                        [(set i64:$RT, (add i64:$RA, i64:$RB))]>;
715// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
716// initial-exec thread-local storage model.  We need to forbid r0 here -
717// while it works for add just fine, the linker can relax this to local-exec
718// addi, which won't work for r0.
719def ADD8TLS  : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB),
720                        "add $RT, $RA, $RB", IIC_IntSimple,
721                        [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>;
722let mayLoad = 1 in {
723def LBZXTLS : XForm_1<31,  87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
724                      "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
725def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
726                      "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
727def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
728                      "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;
729def LWZXTLS : XForm_1<31,  23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
730                      "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
731def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
732                      "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;
733def LDXTLS  : XForm_1<31,  21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
734                      "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;
735def LBZXTLS_32 : XForm_1<31,  87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
736                         "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
737def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
738                         "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
739def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
740                         "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;
741def LWZXTLS_32 : XForm_1<31,  23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
742                         "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
743def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
744                         "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;
745
746}
747let mayLoad = 1, Predicates = [HasFPU] in {
748def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
749                       "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>;
750def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
751                       "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>;
752}
753
754let mayStore = 1 in {
755def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
756                      "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
757                      PPC970_DGroup_Cracked;
758def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
759                      "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
760                      PPC970_DGroup_Cracked;
761def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
762                      "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
763                      PPC970_DGroup_Cracked;
764def STDXTLS  : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
765                       "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,
766                       PPC970_DGroup_Cracked;
767def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
768                         "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
769                         PPC970_DGroup_Cracked;
770def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
771                         "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
772                         PPC970_DGroup_Cracked;
773def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
774                         "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
775                         PPC970_DGroup_Cracked;
776
777}
778let mayStore = 1, Predicates = [HasFPU] in {
779def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
780                       "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>,
781                       PPC970_DGroup_Cracked;
782def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
783                       "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>,
784                       PPC970_DGroup_Cracked;
785}
786
787let isCommutable = 1 in
788defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
789                        "addc", "$RT, $RA, $RB", IIC_IntGeneral,
790                        [(set i64:$RT, (addc i64:$RA, i64:$RB))]>,
791                        PPC970_DGroup_Cracked;
792
793let Defs = [CARRY] in
794def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
795                     "addic $RST, $RA, $D", IIC_IntGeneral,
796                     [(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>;
797def ADDI8  : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
798                     "addi $RST, $RA, $D", IIC_IntSimple,
799                     [(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>;
800def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D),
801                     "addis $RST, $RA, $D", IIC_IntSimple,
802                     [(set i64:$RST, (add i64:$RA, imm16ShiftedSExt:$D))]>;
803
804def LA8     : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
805                     "la $RST, $D($RA)", IIC_IntGeneral,
806                     [(set i64:$RST, (add i64:$RA,
807                                    (PPClo tglobaladdr:$D, 0)))]>;
808
809let Defs = [CARRY] in {
810def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
811                     "subfic $RST, $RA, $D", IIC_IntGeneral,
812                     [(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>;
813}
814defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
815                        "subfc", "$RT, $RA, $RB", IIC_IntGeneral,
816                        [(set i64:$RT, (subc i64:$RB, i64:$RA))]>,
817                        PPC970_DGroup_Cracked;
818defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
819                        "subf", "$RT, $RA, $RB", IIC_IntGeneral,
820                        [(set i64:$RT, (sub i64:$RB, i64:$RA))]>;
821defm NEG8    : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA),
822                        "neg", "$RT, $RA", IIC_IntSimple,
823                        [(set i64:$RT, (ineg i64:$RA))]>;
824let Uses = [CARRY] in {
825let isCommutable = 1 in
826defm ADDE8   : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
827                          "adde", "$RT, $RA, $RB", IIC_IntGeneral,
828                          [(set i64:$RT, (adde i64:$RA, i64:$RB))]>;
829defm ADDME8  : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA),
830                          "addme", "$RT, $RA", IIC_IntGeneral,
831                          [(set i64:$RT, (adde i64:$RA, -1))]>;
832defm ADDZE8  : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA),
833                          "addze", "$RT, $RA", IIC_IntGeneral,
834                          [(set i64:$RT, (adde i64:$RA, 0))]>;
835defm SUBFE8  : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
836                          "subfe", "$RT, $RA, $RB", IIC_IntGeneral,
837                          [(set i64:$RT, (sube i64:$RB, i64:$RA))]>;
838defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA),
839                          "subfme", "$RT, $RA", IIC_IntGeneral,
840                          [(set i64:$RT, (sube -1, i64:$RA))]>;
841defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA),
842                          "subfze", "$RT, $RA", IIC_IntGeneral,
843                          [(set i64:$RT, (sube 0, i64:$RA))]>;
844}
845} // isCodeGenOnly
846
847// FIXME: Duplicating this for the asm parser should be unnecessary, but the
848// previous definition must be marked as CodeGen only to prevent decoding
849// conflicts.
850let isAsmParserOnly = 1 in {
851def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB),
852                        "add $RT, $RA, $RB", IIC_IntSimple, []>;
853
854let mayLoad = 1 in {
855def LBZXTLS_ : XForm_1<31,  87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
856                      "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>;
857def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
858                      "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>;
859def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
860                       "lhax $RST, $RA, $RB", IIC_LdStLoad, []>;
861def LWZXTLS_ : XForm_1<31,  23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
862                      "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>;
863def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
864                       "lwax $RST, $RA, $RB", IIC_LdStLoad, []>;
865def LDXTLS_  : XForm_1<31,  21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
866                      "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64;
867}
868
869let mayLoad = 1, Predicates = [HasFPU] in {
870def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
871                        "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>;
872def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB),
873                        "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>;
874}
875
876let mayStore = 1 in {
877def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
878                      "stbx $RST, $RA, $RB", IIC_LdStStore, []>,
879                      PPC970_DGroup_Cracked;
880def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
881                      "sthx $RST, $RA, $RB", IIC_LdStStore, []>,
882                      PPC970_DGroup_Cracked;
883def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
884                      "stwx $RST, $RA, $RB", IIC_LdStStore, []>,
885                      PPC970_DGroup_Cracked;
886def STDXTLS_  : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
887                       "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64,
888                       PPC970_DGroup_Cracked;
889}
890
891let mayStore = 1, Predicates = [HasFPU] in {
892def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
893                        "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>,
894                        PPC970_DGroup_Cracked;
895def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB),
896                        "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>,
897                        PPC970_DGroup_Cracked;
898}
899}
900
901let isCommutable = 1 in {
902defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
903                       "mulhd", "$RT, $RA, $RB", IIC_IntMulHW,
904                       [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>;
905defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
906                       "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU,
907                       [(set i64:$RT, (mulhu i64:$RA, i64:$RB))]>;
908} // isCommutable
909}
910} // Interpretation64Bit
911
912let isCompare = 1, hasSideEffects = 0 in {
913  def CMPD   : XForm_16_ext<31, 0, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB),
914                            "cmpd $BF, $RA, $RB", IIC_IntCompare>, isPPC64;
915  def CMPLD  : XForm_16_ext<31, 32, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB),
916                            "cmpld $BF, $RA, $RB", IIC_IntCompare>, isPPC64;
917  def CMPDI  : DForm_5_ext<11, (outs crrc:$BF), (ins g8rc:$RA, s16imm64:$D),
918                           "cmpdi $BF, $RA, $D", IIC_IntCompare>, isPPC64;
919  def CMPLDI : DForm_6_ext<10, (outs crrc:$BF), (ins g8rc:$RA, u16imm64:$D),
920                           "cmpldi $BF, $RA, $D",
921                           IIC_IntCompare>, isPPC64;
922  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
923  def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF),
924                                (ins u1imm:$L, g8rc:$RA, g8rc:$RB),
925                                "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>,
926               Requires<[IsISA3_0]>;
927  def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF),
928                             (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB",
929                             IIC_IntCompare, []>, Requires<[IsISA3_0]>;
930}
931
932let hasSideEffects = 0 in {
933defm SLD  : XForm_6r<31,  27, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),
934                     "sld", "$RA, $RST, $RB", IIC_IntRotateD,
935                     [(set i64:$RA, (PPCshl i64:$RST, i32:$RB))]>, isPPC64;
936defm SRD  : XForm_6r<31, 539, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),
937                     "srd", "$RA, $RST, $RB", IIC_IntRotateD,
938                     [(set i64:$RA, (PPCsrl i64:$RST, i32:$RB))]>, isPPC64;
939defm SRAD : XForm_6rc<31, 794, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB),
940                      "srad", "$RA, $RST, $RB", IIC_IntRotateD,
941                      [(set i64:$RA, (PPCsra i64:$RST, i32:$RB))]>, isPPC64;
942
943let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
944defm CNTLZW8 : XForm_11r<31,  26, (outs g8rc:$RA), (ins g8rc:$RST),
945                        "cntlzw", "$RA, $RST", IIC_IntGeneral, []>,
946                        ZExt32To64, SExt32To64;
947defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$RA), (ins g8rc:$RST),
948                        "cnttzw", "$RA, $RST", IIC_IntGeneral, []>,
949               Requires<[IsISA3_0]>, ZExt32To64, SExt32To64;
950
951defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$RA), (ins g8rc:$RST),
952                        "extsb", "$RA, $RST", IIC_IntSimple,
953                        [(set i64:$RA, (sext_inreg i64:$RST, i8))]>, SExt32To64;
954defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$RA), (ins g8rc:$RST),
955                        "extsh", "$RA, $RST", IIC_IntSimple,
956                        [(set i64:$RA, (sext_inreg i64:$RST, i16))]>, SExt32To64;
957
958defm SLW8  : XForm_6r<31,  24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
959                      "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;
960defm SRW8  : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
961                      "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64;
962} // Interpretation64Bit
963
964// For fast-isel:
965let isCodeGenOnly = 1 in {
966def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$RA), (ins gprc:$RST),
967                           "extsb $RA, $RST", IIC_IntSimple, []>, isPPC64,
968                           SExt32To64;
969def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$RA), (ins gprc:$RST),
970                           "extsh $RA, $RST", IIC_IntSimple, []>, isPPC64,
971                           SExt32To64;
972} // isCodeGenOnly for fast-isel
973
974defm EXTSW  : XForm_11r<31, 986, (outs g8rc:$RA), (ins g8rc:$RST),
975                        "extsw", "$RA, $RST", IIC_IntSimple,
976                        [(set i64:$RA, (sext_inreg i64:$RST, i32))]>, isPPC64,
977                        SExt32To64;
978let Interpretation64Bit = 1, isCodeGenOnly = 1 in
979defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$RA), (ins gprc:$RST),
980                             "extsw", "$RA, $RST", IIC_IntSimple,
981                             [(set i64:$RA, (sext i32:$RST))]>, isPPC64,
982                             SExt32To64;
983let isCodeGenOnly = 1 in
984def EXTSW_32 : XForm_11<31, 986, (outs gprc:$RA), (ins gprc:$RST),
985                        "extsw $RA, $RST", IIC_IntSimple,
986                        []>, isPPC64;
987
988defm SRADI  : XSForm_1rc<31, 413, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),
989                         "sradi", "$RA, $RS, $SH", IIC_IntRotateDI,
990                         [(set i64:$RA, (sra i64:$RS, (i32 imm:$SH)))]>, isPPC64;
991
992let Interpretation64Bit = 1, isCodeGenOnly = 1 in
993defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$RA),
994                                (ins gprc:$RS, u6imm:$SH),
995                                "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI,
996                                [(set i64:$RA,
997                                      (PPCextswsli i32:$RS, (i32 imm:$SH)))]>,
998                                isPPC64, Requires<[IsISA3_0]>;
999
1000defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH),
1001                           "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI,
1002                           []>, isPPC64, Requires<[IsISA3_0]>;
1003
1004// For fast-isel:
1005let isCodeGenOnly = 1, Defs = [CARRY] in
1006def SRADI_32  : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH),
1007                         "sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64;
1008
1009defm CNTLZD : XForm_11r<31,  58, (outs g8rc:$RA), (ins g8rc:$RST),
1010                        "cntlzd", "$RA, $RST", IIC_IntGeneral,
1011                        [(set i64:$RA, (ctlz i64:$RST))]>,
1012                        ZExt32To64, SExt32To64;
1013defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$RA), (ins g8rc:$RST),
1014                        "cnttzd", "$RA, $RST", IIC_IntGeneral,
1015                        [(set i64:$RA, (cttz i64:$RST))]>, Requires<[IsISA3_0]>,
1016                        ZExt32To64, SExt32To64;
1017def POPCNTD : XForm_11<31, 506, (outs g8rc:$RA), (ins g8rc:$RST),
1018                       "popcntd $RA, $RST", IIC_IntGeneral,
1019                       [(set i64:$RA, (ctpop i64:$RST))]>,
1020                       ZExt32To64, SExt32To64;
1021def BPERMD : XForm_6<31, 252, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1022                     "bpermd $RA, $RST, $RB", IIC_IntGeneral,
1023                     [(set i64:$RA, (int_ppc_bpermd g8rc:$RST, g8rc:$RB))]>,
1024                     isPPC64, Requires<[HasBPERMD]>;
1025
1026let isCodeGenOnly = 1, isCommutable = 1 in
1027def CMPB8 : XForm_6<31, 508, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
1028                    "cmpb $RA, $RST, $RB", IIC_IntGeneral,
1029                    [(set i64:$RA, (PPCcmpb i64:$RST, i64:$RB))]>;
1030
1031// popcntw also does a population count on the high 32 bits (storing the
1032// results in the high 32-bits of the output). We'll ignore that here (which is
1033// safe because we never separately use the high part of the 64-bit registers).
1034def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST),
1035                       "popcntw $RA, $RST", IIC_IntGeneral,
1036                       [(set i32:$RA, (ctpop i32:$RST))]>;
1037
1038let isCodeGenOnly = 1 in {
1039def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST),
1040                        "popcntb $RA, $RST", IIC_IntGeneral,
1041                        [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>;
1042
1043def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST),
1044                       "cdtbcd $RA, $RST", IIC_IntGeneral, []>;
1045def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST),
1046                       "cbcdtd $RA, $RST", IIC_IntGeneral, []>;
1047
1048def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1049                       "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
1050}
1051
1052defm DIVD  : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1053                          "divd", "$RT, $RA, $RB", IIC_IntDivD,
1054                          [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64;
1055defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1056                          "divdu", "$RT, $RA, $RB", IIC_IntDivD,
1057                          [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64;
1058defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1059                         "divde", "$RT, $RA, $RB", IIC_IntDivD,
1060                         [(set i64:$RT, (int_ppc_divde g8rc:$RA, g8rc:$RB))]>,
1061                         isPPC64, Requires<[HasExtDiv]>;
1062
1063let Predicates = [IsISA3_0] in {
1064def MADDHD : VAForm_1a<48, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
1065                       "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
1066def MADDHDU : VAForm_1a<49,
1067                       (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
1068                       "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
1069def MADDLD : VAForm_1a<51, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
1070                       "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
1071                       [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>,
1072                       isPPC64;
1073let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1074  def MADDLD8 : VAForm_1a<51,
1075                       (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
1076                       "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
1077                       [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
1078                       isPPC64;
1079  def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
1080                       "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64;
1081}
1082def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
1083                     "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
1084def MODSD : XForm_8<31, 777, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB),
1085                        "modsd $RST, $RA, $RB", IIC_IntDivW,
1086                        [(set i64:$RST, (srem i64:$RA, i64:$RB))]>;
1087def MODUD : XForm_8<31, 265, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB),
1088                        "modud $RST, $RA, $RB", IIC_IntDivW,
1089                        [(set i64:$RST, (urem i64:$RA, i64:$RB))]>;
1090}
1091
1092defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1093                          "divdeu", "$RT, $RA, $RB", IIC_IntDivD,
1094                          [(set i64:$RT, (int_ppc_divdeu g8rc:$RA, g8rc:$RB))]>,
1095                          isPPC64, Requires<[HasExtDiv]>;
1096let isCommutable = 1 in
1097defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
1098                        "mulld", "$RT, $RA, $RB", IIC_IntMulHD,
1099                        [(set i64:$RT, (mul i64:$RA, i64:$RB))]>, isPPC64;
1100let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1101def MULLI8 : DForm_2<7, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
1102                       "mulli $RST, $RA, $D", IIC_IntMulLI,
1103                       [(set i64:$RST, (mul i64:$RA, imm64SExt16:$D))]>;
1104}
1105
1106let hasSideEffects = 1 in {
1107def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),
1108                    "darn $RT, $L", IIC_LdStLD>, isPPC64;
1109}
1110
1111let hasSideEffects = 0 in {
1112defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA),
1113                        (ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE),
1114                        "rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1115                        []>, isPPC64, RegConstraint<"$RAi = $RA">,
1116                        NoEncode<"$RAi">;
1117
1118// Rotate instructions.
1119defm RLDCL  : MDSForm_1r<30, 8,
1120                        (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE),
1121                        "rldcl", "$RA, $RS, $RB, $MBE", IIC_IntRotateD,
1122                        []>, isPPC64;
1123defm RLDCR  : MDSForm_1r<30, 9,
1124                        (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE),
1125                        "rldcr", "$RA, $RS, $RB, $MBE", IIC_IntRotateD,
1126                        []>, isPPC64;
1127defm RLDICL : MDForm_1r<30, 0,
1128                        (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),
1129                        "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1130                        []>, isPPC64;
1131// For fast-isel:
1132let isCodeGenOnly = 1 in
1133def RLDICL_32_64 : MDForm_1<30, 0,
1134                            (outs g8rc:$RA),
1135                            (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),
1136                            "rldicl $RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1137                            []>, isPPC64;
1138// End fast-isel.
1139let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1140defm RLDICL_32 : MDForm_1r<30, 0,
1141                           (outs gprc:$RA),
1142                           (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),
1143                           "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1144                           []>, isPPC64;
1145defm RLDICR : MDForm_1r<30, 1,
1146                        (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),
1147                        "rldicr", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1148                        []>, isPPC64;
1149let isCodeGenOnly = 1 in
1150def RLDICR_32 : MDForm_1<30, 1,
1151                         (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE),
1152                         "rldicr $RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1153                         []>, isPPC64;
1154defm RLDIC  : MDForm_1r<30, 2,
1155                        (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE),
1156                        "rldic", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
1157                        []>, isPPC64;
1158
1159let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1160defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA),
1161                        (ins g8rc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1162                        "rlwinm", "$RA, $RS, $SH, $MB, $ME", IIC_IntGeneral,
1163                        []>;
1164
1165defm RLWNM8  : MForm_1r<23, (outs g8rc:$RA),
1166                        (ins g8rc:$RS, g8rc:$RB, u5imm:$MB, u5imm:$ME),
1167                        "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral,
1168                        []>;
1169
1170// RLWIMI can be commuted if the rotate amount is zero.
1171let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1172defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA),
1173                        (ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB,
1174                        u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",
1175                        IIC_IntRotate, []>, PPC970_DGroup_Cracked,
1176                        RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">;
1177
1178let isSelect = 1 in
1179def ISEL8   : AForm_4<31, 15,
1180                     (outs g8rc:$RT), (ins g8rc_nox0:$RA, g8rc:$RB, crbitrc:$COND),
1181                     "isel $RT, $RA, $RB, $COND", IIC_IntISEL,
1182                     []>;
1183}  // Interpretation64Bit
1184}  // hasSideEffects = 0
1185}  // End FXU Operations.
1186
1187def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;
1188def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;
1189
1190def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
1191def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
1192
1193def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
1194def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
1195
1196def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
1197
1198def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
1199def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
1200def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
1201def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
1202
1203def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
1204def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
1205def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
1206def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
1207def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
1208def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
1209
1210def : InstAlias<"isellt $rT, $rA, $rB",
1211                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>;
1212def : InstAlias<"iselgt $rT, $rA, $rB",
1213                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>;
1214def : InstAlias<"iseleq $rT, $rA, $rB",
1215                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>;
1216
1217def : InstAlias<"nop", (ORI8 X0, X0, 0)>;
1218def : InstAlias<"xnop", (XORI8 X0, X0, 0)>;
1219
1220def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>;
1221def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>;
1222
1223def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>;
1224def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>;
1225
1226//Disable this alias on AIX for now because as does not support them.
1227let Predicates = [ModernAs] in {
1228
1229def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>;
1230def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>;
1231
1232def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>;
1233def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>;
1234
1235def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>;
1236def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>;
1237
1238def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>;
1239def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>;
1240
1241def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>;
1242def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>;
1243
1244def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>;
1245def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>;
1246
1247def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>;
1248def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>;
1249
1250def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>;
1251def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>;
1252
1253def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>;
1254def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>;
1255
1256def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>;
1257def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>;
1258
1259def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>;
1260def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>;
1261
1262def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>;
1263def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>;
1264
1265def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>;
1266def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>;
1267
1268def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>;
1269def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>;
1270
1271foreach SPRG = 0-3 in {
1272  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>;
1273  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>;
1274  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>;
1275  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>;
1276}
1277
1278def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>;
1279def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>;
1280
1281def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>;
1282def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>;
1283
1284def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>;
1285
1286def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>;
1287def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>;
1288
1289}
1290
1291//===----------------------------------------------------------------------===//
1292// Load/Store instructions.
1293//
1294
1295
1296// Sign extending loads.
1297let PPC970_Unit = 2 in {
1298let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1299def LHA8: DForm_1<42, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
1300                  "lha $RST, $addr", IIC_LdStLHA,
1301                  [(set i64:$RST, (sextloadi16 DForm:$addr))]>,
1302                  PPC970_DGroup_Cracked, SExt32To64;
1303def LWA  : DSForm_1<58, 2, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr),
1304                    "lwa $RST, $addr", IIC_LdStLWA,
1305                    [(set i64:$RST,
1306                          (sextloadi32 DSForm:$addr))]>, isPPC64,
1307                    PPC970_DGroup_Cracked, SExt32To64;
1308let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1309def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1310                        "lhax $RST, $addr", IIC_LdStLHA,
1311                        [(set i64:$RST, (sextloadi16 XForm:$addr))]>,
1312                        PPC970_DGroup_Cracked, SExt32To64;
1313def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1314                        "lwax $RST, $addr", IIC_LdStLHA,
1315                        [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64,
1316                        PPC970_DGroup_Cracked, SExt32To64;
1317// For fast-isel:
1318let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
1319def LWA_32  : DSForm_1<58, 2, (outs gprc:$RST), (ins (memrix $D, $RA):$addr),
1320                      "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64,
1321                      PPC970_DGroup_Cracked, SExt32To64;
1322def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr),
1323                            "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64,
1324                            PPC970_DGroup_Cracked, SExt32To64;
1325} // end fast-isel isCodeGenOnly
1326
1327// Update forms.
1328let mayLoad = 1, hasSideEffects = 0 in {
1329let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1330def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1331                    (ins (memri $D, $RA):$addr),
1332                    "lhau $RST, $addr", IIC_LdStLHAU,
1333                    []>, RegConstraint<"$addr.reg = $ea_result">,
1334                    NoEncode<"$ea_result">;
1335// NO LWAU!
1336
1337let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1338def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1339                          (ins (memrr $RA, $RB):$addr),
1340                          "lhaux $RST, $addr", IIC_LdStLHAUX,
1341                          []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1342                          NoEncode<"$ea_result">;
1343def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1344                          (ins (memrr $RA, $RB):$addr),
1345                          "lwaux $RST, $addr", IIC_LdStLHAUX,
1346                          []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1347                          NoEncode<"$ea_result">, isPPC64;
1348}
1349}
1350
1351let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1352// Zero extending loads.
1353let PPC970_Unit = 2 in {
1354def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
1355                  "lbz $RST, $addr", IIC_LdStLoad,
1356                  [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64,
1357                  SExt32To64;
1358def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
1359                  "lhz $RST, $addr", IIC_LdStLoad,
1360                  [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64,
1361                  SExt32To64;
1362def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins (memri $D, $RA):$addr),
1363                  "lwz $RST, $addr", IIC_LdStLoad,
1364                  [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64,
1365                  ZExt32To64;
1366
1367def LBZX8 : XForm_1_memOp<31,  87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1368                          "lbzx $RST, $addr", IIC_LdStLoad,
1369                          [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64,
1370                          SExt32To64;
1371def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1372                          "lhzx $RST, $addr", IIC_LdStLoad,
1373                          [(set i64:$RST, (zextloadi16 XForm:$addr))]>,
1374                          ZExt32To64, SExt32To64;
1375def LWZX8 : XForm_1_memOp<31,  23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1376                          "lwzx $RST, $addr", IIC_LdStLoad,
1377                          [(set i64:$RST, (zextloadi32 XForm:$addr))]>,
1378                          ZExt32To64;
1379
1380
1381// Update forms.
1382let mayLoad = 1, hasSideEffects = 0 in {
1383def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1384                    (ins (memri $D, $RA):$addr),
1385                    "lbzu $RST, $addr", IIC_LdStLoadUpd,
1386                    []>, RegConstraint<"$addr.reg = $ea_result">,
1387                    NoEncode<"$ea_result">;
1388def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1389                    (ins (memri $D, $RA):$addr),
1390                    "lhzu $RST, $addr", IIC_LdStLoadUpd,
1391                    []>, RegConstraint<"$addr.reg = $ea_result">,
1392                    NoEncode<"$ea_result">;
1393def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1394                    (ins (memri $D, $RA):$addr),
1395                    "lwzu $RST, $addr", IIC_LdStLoadUpd,
1396                    []>, RegConstraint<"$addr.reg = $ea_result">,
1397                    NoEncode<"$ea_result">;
1398
1399def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1400                          (ins (memrr $RA, $RB):$addr),
1401                          "lbzux $RST, $addr", IIC_LdStLoadUpdX,
1402                          []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1403                          NoEncode<"$ea_result">;
1404def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1405                          (ins (memrr $RA, $RB):$addr),
1406                          "lhzux $RST, $addr", IIC_LdStLoadUpdX,
1407                          []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1408                          NoEncode<"$ea_result">;
1409def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1410                          (ins (memrr $RA, $RB):$addr),
1411                          "lwzux $RST, $addr", IIC_LdStLoadUpdX,
1412                          []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1413                          NoEncode<"$ea_result">;
1414}
1415}
1416} // Interpretation64Bit
1417
1418
1419// Full 8-byte loads.
1420let PPC970_Unit = 2 in {
1421def LD   : DSForm_1<58, 0, (outs g8rc:$RST), (ins (memrix $D, $RA):$addr),
1422                    "ld $RST, $addr", IIC_LdStLD,
1423                    [(set i64:$RST, (load DSForm:$addr))]>, isPPC64;
1424// The following four definitions are selected for small code model only.
1425// Otherwise, we need to create two instructions to form a 32-bit offset,
1426// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
1427def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1428                  "#LDtoc",
1429                  [(set i64:$rD,
1430                     (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
1431def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1432                  "#LDtocJTI",
1433                  [(set i64:$rD,
1434                     (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
1435def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1436                  "#LDtocCPT",
1437                  [(set i64:$rD,
1438                     (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
1439def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
1440                  "#LDtocCPT",
1441                  [(set i64:$rD,
1442                     (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
1443
1444def LDX  : XForm_1_memOp<31,  21, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1445                        "ldx $RST, $addr", IIC_LdStLD,
1446                        [(set i64:$RST, (load XForm:$addr))]>, isPPC64;
1447
1448let Predicates = [IsISA2_06] in {
1449def LDBRX : XForm_1_memOp<31,  532, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1450                          "ldbrx $RST, $addr", IIC_LdStLoad,
1451                          [(set i64:$RST, (PPClbrx ForceXForm:$addr, i64))]>, isPPC64;
1452}
1453
1454let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
1455def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1456                          "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;
1457def LWBRX8 : XForm_1_memOp<31,  534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
1458                          "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64;
1459}
1460
1461let mayLoad = 1, hasSideEffects = 0 in {
1462def LDU  : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1463                    (ins (memrix $D, $RA):$addr),
1464                    "ldu $RST, $addr", IIC_LdStLDU,
1465                    []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
1466                    NoEncode<"$ea_result">;
1467
1468def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
1469                        (ins (memrr $RA, $RB):$addr),
1470                        "ldux $RST, $addr", IIC_LdStLDUX,
1471                        []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1472                        NoEncode<"$ea_result">, isPPC64;
1473}
1474
1475let mayLoad = 1, hasNoSchedulingInfo = 1 in {
1476// Full 16-byte load.
1477// Early clobber $RTp to avoid assigned to the same register as RA.
1478// TODO: Add scheduling info.
1479def LQ   : DQForm_RTp5_RA17_MEM<56, 0,
1480                                (outs g8prc:$RTp),
1481                                (ins (memrix16 $DQ, $RA):$addr),
1482                                "lq $RTp, $addr", IIC_LdStLQ,
1483                                []>,
1484                                RegConstraint<"@earlyclobber $RTp">,
1485                                isPPC64;
1486// We don't really have LQX in the ISA, make a pseudo one so that we can
1487// handle x-form during isel. Make it pre-ra may expose
1488// oppotunities to some opts(CSE, LICM and etc.) for the result of adding
1489// RA and RB.
1490def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp),
1491                                         (ins memrr:$src), "#LQX_PSEUDO", []>;
1492
1493def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src),
1494                                         "#RESTORE_QUADWORD", []>;
1495}
1496
1497}
1498
1499def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src),
1500          (SPLIT_QUADWORD (LQ memrix16:$src))>;
1501
1502def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src),
1503          (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>;
1504
1505// Support for medium and large code model.
1506let hasSideEffects = 0 in {
1507let isReMaterializable = 1 in {
1508def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
1509                       "#ADDIStocHA8", []>, isPPC64;
1510def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
1511                     "#ADDItocL", []>, isPPC64;
1512}
1513
1514// Local Data Transform
1515def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
1516                   "#ADDItoc8",
1517                   [(set i64:$rD,
1518                     (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
1519
1520let mayLoad = 1 in
1521def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
1522                   "#LDtocL", []>, isPPC64;
1523}
1524
1525// Support for thread-local storage.
1526def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1527                         "#ADDISgotTprelHA",
1528                         [(set i64:$rD,
1529                           (PPCaddisGotTprelHA i64:$reg,
1530                                               tglobaltlsaddr:$disp))]>,
1531                  isPPC64;
1532def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
1533                        "#LDgotTprelL",
1534                        [(set i64:$rD,
1535                          (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
1536                 isPPC64;
1537
1538let Defs = [CR7], Itinerary = IIC_LdStSync in
1539def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
1540
1541def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
1542          (ADD8TLS $in, tglobaltlsaddr:$g)>;
1543def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1544                         "#ADDIStlsgdHA",
1545                         [(set i64:$rD,
1546                           (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
1547                  isPPC64;
1548def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1549                       "#ADDItlsgdL",
1550                       [(set i64:$rD,
1551                         (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
1552                 isPPC64;
1553
1554class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
1555                                             asmstr,
1556                                             [(set i64:$rD,
1557                                               (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
1558                                      isPPC64;
1559class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
1560                                             asmstr,
1561                                             [(set i64:$rD,
1562                                               (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
1563                                      isPPC64;
1564
1565let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in {
1566// LR8 is a true define, while the rest of the Defs are clobbers. X3 is
1567// explicitly defined when this op is created, so not mentioned here.
1568// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be
1569// correct because the branch select pass is relying on it.
1570let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in
1571def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">;
1572let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in
1573def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">;
1574
1575// LR8 is a true define, while the rest of the Defs are clobbers. X3 is
1576// explicitly defined when this op is created, so not mentioned here.
1577let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1578def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">;
1579let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1580def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">;
1581
1582// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the
1583// offset and region handle respectively. The call is not followed by a nop
1584// so we don't need to mark it with a size of 8 bytes. Finally, the assembly
1585// manual mentions this exact set of registers as the clobbered set, others
1586// are guaranteed not to be clobbered.
1587let Defs = [X0,X4,X5,X11,LR8,CR0] in
1588def GETtlsADDR64AIX :
1589  PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle),
1590                    "GETtlsADDR64AIX",
1591                    [(set i64:$rD,
1592                      (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64;
1593}
1594
1595// Combined op for ADDItlsgdL and GETtlsADDR, late expanded.  X3 and LR8
1596// are true defines while the rest of the Defs are clobbers.
1597let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1598    Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1599    in
1600def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),
1601                            (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
1602                            "#ADDItlsgdLADDR",
1603                            [(set i64:$rD,
1604                              (PPCaddiTlsgdLAddr i64:$reg,
1605                                                 tglobaltlsaddr:$disp,
1606                                                 tglobaltlsaddr:$sym))]>,
1607                     isPPC64;
1608def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1609                         "#ADDIStlsldHA",
1610                         [(set i64:$rD,
1611                           (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
1612                  isPPC64;
1613def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1614                       "#ADDItlsldL",
1615                       [(set i64:$rD,
1616                         (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
1617                 isPPC64;
1618// This pseudo is expanded to two copies to put the variable offset in R4 and
1619// the region handle in R3 and GETtlsADDR64AIX.
1620def TLSGDAIX8 :
1621  PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle),
1622                     "#TLSGDAIX8",
1623                     [(set i64:$rD,
1624                       (PPCTlsgdAIX i64:$offset, i64:$handle))]>;
1625// Combined op for ADDItlsldL and GETtlsADDR, late expanded.  X3 and LR8
1626// are true defines, while the rest of the Defs are clobbers.
1627let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1628    Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1629    in
1630def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),
1631                            (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
1632                            "#ADDItlsldLADDR",
1633                            [(set i64:$rD,
1634                              (PPCaddiTlsldLAddr i64:$reg,
1635                                                 tglobaltlsaddr:$disp,
1636                                                 tglobaltlsaddr:$sym))]>,
1637                     isPPC64;
1638def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1639                          "#ADDISdtprelHA",
1640                          [(set i64:$rD,
1641                            (PPCaddisDtprelHA i64:$reg,
1642                                              tglobaltlsaddr:$disp))]>,
1643                   isPPC64;
1644def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1645                         "#ADDIdtprelL",
1646                         [(set i64:$rD,
1647                           (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
1648                  isPPC64;
1649def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
1650                          "#PADDIdtprel",
1651                          [(set i64:$rD,
1652                            (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>,
1653                  isPPC64;
1654
1655let PPC970_Unit = 2 in {
1656let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1657// Truncating stores.
1658def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),
1659                   "stb $RST, $addr", IIC_LdStStore,
1660                   [(truncstorei8 i64:$RST, DForm:$addr)]>;
1661def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),
1662                   "sth $RST, $addr", IIC_LdStStore,
1663                   [(truncstorei16 i64:$RST, DForm:$addr)]>;
1664def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, (memri $D, $RA):$addr),
1665                   "stw $RST, $addr", IIC_LdStStore,
1666                   [(truncstorei32 i64:$RST, DForm:$addr)]>;
1667def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1668                          "stbx $RST, $addr", IIC_LdStStore,
1669                          [(truncstorei8 i64:$RST, XForm:$addr)]>,
1670                          PPC970_DGroup_Cracked;
1671def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1672                          "sthx $RST, $addr", IIC_LdStStore,
1673                          [(truncstorei16 i64:$RST, XForm:$addr)]>,
1674                          PPC970_DGroup_Cracked;
1675def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1676                          "stwx $RST, $addr", IIC_LdStStore,
1677                          [(truncstorei32 i64:$RST, XForm:$addr)]>,
1678                          PPC970_DGroup_Cracked;
1679} // Interpretation64Bit
1680
1681// Normal 8-byte stores.
1682def STD  : DSForm_1<62, 0, (outs), (ins g8rc:$RST, (memrix $D, $RA):$addr),
1683                    "std $RST, $addr", IIC_LdStSTD,
1684                    [(store i64:$RST, DSForm:$addr)]>, isPPC64;
1685def STDX  : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1686                          "stdx $RST, $addr", IIC_LdStSTD,
1687                          [(store i64:$RST, XForm:$addr)]>, isPPC64,
1688                          PPC970_DGroup_Cracked;
1689
1690let Predicates = [IsISA2_06] in {
1691def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1692                          "stdbrx $RST, $addr", IIC_LdStStore,
1693                          [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64,
1694                          PPC970_DGroup_Cracked;
1695}
1696
1697let mayStore = 1, hasNoSchedulingInfo = 1 in {
1698// Normal 16-byte stores.
1699// TODO: Add scheduling info.
1700def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, (memrix $D, $RA):$addr),
1701                   "stq $RST, $addr", IIC_LdStSTQ,
1702                   []>, isPPC64;
1703
1704def STQX_PSEUDO : PPCCustomInserterPseudo<(outs),
1705                                          (ins g8prc:$RSp, memrr:$dst),
1706                                          "#STQX_PSEUDO", []>;
1707
1708def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst),
1709                                       "#SPILL_QUADWORD", []>;
1710}
1711
1712}
1713
1714def BUILD_QUADWORD : PPCPostRAExpPseudo<
1715                       (outs g8prc:$RTp),
1716                       (ins g8rc:$lo, g8rc:$hi),
1717                       "#BUILD_QUADWORD", []>;
1718
1719def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst),
1720          (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>;
1721
1722def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst),
1723          (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>;
1724
1725// Stores with Update (pre-inc).
1726let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1727let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1728def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
1729                   "stbu $RST, $addr", IIC_LdStSTU, []>,
1730                   RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
1731def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
1732                   "sthu $RST, $addr", IIC_LdStSTU, []>,
1733                   RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
1734def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
1735                   "stwu $RST, $addr", IIC_LdStSTU, []>,
1736                   RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
1737
1738def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
1739                          (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1740                          "stbux $RST, $addr", IIC_LdStSTUX, []>,
1741                          RegConstraint<"$addr.ptrreg = $ea_res">,
1742                          NoEncode<"$ea_res">,
1743                          PPC970_DGroup_Cracked;
1744def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
1745                          (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1746                          "sthux $RST, $addr", IIC_LdStSTUX, []>,
1747                          RegConstraint<"$addr.ptrreg = $ea_res">,
1748                          NoEncode<"$ea_res">,
1749                          PPC970_DGroup_Cracked;
1750def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
1751                          (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1752                          "stwux $RST, $addr", IIC_LdStSTUX, []>,
1753                          RegConstraint<"$addr.ptrreg = $ea_res">,
1754                          NoEncode<"$ea_res">,
1755                          PPC970_DGroup_Cracked;
1756} // Interpretation64Bit
1757
1758def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),
1759                   (ins g8rc:$RST, (memrix $D, $RA):$addr),
1760                   "stdu $RST, $addr", IIC_LdStSTU, []>,
1761                   RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">,
1762                   isPPC64;
1763
1764def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),
1765                          (ins g8rc:$RST, (memrr $RA, $RB):$addr),
1766                          "stdux $RST, $addr", IIC_LdStSTUX, []>,
1767                          RegConstraint<"$addr.ptrreg = $ea_res">,
1768                          NoEncode<"$ea_res">,
1769                          PPC970_DGroup_Cracked, isPPC64;
1770}
1771
1772// Patterns to match the pre-inc stores.  We can't put the patterns on
1773// the instruction definitions directly as ISel wants the address base
1774// and offset to be separate operands, not a single complex operand.
1775def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1776          (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1777def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1778          (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1779def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1780          (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1781def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1782          (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1783
1784def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1785          (STBUX8 $rS, $ptrreg, $ptroff)>;
1786def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1787          (STHUX8 $rS, $ptrreg, $ptroff)>;
1788def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1789          (STWUX8 $rS, $ptrreg, $ptroff)>;
1790def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1791          (STDUX $rS, $ptrreg, $ptroff)>;
1792
1793
1794//===----------------------------------------------------------------------===//
1795// Floating point instructions.
1796//
1797
1798
1799let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1,
1800    Uses = [RM] in {  // FPU Operations.
1801defm FCFID  : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB),
1802                        "fcfid", "$RST, $RB", IIC_FPGeneral,
1803                        [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64;
1804defm FCTID  : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB),
1805                        "fctid", "$RST, $RB", IIC_FPGeneral,
1806                        []>, isPPC64;
1807defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB),
1808                        "fctidu", "$RST, $RB", IIC_FPGeneral,
1809                        []>, isPPC64;
1810defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB),
1811                        "fctidz", "$RST, $RB", IIC_FPGeneral,
1812                        [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64;
1813
1814defm FCFIDU  : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB),
1815                        "fcfidu", "$RST, $RB", IIC_FPGeneral,
1816                        [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64;
1817defm FCFIDS  : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB),
1818                        "fcfids", "$RST, $RB", IIC_FPGeneral,
1819                        [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64;
1820defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB),
1821                        "fcfidus", "$RST, $RB", IIC_FPGeneral,
1822                        [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64;
1823defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB),
1824                        "fctiduz", "$RST, $RB", IIC_FPGeneral,
1825                        [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64;
1826defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),
1827                        "fctiwuz", "$RST, $RB", IIC_FPGeneral,
1828                        [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;
1829}
1830
1831// These instructions store a hash computed from the value of the link register
1832// and the value of the stack pointer.
1833let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1834def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs),
1835                                (ins g8rc:$RB, (memrihash $D, $RA):$addr),
1836                                "hashst $RB, $addr", IIC_IntGeneral, []>;
1837def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs),
1838                                 (ins g8rc:$RB, (memrihash $D, $RA):$addr),
1839                                 "hashstp $RB, $addr", IIC_IntGeneral, []>;
1840}
1841
1842// These instructions check a hash computed from the value of the link register
1843// and the value of the stack pointer. The hasSideEffects flag is needed as the
1844// instruction may TRAP if the hash does not match the hash stored at the
1845// specified address.
1846let mayLoad = 1, hasSideEffects = 1,
1847    Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1848def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs),
1849                                 (ins g8rc:$RB, (memrihash $D, $RA):$addr),
1850                                 "hashchk $RB, $addr", IIC_IntGeneral, []>;
1851def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs),
1852                                  (ins g8rc:$RB, (memrihash $D, $RA):$addr),
1853                                  "hashchkp $RB, $addr", IIC_IntGeneral, []>;
1854}
1855
1856let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
1857def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT),
1858                              (ins g8rc:$RA, g8rc:$RB, u2imm:$CY),
1859                              "addex $RT, $RA, $RB, $CY", IIC_IntGeneral,
1860                              [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB,
1861                                                            timm:$CY))]>;
1862
1863//===----------------------------------------------------------------------===//
1864// Instruction Patterns
1865//
1866
1867// Extensions and truncates to/from 32-bit regs.
1868def : Pat<(i64 (zext i32:$in)),
1869          (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1870                  0, 32)>;
1871def : Pat<(i64 (anyext i32:$in)),
1872          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1873def : Pat<(i32 (trunc i64:$in)),
1874          (EXTRACT_SUBREG $in, sub_32)>;
1875
1876// Implement the 'not' operation with the NOR instruction.
1877// (we could use the default xori pattern, but nor has lower latency on some
1878// cores (such as the A2)).
1879def i64not : OutPatFrag<(ops node:$in),
1880                        (NOR8 $in, $in)>;
1881def        : Pat<(not i64:$in),
1882                 (i64not $in)>;
1883
1884// Extending loads with i64 targets.
1885def : Pat<(zextloadi1 DForm:$src),
1886          (LBZ8 DForm:$src)>;
1887def : Pat<(zextloadi1 XForm:$src),
1888          (LBZX8 XForm:$src)>;
1889def : Pat<(extloadi1 DForm:$src),
1890          (LBZ8 DForm:$src)>;
1891def : Pat<(extloadi1 XForm:$src),
1892          (LBZX8 XForm:$src)>;
1893def : Pat<(extloadi8 DForm:$src),
1894          (LBZ8 DForm:$src)>;
1895def : Pat<(extloadi8 XForm:$src),
1896          (LBZX8 XForm:$src)>;
1897def : Pat<(extloadi16 DForm:$src),
1898          (LHZ8 DForm:$src)>;
1899def : Pat<(extloadi16 XForm:$src),
1900          (LHZX8 XForm:$src)>;
1901def : Pat<(extloadi32 DForm:$src),
1902          (LWZ8 DForm:$src)>;
1903def : Pat<(extloadi32 XForm:$src),
1904          (LWZX8 XForm:$src)>;
1905
1906// Standard shifts.  These are represented separately from the real shifts above
1907// so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1908// amounts.
1909def : Pat<(sra i64:$rS, i32:$rB),
1910          (SRAD $rS, $rB)>;
1911def : Pat<(srl i64:$rS, i32:$rB),
1912          (SRD $rS, $rB)>;
1913def : Pat<(shl i64:$rS, i32:$rB),
1914          (SLD $rS, $rB)>;
1915
1916// SUBFIC
1917def : Pat<(sub imm64SExt16:$imm, i64:$in),
1918          (SUBFIC8 $in, imm:$imm)>;
1919
1920// SHL/SRL
1921def : Pat<(shl i64:$in, (i32 imm:$imm)),
1922          (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1923def : Pat<(srl i64:$in, (i32 imm:$imm)),
1924          (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1925
1926// ROTL
1927def : Pat<(rotl i64:$in, i32:$sh),
1928          (RLDCL $in, $sh, 0)>;
1929def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1930          (RLDICL $in, imm:$imm, 0)>;
1931
1932// Hi and Lo for Darwin Global Addresses.
1933def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1934def : Pat<(PPClo tglobaladdr:$in, 0), (LI8  tglobaladdr:$in)>;
1935def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1936def : Pat<(PPClo tconstpool:$in , 0), (LI8  tconstpool:$in)>;
1937def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1938def : Pat<(PPClo tjumptable:$in , 0), (LI8  tjumptable:$in)>;
1939def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1940def : Pat<(PPClo tblockaddress:$in, 0), (LI8  tblockaddress:$in)>;
1941def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1942          (ADDIS8 $in, tglobaltlsaddr:$g)>;
1943def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1944          (ADDI8 $in, tglobaltlsaddr:$g)>;
1945def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1946          (ADDIS8 $in, tglobaladdr:$g)>;
1947def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1948          (ADDIS8 $in, tconstpool:$g)>;
1949def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1950          (ADDIS8 $in, tjumptable:$g)>;
1951def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1952          (ADDIS8 $in, tblockaddress:$g)>;
1953
1954// AIX 64-bit small code model TLS access.
1955// This is used for global dynamic accesses when loading the region handle and
1956// variable offset, and also for local-exec accesses to load the offset of a
1957// TLS variable from the TOC, prior to adding it to r13.
1958def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)),
1959          (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>;
1960
1961// The following pattern matches 64-bit local-exec TLS accesses on AIX.
1962// PPCaddTls is used in local-exec accesses in order to:
1963//   - Get the address of a variable (adding the variable offset to the thread
1964//     pointer in r13).
1965//   - Create an opportunity to optimize the user of the loaded address.
1966def : Pat<(PPCaddTls i64:$in, i64:$addr),
1967          (ADD8TLS $in, $addr)>;
1968
1969// 64-bits atomic loads and stores
1970def : Pat<(atomic_load_64 DSForm:$src), (LD  memrix:$src)>;
1971def : Pat<(atomic_load_64 XForm:$src),  (LDX memrr:$src)>;
1972
1973def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD  g8rc:$val, memrix:$ptr)>;
1974def : Pat<(atomic_store_64 XForm:$ptr,  i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
1975
1976let Predicates = [IsISA3_0, In64BitMode] in {
1977def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)),
1978          (i64 (SETB8 (CMPEQB $a, $b)))>;
1979def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)),
1980          (i64 (SETB8 (CMPD $a, $b)))>;
1981def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)),
1982          (i64 (MADDHD $a, $b, $c))>;
1983def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)),
1984          (i64 (MADDHDU $a, $b, $c))>;
1985def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)),
1986          (i64 (MADDLD8 $a, $b, $c))>;
1987}
1988
1989let Predicates = [In64BitMode] in {
1990def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),
1991          (i64 (MULHD $a, $b))>;
1992def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),
1993          (i64 (MULHDU $a, $b))>;
1994def : Pat<(int_ppc_load8r ForceXForm:$ptr),
1995          (LDBRX ForceXForm:$ptr)>;
1996def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr),
1997          (STDBRX g8rc:$a, ForceXForm:$ptr)>;
1998}
1999
2000def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)),
2001          (i64 (CMPB8 $a, $b))>;
2002
2003let Predicates = [IsISA3_0] in {
2004// DARN (deliver random number)
2005// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
2006def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>;
2007def : Pat<(int_ppc_darn), (DARN 1)>;
2008def : Pat<(int_ppc_darnraw), (DARN 2)>;
2009
2010class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
2011                   InstrItinClass itin, list<dag> pattern>
2012  : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L),
2013                 !strconcat(opc, " $RA, $RB"), itin, pattern>{
2014   let L = 1;
2015}
2016
2017class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
2018                   InstrItinClass itin, list<dag> pattern>
2019  : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L),
2020                 !strconcat(opc, " $RA, $RB, $L"), itin, pattern>;
2021
2022let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
2023def CP_COPY8   : X_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
2024def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
2025}
2026
2027// SLB Invalidate Entry Global
2028def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RST, gprc:$RB),
2029                      "slbieg $RST, $RB", IIC_SprSLBIEG, []>;
2030// SLB Synchronize
2031def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
2032
2033} // IsISA3_0
2034
2035def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
2036          (STDCX g8rc:$A, ForceXForm:$dst)>;
2037def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8),
2038          (STDCX g8rc:$A, ForceXForm:$dst)>;
2039
2040def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
2041          (MFSPR8 $SPR)>;
2042def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
2043          (MTSPR8 $SPR, $RT)>;
2044