1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, 182 isCodeGenOnly = 1, Uses = [RM] in { 183 // Convenient aliases for call instructions 184 def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), 185 "bl $func", IIC_BrB, []>; // See Pat patterns below. 186 187 def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 188 "bla $func", IIC_BrB, [(PPCcall_rm (i64 imm:$func))]>; 189 def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 190 (outs), (ins calltarget:$func), 191 "bl $func\n\tnop", IIC_BrB, []>; 192 193 def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, 194 (outs), (ins abscalltarget:$func), 195 "bla $func\n\tnop", IIC_BrB, 196 [(PPCcall_nop_rm (i64 imm:$func))]>; 197 let Predicates = [PCRelativeMemops] in { 198 // BL8_NOTOC means that the caller does not use the TOC pointer and if 199 // it does use R2 then it is just a caller saved register. Therefore it is 200 // safe to emit only the bl and not the nop for this instruction. The 201 // linker will not try to restore R2 after the call. 202 def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), 203 (ins calltarget:$func), 204 "bl $func", IIC_BrB, []>; 205 } 206 let Uses = [CTR8, RM] in { 207 let isPredicable = 1 in 208 def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 209 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 210 Requires<[In64BitMode]>; 211 } 212} 213 214let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 215 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 216 def BCTRL8_LDinto_toc : 217 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 218 (ins memrix:$src), 219 "bctrl\n\tld 2, $src", IIC_BrB, 220 [(PPCbctrl_load_toc iaddrX4:$src)]>, 221 Requires<[In64BitMode]>; 222} 223 224let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 225 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in { 226 def BCTRL8_LDinto_toc_RM : 227 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 228 (ins memrix:$src), 229 "bctrl\n\tld 2, $src", IIC_BrB, 230 [(PPCbctrl_load_toc_rm iaddrX4:$src)]>, 231 Requires<[In64BitMode]>; 232} 233 234} // Interpretation64Bit 235 236// FIXME: Duplicating this for the asm parser should be unnecessary, but the 237// previous definition must be marked as CodeGen only to prevent decoding 238// conflicts. 239let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in 240let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 241def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 242 "bl $func", IIC_BrB, []>; 243 244// Calls 245def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 246 (BL8 tglobaladdr:$dst)>; 247def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 248 (BL8_NOP tglobaladdr:$dst)>; 249 250def : Pat<(PPCcall (i64 texternalsym:$dst)), 251 (BL8 texternalsym:$dst)>; 252def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 253 (BL8_NOP texternalsym:$dst)>; 254 255def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 256 (BL8_NOTOC tglobaladdr:$dst)>; 257def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 258 (BL8_NOTOC texternalsym:$dst)>; 259 260def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)), 261 (BL8_RM tglobaladdr:$dst)>; 262def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)), 263 (BL8_NOP_RM tglobaladdr:$dst)>; 264 265def : Pat<(PPCcall_rm (i64 texternalsym:$dst)), 266 (BL8_RM texternalsym:$dst)>; 267def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)), 268 (BL8_NOP_RM texternalsym:$dst)>; 269 270def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)), 271 (BL8_NOTOC_RM tglobaladdr:$dst)>; 272def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)), 273 (BL8_NOTOC_RM texternalsym:$dst)>; 274 275// Calls for AIX 276def : Pat<(PPCcall (i64 mcsym:$dst)), 277 (BL8 mcsym:$dst)>; 278def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 279 (BL8_NOP mcsym:$dst)>; 280 281def : Pat<(PPCcall_rm (i64 mcsym:$dst)), 282 (BL8_RM mcsym:$dst)>; 283def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)), 284 (BL8_NOP_RM mcsym:$dst)>; 285 286// Atomic operations 287// FIXME: some of these might be used with constant operands. This will result 288// in constant materialization instructions that may be redundant. We currently 289// clean this up in PPCMIPeephole with calls to 290// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 291// in the first place. 292let Defs = [CR0] in { 293 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 294 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 295 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 296 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 297 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 298 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 299 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 300 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 301 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 302 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 303 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 304 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 305 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 306 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 307 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 308 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 309 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 310 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 311 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 312 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 313 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 314 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 315 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 316 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 317 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 318 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 319 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 320 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 321 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 322 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 323 324 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 325 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 326 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 327 328 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 329 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 330 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 331} 332 333// Instructions to support atomic operations 334let mayLoad = 1, hasSideEffects = 0 in { 335def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 336 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 337// TODO: Add scheduling info. 338let hasNoSchedulingInfo = 1 in 339def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 340 "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; 341 342// Instruction to support lock versions of atomics 343// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 344def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 345 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 346// TODO: Add scheduling info. 347let hasNoSchedulingInfo = 1 in 348// FIXME: We have to seek a way to remove isRecordForm since 349// LQARXL is not really altering CR0. 350def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 351 "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, 352 isPPC64, isRecordForm; 353 354let hasExtraDefRegAllocReq = 1 in 355def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 356 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 357 Requires<[IsISA3_0]>; 358} 359 360let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 361def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 362 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 363// TODO: Add scheduling info. 364let hasNoSchedulingInfo = 1 in 365def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), 366 "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, 367 isPPC64, isRecordForm; 368} 369 370def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 371 (ins g8prc:$src), 372 "#SPLIT_QUADWORD", []>; 373class AtomicRMW128<string asmstr> 374 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 375 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 376 asmstr, []>; 377// We have to keep values in MI's uses during LL/SC looping as they are, 378// so set both $RTp and $scratch earlyclobber. 379let mayStore = 1, mayLoad = 1, 380 Defs = [CR0], 381 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 382// Atomic pseudo instructions expanded post-ra. 383def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 384def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 385def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 386def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 387def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 388def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 389def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 390 391def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 392 (outs g8prc:$RTp, g8prc:$scratch), 393 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 394 g8rc:$new_lo, g8rc:$new_hi), 395 "#ATOMIC_CMP_SWAP_I128", []>; 396} 397 398def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr, 399 i64:$incr_lo, 400 i64:$incr_hi), 401 (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr, 402 g8rc:$incr_lo, 403 g8rc:$incr_hi))>; 404def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr, 405 i64:$incr_lo, 406 i64:$incr_hi), 407 (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr, 408 g8rc:$incr_lo, 409 g8rc:$incr_hi))>; 410def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr, 411 i64:$incr_lo, 412 i64:$incr_hi), 413 (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr, 414 g8rc:$incr_lo, 415 g8rc:$incr_hi))>; 416def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr, 417 i64:$incr_lo, 418 i64:$incr_hi), 419 (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr, 420 g8rc:$incr_lo, 421 g8rc:$incr_hi))>; 422def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr, 423 i64:$incr_lo, 424 i64:$incr_hi), 425 (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr, 426 g8rc:$incr_lo, 427 g8rc:$incr_hi))>; 428def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr, 429 i64:$incr_lo, 430 i64:$incr_hi), 431 (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr, 432 g8rc:$incr_lo, 433 g8rc:$incr_hi))>; 434def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr, 435 i64:$incr_lo, 436 i64:$incr_hi), 437 (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr, 438 g8rc:$incr_lo, 439 g8rc:$incr_hi))>; 440def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 441 i64:$cmp_lo, 442 i64:$cmp_hi, 443 i64:$new_lo, 444 i64:$new_hi), 445 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 446 memrr:$ptr, 447 g8rc:$cmp_lo, 448 g8rc:$cmp_hi, 449 g8rc:$new_lo, 450 g8rc:$new_hi))>; 451 452let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 453def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 454 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 455 Requires<[IsISA3_0]>; 456 457let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 458let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 459def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 460 (ins calltarget:$dst, i32imm:$offset), 461 "#TC_RETURNd8 $dst $offset", 462 []>; 463 464let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 465def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 466 "#TC_RETURNa8 $func $offset", 467 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 468 469let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 470def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 471 "#TC_RETURNr8 $dst $offset", 472 []>; 473 474let hasSideEffects = 0 in { 475let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 476 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 477def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 478 []>, 479 Requires<[In64BitMode]>; 480 481let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 482 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 483def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 484 "b $dst", IIC_BrB, 485 []>; 486 487let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 488 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 489def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 490 "ba $dst", IIC_BrB, 491 []>; 492} 493} // Interpretation64Bit 494 495def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 496 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 497 498def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 499 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 500 501def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 502 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 503 504 505// 64-bit CR instructions 506let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 507let hasSideEffects = 0 in { 508// mtocrf's input needs to be prepared by shifting by an amount dependent 509// on the cr register selected. Thus, post-ra anti-dep breaking must not 510// later change that register assignment. 511let hasExtraDefRegAllocReq = 1 in { 512def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 513 "mtocrf $FXM, $ST", IIC_BrMCRX>, 514 PPC970_DGroup_First, PPC970_Unit_CRU; 515 516// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 517// is dependent on the cr fields being set. 518def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 519 "mtcrf $FXM, $rS", IIC_BrMCRX>, 520 PPC970_MicroCode, PPC970_Unit_CRU; 521} // hasExtraDefRegAllocReq = 1 522 523// mfocrf's input needs to be prepared by shifting by an amount dependent 524// on the cr register selected. Thus, post-ra anti-dep breaking must not 525// later change that register assignment. 526let hasExtraSrcRegAllocReq = 1 in { 527def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 528 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 529 PPC970_DGroup_First, PPC970_Unit_CRU; 530 531// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 532// is dependent on the cr fields being copied. 533def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 534 "mfcr $rT", IIC_SprMFCR>, 535 PPC970_MicroCode, PPC970_Unit_CRU; 536} // hasExtraSrcRegAllocReq = 1 537} // hasSideEffects = 0 538 539// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 540// is not. 541let hasSideEffects = 1 in { 542 let Defs = [CTR8] in 543 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 544 "#EH_SJLJ_SETJMP64", 545 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 546 Requires<[In64BitMode]>; 547} 548 549let hasSideEffects = 1, isBarrier = 1 in { 550 let isTerminator = 1 in 551 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 552 "#EH_SJLJ_LONGJMP64", 553 [(PPCeh_sjlj_longjmp addr:$buf)]>, 554 Requires<[In64BitMode]>; 555} 556 557def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 558 "mfspr $RT, $SPR", IIC_SprMFSPR>; 559def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 560 "mtspr $SPR, $RT", IIC_SprMTSPR>; 561 562 563//===----------------------------------------------------------------------===// 564// 64-bit SPR manipulation instrs. 565 566let Uses = [CTR8] in { 567def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 568 "mfctr $rT", IIC_SprMFSPR>, 569 PPC970_DGroup_First, PPC970_Unit_FXU; 570} 571let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 572def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 573 "mtctr $rS", IIC_SprMTSPR>, 574 PPC970_DGroup_First, PPC970_Unit_FXU; 575} 576// MTCTR[8|]loop must be inside a loop-preheader, duplicating 577// the loop-preheader block will break this assumption. 578let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in { 579let Pattern = [(int_set_loop_iterations i64:$rS)] in 580def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 581 "mtctr $rS", IIC_SprMTSPR>, 582 PPC970_DGroup_First, PPC970_Unit_FXU; 583} 584 585let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR8], Defs = [CTR8] in 586def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), 587 "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>; 588 589let Pattern = [(set i64:$rT, readcyclecounter)] in 590def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 591 "mfspr $rT, 268", IIC_SprMFTB>, 592 PPC970_DGroup_First, PPC970_Unit_FXU; 593// Note that encoding mftb using mfspr is now the preferred form, 594// and has been since at least ISA v2.03. The mftb instruction has 595// now been phased out. Using mfspr, however, is known not to work on 596// the POWER3. 597 598let Defs = [X1], Uses = [X1] in 599def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 600 [(set i64:$result, 601 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 602def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 603 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 604// Probed alloca to support stack clash protection. 605let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 606def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 607 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 608 [(set i64:$result, 609 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 610def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 611 g8rc:$fp, g8rc:$actual_negsize), 612 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 613def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 614 g8rc:$fp, g8rc:$actual_negsize), 615 (ins g8rc:$negsize, memri:$fpsi), 616 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 617 RegConstraint<"$actual_negsize = $negsize">; 618def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 619 (ins i64imm:$stacksize), 620 "#PROBED_STACKALLOC_64", []>; 621} 622 623let hasSideEffects = 0 in { 624let Defs = [LR8] in { 625def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 626 "mtlr $rS", IIC_SprMTSPR>, 627 PPC970_DGroup_First, PPC970_Unit_FXU; 628} 629let Uses = [LR8] in { 630def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 631 "mflr $rT", IIC_SprMFSPR>, 632 PPC970_DGroup_First, PPC970_Unit_FXU; 633} 634} // Interpretation64Bit 635} 636 637//===----------------------------------------------------------------------===// 638// Fixed point instructions. 639// 640 641let PPC970_Unit = 1 in { // FXU Operations. 642let Interpretation64Bit = 1 in { 643let hasSideEffects = 0 in { 644let isCodeGenOnly = 1 in { 645 646let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 647def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 648 "li $rD, $imm", IIC_IntSimple, 649 [(set i64:$rD, imm64SExt16:$imm)]>, SExt32To64; 650def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 651 "lis $rD, $imm", IIC_IntSimple, 652 [(set i64:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64; 653} 654 655// Logical ops. 656let isCommutable = 1 in { 657defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 658 "nand", "$rA, $rS, $rB", IIC_IntSimple, 659 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 660defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 661 "and", "$rA, $rS, $rB", IIC_IntSimple, 662 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 663} // isCommutable 664defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 665 "andc", "$rA, $rS, $rB", IIC_IntSimple, 666 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 667let isCommutable = 1 in { 668defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 669 "or", "$rA, $rS, $rB", IIC_IntSimple, 670 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 671defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 672 "nor", "$rA, $rS, $rB", IIC_IntSimple, 673 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 674} // isCommutable 675defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 676 "orc", "$rA, $rS, $rB", IIC_IntSimple, 677 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 678let isCommutable = 1 in { 679defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 680 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 681 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 682defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 683 "xor", "$rA, $rS, $rB", IIC_IntSimple, 684 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 685} // let isCommutable = 1 686 687// Logical ops with immediate. 688let Defs = [CR0] in { 689def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 690 "andi. $dst, $src1, $src2", IIC_IntGeneral, 691 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 692 isRecordForm, SExt32To64, ZExt32To64; 693def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 694 "andis. $dst, $src1, $src2", IIC_IntGeneral, 695 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 696 isRecordForm, ZExt32To64; 697} 698def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 699 "ori $dst, $src1, $src2", IIC_IntSimple, 700 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 701def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 702 "oris $dst, $src1, $src2", IIC_IntSimple, 703 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 704def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 705 "xori $dst, $src1, $src2", IIC_IntSimple, 706 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 707def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 708 "xoris $dst, $src1, $src2", IIC_IntSimple, 709 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 710 711let isCommutable = 1 in 712defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 713 "add", "$rT, $rA, $rB", IIC_IntSimple, 714 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 715// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 716// initial-exec thread-local storage model. We need to forbid r0 here - 717// while it works for add just fine, the linker can relax this to local-exec 718// addi, which won't work for r0. 719def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 720 "add $rT, $rA, $rB", IIC_IntSimple, 721 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 722let mayLoad = 1 in { 723def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 724 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 725def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 726 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 727def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 728 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 729def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 730 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 731def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 732 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 733def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 734 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 735def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 736 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 737 738} 739 740let mayStore = 1 in { 741def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 742 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 743 PPC970_DGroup_Cracked; 744def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 745 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 746 PPC970_DGroup_Cracked; 747def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 748 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 749 PPC970_DGroup_Cracked; 750def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 751 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 752 PPC970_DGroup_Cracked; 753def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 754 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 755 PPC970_DGroup_Cracked; 756def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 757 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 758 PPC970_DGroup_Cracked; 759def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 760 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 761 PPC970_DGroup_Cracked; 762 763} 764 765let isCommutable = 1 in 766defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 767 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 768 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 769 PPC970_DGroup_Cracked; 770 771let Defs = [CARRY] in 772def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 773 "addic $rD, $rA, $imm", IIC_IntGeneral, 774 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 775def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 776 "addi $rD, $rA, $imm", IIC_IntSimple, 777 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 778def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 779 "addis $rD, $rA, $imm", IIC_IntSimple, 780 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 781 782def LA8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$sym), 783 "la $rD, $sym($rA)", IIC_IntGeneral, 784 [(set i64:$rD, (add i64:$rA, 785 (PPClo tglobaladdr:$sym, 0)))]>; 786 787let Defs = [CARRY] in { 788def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 789 "subfic $rD, $rA, $imm", IIC_IntGeneral, 790 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 791} 792defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 793 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 794 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 795 PPC970_DGroup_Cracked; 796defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 797 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 798 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 799defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 800 "neg", "$rT, $rA", IIC_IntSimple, 801 [(set i64:$rT, (ineg i64:$rA))]>; 802let Uses = [CARRY] in { 803let isCommutable = 1 in 804defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 805 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 806 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 807defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 808 "addme", "$rT, $rA", IIC_IntGeneral, 809 [(set i64:$rT, (adde i64:$rA, -1))]>; 810defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 811 "addze", "$rT, $rA", IIC_IntGeneral, 812 [(set i64:$rT, (adde i64:$rA, 0))]>; 813defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 814 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 815 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 816defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 817 "subfme", "$rT, $rA", IIC_IntGeneral, 818 [(set i64:$rT, (sube -1, i64:$rA))]>; 819defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 820 "subfze", "$rT, $rA", IIC_IntGeneral, 821 [(set i64:$rT, (sube 0, i64:$rA))]>; 822} 823} // isCodeGenOnly 824 825// FIXME: Duplicating this for the asm parser should be unnecessary, but the 826// previous definition must be marked as CodeGen only to prevent decoding 827// conflicts. 828let isAsmParserOnly = 1 in { 829def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 830 "add $rT, $rA, $rB", IIC_IntSimple, []>; 831 832let mayLoad = 1 in { 833def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 834 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 835def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 836 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 837def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 838 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 839def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 840 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 841} 842 843let mayStore = 1 in { 844def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 845 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 846 PPC970_DGroup_Cracked; 847def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 848 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 849 PPC970_DGroup_Cracked; 850def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 851 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 852 PPC970_DGroup_Cracked; 853def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 854 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 855 PPC970_DGroup_Cracked; 856} 857} 858 859let isCommutable = 1 in { 860defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 861 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 862 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 863defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 864 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 865 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 866} // isCommutable 867} 868} // Interpretation64Bit 869 870let isCompare = 1, hasSideEffects = 0 in { 871 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 872 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 873 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 874 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 875 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 876 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 877 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 878 "cmpldi $dst, $src1, $src2", 879 IIC_IntCompare>, isPPC64; 880 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 881 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 882 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 883 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 884 Requires<[IsISA3_0]>; 885 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 886 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 887 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 888} 889 890let hasSideEffects = 0 in { 891defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 892 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 893 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 894defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 895 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 896 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 897defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 898 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 899 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 900 901let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 902defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 903 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>, 904 ZExt32To64, SExt32To64; 905defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 906 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 907 Requires<[IsISA3_0]>, ZExt32To64, SExt32To64; 908 909defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 910 "extsb", "$rA, $rS", IIC_IntSimple, 911 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>, SExt32To64; 912defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 913 "extsh", "$rA, $rS", IIC_IntSimple, 914 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>, SExt32To64; 915 916defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 917 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64; 918defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 919 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64; 920} // Interpretation64Bit 921 922// For fast-isel: 923let isCodeGenOnly = 1 in { 924def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 925 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64, 926 SExt32To64; 927def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 928 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64, 929 SExt32To64; 930} // isCodeGenOnly for fast-isel 931 932defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 933 "extsw", "$rA, $rS", IIC_IntSimple, 934 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64, 935 SExt32To64; 936let Interpretation64Bit = 1, isCodeGenOnly = 1 in 937defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 938 "extsw", "$rA, $rS", IIC_IntSimple, 939 [(set i64:$rA, (sext i32:$rS))]>, isPPC64, 940 SExt32To64; 941let isCodeGenOnly = 1 in 942def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 943 "extsw $rA, $rS", IIC_IntSimple, 944 []>, isPPC64; 945 946defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 947 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 948 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 949 950let Interpretation64Bit = 1, isCodeGenOnly = 1 in 951defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 952 (ins gprc:$rS, u6imm:$SH), 953 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 954 [(set i64:$rA, 955 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 956 isPPC64, Requires<[IsISA3_0]>; 957 958defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 959 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 960 []>, isPPC64, Requires<[IsISA3_0]>; 961 962// For fast-isel: 963let isCodeGenOnly = 1, Defs = [CARRY] in 964def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 965 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 966 967defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 968 "cntlzd", "$rA, $rS", IIC_IntGeneral, 969 [(set i64:$rA, (ctlz i64:$rS))]>, 970 ZExt32To64, SExt32To64; 971defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 972 "cnttzd", "$rA, $rS", IIC_IntGeneral, 973 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>, 974 ZExt32To64, SExt32To64; 975def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 976 "popcntd $rA, $rS", IIC_IntGeneral, 977 [(set i64:$rA, (ctpop i64:$rS))]>, 978 ZExt32To64, SExt32To64; 979def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 980 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 981 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 982 isPPC64, Requires<[HasBPERMD]>; 983 984let isCodeGenOnly = 1, isCommutable = 1 in 985def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 986 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 987 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 988 989// popcntw also does a population count on the high 32 bits (storing the 990// results in the high 32-bits of the output). We'll ignore that here (which is 991// safe because we never separately use the high part of the 64-bit registers). 992def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 993 "popcntw $rA, $rS", IIC_IntGeneral, 994 [(set i32:$rA, (ctpop i32:$rS))]>; 995 996let isCodeGenOnly = 1 in 997def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 998 "popcntb $rA, $rS", IIC_IntGeneral, 999 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 1000 1001defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1002 "divd", "$rT, $rA, $rB", IIC_IntDivD, 1003 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 1004defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1005 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 1006 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 1007defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1008 "divde", "$rT, $rA, $rB", IIC_IntDivD, 1009 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 1010 isPPC64, Requires<[HasExtDiv]>; 1011 1012let Predicates = [IsISA3_0] in { 1013def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1014 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1015def MADDHDU : VAForm_1a<49, 1016 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1017 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1018def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 1019 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1020 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 1021 isPPC64; 1022let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1023 def MADDLD8 : VAForm_1a<51, 1024 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1025 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1026 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 1027 isPPC64; 1028 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 1029 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64; 1030} 1031def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 1032 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 1033def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1034 "modsd $rT, $rA, $rB", IIC_IntDivW, 1035 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 1036def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1037 "modud $rT, $rA, $rB", IIC_IntDivW, 1038 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 1039} 1040 1041defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1042 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 1043 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 1044 isPPC64, Requires<[HasExtDiv]>; 1045let isCommutable = 1 in 1046defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1047 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 1048 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 1049let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1050def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 1051 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1052 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 1053} 1054 1055let hasSideEffects = 1 in { 1056def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 1057 "darn $RT, $L", IIC_LdStLD>, isPPC64; 1058} 1059 1060let hasSideEffects = 0 in { 1061defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 1062 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1063 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1064 []>, isPPC64, RegConstraint<"$rSi = $rA">, 1065 NoEncode<"$rSi">; 1066 1067// Rotate instructions. 1068defm RLDCL : MDSForm_1r<30, 8, 1069 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 1070 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 1071 []>, isPPC64; 1072defm RLDCR : MDSForm_1r<30, 9, 1073 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 1074 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 1075 []>, isPPC64; 1076defm RLDICL : MDForm_1r<30, 0, 1077 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1078 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1079 []>, isPPC64; 1080// For fast-isel: 1081let isCodeGenOnly = 1 in 1082def RLDICL_32_64 : MDForm_1<30, 0, 1083 (outs g8rc:$rA), 1084 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1085 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1086 []>, isPPC64; 1087// End fast-isel. 1088let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1089defm RLDICL_32 : MDForm_1r<30, 0, 1090 (outs gprc:$rA), 1091 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1092 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1093 []>, isPPC64; 1094defm RLDICR : MDForm_1r<30, 1, 1095 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1096 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1097 []>, isPPC64; 1098let isCodeGenOnly = 1 in 1099def RLDICR_32 : MDForm_1<30, 1, 1100 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1101 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1102 []>, isPPC64; 1103defm RLDIC : MDForm_1r<30, 2, 1104 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1105 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1106 []>, isPPC64; 1107 1108let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1109defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 1110 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1111 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 1112 []>; 1113 1114defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 1115 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 1116 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 1117 []>; 1118 1119// RLWIMI can be commuted if the rotate amount is zero. 1120let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1121defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 1122 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 1123 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 1124 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1125 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 1126 1127let isSelect = 1 in 1128def ISEL8 : AForm_4<31, 15, 1129 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 1130 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 1131 []>; 1132} // Interpretation64Bit 1133} // hasSideEffects = 0 1134} // End FXU Operations. 1135 1136def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1137def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1138 1139def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1140def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1141 1142def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1143def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1144 1145def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1146 1147def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1148def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1149def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1150def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1151 1152def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1153def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1154def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1155def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1156def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1157def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1158 1159def : InstAlias<"isellt $rT, $rA, $rB", 1160 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1161def : InstAlias<"iselgt $rT, $rA, $rB", 1162 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1163def : InstAlias<"iseleq $rT, $rA, $rB", 1164 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1165 1166def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1167def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1168 1169def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1170def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1171 1172def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1173def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1174 1175//Disable this alias on AIX for now because as does not support them. 1176let Predicates = [ModernAs] in { 1177 1178def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1179def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1180 1181def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1182def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1183 1184def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1185def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1186 1187def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1188def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1189 1190def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1191def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1192 1193def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1194def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1195 1196def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1197def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1198 1199def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1200def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1201 1202def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1203def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1204 1205def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1206def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1207 1208def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1209def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1210 1211def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1212def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1213 1214def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1215def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1216 1217def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1218def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1219 1220foreach SPRG = 0-3 in { 1221 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1222 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1223 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1224 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1225} 1226 1227def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1228def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1229 1230def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1231def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1232 1233def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1234 1235def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1236def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1237 1238} 1239 1240//===----------------------------------------------------------------------===// 1241// Load/Store instructions. 1242// 1243 1244 1245// Sign extending loads. 1246let PPC970_Unit = 2 in { 1247let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1248def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1249 "lha $rD, $src", IIC_LdStLHA, 1250 [(set i64:$rD, (sextloadi16 DForm:$src))]>, 1251 PPC970_DGroup_Cracked, SExt32To64; 1252def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1253 "lwa $rD, $src", IIC_LdStLWA, 1254 [(set i64:$rD, 1255 (sextloadi32 DSForm:$src))]>, isPPC64, 1256 PPC970_DGroup_Cracked, SExt32To64; 1257let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1258def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1259 "lhax $rD, $src", IIC_LdStLHA, 1260 [(set i64:$rD, (sextloadi16 XForm:$src))]>, 1261 PPC970_DGroup_Cracked, SExt32To64; 1262def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1263 "lwax $rD, $src", IIC_LdStLHA, 1264 [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, 1265 PPC970_DGroup_Cracked, SExt32To64; 1266// For fast-isel: 1267let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1268def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1269 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1270 PPC970_DGroup_Cracked, SExt32To64; 1271def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1272 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1273 PPC970_DGroup_Cracked, SExt32To64; 1274} // end fast-isel isCodeGenOnly 1275 1276// Update forms. 1277let mayLoad = 1, hasSideEffects = 0 in { 1278let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1279def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1280 (ins memri:$addr), 1281 "lhau $rD, $addr", IIC_LdStLHAU, 1282 []>, RegConstraint<"$addr.reg = $ea_result">, 1283 NoEncode<"$ea_result">; 1284// NO LWAU! 1285 1286let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1287def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1288 (ins memrr:$addr), 1289 "lhaux $rD, $addr", IIC_LdStLHAUX, 1290 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1291 NoEncode<"$ea_result">; 1292def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1293 (ins memrr:$addr), 1294 "lwaux $rD, $addr", IIC_LdStLHAUX, 1295 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1296 NoEncode<"$ea_result">, isPPC64; 1297} 1298} 1299 1300let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1301// Zero extending loads. 1302let PPC970_Unit = 2 in { 1303def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1304 "lbz $rD, $src", IIC_LdStLoad, 1305 [(set i64:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64, 1306 SExt32To64; 1307def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1308 "lhz $rD, $src", IIC_LdStLoad, 1309 [(set i64:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64, 1310 SExt32To64; 1311def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1312 "lwz $rD, $src", IIC_LdStLoad, 1313 [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64, 1314 ZExt32To64; 1315 1316def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1317 "lbzx $rD, $src", IIC_LdStLoad, 1318 [(set i64:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64, 1319 SExt32To64; 1320def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1321 "lhzx $rD, $src", IIC_LdStLoad, 1322 [(set i64:$rD, (zextloadi16 XForm:$src))]>, 1323 ZExt32To64, SExt32To64; 1324def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1325 "lwzx $rD, $src", IIC_LdStLoad, 1326 [(set i64:$rD, (zextloadi32 XForm:$src))]>, 1327 ZExt32To64; 1328 1329 1330// Update forms. 1331let mayLoad = 1, hasSideEffects = 0 in { 1332def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1333 (ins memri:$addr), 1334 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1335 []>, RegConstraint<"$addr.reg = $ea_result">, 1336 NoEncode<"$ea_result">; 1337def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1338 (ins memri:$addr), 1339 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1340 []>, RegConstraint<"$addr.reg = $ea_result">, 1341 NoEncode<"$ea_result">; 1342def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1343 (ins memri:$addr), 1344 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1345 []>, RegConstraint<"$addr.reg = $ea_result">, 1346 NoEncode<"$ea_result">; 1347 1348def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1349 (ins memrr:$addr), 1350 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1351 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1352 NoEncode<"$ea_result">; 1353def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1354 (ins memrr:$addr), 1355 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1356 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1357 NoEncode<"$ea_result">; 1358def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1359 (ins memrr:$addr), 1360 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1361 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1362 NoEncode<"$ea_result">; 1363} 1364} 1365} // Interpretation64Bit 1366 1367 1368// Full 8-byte loads. 1369let PPC970_Unit = 2 in { 1370def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1371 "ld $rD, $src", IIC_LdStLD, 1372 [(set i64:$rD, (load DSForm:$src))]>, isPPC64; 1373// The following four definitions are selected for small code model only. 1374// Otherwise, we need to create two instructions to form a 32-bit offset, 1375// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1376def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1377 "#LDtoc", 1378 [(set i64:$rD, 1379 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1380def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1381 "#LDtocJTI", 1382 [(set i64:$rD, 1383 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1384def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1385 "#LDtocCPT", 1386 [(set i64:$rD, 1387 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1388def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1389 "#LDtocCPT", 1390 [(set i64:$rD, 1391 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1392 1393def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1394 "ldx $rD, $src", IIC_LdStLD, 1395 [(set i64:$rD, (load XForm:$src))]>, isPPC64; 1396 1397let Predicates = [IsISA2_06] in { 1398def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1399 "ldbrx $rD, $src", IIC_LdStLoad, 1400 [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; 1401} 1402 1403let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1404def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1405 "lhbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64; 1406def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1407 "lwbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64; 1408} 1409 1410let mayLoad = 1, hasSideEffects = 0 in { 1411def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1412 (ins memrix:$addr), 1413 "ldu $rD, $addr", IIC_LdStLDU, 1414 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1415 NoEncode<"$ea_result">; 1416 1417def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1418 (ins memrr:$addr), 1419 "ldux $rD, $addr", IIC_LdStLDUX, 1420 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1421 NoEncode<"$ea_result">, isPPC64; 1422} 1423 1424let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1425// Full 16-byte load. 1426// Early clobber $RTp to avoid assigned to the same register as RA. 1427// TODO: Add scheduling info. 1428def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1429 (outs g8prc:$RTp), 1430 (ins memrix16:$src), 1431 "lq $RTp, $src", IIC_LdStLQ, 1432 []>, 1433 RegConstraint<"@earlyclobber $RTp">, 1434 isPPC64; 1435// We don't really have LQX in the ISA, make a pseudo one so that we can 1436// handle x-form during isel. Make it pre-ra may expose 1437// oppotunities to some opts(CSE, LICM and etc.) for the result of adding 1438// RA and RB. 1439def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), 1440 (ins memrr:$src), "#LQX_PSEUDO", []>; 1441 1442def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1443 "#RESTORE_QUADWORD", []>; 1444} 1445 1446} 1447 1448def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src), 1449 (SPLIT_QUADWORD (LQ memrix16:$src))>; 1450 1451def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src), 1452 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>; 1453 1454// Support for medium and large code model. 1455let hasSideEffects = 0 in { 1456let isReMaterializable = 1 in { 1457def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1458 "#ADDIStocHA8", []>, isPPC64; 1459def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1460 "#ADDItocL", []>, isPPC64; 1461} 1462 1463// Local Data Transform 1464def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1465 "#ADDItoc8", 1466 [(set i64:$rD, 1467 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1468 1469let mayLoad = 1 in 1470def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1471 "#LDtocL", []>, isPPC64; 1472} 1473 1474// Support for thread-local storage. 1475def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1476 "#ADDISgotTprelHA", 1477 [(set i64:$rD, 1478 (PPCaddisGotTprelHA i64:$reg, 1479 tglobaltlsaddr:$disp))]>, 1480 isPPC64; 1481def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1482 "#LDgotTprelL", 1483 [(set i64:$rD, 1484 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1485 isPPC64; 1486 1487let Defs = [CR7], Itinerary = IIC_LdStSync in 1488def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1489 1490def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1491 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1492def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1493 "#ADDIStlsgdHA", 1494 [(set i64:$rD, 1495 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1496 isPPC64; 1497def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1498 "#ADDItlsgdL", 1499 [(set i64:$rD, 1500 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1501 isPPC64; 1502 1503class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1504 asmstr, 1505 [(set i64:$rD, 1506 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1507 isPPC64; 1508class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1509 asmstr, 1510 [(set i64:$rD, 1511 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1512 isPPC64; 1513 1514let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1515// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1516// explicitly defined when this op is created, so not mentioned here. 1517// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1518// correct because the branch select pass is relying on it. 1519let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1520def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1521let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1522def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1523 1524// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1525// explicitly defined when this op is created, so not mentioned here. 1526let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1527def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1528let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1529def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1530 1531// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1532// offset and region handle respectively. The call is not followed by a nop 1533// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1534// manual mentions this exact set of registers as the clobbered set, others 1535// are guaranteed not to be clobbered. 1536let Defs = [X0,X4,X5,X11,LR8,CR0] in 1537def GETtlsADDR64AIX : 1538 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1539 "GETtlsADDR64AIX", 1540 [(set i64:$rD, 1541 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1542} 1543 1544// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1545// are true defines while the rest of the Defs are clobbers. 1546let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1547 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1548 in 1549def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1550 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1551 "#ADDItlsgdLADDR", 1552 [(set i64:$rD, 1553 (PPCaddiTlsgdLAddr i64:$reg, 1554 tglobaltlsaddr:$disp, 1555 tglobaltlsaddr:$sym))]>, 1556 isPPC64; 1557def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1558 "#ADDIStlsldHA", 1559 [(set i64:$rD, 1560 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1561 isPPC64; 1562def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1563 "#ADDItlsldL", 1564 [(set i64:$rD, 1565 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1566 isPPC64; 1567// This pseudo is expanded to two copies to put the variable offset in R4 and 1568// the region handle in R3 and GETtlsADDR64AIX. 1569def TLSGDAIX8 : 1570 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1571 "#TLSGDAIX8", 1572 [(set i64:$rD, 1573 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1574// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1575// are true defines, while the rest of the Defs are clobbers. 1576let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1577 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1578 in 1579def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1580 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1581 "#ADDItlsldLADDR", 1582 [(set i64:$rD, 1583 (PPCaddiTlsldLAddr i64:$reg, 1584 tglobaltlsaddr:$disp, 1585 tglobaltlsaddr:$sym))]>, 1586 isPPC64; 1587def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1588 "#ADDISdtprelHA", 1589 [(set i64:$rD, 1590 (PPCaddisDtprelHA i64:$reg, 1591 tglobaltlsaddr:$disp))]>, 1592 isPPC64; 1593def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1594 "#ADDIdtprelL", 1595 [(set i64:$rD, 1596 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1597 isPPC64; 1598def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1599 "#PADDIdtprel", 1600 [(set i64:$rD, 1601 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1602 isPPC64; 1603 1604let PPC970_Unit = 2 in { 1605let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1606// Truncating stores. 1607def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1608 "stb $rS, $src", IIC_LdStStore, 1609 [(truncstorei8 i64:$rS, DForm:$src)]>; 1610def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1611 "sth $rS, $src", IIC_LdStStore, 1612 [(truncstorei16 i64:$rS, DForm:$src)]>; 1613def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1614 "stw $rS, $src", IIC_LdStStore, 1615 [(truncstorei32 i64:$rS, DForm:$src)]>; 1616def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1617 "stbx $rS, $dst", IIC_LdStStore, 1618 [(truncstorei8 i64:$rS, XForm:$dst)]>, 1619 PPC970_DGroup_Cracked; 1620def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1621 "sthx $rS, $dst", IIC_LdStStore, 1622 [(truncstorei16 i64:$rS, XForm:$dst)]>, 1623 PPC970_DGroup_Cracked; 1624def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1625 "stwx $rS, $dst", IIC_LdStStore, 1626 [(truncstorei32 i64:$rS, XForm:$dst)]>, 1627 PPC970_DGroup_Cracked; 1628} // Interpretation64Bit 1629 1630// Normal 8-byte stores. 1631def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1632 "std $rS, $dst", IIC_LdStSTD, 1633 [(store i64:$rS, DSForm:$dst)]>, isPPC64; 1634def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1635 "stdx $rS, $dst", IIC_LdStSTD, 1636 [(store i64:$rS, XForm:$dst)]>, isPPC64, 1637 PPC970_DGroup_Cracked; 1638 1639let Predicates = [IsISA2_06] in { 1640def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1641 "stdbrx $rS, $dst", IIC_LdStStore, 1642 [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, 1643 PPC970_DGroup_Cracked; 1644} 1645 1646let mayStore = 1, hasNoSchedulingInfo = 1 in { 1647// Normal 16-byte stores. 1648// TODO: Add scheduling info. 1649def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), 1650 "stq $RSp, $dst", IIC_LdStSTQ, 1651 []>, isPPC64; 1652 1653def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), 1654 (ins g8prc:$RSp, memrr:$dst), 1655 "#STQX_PSEUDO", []>; 1656 1657def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1658 "#SPILL_QUADWORD", []>; 1659} 1660 1661} 1662 1663def BUILD_QUADWORD : PPCPostRAExpPseudo< 1664 (outs g8prc:$RTp), 1665 (ins g8rc:$lo, g8rc:$hi), 1666 "#BUILD_QUADWORD", []>; 1667 1668def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst), 1669 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; 1670 1671def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), 1672 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; 1673 1674// Stores with Update (pre-inc). 1675let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1676let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1677def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1678 "stbu $rS, $dst", IIC_LdStSTU, []>, 1679 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1680def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1681 "sthu $rS, $dst", IIC_LdStSTU, []>, 1682 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1683def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1684 "stwu $rS, $dst", IIC_LdStSTU, []>, 1685 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1686 1687def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1688 (ins g8rc:$rS, memrr:$dst), 1689 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1690 RegConstraint<"$dst.ptrreg = $ea_res">, 1691 NoEncode<"$ea_res">, 1692 PPC970_DGroup_Cracked; 1693def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1694 (ins g8rc:$rS, memrr:$dst), 1695 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1696 RegConstraint<"$dst.ptrreg = $ea_res">, 1697 NoEncode<"$ea_res">, 1698 PPC970_DGroup_Cracked; 1699def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1700 (ins g8rc:$rS, memrr:$dst), 1701 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1702 RegConstraint<"$dst.ptrreg = $ea_res">, 1703 NoEncode<"$ea_res">, 1704 PPC970_DGroup_Cracked; 1705} // Interpretation64Bit 1706 1707def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1708 (ins g8rc:$rS, memrix:$dst), 1709 "stdu $rS, $dst", IIC_LdStSTU, []>, 1710 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1711 isPPC64; 1712 1713def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1714 (ins g8rc:$rS, memrr:$dst), 1715 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1716 RegConstraint<"$dst.ptrreg = $ea_res">, 1717 NoEncode<"$ea_res">, 1718 PPC970_DGroup_Cracked, isPPC64; 1719} 1720 1721// Patterns to match the pre-inc stores. We can't put the patterns on 1722// the instruction definitions directly as ISel wants the address base 1723// and offset to be separate operands, not a single complex operand. 1724def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1725 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1726def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1727 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1728def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1729 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1730def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1731 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1732 1733def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1734 (STBUX8 $rS, $ptrreg, $ptroff)>; 1735def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1736 (STHUX8 $rS, $ptrreg, $ptroff)>; 1737def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1738 (STWUX8 $rS, $ptrreg, $ptroff)>; 1739def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1740 (STDUX $rS, $ptrreg, $ptroff)>; 1741 1742 1743//===----------------------------------------------------------------------===// 1744// Floating point instructions. 1745// 1746 1747 1748let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1749 Uses = [RM] in { // FPU Operations. 1750defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1751 "fcfid", "$frD, $frB", IIC_FPGeneral, 1752 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1753defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1754 "fctid", "$frD, $frB", IIC_FPGeneral, 1755 []>, isPPC64; 1756defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1757 "fctidu", "$frD, $frB", IIC_FPGeneral, 1758 []>, isPPC64; 1759defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1760 "fctidz", "$frD, $frB", IIC_FPGeneral, 1761 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1762 1763defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1764 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1765 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1766defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1767 "fcfids", "$frD, $frB", IIC_FPGeneral, 1768 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1769defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1770 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1771 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1772defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1773 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1774 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1775defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1776 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1777 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1778} 1779 1780// These instructions store a hash computed from the value of the link register 1781// and the value of the stack pointer. 1782let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1783def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs), 1784 (ins g8rc:$RB, memrihash:$D_RA_XD), 1785 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 1786def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs), 1787 (ins g8rc:$RB, memrihash:$D_RA_XD), 1788 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1789} 1790 1791// These instructions check a hash computed from the value of the link register 1792// and the value of the stack pointer. The hasSideEffects flag is needed as the 1793// instruction may TRAP if the hash does not match the hash stored at the 1794// specified address. 1795let mayLoad = 1, hasSideEffects = 1, 1796 Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1797def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs), 1798 (ins g8rc:$RB, memrihash:$D_RA_XD), 1799 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 1800def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs), 1801 (ins g8rc:$RB, memrihash:$D_RA_XD), 1802 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1803} 1804 1805let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in 1806def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT), 1807 (ins g8rc:$rA, g8rc:$rB, u2imm:$CY), 1808 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, 1809 [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB, 1810 timm:$CY))]>; 1811 1812//===----------------------------------------------------------------------===// 1813// Instruction Patterns 1814// 1815 1816// Extensions and truncates to/from 32-bit regs. 1817def : Pat<(i64 (zext i32:$in)), 1818 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1819 0, 32)>; 1820def : Pat<(i64 (anyext i32:$in)), 1821 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1822def : Pat<(i32 (trunc i64:$in)), 1823 (EXTRACT_SUBREG $in, sub_32)>; 1824 1825// Implement the 'not' operation with the NOR instruction. 1826// (we could use the default xori pattern, but nor has lower latency on some 1827// cores (such as the A2)). 1828def i64not : OutPatFrag<(ops node:$in), 1829 (NOR8 $in, $in)>; 1830def : Pat<(not i64:$in), 1831 (i64not $in)>; 1832 1833// Extending loads with i64 targets. 1834def : Pat<(zextloadi1 DForm:$src), 1835 (LBZ8 DForm:$src)>; 1836def : Pat<(zextloadi1 XForm:$src), 1837 (LBZX8 XForm:$src)>; 1838def : Pat<(extloadi1 DForm:$src), 1839 (LBZ8 DForm:$src)>; 1840def : Pat<(extloadi1 XForm:$src), 1841 (LBZX8 XForm:$src)>; 1842def : Pat<(extloadi8 DForm:$src), 1843 (LBZ8 DForm:$src)>; 1844def : Pat<(extloadi8 XForm:$src), 1845 (LBZX8 XForm:$src)>; 1846def : Pat<(extloadi16 DForm:$src), 1847 (LHZ8 DForm:$src)>; 1848def : Pat<(extloadi16 XForm:$src), 1849 (LHZX8 XForm:$src)>; 1850def : Pat<(extloadi32 DForm:$src), 1851 (LWZ8 DForm:$src)>; 1852def : Pat<(extloadi32 XForm:$src), 1853 (LWZX8 XForm:$src)>; 1854 1855// Standard shifts. These are represented separately from the real shifts above 1856// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1857// amounts. 1858def : Pat<(sra i64:$rS, i32:$rB), 1859 (SRAD $rS, $rB)>; 1860def : Pat<(srl i64:$rS, i32:$rB), 1861 (SRD $rS, $rB)>; 1862def : Pat<(shl i64:$rS, i32:$rB), 1863 (SLD $rS, $rB)>; 1864 1865// SUBFIC 1866def : Pat<(sub imm64SExt16:$imm, i64:$in), 1867 (SUBFIC8 $in, imm:$imm)>; 1868 1869// SHL/SRL 1870def : Pat<(shl i64:$in, (i32 imm:$imm)), 1871 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1872def : Pat<(srl i64:$in, (i32 imm:$imm)), 1873 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1874 1875// ROTL 1876def : Pat<(rotl i64:$in, i32:$sh), 1877 (RLDCL $in, $sh, 0)>; 1878def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1879 (RLDICL $in, imm:$imm, 0)>; 1880 1881// Hi and Lo for Darwin Global Addresses. 1882def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1883def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1884def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1885def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1886def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1887def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1888def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1889def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1890def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1891 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1892def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1893 (ADDI8 $in, tglobaltlsaddr:$g)>; 1894def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1895 (ADDIS8 $in, tglobaladdr:$g)>; 1896def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1897 (ADDIS8 $in, tconstpool:$g)>; 1898def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1899 (ADDIS8 $in, tjumptable:$g)>; 1900def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1901 (ADDIS8 $in, tblockaddress:$g)>; 1902 1903// AIX 64-bit small code model TLS access. 1904def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1905 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1906 1907// 64-bits atomic loads and stores 1908def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1909def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1910 1911def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1912def : Pat<(atomic_store_64 XForm:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1913 1914let Predicates = [IsISA3_0, In64BitMode] in { 1915def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1916 (i64 (SETB8 (CMPEQB $a, $b)))>; 1917def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1918 (i64 (SETB8 (CMPD $a, $b)))>; 1919def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1920 (i64 (MADDHD $a, $b, $c))>; 1921def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1922 (i64 (MADDHDU $a, $b, $c))>; 1923def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1924 (i64 (MADDLD8 $a, $b, $c))>; 1925} 1926 1927let Predicates = [In64BitMode] in { 1928def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1929 (i64 (MULHD $a, $b))>; 1930def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1931 (i64 (MULHDU $a, $b))>; 1932def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1933 (LDBRX ForceXForm:$ptr)>; 1934def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1935 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1936} 1937 1938def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1939 (i64 (CMPB8 $a, $b))>; 1940 1941let Predicates = [IsISA3_0] in { 1942// DARN (deliver random number) 1943// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1944def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1945def : Pat<(int_ppc_darn), (DARN 1)>; 1946def : Pat<(int_ppc_darnraw), (DARN 2)>; 1947 1948class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1949 InstrItinClass itin, list<dag> pattern> 1950 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1951 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1952 let L = 1; 1953} 1954 1955class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1956 InstrItinClass itin, list<dag> pattern> 1957 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1958 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1959 1960let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1961def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1962def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1963} 1964 1965// SLB Invalidate Entry Global 1966def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1967 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1968// SLB Synchronize 1969def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1970 1971} // IsISA3_0 1972 1973def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 1974 (STDCX g8rc:$A, ForceXForm:$dst)>; 1975def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8), 1976 (STDCX g8rc:$A, ForceXForm:$dst)>; 1977 1978def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 1979 (MFSPR8 $SPR)>; 1980def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 1981 (MTSPR8 $SPR, $RT)>; 1982