1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 182 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 183 def BCTRL8_LDinto_toc : 184 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 185 (ins memrix:$src), 186 "bctrl\n\tld 2, $src", IIC_BrB, 187 [(PPCbctrl_load_toc iaddrX4:$src)]>, 188 Requires<[In64BitMode]>; 189} 190 191} // Interpretation64Bit 192 193// FIXME: Duplicating this for the asm parser should be unnecessary, but the 194// previous definition must be marked as CodeGen only to prevent decoding 195// conflicts. 196let Interpretation64Bit = 1, isAsmParserOnly = 1 in 197let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 198def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 199 "bl $func", IIC_BrB, []>; 200 201// Calls 202def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 203 (BL8 tglobaladdr:$dst)>; 204def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 205 (BL8_NOP tglobaladdr:$dst)>; 206 207def : Pat<(PPCcall (i64 texternalsym:$dst)), 208 (BL8 texternalsym:$dst)>; 209def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 210 (BL8_NOP texternalsym:$dst)>; 211 212def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 213 (BL8_NOTOC tglobaladdr:$dst)>; 214def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 215 (BL8_NOTOC texternalsym:$dst)>; 216 217// Calls for AIX 218def : Pat<(PPCcall (i64 mcsym:$dst)), 219 (BL8 mcsym:$dst)>; 220def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 221 (BL8_NOP mcsym:$dst)>; 222 223// Atomic operations 224// FIXME: some of these might be used with constant operands. This will result 225// in constant materialization instructions that may be redundant. We currently 226// clean this up in PPCMIPeephole with calls to 227// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 228// in the first place. 229let Defs = [CR0] in { 230 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 232 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 235 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 238 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 241 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 244 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 247 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 250 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 253 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 254 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 255 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 256 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 257 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 258 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 259 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 260 261 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 262 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 263 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 264 265 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 266 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 267 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 268} 269 270// Instructions to support atomic operations 271let mayLoad = 1, hasSideEffects = 0 in { 272def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 273 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 274// TODO: Add scheduling info. 275let hasNoSchedulingInfo = 1 in 276def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 277 "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; 278 279// Instruction to support lock versions of atomics 280// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 281def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 282 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 283// TODO: Add scheduling info. 284let hasNoSchedulingInfo = 1 in 285// FIXME: We have to seek a way to remove isRecordForm since 286// LQARXL is not really altering CR0. 287def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 288 "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, 289 isPPC64, isRecordForm; 290 291let hasExtraDefRegAllocReq = 1 in 292def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 293 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 294 Requires<[IsISA3_0]>; 295} 296 297let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 298def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 299 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 300// TODO: Add scheduling info. 301let hasNoSchedulingInfo = 1 in 302def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), 303 "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, 304 isPPC64, isRecordForm; 305} 306 307def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 308 (ins g8prc:$src), 309 "#SPLIT_QUADWORD", []>; 310class AtomicRMW128<string asmstr> 311 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 312 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 313 asmstr, []>; 314// We have to keep values in MI's uses during LL/SC looping as they are, 315// so set both $RTp and $scratch earlyclobber. 316let mayStore = 1, mayLoad = 1, 317 Defs = [CR0], 318 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 319// Atomic pseudo instructions expanded post-ra. 320def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 321def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 322def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 323def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 324def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 325def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 326def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 327 328def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 329 (outs g8prc:$RTp, g8prc:$scratch), 330 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 331 g8rc:$new_lo, g8rc:$new_hi), 332 "#ATOMIC_CMP_SWAP_I128", []>; 333} 334 335def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr, 336 i64:$incr_lo, 337 i64:$incr_hi), 338 (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr, 339 g8rc:$incr_lo, 340 g8rc:$incr_hi))>; 341def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr, 342 i64:$incr_lo, 343 i64:$incr_hi), 344 (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr, 345 g8rc:$incr_lo, 346 g8rc:$incr_hi))>; 347def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr, 348 i64:$incr_lo, 349 i64:$incr_hi), 350 (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr, 351 g8rc:$incr_lo, 352 g8rc:$incr_hi))>; 353def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr, 354 i64:$incr_lo, 355 i64:$incr_hi), 356 (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr, 357 g8rc:$incr_lo, 358 g8rc:$incr_hi))>; 359def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr, 360 i64:$incr_lo, 361 i64:$incr_hi), 362 (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr, 363 g8rc:$incr_lo, 364 g8rc:$incr_hi))>; 365def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr, 366 i64:$incr_lo, 367 i64:$incr_hi), 368 (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr, 369 g8rc:$incr_lo, 370 g8rc:$incr_hi))>; 371def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr, 372 i64:$incr_lo, 373 i64:$incr_hi), 374 (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr, 375 g8rc:$incr_lo, 376 g8rc:$incr_hi))>; 377def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 378 i64:$cmp_lo, 379 i64:$cmp_hi, 380 i64:$new_lo, 381 i64:$new_hi), 382 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 383 memrr:$ptr, 384 g8rc:$cmp_lo, 385 g8rc:$cmp_hi, 386 g8rc:$new_lo, 387 g8rc:$new_hi))>; 388 389let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 390def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 391 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 392 Requires<[IsISA3_0]>; 393 394let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 395let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 396def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 397 (ins calltarget:$dst, i32imm:$offset), 398 "#TC_RETURNd8 $dst $offset", 399 []>; 400 401let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 402def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 403 "#TC_RETURNa8 $func $offset", 404 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 405 406let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 407def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 408 "#TC_RETURNr8 $dst $offset", 409 []>; 410 411let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 412 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 413def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 414 []>, 415 Requires<[In64BitMode]>; 416 417let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 418 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 419def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 420 "b $dst", IIC_BrB, 421 []>; 422 423let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 424 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 425def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 426 "ba $dst", IIC_BrB, 427 []>; 428} // Interpretation64Bit 429 430def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 431 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 432 433def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 434 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 435 436def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 437 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 438 439 440// 64-bit CR instructions 441let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 442let hasSideEffects = 0 in { 443// mtocrf's input needs to be prepared by shifting by an amount dependent 444// on the cr register selected. Thus, post-ra anti-dep breaking must not 445// later change that register assignment. 446let hasExtraDefRegAllocReq = 1 in { 447def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 448 "mtocrf $FXM, $ST", IIC_BrMCRX>, 449 PPC970_DGroup_First, PPC970_Unit_CRU; 450 451// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 452// is dependent on the cr fields being set. 453def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 454 "mtcrf $FXM, $rS", IIC_BrMCRX>, 455 PPC970_MicroCode, PPC970_Unit_CRU; 456} // hasExtraDefRegAllocReq = 1 457 458// mfocrf's input needs to be prepared by shifting by an amount dependent 459// on the cr register selected. Thus, post-ra anti-dep breaking must not 460// later change that register assignment. 461let hasExtraSrcRegAllocReq = 1 in { 462def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 463 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 464 PPC970_DGroup_First, PPC970_Unit_CRU; 465 466// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 467// is dependent on the cr fields being copied. 468def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 469 "mfcr $rT", IIC_SprMFCR>, 470 PPC970_MicroCode, PPC970_Unit_CRU; 471} // hasExtraSrcRegAllocReq = 1 472} // hasSideEffects = 0 473 474// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 475// is not. 476let hasSideEffects = 1 in { 477 let Defs = [CTR8] in 478 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 479 "#EH_SJLJ_SETJMP64", 480 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 481 Requires<[In64BitMode]>; 482} 483 484let hasSideEffects = 1, isBarrier = 1 in { 485 let isTerminator = 1 in 486 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 487 "#EH_SJLJ_LONGJMP64", 488 [(PPCeh_sjlj_longjmp addr:$buf)]>, 489 Requires<[In64BitMode]>; 490} 491 492def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 493 "mfspr $RT, $SPR", IIC_SprMFSPR>; 494def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 495 "mtspr $SPR, $RT", IIC_SprMTSPR>; 496 497 498//===----------------------------------------------------------------------===// 499// 64-bit SPR manipulation instrs. 500 501let Uses = [CTR8] in { 502def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 503 "mfctr $rT", IIC_SprMFSPR>, 504 PPC970_DGroup_First, PPC970_Unit_FXU; 505} 506let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 507def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 508 "mtctr $rS", IIC_SprMTSPR>, 509 PPC970_DGroup_First, PPC970_Unit_FXU; 510} 511let hasSideEffects = 1, Defs = [CTR8] in { 512let Pattern = [(int_set_loop_iterations i64:$rS)] in 513def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 514 "mtctr $rS", IIC_SprMTSPR>, 515 PPC970_DGroup_First, PPC970_Unit_FXU; 516} 517 518let Pattern = [(set i64:$rT, readcyclecounter)] in 519def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 520 "mfspr $rT, 268", IIC_SprMFTB>, 521 PPC970_DGroup_First, PPC970_Unit_FXU; 522// Note that encoding mftb using mfspr is now the preferred form, 523// and has been since at least ISA v2.03. The mftb instruction has 524// now been phased out. Using mfspr, however, is known not to work on 525// the POWER3. 526 527let Defs = [X1], Uses = [X1] in 528def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 529 [(set i64:$result, 530 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 531def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 532 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 533// Probed alloca to support stack clash protection. 534let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 535def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 536 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 537 [(set i64:$result, 538 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 539def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 540 g8rc:$fp, g8rc:$actual_negsize), 541 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 542def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 543 g8rc:$fp, g8rc:$actual_negsize), 544 (ins g8rc:$negsize, memri:$fpsi), 545 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 546 RegConstraint<"$actual_negsize = $negsize">; 547def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 548 (ins i64imm:$stacksize), 549 "#PROBED_STACKALLOC_64", []>; 550} 551 552let hasSideEffects = 0 in { 553let Defs = [LR8] in { 554def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 555 "mtlr $rS", IIC_SprMTSPR>, 556 PPC970_DGroup_First, PPC970_Unit_FXU; 557} 558let Uses = [LR8] in { 559def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 560 "mflr $rT", IIC_SprMFSPR>, 561 PPC970_DGroup_First, PPC970_Unit_FXU; 562} 563} // Interpretation64Bit 564} 565 566//===----------------------------------------------------------------------===// 567// Fixed point instructions. 568// 569 570let PPC970_Unit = 1 in { // FXU Operations. 571let Interpretation64Bit = 1 in { 572let hasSideEffects = 0 in { 573let isCodeGenOnly = 1 in { 574 575let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 576def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 577 "li $rD, $imm", IIC_IntSimple, 578 [(set i64:$rD, imm64SExt16:$imm)]>; 579def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 580 "lis $rD, $imm", IIC_IntSimple, 581 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 582} 583 584// Logical ops. 585let isCommutable = 1 in { 586defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 587 "nand", "$rA, $rS, $rB", IIC_IntSimple, 588 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 589defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 590 "and", "$rA, $rS, $rB", IIC_IntSimple, 591 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 592} // isCommutable 593defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 594 "andc", "$rA, $rS, $rB", IIC_IntSimple, 595 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 596let isCommutable = 1 in { 597defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 598 "or", "$rA, $rS, $rB", IIC_IntSimple, 599 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 600defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 601 "nor", "$rA, $rS, $rB", IIC_IntSimple, 602 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 603} // isCommutable 604defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 605 "orc", "$rA, $rS, $rB", IIC_IntSimple, 606 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 607let isCommutable = 1 in { 608defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 609 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 610 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 611defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 612 "xor", "$rA, $rS, $rB", IIC_IntSimple, 613 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 614} // let isCommutable = 1 615 616// Logical ops with immediate. 617let Defs = [CR0] in { 618def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 619 "andi. $dst, $src1, $src2", IIC_IntGeneral, 620 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 621 isRecordForm; 622def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 623 "andis. $dst, $src1, $src2", IIC_IntGeneral, 624 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 625 isRecordForm; 626} 627def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 628 "ori $dst, $src1, $src2", IIC_IntSimple, 629 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 630def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 631 "oris $dst, $src1, $src2", IIC_IntSimple, 632 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 633def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 634 "xori $dst, $src1, $src2", IIC_IntSimple, 635 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 636def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 637 "xoris $dst, $src1, $src2", IIC_IntSimple, 638 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 639 640let isCommutable = 1 in 641defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 642 "add", "$rT, $rA, $rB", IIC_IntSimple, 643 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 644// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 645// initial-exec thread-local storage model. We need to forbid r0 here - 646// while it works for add just fine, the linker can relax this to local-exec 647// addi, which won't work for r0. 648def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 649 "add $rT, $rA, $rB", IIC_IntSimple, 650 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 651let mayLoad = 1 in { 652def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 653 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 654def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 655 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 656def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 657 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 658def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 659 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 660def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 661 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 662def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 663 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 664def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 665 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 666 667} 668 669let mayStore = 1 in { 670def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 671 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 672 PPC970_DGroup_Cracked; 673def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 674 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 675 PPC970_DGroup_Cracked; 676def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 677 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 678 PPC970_DGroup_Cracked; 679def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 680 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 681 PPC970_DGroup_Cracked; 682def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 683 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 684 PPC970_DGroup_Cracked; 685def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 686 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 687 PPC970_DGroup_Cracked; 688def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 689 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 690 PPC970_DGroup_Cracked; 691 692} 693 694let isCommutable = 1 in 695defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 696 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 697 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 698 PPC970_DGroup_Cracked; 699 700let Defs = [CARRY] in 701def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 702 "addic $rD, $rA, $imm", IIC_IntGeneral, 703 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 704def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 705 "addi $rD, $rA, $imm", IIC_IntSimple, 706 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 707def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 708 "addis $rD, $rA, $imm", IIC_IntSimple, 709 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 710 711let Defs = [CARRY] in { 712def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 713 "subfic $rD, $rA, $imm", IIC_IntGeneral, 714 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 715} 716defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 717 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 718 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 719 PPC970_DGroup_Cracked; 720defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 721 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 722 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 723defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 724 "neg", "$rT, $rA", IIC_IntSimple, 725 [(set i64:$rT, (ineg i64:$rA))]>; 726let Uses = [CARRY] in { 727let isCommutable = 1 in 728defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 729 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 730 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 731defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 732 "addme", "$rT, $rA", IIC_IntGeneral, 733 [(set i64:$rT, (adde i64:$rA, -1))]>; 734defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 735 "addze", "$rT, $rA", IIC_IntGeneral, 736 [(set i64:$rT, (adde i64:$rA, 0))]>; 737defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 738 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 739 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 740defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 741 "subfme", "$rT, $rA", IIC_IntGeneral, 742 [(set i64:$rT, (sube -1, i64:$rA))]>; 743defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 744 "subfze", "$rT, $rA", IIC_IntGeneral, 745 [(set i64:$rT, (sube 0, i64:$rA))]>; 746} 747} // isCodeGenOnly 748 749// FIXME: Duplicating this for the asm parser should be unnecessary, but the 750// previous definition must be marked as CodeGen only to prevent decoding 751// conflicts. 752let isAsmParserOnly = 1 in { 753def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 754 "add $rT, $rA, $rB", IIC_IntSimple, []>; 755 756let mayLoad = 1 in { 757def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 758 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 759def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 760 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 761def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 762 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 763def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 764 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 765} 766 767let mayStore = 1 in { 768def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 769 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 770 PPC970_DGroup_Cracked; 771def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 772 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 773 PPC970_DGroup_Cracked; 774def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 775 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 776 PPC970_DGroup_Cracked; 777def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 778 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 779 PPC970_DGroup_Cracked; 780} 781} 782 783let isCommutable = 1 in { 784defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 785 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 786 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 787defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 788 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 789 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 790} // isCommutable 791} 792} // Interpretation64Bit 793 794let isCompare = 1, hasSideEffects = 0 in { 795 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 796 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 797 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 798 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 799 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 800 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 801 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 802 "cmpldi $dst, $src1, $src2", 803 IIC_IntCompare>, isPPC64; 804 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 805 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 806 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 807 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 808 Requires<[IsISA3_0]>; 809 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 810 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 811 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 812} 813 814let hasSideEffects = 0 in { 815defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 816 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 817 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 818defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 819 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 820 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 821defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 822 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 823 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 824 825let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 826defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 827 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 828defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 829 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 830 Requires<[IsISA3_0]>; 831 832defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 833 "extsb", "$rA, $rS", IIC_IntSimple, 834 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 835defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 836 "extsh", "$rA, $rS", IIC_IntSimple, 837 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 838 839defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 840 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 841defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 842 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 843} // Interpretation64Bit 844 845// For fast-isel: 846let isCodeGenOnly = 1 in { 847def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 848 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 849def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 850 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 851} // isCodeGenOnly for fast-isel 852 853defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 854 "extsw", "$rA, $rS", IIC_IntSimple, 855 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 856let Interpretation64Bit = 1, isCodeGenOnly = 1 in 857defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 858 "extsw", "$rA, $rS", IIC_IntSimple, 859 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 860let isCodeGenOnly = 1 in 861def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 862 "extsw $rA, $rS", IIC_IntSimple, 863 []>, isPPC64; 864 865defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 866 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 867 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 868 869let Interpretation64Bit = 1, isCodeGenOnly = 1 in 870defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 871 (ins gprc:$rS, u6imm:$SH), 872 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 873 [(set i64:$rA, 874 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 875 isPPC64, Requires<[IsISA3_0]>; 876 877defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 878 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 879 []>, isPPC64, Requires<[IsISA3_0]>; 880 881// For fast-isel: 882let isCodeGenOnly = 1, Defs = [CARRY] in 883def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 884 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 885 886defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 887 "cntlzd", "$rA, $rS", IIC_IntGeneral, 888 [(set i64:$rA, (ctlz i64:$rS))]>; 889defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 890 "cnttzd", "$rA, $rS", IIC_IntGeneral, 891 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 892def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 893 "popcntd $rA, $rS", IIC_IntGeneral, 894 [(set i64:$rA, (ctpop i64:$rS))]>; 895def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 896 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 897 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 898 isPPC64, Requires<[HasBPERMD]>; 899 900let isCodeGenOnly = 1, isCommutable = 1 in 901def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 902 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 903 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 904 905// popcntw also does a population count on the high 32 bits (storing the 906// results in the high 32-bits of the output). We'll ignore that here (which is 907// safe because we never separately use the high part of the 64-bit registers). 908def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 909 "popcntw $rA, $rS", IIC_IntGeneral, 910 [(set i32:$rA, (ctpop i32:$rS))]>; 911 912let isCodeGenOnly = 1 in 913def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 914 "popcntb $rA, $rS", IIC_IntGeneral, 915 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 916 917defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 918 "divd", "$rT, $rA, $rB", IIC_IntDivD, 919 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 920defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 921 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 922 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 923defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 924 "divde", "$rT, $rA, $rB", IIC_IntDivD, 925 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 926 isPPC64, Requires<[HasExtDiv]>; 927 928let Predicates = [IsISA3_0] in { 929def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 930 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 931def MADDHDU : VAForm_1a<49, 932 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 933 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 934def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 935 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 936 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 937 isPPC64; 938let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 939 def MADDLD8 : VAForm_1a<51, 940 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 941 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 942 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 943 isPPC64; 944 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 945 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 946} 947def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 948 "darn $RT, $L", IIC_LdStLD>, isPPC64; 949def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 950 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 951def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 952 "modsd $rT, $rA, $rB", IIC_IntDivW, 953 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 954def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 955 "modud $rT, $rA, $rB", IIC_IntDivW, 956 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 957} 958 959defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 960 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 961 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 962 isPPC64, Requires<[HasExtDiv]>; 963let isCommutable = 1 in 964defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 965 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 966 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 967let Interpretation64Bit = 1, isCodeGenOnly = 1 in 968def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 969 "mulli $rD, $rA, $imm", IIC_IntMulLI, 970 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 971} 972 973let hasSideEffects = 0 in { 974defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 975 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 976 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 977 []>, isPPC64, RegConstraint<"$rSi = $rA">, 978 NoEncode<"$rSi">; 979 980// Rotate instructions. 981defm RLDCL : MDSForm_1r<30, 8, 982 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 983 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 984 []>, isPPC64; 985defm RLDCR : MDSForm_1r<30, 9, 986 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 987 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 988 []>, isPPC64; 989defm RLDICL : MDForm_1r<30, 0, 990 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 991 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 992 []>, isPPC64; 993// For fast-isel: 994let isCodeGenOnly = 1 in 995def RLDICL_32_64 : MDForm_1<30, 0, 996 (outs g8rc:$rA), 997 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 998 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 999 []>, isPPC64; 1000// End fast-isel. 1001let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1002defm RLDICL_32 : MDForm_1r<30, 0, 1003 (outs gprc:$rA), 1004 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1005 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1006 []>, isPPC64; 1007defm RLDICR : MDForm_1r<30, 1, 1008 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1009 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1010 []>, isPPC64; 1011let isCodeGenOnly = 1 in 1012def RLDICR_32 : MDForm_1<30, 1, 1013 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1014 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1015 []>, isPPC64; 1016defm RLDIC : MDForm_1r<30, 2, 1017 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1018 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1019 []>, isPPC64; 1020 1021let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1022defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 1023 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1024 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 1025 []>; 1026 1027defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 1028 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 1029 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 1030 []>; 1031 1032// RLWIMI can be commuted if the rotate amount is zero. 1033let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1034defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 1035 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 1036 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 1037 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1038 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 1039 1040let isSelect = 1 in 1041def ISEL8 : AForm_4<31, 15, 1042 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 1043 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 1044 []>; 1045} // Interpretation64Bit 1046} // hasSideEffects = 0 1047} // End FXU Operations. 1048 1049def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1050def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1051 1052def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1053def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1054 1055def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1056def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1057 1058def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1059 1060def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1061def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1062def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1063def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1064 1065def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1066def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1067def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1068def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1069def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1070def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1071 1072def : InstAlias<"isellt $rT, $rA, $rB", 1073 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1074def : InstAlias<"iselgt $rT, $rA, $rB", 1075 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1076def : InstAlias<"iseleq $rT, $rA, $rB", 1077 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1078 1079def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1080def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1081 1082def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1083def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1084 1085def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1086def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1087 1088//Disable this alias on AIX for now because as does not support them. 1089let Predicates = [ModernAs] in { 1090 1091def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1092def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1093 1094def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1095def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1096 1097def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1098def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1099 1100def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1101def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1102 1103def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1104def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1105 1106def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1107def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1108 1109def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1110def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1111 1112def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1113def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1114 1115def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1116def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1117 1118def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1119def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1120 1121def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1122def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1123 1124def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1125def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1126 1127def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1128def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1129 1130def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1131def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1132 1133foreach SPRG = 0-3 in { 1134 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1135 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1136 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1137 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1138} 1139 1140def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1141def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1142 1143def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1144def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1145 1146def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1147 1148def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1149def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1150 1151} 1152 1153//===----------------------------------------------------------------------===// 1154// Load/Store instructions. 1155// 1156 1157 1158// Sign extending loads. 1159let PPC970_Unit = 2 in { 1160let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1161def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1162 "lha $rD, $src", IIC_LdStLHA, 1163 [(set i64:$rD, (sextloadi16 DForm:$src))]>, 1164 PPC970_DGroup_Cracked; 1165def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1166 "lwa $rD, $src", IIC_LdStLWA, 1167 [(set i64:$rD, 1168 (sextloadi32 DSForm:$src))]>, isPPC64, 1169 PPC970_DGroup_Cracked; 1170let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1171def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1172 "lhax $rD, $src", IIC_LdStLHA, 1173 [(set i64:$rD, (sextloadi16 XForm:$src))]>, 1174 PPC970_DGroup_Cracked; 1175def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1176 "lwax $rD, $src", IIC_LdStLHA, 1177 [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, 1178 PPC970_DGroup_Cracked; 1179// For fast-isel: 1180let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1181def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1182 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1183 PPC970_DGroup_Cracked; 1184def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1185 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1186 PPC970_DGroup_Cracked; 1187} // end fast-isel isCodeGenOnly 1188 1189// Update forms. 1190let mayLoad = 1, hasSideEffects = 0 in { 1191let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1192def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1193 (ins memri:$addr), 1194 "lhau $rD, $addr", IIC_LdStLHAU, 1195 []>, RegConstraint<"$addr.reg = $ea_result">, 1196 NoEncode<"$ea_result">; 1197// NO LWAU! 1198 1199let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1200def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1201 (ins memrr:$addr), 1202 "lhaux $rD, $addr", IIC_LdStLHAUX, 1203 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1204 NoEncode<"$ea_result">; 1205def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1206 (ins memrr:$addr), 1207 "lwaux $rD, $addr", IIC_LdStLHAUX, 1208 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1209 NoEncode<"$ea_result">, isPPC64; 1210} 1211} 1212 1213let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1214// Zero extending loads. 1215let PPC970_Unit = 2 in { 1216def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1217 "lbz $rD, $src", IIC_LdStLoad, 1218 [(set i64:$rD, (zextloadi8 DForm:$src))]>; 1219def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1220 "lhz $rD, $src", IIC_LdStLoad, 1221 [(set i64:$rD, (zextloadi16 DForm:$src))]>; 1222def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1223 "lwz $rD, $src", IIC_LdStLoad, 1224 [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64; 1225 1226def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1227 "lbzx $rD, $src", IIC_LdStLoad, 1228 [(set i64:$rD, (zextloadi8 XForm:$src))]>; 1229def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1230 "lhzx $rD, $src", IIC_LdStLoad, 1231 [(set i64:$rD, (zextloadi16 XForm:$src))]>; 1232def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1233 "lwzx $rD, $src", IIC_LdStLoad, 1234 [(set i64:$rD, (zextloadi32 XForm:$src))]>; 1235 1236 1237// Update forms. 1238let mayLoad = 1, hasSideEffects = 0 in { 1239def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1240 (ins memri:$addr), 1241 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1242 []>, RegConstraint<"$addr.reg = $ea_result">, 1243 NoEncode<"$ea_result">; 1244def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1245 (ins memri:$addr), 1246 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1247 []>, RegConstraint<"$addr.reg = $ea_result">, 1248 NoEncode<"$ea_result">; 1249def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1250 (ins memri:$addr), 1251 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1252 []>, RegConstraint<"$addr.reg = $ea_result">, 1253 NoEncode<"$ea_result">; 1254 1255def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1256 (ins memrr:$addr), 1257 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1258 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1259 NoEncode<"$ea_result">; 1260def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1261 (ins memrr:$addr), 1262 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1263 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1264 NoEncode<"$ea_result">; 1265def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1266 (ins memrr:$addr), 1267 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1268 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1269 NoEncode<"$ea_result">; 1270} 1271} 1272} // Interpretation64Bit 1273 1274 1275// Full 8-byte loads. 1276let PPC970_Unit = 2 in { 1277def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1278 "ld $rD, $src", IIC_LdStLD, 1279 [(set i64:$rD, (load DSForm:$src))]>, isPPC64; 1280// The following four definitions are selected for small code model only. 1281// Otherwise, we need to create two instructions to form a 32-bit offset, 1282// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1283def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1284 "#LDtoc", 1285 [(set i64:$rD, 1286 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1287def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1288 "#LDtocJTI", 1289 [(set i64:$rD, 1290 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1291def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1292 "#LDtocCPT", 1293 [(set i64:$rD, 1294 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1295def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1296 "#LDtocCPT", 1297 [(set i64:$rD, 1298 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1299 1300def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1301 "ldx $rD, $src", IIC_LdStLD, 1302 [(set i64:$rD, (load XForm:$src))]>, isPPC64; 1303def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1304 "ldbrx $rD, $src", IIC_LdStLoad, 1305 [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; 1306 1307let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1308def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1309 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1310def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1311 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1312} 1313 1314let mayLoad = 1, hasSideEffects = 0 in { 1315def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1316 (ins memrix:$addr), 1317 "ldu $rD, $addr", IIC_LdStLDU, 1318 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1319 NoEncode<"$ea_result">; 1320 1321def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1322 (ins memrr:$addr), 1323 "ldux $rD, $addr", IIC_LdStLDUX, 1324 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1325 NoEncode<"$ea_result">, isPPC64; 1326 1327def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1328 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1329 Requires<[IsISA3_0]>; 1330} 1331 1332let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1333// Full 16-byte load. 1334// Early clobber $RTp to avoid assigned to the same register as RA. 1335// TODO: Add scheduling info. 1336def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1337 (outs g8prc:$RTp), 1338 (ins memrix16:$src), 1339 "lq $RTp, $src", IIC_LdStLQ, 1340 []>, 1341 RegConstraint<"@earlyclobber $RTp">, 1342 isPPC64; 1343def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1344 "#RESTORE_QUADWORD", []>; 1345} 1346 1347} 1348 1349// Support for medium and large code model. 1350let hasSideEffects = 0 in { 1351let isReMaterializable = 1 in { 1352def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1353 "#ADDIStocHA8", []>, isPPC64; 1354def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1355 "#ADDItocL", []>, isPPC64; 1356} 1357let mayLoad = 1 in 1358def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1359 "#LDtocL", []>, isPPC64; 1360} 1361 1362// Support for thread-local storage. 1363def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1364 "#ADDISgotTprelHA", 1365 [(set i64:$rD, 1366 (PPCaddisGotTprelHA i64:$reg, 1367 tglobaltlsaddr:$disp))]>, 1368 isPPC64; 1369def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1370 "#LDgotTprelL", 1371 [(set i64:$rD, 1372 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1373 isPPC64; 1374 1375let Defs = [CR7], Itinerary = IIC_LdStSync in 1376def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1377 1378def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1379 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1380def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1381 "#ADDIStlsgdHA", 1382 [(set i64:$rD, 1383 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1384 isPPC64; 1385def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1386 "#ADDItlsgdL", 1387 [(set i64:$rD, 1388 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1389 isPPC64; 1390 1391class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1392 asmstr, 1393 [(set i64:$rD, 1394 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1395 isPPC64; 1396class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1397 asmstr, 1398 [(set i64:$rD, 1399 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1400 isPPC64; 1401 1402let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1403// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1404// explicitly defined when this op is created, so not mentioned here. 1405// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1406// correct because the branch select pass is relying on it. 1407let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1408def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1409let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1410def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1411 1412// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1413// explicitly defined when this op is created, so not mentioned here. 1414let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1415def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1416let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1417def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1418 1419// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1420// offset and region handle respectively. The call is not followed by a nop 1421// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1422// manual mentions this exact set of registers as the clobbered set, others 1423// are guaranteed not to be clobbered. 1424let Defs = [X0,X4,X5,X11,LR8,CR0] in 1425def GETtlsADDR64AIX : 1426 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1427 "GETtlsADDR64AIX", 1428 [(set i64:$rD, 1429 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1430} 1431 1432// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1433// are true defines while the rest of the Defs are clobbers. 1434let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1435 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1436 in 1437def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1438 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1439 "#ADDItlsgdLADDR", 1440 [(set i64:$rD, 1441 (PPCaddiTlsgdLAddr i64:$reg, 1442 tglobaltlsaddr:$disp, 1443 tglobaltlsaddr:$sym))]>, 1444 isPPC64; 1445def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1446 "#ADDIStlsldHA", 1447 [(set i64:$rD, 1448 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1449 isPPC64; 1450def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1451 "#ADDItlsldL", 1452 [(set i64:$rD, 1453 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1454 isPPC64; 1455// This pseudo is expanded to two copies to put the variable offset in R4 and 1456// the region handle in R3 and GETtlsADDR64AIX. 1457def TLSGDAIX8 : 1458 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1459 "#TLSGDAIX8", 1460 [(set i64:$rD, 1461 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1462// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1463// are true defines, while the rest of the Defs are clobbers. 1464let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1465 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1466 in 1467def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1468 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1469 "#ADDItlsldLADDR", 1470 [(set i64:$rD, 1471 (PPCaddiTlsldLAddr i64:$reg, 1472 tglobaltlsaddr:$disp, 1473 tglobaltlsaddr:$sym))]>, 1474 isPPC64; 1475def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1476 "#ADDISdtprelHA", 1477 [(set i64:$rD, 1478 (PPCaddisDtprelHA i64:$reg, 1479 tglobaltlsaddr:$disp))]>, 1480 isPPC64; 1481def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1482 "#ADDIdtprelL", 1483 [(set i64:$rD, 1484 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1485 isPPC64; 1486def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1487 "#PADDIdtprel", 1488 [(set i64:$rD, 1489 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1490 isPPC64; 1491 1492let PPC970_Unit = 2 in { 1493let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1494// Truncating stores. 1495def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1496 "stb $rS, $src", IIC_LdStStore, 1497 [(truncstorei8 i64:$rS, DForm:$src)]>; 1498def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1499 "sth $rS, $src", IIC_LdStStore, 1500 [(truncstorei16 i64:$rS, DForm:$src)]>; 1501def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1502 "stw $rS, $src", IIC_LdStStore, 1503 [(truncstorei32 i64:$rS, DForm:$src)]>; 1504def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1505 "stbx $rS, $dst", IIC_LdStStore, 1506 [(truncstorei8 i64:$rS, XForm:$dst)]>, 1507 PPC970_DGroup_Cracked; 1508def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1509 "sthx $rS, $dst", IIC_LdStStore, 1510 [(truncstorei16 i64:$rS, XForm:$dst)]>, 1511 PPC970_DGroup_Cracked; 1512def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1513 "stwx $rS, $dst", IIC_LdStStore, 1514 [(truncstorei32 i64:$rS, XForm:$dst)]>, 1515 PPC970_DGroup_Cracked; 1516} // Interpretation64Bit 1517 1518// Normal 8-byte stores. 1519def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1520 "std $rS, $dst", IIC_LdStSTD, 1521 [(store i64:$rS, DSForm:$dst)]>, isPPC64; 1522def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1523 "stdx $rS, $dst", IIC_LdStSTD, 1524 [(store i64:$rS, XForm:$dst)]>, isPPC64, 1525 PPC970_DGroup_Cracked; 1526def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1527 "stdbrx $rS, $dst", IIC_LdStStore, 1528 [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, 1529 PPC970_DGroup_Cracked; 1530 1531let mayStore = 1, hasNoSchedulingInfo = 1 in { 1532// Normal 16-byte stores. 1533// TODO: Add scheduling info. 1534def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), 1535 "stq $RSp, $dst", IIC_LdStSTQ, 1536 []>, isPPC64; 1537def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1538 "#SPILL_QUADWORD", []>; 1539} 1540 1541} 1542 1543// Stores with Update (pre-inc). 1544let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1545let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1546def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1547 "stbu $rS, $dst", IIC_LdStSTU, []>, 1548 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1549def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1550 "sthu $rS, $dst", IIC_LdStSTU, []>, 1551 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1552def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1553 "stwu $rS, $dst", IIC_LdStSTU, []>, 1554 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1555 1556def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1557 (ins g8rc:$rS, memrr:$dst), 1558 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1559 RegConstraint<"$dst.ptrreg = $ea_res">, 1560 NoEncode<"$ea_res">, 1561 PPC970_DGroup_Cracked; 1562def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1563 (ins g8rc:$rS, memrr:$dst), 1564 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1565 RegConstraint<"$dst.ptrreg = $ea_res">, 1566 NoEncode<"$ea_res">, 1567 PPC970_DGroup_Cracked; 1568def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1569 (ins g8rc:$rS, memrr:$dst), 1570 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1571 RegConstraint<"$dst.ptrreg = $ea_res">, 1572 NoEncode<"$ea_res">, 1573 PPC970_DGroup_Cracked; 1574} // Interpretation64Bit 1575 1576def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1577 (ins g8rc:$rS, memrix:$dst), 1578 "stdu $rS, $dst", IIC_LdStSTU, []>, 1579 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1580 isPPC64; 1581 1582def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1583 (ins g8rc:$rS, memrr:$dst), 1584 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1585 RegConstraint<"$dst.ptrreg = $ea_res">, 1586 NoEncode<"$ea_res">, 1587 PPC970_DGroup_Cracked, isPPC64; 1588} 1589 1590// Patterns to match the pre-inc stores. We can't put the patterns on 1591// the instruction definitions directly as ISel wants the address base 1592// and offset to be separate operands, not a single complex operand. 1593def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1594 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1595def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1596 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1597def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1598 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1599def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1600 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1601 1602def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1603 (STBUX8 $rS, $ptrreg, $ptroff)>; 1604def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1605 (STHUX8 $rS, $ptrreg, $ptroff)>; 1606def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1607 (STWUX8 $rS, $ptrreg, $ptroff)>; 1608def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1609 (STDUX $rS, $ptrreg, $ptroff)>; 1610 1611 1612//===----------------------------------------------------------------------===// 1613// Floating point instructions. 1614// 1615 1616 1617let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1618 Uses = [RM] in { // FPU Operations. 1619defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1620 "fcfid", "$frD, $frB", IIC_FPGeneral, 1621 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1622defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1623 "fctid", "$frD, $frB", IIC_FPGeneral, 1624 []>, isPPC64; 1625defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1626 "fctidu", "$frD, $frB", IIC_FPGeneral, 1627 []>, isPPC64; 1628defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1629 "fctidz", "$frD, $frB", IIC_FPGeneral, 1630 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1631 1632defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1633 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1634 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1635defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1636 "fcfids", "$frD, $frB", IIC_FPGeneral, 1637 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1638defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1639 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1640 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1641defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1642 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1643 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1644defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1645 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1646 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1647} 1648 1649// These instructions store a hash computed from the value of the link register 1650// and the value of the stack pointer. 1651let mayStore = 1 in { 1652def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 1653 (ins g8rc:$RB, memrihash:$D_RA_XD), 1654 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 1655def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 1656 (ins g8rc:$RB, memrihash:$D_RA_XD), 1657 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1658} 1659 1660// These instructions check a hash computed from the value of the link register 1661// and the value of the stack pointer. The hasSideEffects flag is needed as the 1662// instruction may TRAP if the hash does not match the hash stored at the 1663// specified address. 1664let mayLoad = 1, hasSideEffects = 1 in { 1665def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 1666 (ins g8rc:$RB, memrihash:$D_RA_XD), 1667 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 1668def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 1669 (ins g8rc:$RB, memrihash:$D_RA_XD), 1670 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1671} 1672 1673//===----------------------------------------------------------------------===// 1674// Instruction Patterns 1675// 1676 1677// Extensions and truncates to/from 32-bit regs. 1678def : Pat<(i64 (zext i32:$in)), 1679 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1680 0, 32)>; 1681def : Pat<(i64 (anyext i32:$in)), 1682 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1683def : Pat<(i32 (trunc i64:$in)), 1684 (EXTRACT_SUBREG $in, sub_32)>; 1685 1686// Implement the 'not' operation with the NOR instruction. 1687// (we could use the default xori pattern, but nor has lower latency on some 1688// cores (such as the A2)). 1689def i64not : OutPatFrag<(ops node:$in), 1690 (NOR8 $in, $in)>; 1691def : Pat<(not i64:$in), 1692 (i64not $in)>; 1693 1694// Extending loads with i64 targets. 1695def : Pat<(zextloadi1 DForm:$src), 1696 (LBZ8 DForm:$src)>; 1697def : Pat<(zextloadi1 XForm:$src), 1698 (LBZX8 XForm:$src)>; 1699def : Pat<(extloadi1 DForm:$src), 1700 (LBZ8 DForm:$src)>; 1701def : Pat<(extloadi1 XForm:$src), 1702 (LBZX8 XForm:$src)>; 1703def : Pat<(extloadi8 DForm:$src), 1704 (LBZ8 DForm:$src)>; 1705def : Pat<(extloadi8 XForm:$src), 1706 (LBZX8 XForm:$src)>; 1707def : Pat<(extloadi16 DForm:$src), 1708 (LHZ8 DForm:$src)>; 1709def : Pat<(extloadi16 XForm:$src), 1710 (LHZX8 XForm:$src)>; 1711def : Pat<(extloadi32 DForm:$src), 1712 (LWZ8 DForm:$src)>; 1713def : Pat<(extloadi32 XForm:$src), 1714 (LWZX8 XForm:$src)>; 1715 1716// Standard shifts. These are represented separately from the real shifts above 1717// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1718// amounts. 1719def : Pat<(sra i64:$rS, i32:$rB), 1720 (SRAD $rS, $rB)>; 1721def : Pat<(srl i64:$rS, i32:$rB), 1722 (SRD $rS, $rB)>; 1723def : Pat<(shl i64:$rS, i32:$rB), 1724 (SLD $rS, $rB)>; 1725 1726// SUBFIC 1727def : Pat<(sub imm64SExt16:$imm, i64:$in), 1728 (SUBFIC8 $in, imm:$imm)>; 1729 1730// SHL/SRL 1731def : Pat<(shl i64:$in, (i32 imm:$imm)), 1732 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1733def : Pat<(srl i64:$in, (i32 imm:$imm)), 1734 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1735 1736// ROTL 1737def : Pat<(rotl i64:$in, i32:$sh), 1738 (RLDCL $in, $sh, 0)>; 1739def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1740 (RLDICL $in, imm:$imm, 0)>; 1741 1742// Hi and Lo for Darwin Global Addresses. 1743def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1744def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1745def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1746def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1747def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1748def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1749def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1750def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1751def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1752 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1753def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1754 (ADDI8 $in, tglobaltlsaddr:$g)>; 1755def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1756 (ADDIS8 $in, tglobaladdr:$g)>; 1757def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1758 (ADDIS8 $in, tconstpool:$g)>; 1759def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1760 (ADDIS8 $in, tjumptable:$g)>; 1761def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1762 (ADDIS8 $in, tblockaddress:$g)>; 1763 1764// AIX 64-bit small code model TLS access. 1765def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1766 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1767 1768// 64-bits atomic loads and stores 1769def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1770def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1771 1772def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1773def : Pat<(atomic_store_64 XForm:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1774 1775let Predicates = [IsISA3_0, In64BitMode] in { 1776def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1777 (i64 (SETB8 (CMPEQB $a, $b)))>; 1778def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1779 (i64 (SETB8 (CMPD $a, $b)))>; 1780def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1781 (i64 (MADDHD $a, $b, $c))>; 1782def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1783 (i64 (MADDHDU $a, $b, $c))>; 1784def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1785 (i64 (MADDLD8 $a, $b, $c))>; 1786} 1787 1788let Predicates = [In64BitMode] in { 1789def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1790 (i64 (MULHD $a, $b))>; 1791def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1792 (i64 (MULHDU $a, $b))>; 1793def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1794 (LDBRX ForceXForm:$ptr)>; 1795def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1796 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1797} 1798 1799def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1800 (i64 (CMPB8 $a, $b))>; 1801 1802let Predicates = [IsISA3_0] in { 1803// DARN (deliver random number) 1804// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1805def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1806def : Pat<(int_ppc_darn), (DARN 1)>; 1807def : Pat<(int_ppc_darnraw), (DARN 2)>; 1808 1809class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1810 InstrItinClass itin, list<dag> pattern> 1811 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1812 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1813 let L = 1; 1814} 1815 1816class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1817 InstrItinClass itin, list<dag> pattern> 1818 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1819 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1820 1821let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1822def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1823def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1824} 1825 1826// SLB Invalidate Entry Global 1827def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1828 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1829// SLB Synchronize 1830def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1831 1832} // IsISA3_0 1833 1834def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 1835 (STDCX g8rc:$A, ForceXForm:$dst)>; 1836def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM), 1837 (TD $IMM, $A, $B)>; 1838 1839// trapd 1840def : Pat<(int_ppc_trapd g8rc:$A), 1841 (TDI 24, $A, 0)>; 1842def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 1843 (MFSPR8 $SPR)>; 1844def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 1845 (MTSPR8 $SPR, $RT)>; 1846