1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/SelectionDAGNodes.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/Metadata.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/MachineValueType.h" 32 #include <utility> 33 34 namespace llvm { 35 36 namespace PPCISD { 37 38 // When adding a NEW PPCISD node please add it to the correct position in 39 // the enum. The order of elements in this enum matters! 40 // Values that are added after this entry: 41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 42 // are considered memory opcodes and are treated differently than entries 43 // that come before it. For example, ADD or MUL should be placed before 44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 45 // after it. 46 enum NodeType : unsigned { 47 // Start the numbering where the builtin ops and target ops leave off. 48 FIRST_NUMBER = ISD::BUILTIN_OP_END, 49 50 /// FSEL - Traditional three-operand fsel node. 51 /// 52 FSEL, 53 54 /// XSMAXCDP, XSMINCDP - C-type min/max instructions. 55 XSMAXCDP, 56 XSMINCDP, 57 58 /// FCFID - The FCFID instruction, taking an f64 operand and producing 59 /// and f64 value containing the FP representation of the integer that 60 /// was temporarily in the f64 operand. 61 FCFID, 62 63 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 64 /// unsigned integers and single-precision outputs. 65 FCFIDU, 66 FCFIDS, 67 FCFIDUS, 68 69 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 70 /// operand, producing an f64 value containing the integer representation 71 /// of that FP value. 72 FCTIDZ, 73 FCTIWZ, 74 75 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 76 /// unsigned integers with round toward zero. 77 FCTIDUZ, 78 FCTIWUZ, 79 80 /// Floating-point-to-interger conversion instructions 81 FP_TO_UINT_IN_VSR, 82 FP_TO_SINT_IN_VSR, 83 84 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 85 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 86 VEXTS, 87 88 /// Reciprocal estimate instructions (unary FP ops). 89 FRE, 90 FRSQRTE, 91 92 /// Test instruction for software square root. 93 FTSQRT, 94 95 /// Square root instruction. 96 FSQRT, 97 98 /// VPERM - The PPC VPERM Instruction. 99 /// 100 VPERM, 101 102 /// XXSPLT - The PPC VSX splat instructions 103 /// 104 XXSPLT, 105 106 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for 107 /// converting immediate single precision numbers to double precision 108 /// vector or scalar. 109 XXSPLTI_SP_TO_DP, 110 111 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. 112 /// 113 XXSPLTI32DX, 114 115 /// VECINSERT - The PPC vector insert instruction 116 /// 117 VECINSERT, 118 119 /// VECSHL - The PPC vector shift left instruction 120 /// 121 VECSHL, 122 123 /// XXPERMDI - The PPC XXPERMDI instruction 124 /// 125 XXPERMDI, 126 127 /// The CMPB instruction (takes two operands of i32 or i64). 128 CMPB, 129 130 /// Hi/Lo - These represent the high and low 16-bit parts of a global 131 /// address respectively. These nodes have two operands, the first of 132 /// which must be a TargetGlobalAddress, and the second of which must be a 133 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 134 /// though these are usually folded into other nodes. 135 Hi, 136 Lo, 137 138 /// The following two target-specific nodes are used for calls through 139 /// function pointers in the 64-bit SVR4 ABI. 140 141 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 142 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 143 /// compute an allocation on the stack. 144 DYNALLOC, 145 146 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 147 /// compute an offset from native SP to the address of the most recent 148 /// dynamic alloca. 149 DYNAREAOFFSET, 150 151 /// To avoid stack clash, allocation is performed by block and each block is 152 /// probed. 153 PROBED_ALLOCA, 154 155 /// The result of the mflr at function entry, used for PIC code. 156 GlobalBaseReg, 157 158 /// These nodes represent PPC shifts. 159 /// 160 /// For scalar types, only the last `n + 1` bits of the shift amounts 161 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 162 /// for exact behaviors. 163 /// 164 /// For vector types, only the last n bits are used. See vsld. 165 SRL, 166 SRA, 167 SHL, 168 169 /// FNMSUB - Negated multiply-subtract instruction. 170 FNMSUB, 171 172 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 173 /// word and shift left immediate. 174 EXTSWSLI, 175 176 /// The combination of sra[wd]i and addze used to implemented signed 177 /// integer division by a power of 2. The first operand is the dividend, 178 /// and the second is the constant shift amount (representing the 179 /// divisor). 180 SRA_ADDZE, 181 182 /// CALL - A direct function call. 183 /// CALL_NOP is a call with the special NOP which follows 64-bit 184 /// CALL_NOTOC the caller does not use the TOC. 185 /// SVR4 calls and 32-bit/64-bit AIX calls. 186 CALL, 187 CALL_NOP, 188 CALL_NOTOC, 189 190 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 191 /// MTCTR instruction. 192 MTCTR, 193 194 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 195 /// BCTRL instruction. 196 BCTRL, 197 198 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 199 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 200 /// and 64-bit AIX. 201 BCTRL_LOAD_TOC, 202 203 /// The variants that implicitly define rounding mode for calls with 204 /// strictfp semantics. 205 CALL_RM, 206 CALL_NOP_RM, 207 CALL_NOTOC_RM, 208 BCTRL_RM, 209 BCTRL_LOAD_TOC_RM, 210 211 /// Return with a flag operand, matched by 'blr' 212 RET_FLAG, 213 214 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 215 /// This copies the bits corresponding to the specified CRREG into the 216 /// resultant GPR. Bits corresponding to other CR regs are undefined. 217 MFOCRF, 218 219 /// Direct move from a VSX register to a GPR 220 MFVSR, 221 222 /// Direct move from a GPR to a VSX register (algebraic) 223 MTVSRA, 224 225 /// Direct move from a GPR to a VSX register (zero) 226 MTVSRZ, 227 228 /// Direct move of 2 consecutive GPR to a VSX register. 229 BUILD_FP128, 230 231 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 232 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 233 /// unsupported for this target. 234 /// Merge 2 GPRs to a single SPE register. 235 BUILD_SPE64, 236 237 /// Extract SPE register component, second argument is high or low. 238 EXTRACT_SPE, 239 240 /// Extract a subvector from signed integer vector and convert to FP. 241 /// It is primarily used to convert a (widened) illegal integer vector 242 /// type to a legal floating point vector type. 243 /// For example v2i32 -> widened to v4i32 -> v2f64 244 SINT_VEC_TO_FP, 245 246 /// Extract a subvector from unsigned integer vector and convert to FP. 247 /// As with SINT_VEC_TO_FP, used for converting illegal types. 248 UINT_VEC_TO_FP, 249 250 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to 251 /// place the value into the least significant element of the most 252 /// significant doubleword in the vector. This is not element zero for 253 /// anything smaller than a doubleword on either endianness. This node has 254 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in 255 /// the aforementioned location in the vector register. 256 SCALAR_TO_VECTOR_PERMUTED, 257 258 // FIXME: Remove these once the ANDI glue bug is fixed: 259 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 260 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 261 /// implement truncation of i32 or i64 to i1. 262 ANDI_rec_1_EQ_BIT, 263 ANDI_rec_1_GT_BIT, 264 265 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 266 // target (returns (Lo, Hi)). It takes a chain operand. 267 READ_TIME_BASE, 268 269 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 270 EH_SJLJ_SETJMP, 271 272 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 273 EH_SJLJ_LONGJMP, 274 275 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 276 /// instructions. For lack of better number, we use the opcode number 277 /// encoding for the OPC field to identify the compare. For example, 838 278 /// is VCMPGTSH. 279 VCMP, 280 281 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the 282 /// altivec VCMP*_rec instructions. For lack of better number, we use the 283 /// opcode number encoding for the OPC field to identify the compare. For 284 /// example, 838 is VCMPGTSH. 285 VCMP_rec, 286 287 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 288 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 289 /// condition register to branch on, OPC is the branch opcode to use (e.g. 290 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 291 /// an optional input flag argument. 292 COND_BRANCH, 293 294 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 295 /// loops. 296 BDNZ, 297 BDZ, 298 299 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 300 /// towards zero. Used only as part of the long double-to-int 301 /// conversion sequence. 302 FADDRTZ, 303 304 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 305 MFFS, 306 307 /// TC_RETURN - A tail call return. 308 /// operand #0 chain 309 /// operand #1 callee (register or absolute) 310 /// operand #2 stack adjustment 311 /// operand #3 optional in flag 312 TC_RETURN, 313 314 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 315 CR6SET, 316 CR6UNSET, 317 318 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 319 /// for non-position independent code on PPC32. 320 PPC32_GOT, 321 322 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 323 /// local dynamic TLS and position indendepent code on PPC32. 324 PPC32_PICGOT, 325 326 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 327 /// TLS model, produces an ADDIS8 instruction that adds the GOT 328 /// base to sym\@got\@tprel\@ha. 329 ADDIS_GOT_TPREL_HA, 330 331 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 332 /// TLS model, produces a LD instruction with base register G8RReg 333 /// and offset sym\@got\@tprel\@l. This completes the addition that 334 /// finds the offset of "sym" relative to the thread pointer. 335 LD_GOT_TPREL_L, 336 337 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 338 /// model, produces an ADD instruction that adds the contents of 339 /// G8RReg to the thread pointer. Symbol contains a relocation 340 /// sym\@tls which is to be replaced by the thread pointer and 341 /// identifies to the linker that the instruction is part of a 342 /// TLS sequence. 343 ADD_TLS, 344 345 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 346 /// model, produces an ADDIS8 instruction that adds the GOT base 347 /// register to sym\@got\@tlsgd\@ha. 348 ADDIS_TLSGD_HA, 349 350 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 351 /// model, produces an ADDI8 instruction that adds G8RReg to 352 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 353 /// ADDIS_TLSGD_L_ADDR until after register assignment. 354 ADDI_TLSGD_L, 355 356 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 357 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 358 /// ADDIS_TLSGD_L_ADDR until after register assignment. 359 GET_TLS_ADDR, 360 361 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 362 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 363 /// register assignment. 364 ADDI_TLSGD_L_ADDR, 365 366 /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY 367 /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY 368 /// Op that combines two register copies of TOC entries 369 /// (region handle into R3 and variable offset into R4) followed by a 370 /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr. 371 /// This node is used in 64-bit mode as well (in which case the result is 372 /// G8RC and inputs are X3/X4). 373 TLSGD_AIX, 374 375 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 376 /// model, produces an ADDIS8 instruction that adds the GOT base 377 /// register to sym\@got\@tlsld\@ha. 378 ADDIS_TLSLD_HA, 379 380 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 381 /// model, produces an ADDI8 instruction that adds G8RReg to 382 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 383 /// ADDIS_TLSLD_L_ADDR until after register assignment. 384 ADDI_TLSLD_L, 385 386 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 387 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 388 /// ADDIS_TLSLD_L_ADDR until after register assignment. 389 GET_TLSLD_ADDR, 390 391 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 392 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 393 /// following register assignment. 394 ADDI_TLSLD_L_ADDR, 395 396 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 397 /// model, produces an ADDIS8 instruction that adds X3 to 398 /// sym\@dtprel\@ha. 399 ADDIS_DTPREL_HA, 400 401 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 402 /// model, produces an ADDI8 instruction that adds G8RReg to 403 /// sym\@got\@dtprel\@l. 404 ADDI_DTPREL_L, 405 406 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS 407 /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. 408 PADDI_DTPREL, 409 410 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 411 /// during instruction selection to optimize a BUILD_VECTOR into 412 /// operations on splats. This is necessary to avoid losing these 413 /// optimizations due to constant folding. 414 VADD_SPLAT, 415 416 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 417 /// operand identifies the operating system entry point. 418 SC, 419 420 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 421 CLRBHRB, 422 423 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 424 /// history rolling buffer entry. 425 MFBHRBE, 426 427 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 428 RFEBB, 429 430 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 431 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 432 /// or stxvd2x instruction. The chain is necessary because the 433 /// sequence replaces a load and needs to provide the same number 434 /// of outputs. 435 XXSWAPD, 436 437 /// An SDNode for swaps that are not associated with any loads/stores 438 /// and thereby have no chain. 439 SWAP_NO_CHAIN, 440 441 /// An SDNode for Power9 vector absolute value difference. 442 /// operand #0 vector 443 /// operand #1 vector 444 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 445 /// the most significant bit for signed i32 446 /// 447 /// Power9 VABSD* instructions are designed to support unsigned integer 448 /// vectors (byte/halfword/word), if we want to make use of them for signed 449 /// integer vectors, we have to flip their sign bits first. To flip sign bit 450 /// for byte/halfword integer vector would become inefficient, but for word 451 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: 452 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 453 /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) 454 VABSD, 455 456 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 457 /// lower (IDX=1) half of v4f32 to v2f64. 458 FP_EXTEND_HALF, 459 460 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done 461 /// either through an add like PADDI or through a PC Relative load like 462 /// PLD. 463 MAT_PCREL_ADDR, 464 465 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for 466 /// TLS global address when using dynamic access models. This can be done 467 /// through an add like PADDI. 468 TLS_DYNAMIC_MAT_PCREL_ADDR, 469 470 /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address 471 /// when using local exec access models, and when prefixed instructions are 472 /// available. This is used with ADD_TLS to produce an add like PADDI. 473 TLS_LOCAL_EXEC_MAT_ADDR, 474 475 /// ACC_BUILD = Build an accumulator register from 4 VSX registers. 476 ACC_BUILD, 477 478 /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. 479 PAIR_BUILD, 480 481 /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of 482 /// an accumulator or pair register. This node is needed because 483 /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same 484 /// element type. 485 EXTRACT_VSX_REG, 486 487 /// XXMFACC = This corresponds to the xxmfacc instruction. 488 XXMFACC, 489 490 // Constrained conversion from floating point to int 491 STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, 492 STRICT_FCTIWZ, 493 STRICT_FCTIDUZ, 494 STRICT_FCTIWUZ, 495 496 /// Constrained integer-to-floating-point conversion instructions. 497 STRICT_FCFID, 498 STRICT_FCFIDU, 499 STRICT_FCFIDS, 500 STRICT_FCFIDUS, 501 502 /// Constrained floating point add in round-to-zero mode. 503 STRICT_FADDRTZ, 504 505 // NOTE: The nodes below may require PC-Rel specific patterns if the 506 // address could be PC-Relative. When adding new nodes below, consider 507 // whether or not the address can be PC-Relative and add the corresponding 508 // PC-relative patterns and tests. 509 510 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 511 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 512 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 513 /// i32. 514 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 515 516 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 517 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 518 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 519 /// or i32. 520 LBRX, 521 522 /// STFIWX - The STFIWX instruction. The first operand is an input token 523 /// chain, then an f64 value to store, then an address to store it to. 524 STFIWX, 525 526 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 527 /// load which sign-extends from a 32-bit integer value into the 528 /// destination 64-bit register. 529 LFIWAX, 530 531 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 532 /// load which zero-extends from a 32-bit integer value into the 533 /// destination 64-bit register. 534 LFIWZX, 535 536 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 537 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 538 /// This can be used for converting loaded integers to floating point. 539 LXSIZX, 540 541 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 542 /// chain, then an f64 value to store, then an address to store it to, 543 /// followed by a byte-width for the store. 544 STXSIX, 545 546 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 547 /// Maps directly to an lxvd2x instruction that will be followed by 548 /// an xxswapd. 549 LXVD2X, 550 551 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend 552 /// This node represents v1i128 BUILD_VECTOR of a zero extending load 553 /// instruction from <byte, halfword, word, or doubleword> to i128. 554 /// Allows utilization of the Load VSX Vector Rightmost Instructions. 555 LXVRZX, 556 557 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 558 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 559 /// the vector type to load vector in big-endian element order. 560 LOAD_VEC_BE, 561 562 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 563 /// v2f32 value into the lower half of a VSR register. 564 LD_VSX_LH, 565 566 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 567 /// instructions such as LXVDSX, LXVWSX. 568 LD_SPLAT, 569 570 /// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory 571 /// that zero-extends. 572 ZEXT_LD_SPLAT, 573 574 /// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory 575 /// that sign-extends. 576 SEXT_LD_SPLAT, 577 578 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 579 /// Maps directly to an stxvd2x instruction that will be preceded by 580 /// an xxswapd. 581 STXVD2X, 582 583 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 584 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 585 /// the vector type to store vector in big-endian element order. 586 STORE_VEC_BE, 587 588 /// Store scalar integers from VSR. 589 ST_VSR_SCAL_INT, 590 591 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 592 /// except they ensure that the compare input is zero-extended for 593 /// sub-word versions because the atomic loads zero-extend. 594 ATOMIC_CMP_SWAP_8, 595 ATOMIC_CMP_SWAP_16, 596 597 /// GPRC = TOC_ENTRY GA, TOC 598 /// Loads the entry for GA from the TOC, where the TOC base is given by 599 /// the last operand. 600 TOC_ENTRY 601 }; 602 603 } // end namespace PPCISD 604 605 /// Define some predicates that are used for node matching. 606 namespace PPC { 607 608 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 609 /// VPKUHUM instruction. 610 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 611 SelectionDAG &DAG); 612 613 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 614 /// VPKUWUM instruction. 615 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 616 SelectionDAG &DAG); 617 618 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 619 /// VPKUDUM instruction. 620 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 621 SelectionDAG &DAG); 622 623 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 624 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 625 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 626 unsigned ShuffleKind, SelectionDAG &DAG); 627 628 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 629 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 630 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 631 unsigned ShuffleKind, SelectionDAG &DAG); 632 633 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 634 /// a VMRGEW or VMRGOW instruction 635 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 636 unsigned ShuffleKind, SelectionDAG &DAG); 637 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 638 /// for a XXSLDWI instruction. 639 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 640 bool &Swap, bool IsLE); 641 642 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 643 /// for a XXBRH instruction. 644 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 645 646 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 647 /// for a XXBRW instruction. 648 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 649 650 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 651 /// for a XXBRD instruction. 652 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 653 654 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 655 /// for a XXBRQ instruction. 656 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 657 658 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 659 /// for a XXPERMDI instruction. 660 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 661 bool &Swap, bool IsLE); 662 663 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 664 /// shift amount, otherwise return -1. 665 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 666 SelectionDAG &DAG); 667 668 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 669 /// specifies a splat of a single element that is suitable for input to 670 /// VSPLTB/VSPLTH/VSPLTW. 671 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 672 673 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 674 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 675 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 676 /// vector into the other. This function will also set a couple of 677 /// output parameters for how much the source vector needs to be shifted and 678 /// what byte number needs to be specified for the instruction to put the 679 /// element in the desired location of the target vector. 680 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 681 unsigned &InsertAtByte, bool &Swap, bool IsLE); 682 683 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 684 /// appropriate for PPC mnemonics (which have a big endian bias - namely 685 /// elements are counted from the left of the vector register). 686 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 687 SelectionDAG &DAG); 688 689 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 690 /// formed by using a vspltis[bhw] instruction of the specified element 691 /// size, return the constant being splatted. The ByteSize field indicates 692 /// the number of bytes of each element [124] -> [bhw]. 693 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 694 695 // Flags for computing the optimal addressing mode for loads and stores. 696 enum MemOpFlags { 697 MOF_None = 0, 698 699 // Extension mode for integer loads. 700 MOF_SExt = 1, 701 MOF_ZExt = 1 << 1, 702 MOF_NoExt = 1 << 2, 703 704 // Address computation flags. 705 MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar. 706 MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant. 707 MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation 708 MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4. 709 MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16. 710 MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant. 711 MOF_RPlusR = 1 << 11, // Sum of two variables. 712 MOF_PCRel = 1 << 12, // PC-Relative relocation. 713 MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant. 714 715 // The in-memory type. 716 MOF_SubWordInt = 1 << 15, 717 MOF_WordInt = 1 << 16, 718 MOF_DoubleWordInt = 1 << 17, 719 MOF_ScalarFloat = 1 << 18, // Scalar single or double precision. 720 MOF_Vector = 1 << 19, // Vector types and quad precision scalars. 721 MOF_Vector256 = 1 << 20, 722 723 // Subtarget features. 724 MOF_SubtargetBeforeP9 = 1 << 22, 725 MOF_SubtargetP9 = 1 << 23, 726 MOF_SubtargetP10 = 1 << 24, 727 MOF_SubtargetSPE = 1 << 25 728 }; 729 730 // The addressing modes for loads and stores. 731 enum AddrMode { 732 AM_None, 733 AM_DForm, 734 AM_DSForm, 735 AM_DQForm, 736 AM_PrefixDForm, 737 AM_XForm, 738 AM_PCRel 739 }; 740 } // end namespace PPC 741 742 class PPCTargetLowering : public TargetLowering { 743 const PPCSubtarget &Subtarget; 744 745 public: 746 explicit PPCTargetLowering(const PPCTargetMachine &TM, 747 const PPCSubtarget &STI); 748 749 /// getTargetNodeName() - This method returns the name of a target specific 750 /// DAG node. 751 const char *getTargetNodeName(unsigned Opcode) const override; 752 753 bool isSelectSupported(SelectSupportKind Kind) const override { 754 // PowerPC does not support scalar condition selects on vectors. 755 return (Kind != SelectSupportKind::ScalarCondVectorVal); 756 } 757 758 /// getPreferredVectorAction - The code we generate when vector types are 759 /// legalized by promoting the integer element type is often much worse 760 /// than code we generate if we widen the type for applicable vector types. 761 /// The issue with promoting is that the vector is scalaraized, individual 762 /// elements promoted and then the vector is rebuilt. So say we load a pair 763 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 764 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 765 /// then the VPERM for the shuffle. All in all a very slow sequence. 766 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 767 const override { 768 // Default handling for scalable and single-element vectors. 769 if (VT.isScalableVector() || VT.getVectorNumElements() == 1) 770 return TargetLoweringBase::getPreferredVectorAction(VT); 771 772 // Split and promote vNi1 vectors so we don't produce v256i1/v512i1 773 // types as those are only for MMA instructions. 774 if (VT.getScalarSizeInBits() == 1 && VT.getSizeInBits() > 16) 775 return TypeSplitVector; 776 if (VT.getScalarSizeInBits() == 1) 777 return TypePromoteInteger; 778 779 // Widen vectors that have reasonably sized elements. 780 if (VT.getScalarSizeInBits() % 8 == 0) 781 return TypeWidenVector; 782 return TargetLoweringBase::getPreferredVectorAction(VT); 783 } 784 785 bool useSoftFloat() const override; 786 787 bool hasSPE() const; 788 789 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 790 return MVT::i32; 791 } 792 793 bool isCheapToSpeculateCttz() const override { 794 return true; 795 } 796 797 bool isCheapToSpeculateCtlz() const override { 798 return true; 799 } 800 801 bool isCtlzFast() const override { 802 return true; 803 } 804 805 bool isEqualityCmpFoldedWithSignedCmp() const override { 806 return false; 807 } 808 809 bool hasAndNotCompare(SDValue) const override { 810 return true; 811 } 812 813 bool preferIncOfAddToSubOfNot(EVT VT) const override; 814 815 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 816 return VT.isScalarInteger(); 817 } 818 819 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, 820 bool OptForSize, NegatibleCost &Cost, 821 unsigned Depth = 0) const override; 822 823 /// getSetCCResultType - Return the ISD::SETCC ValueType 824 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 825 EVT VT) const override; 826 827 /// Return true if target always benefits from combining into FMA for a 828 /// given value type. This must typically return false on targets where FMA 829 /// takes more cycles to execute than FADD. 830 bool enableAggressiveFMAFusion(EVT VT) const override; 831 832 /// getPreIndexedAddressParts - returns true by value, base pointer and 833 /// offset pointer and addressing mode by reference if the node's address 834 /// can be legally represented as pre-indexed load / store address. 835 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 836 SDValue &Offset, 837 ISD::MemIndexedMode &AM, 838 SelectionDAG &DAG) const override; 839 840 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 841 /// it can be more efficiently represented as [r+imm]. 842 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 843 SelectionDAG &DAG) const; 844 845 /// SelectAddressRegReg - Given the specified addressed, check to see if it 846 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 847 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 848 /// Returns false if it can be represented by [r+imm], which are preferred. 849 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 850 SelectionDAG &DAG, 851 MaybeAlign EncodingAlignment = None) const; 852 853 /// SelectAddressRegImm - Returns true if the address N can be represented 854 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 855 /// is not better represented as reg+reg. If \p EncodingAlignment is 856 /// non-zero, only accept displacements suitable for instruction encoding 857 /// requirement, i.e. multiples of 4 for DS form. 858 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 859 SelectionDAG &DAG, 860 MaybeAlign EncodingAlignment) const; 861 bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, 862 SelectionDAG &DAG) const; 863 864 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 865 /// represented as an indexed [r+r] operation. 866 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 867 SelectionDAG &DAG) const; 868 869 /// SelectAddressPCRel - Represent the specified address as pc relative to 870 /// be represented as [pc+imm] 871 bool SelectAddressPCRel(SDValue N, SDValue &Base) const; 872 873 Sched::Preference getSchedulingPreference(SDNode *N) const override; 874 875 /// LowerOperation - Provide custom lowering hooks for some operations. 876 /// 877 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 878 879 /// ReplaceNodeResults - Replace the results of node with an illegal result 880 /// type with new values built out of custom code. 881 /// 882 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 883 SelectionDAG &DAG) const override; 884 885 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 886 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 887 888 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 889 890 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 891 SmallVectorImpl<SDNode *> &Created) const override; 892 893 Register getRegisterByName(const char* RegName, LLT VT, 894 const MachineFunction &MF) const override; 895 896 void computeKnownBitsForTargetNode(const SDValue Op, 897 KnownBits &Known, 898 const APInt &DemandedElts, 899 const SelectionDAG &DAG, 900 unsigned Depth = 0) const override; 901 902 Align getPrefLoopAlignment(MachineLoop *ML) const override; 903 904 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 905 return true; 906 } 907 908 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 909 AtomicOrdering Ord) const override; 910 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 911 AtomicOrdering Ord) const override; 912 913 TargetLowering::AtomicExpansionKind 914 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 915 916 TargetLowering::AtomicExpansionKind 917 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 918 919 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, 920 AtomicRMWInst *AI, Value *AlignedAddr, 921 Value *Incr, Value *Mask, 922 Value *ShiftAmt, 923 AtomicOrdering Ord) const override; 924 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 925 AtomicCmpXchgInst *CI, 926 Value *AlignedAddr, Value *CmpVal, 927 Value *NewVal, Value *Mask, 928 AtomicOrdering Ord) const override; 929 930 MachineBasicBlock * 931 EmitInstrWithCustomInserter(MachineInstr &MI, 932 MachineBasicBlock *MBB) const override; 933 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 934 MachineBasicBlock *MBB, 935 unsigned AtomicSize, 936 unsigned BinOpcode, 937 unsigned CmpOpcode = 0, 938 unsigned CmpPred = 0) const; 939 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 940 MachineBasicBlock *MBB, 941 bool is8bit, 942 unsigned Opcode, 943 unsigned CmpOpcode = 0, 944 unsigned CmpPred = 0) const; 945 946 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 947 MachineBasicBlock *MBB) const; 948 949 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 950 MachineBasicBlock *MBB) const; 951 952 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 953 MachineBasicBlock *MBB) const; 954 955 bool hasInlineStackProbe(MachineFunction &MF) const override; 956 957 unsigned getStackProbeSize(MachineFunction &MF) const; 958 959 ConstraintType getConstraintType(StringRef Constraint) const override; 960 961 /// Examine constraint string and operand type and determine a weight value. 962 /// The operand object must already have been set up with the operand type. 963 ConstraintWeight getSingleConstraintMatchWeight( 964 AsmOperandInfo &info, const char *constraint) const override; 965 966 std::pair<unsigned, const TargetRegisterClass *> 967 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 968 StringRef Constraint, MVT VT) const override; 969 970 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 971 /// function arguments in the caller parameter area. This is the actual 972 /// alignment, not its logarithm. 973 uint64_t getByValTypeAlignment(Type *Ty, 974 const DataLayout &DL) const override; 975 976 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 977 /// vector. If it is invalid, don't add anything to Ops. 978 void LowerAsmOperandForConstraint(SDValue Op, 979 std::string &Constraint, 980 std::vector<SDValue> &Ops, 981 SelectionDAG &DAG) const override; 982 983 unsigned 984 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 985 if (ConstraintCode == "es") 986 return InlineAsm::Constraint_es; 987 else if (ConstraintCode == "Q") 988 return InlineAsm::Constraint_Q; 989 else if (ConstraintCode == "Z") 990 return InlineAsm::Constraint_Z; 991 else if (ConstraintCode == "Zy") 992 return InlineAsm::Constraint_Zy; 993 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 994 } 995 996 /// isLegalAddressingMode - Return true if the addressing mode represented 997 /// by AM is legal for this target, for a load/store of the specified type. 998 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 999 Type *Ty, unsigned AS, 1000 Instruction *I = nullptr) const override; 1001 1002 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1003 /// icmp immediate, that is the target has icmp instructions which can 1004 /// compare a register against the immediate without having to materialize 1005 /// the immediate into a register. 1006 bool isLegalICmpImmediate(int64_t Imm) const override; 1007 1008 /// isLegalAddImmediate - Return true if the specified immediate is legal 1009 /// add immediate, that is the target has add instructions which can 1010 /// add a register and the immediate without having to materialize 1011 /// the immediate into a register. 1012 bool isLegalAddImmediate(int64_t Imm) const override; 1013 1014 /// isTruncateFree - Return true if it's free to truncate a value of 1015 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 1016 /// register X1 to i32 by referencing its sub-register R1. 1017 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 1018 bool isTruncateFree(EVT VT1, EVT VT2) const override; 1019 1020 bool isZExtFree(SDValue Val, EVT VT2) const override; 1021 1022 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 1023 1024 /// Returns true if it is beneficial to convert a load of a constant 1025 /// to just the constant itself. 1026 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 1027 Type *Ty) const override; 1028 1029 bool convertSelectOfConstantsToMath(EVT VT) const override { 1030 return true; 1031 } 1032 1033 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 1034 SDValue C) const override; 1035 1036 bool isDesirableToTransformToIntegerOp(unsigned Opc, 1037 EVT VT) const override { 1038 // Only handle float load/store pair because float(fpr) load/store 1039 // instruction has more cycles than integer(gpr) load/store in PPC. 1040 if (Opc != ISD::LOAD && Opc != ISD::STORE) 1041 return false; 1042 if (VT != MVT::f32 && VT != MVT::f64) 1043 return false; 1044 1045 return true; 1046 } 1047 1048 // Returns true if the address of the global is stored in TOC entry. 1049 bool isAccessedAsGotIndirect(SDValue N) const; 1050 1051 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 1052 1053 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 1054 const CallInst &I, 1055 MachineFunction &MF, 1056 unsigned Intrinsic) const override; 1057 1058 /// It returns EVT::Other if the type should be determined using generic 1059 /// target-independent logic. 1060 EVT getOptimalMemOpType(const MemOp &Op, 1061 const AttributeList &FuncAttributes) const override; 1062 1063 /// Is unaligned memory access allowed for the given type, and is it fast 1064 /// relative to software emulation. 1065 bool allowsMisalignedMemoryAccesses( 1066 EVT VT, unsigned AddrSpace, Align Alignment = Align(1), 1067 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1068 bool *Fast = nullptr) const override; 1069 1070 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 1071 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 1072 /// expanded to FMAs when this method returns true, otherwise fmuladd is 1073 /// expanded to fmul + fadd. 1074 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 1075 EVT VT) const override; 1076 1077 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 1078 1079 /// isProfitableToHoist - Check if it is profitable to hoist instruction 1080 /// \p I to its dominator block. 1081 /// For example, it is not profitable if \p I and it's only user can form a 1082 /// FMA instruction, because Powerpc prefers FMADD. 1083 bool isProfitableToHoist(Instruction *I) const override; 1084 1085 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 1086 1087 // Should we expand the build vector with shuffles? 1088 bool 1089 shouldExpandBuildVectorWithShuffles(EVT VT, 1090 unsigned DefinedValues) const override; 1091 1092 // Keep the zero-extensions for arguments to libcalls. 1093 bool shouldKeepZExtForFP16Conv() const override { return true; } 1094 1095 /// createFastISel - This method returns a target-specific FastISel object, 1096 /// or null if the target does not support "fast" instruction selection. 1097 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1098 const TargetLibraryInfo *LibInfo) const override; 1099 1100 /// Returns true if an argument of type Ty needs to be passed in a 1101 /// contiguous block of registers in calling convention CallConv. 1102 bool functionArgumentNeedsConsecutiveRegisters( 1103 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 1104 const DataLayout &DL) const override { 1105 // We support any array type as "consecutive" block in the parameter 1106 // save area. The element type defines the alignment requirement and 1107 // whether the argument should go in GPRs, FPRs, or VRs if available. 1108 // 1109 // Note that clang uses this capability both to implement the ELFv2 1110 // homogeneous float/vector aggregate ABI, and to avoid having to use 1111 // "byval" when passing aggregates that might fully fit in registers. 1112 return Ty->isArrayTy(); 1113 } 1114 1115 /// If a physical register, this returns the register that receives the 1116 /// exception address on entry to an EH pad. 1117 Register 1118 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 1119 1120 /// If a physical register, this returns the register that receives the 1121 /// exception typeid on entry to a landing pad. 1122 Register 1123 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 1124 1125 /// Override to support customized stack guard loading. 1126 bool useLoadStackGuardNode() const override; 1127 void insertSSPDeclarations(Module &M) const override; 1128 Value *getSDagStackGuard(const Module &M) const override; 1129 1130 bool isFPImmLegal(const APFloat &Imm, EVT VT, 1131 bool ForCodeSize) const override; 1132 1133 unsigned getJumpTableEncoding() const override; 1134 bool isJumpTableRelative() const override; 1135 SDValue getPICJumpTableRelocBase(SDValue Table, 1136 SelectionDAG &DAG) const override; 1137 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1138 unsigned JTI, 1139 MCContext &Ctx) const override; 1140 1141 /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), 1142 /// compute the address flags of the node, get the optimal address mode 1143 /// based on the flags, and set the Base and Disp based on the address mode. 1144 PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, 1145 SDValue &Disp, SDValue &Base, 1146 SelectionDAG &DAG, 1147 MaybeAlign Align) const; 1148 /// SelectForceXFormMode - Given the specified address, force it to be 1149 /// represented as an indexed [r+r] operation (an XForm instruction). 1150 PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, 1151 SelectionDAG &DAG) const; 1152 1153 bool 1154 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, 1155 SDValue *Parts, unsigned NumParts, MVT PartVT, 1156 Optional<CallingConv::ID> CC) const override; 1157 /// Structure that collects some common arguments that get passed around 1158 /// between the functions for call lowering. 1159 struct CallFlags { 1160 const CallingConv::ID CallConv; 1161 const bool IsTailCall : 1; 1162 const bool IsVarArg : 1; 1163 const bool IsPatchPoint : 1; 1164 const bool IsIndirect : 1; 1165 const bool HasNest : 1; 1166 const bool NoMerge : 1; 1167 1168 CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, 1169 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge) 1170 : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg), 1171 IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect), 1172 HasNest(HasNest), NoMerge(NoMerge) {} 1173 }; 1174 1175 CCAssignFn *ccAssignFnForCall(CallingConv::ID CC, bool Return, 1176 bool IsVarArg) const; 1177 1178 private: 1179 struct ReuseLoadInfo { 1180 SDValue Ptr; 1181 SDValue Chain; 1182 SDValue ResChain; 1183 MachinePointerInfo MPI; 1184 bool IsDereferenceable = false; 1185 bool IsInvariant = false; 1186 Align Alignment; 1187 AAMDNodes AAInfo; 1188 const MDNode *Ranges = nullptr; 1189 1190 ReuseLoadInfo() = default; 1191 1192 MachineMemOperand::Flags MMOFlags() const { 1193 MachineMemOperand::Flags F = MachineMemOperand::MONone; 1194 if (IsDereferenceable) 1195 F |= MachineMemOperand::MODereferenceable; 1196 if (IsInvariant) 1197 F |= MachineMemOperand::MOInvariant; 1198 return F; 1199 } 1200 }; 1201 1202 // Map that relates a set of common address flags to PPC addressing modes. 1203 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap; 1204 void initializeAddrModeMap(); 1205 1206 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1207 SelectionDAG &DAG, 1208 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1209 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1210 SelectionDAG &DAG) const; 1211 1212 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1213 SelectionDAG &DAG, const SDLoc &dl) const; 1214 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1215 const SDLoc &dl) const; 1216 1217 bool directMoveIsProfitable(const SDValue &Op) const; 1218 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1219 const SDLoc &dl) const; 1220 1221 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1222 const SDLoc &dl) const; 1223 1224 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1225 1226 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1227 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1228 1229 bool 1230 IsEligibleForTailCallOptimization(SDValue Callee, 1231 CallingConv::ID CalleeCC, 1232 bool isVarArg, 1233 const SmallVectorImpl<ISD::InputArg> &Ins, 1234 SelectionDAG& DAG) const; 1235 1236 bool IsEligibleForTailCallOptimization_64SVR4( 1237 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, 1238 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, 1239 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 1240 1241 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1242 SDValue Chain, SDValue &LROpOut, 1243 SDValue &FPOpOut, 1244 const SDLoc &dl) const; 1245 1246 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1247 1248 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1249 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1250 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1251 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1252 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1253 SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const; 1254 SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const; 1255 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1256 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1257 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1258 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1259 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1260 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 1261 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1262 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1263 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1264 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1265 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1266 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1267 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1268 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1269 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1270 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1271 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1272 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1273 const SDLoc &dl) const; 1274 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1275 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1276 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1277 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1278 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1279 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; 1280 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1281 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1282 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1283 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1284 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1285 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1286 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1287 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const; 1288 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1289 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1290 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1291 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 1292 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 1293 1294 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1295 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1296 1297 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1298 CallingConv::ID CallConv, bool isVarArg, 1299 const SmallVectorImpl<ISD::InputArg> &Ins, 1300 const SDLoc &dl, SelectionDAG &DAG, 1301 SmallVectorImpl<SDValue> &InVals) const; 1302 1303 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, 1304 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1305 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1306 SDValue &Callee, int SPDiff, unsigned NumBytes, 1307 const SmallVectorImpl<ISD::InputArg> &Ins, 1308 SmallVectorImpl<SDValue> &InVals, 1309 const CallBase *CB) const; 1310 1311 SDValue 1312 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1313 const SmallVectorImpl<ISD::InputArg> &Ins, 1314 const SDLoc &dl, SelectionDAG &DAG, 1315 SmallVectorImpl<SDValue> &InVals) const override; 1316 1317 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1318 SmallVectorImpl<SDValue> &InVals) const override; 1319 1320 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1321 bool isVarArg, 1322 const SmallVectorImpl<ISD::OutputArg> &Outs, 1323 LLVMContext &Context) const override; 1324 1325 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1326 const SmallVectorImpl<ISD::OutputArg> &Outs, 1327 const SmallVectorImpl<SDValue> &OutVals, 1328 const SDLoc &dl, SelectionDAG &DAG) const override; 1329 1330 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1331 SelectionDAG &DAG, SDValue ArgVal, 1332 const SDLoc &dl) const; 1333 1334 SDValue LowerFormalArguments_AIX( 1335 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1336 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1337 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1338 SDValue LowerFormalArguments_64SVR4( 1339 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1340 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1341 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1342 SDValue LowerFormalArguments_32SVR4( 1343 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1344 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1345 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1346 1347 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1348 SDValue CallSeqStart, 1349 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1350 const SDLoc &dl) const; 1351 1352 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1353 const SmallVectorImpl<ISD::OutputArg> &Outs, 1354 const SmallVectorImpl<SDValue> &OutVals, 1355 const SmallVectorImpl<ISD::InputArg> &Ins, 1356 const SDLoc &dl, SelectionDAG &DAG, 1357 SmallVectorImpl<SDValue> &InVals, 1358 const CallBase *CB) const; 1359 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1360 const SmallVectorImpl<ISD::OutputArg> &Outs, 1361 const SmallVectorImpl<SDValue> &OutVals, 1362 const SmallVectorImpl<ISD::InputArg> &Ins, 1363 const SDLoc &dl, SelectionDAG &DAG, 1364 SmallVectorImpl<SDValue> &InVals, 1365 const CallBase *CB) const; 1366 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, 1367 const SmallVectorImpl<ISD::OutputArg> &Outs, 1368 const SmallVectorImpl<SDValue> &OutVals, 1369 const SmallVectorImpl<ISD::InputArg> &Ins, 1370 const SDLoc &dl, SelectionDAG &DAG, 1371 SmallVectorImpl<SDValue> &InVals, 1372 const CallBase *CB) const; 1373 1374 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1375 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1376 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1377 1378 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1379 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1380 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1381 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1382 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1383 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1384 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1385 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1386 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1387 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1388 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const; 1389 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1390 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1391 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const; 1392 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const; 1393 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN, 1394 SelectionDAG &DAG) const; 1395 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1396 DAGCombinerInfo &DCI) const; 1397 1398 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1399 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1400 /// (2) keeping the result of comparison in GPR has performance benefit. 1401 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1402 1403 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1404 int &RefinementSteps, bool &UseOneConstNR, 1405 bool Reciprocal) const override; 1406 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1407 int &RefinementSteps) const override; 1408 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1409 const DenormalMode &Mode) const override; 1410 SDValue getSqrtResultForDenormInput(SDValue Operand, 1411 SelectionDAG &DAG) const override; 1412 unsigned combineRepeatedFPDivisors() const override; 1413 1414 SDValue 1415 combineElementTruncationToVectorTruncation(SDNode *N, 1416 DAGCombinerInfo &DCI) const; 1417 1418 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1419 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1420 /// essentially any shuffle of v8i16 vectors that just inserts one element 1421 /// from one vector into the other. 1422 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1423 1424 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1425 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1426 /// essentially v16i8 vector version of VINSERTH. 1427 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1428 1429 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be 1430 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1. 1431 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1432 1433 // Return whether the call instruction can potentially be optimized to a 1434 // tail call. This will cause the optimizers to attempt to move, or 1435 // duplicate return instructions to help enable tail call optimizations. 1436 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1437 bool hasBitPreservingFPLogic(EVT VT) const override; 1438 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1439 1440 /// getAddrModeForFlags - Based on the set of address flags, select the most 1441 /// optimal instruction format to match by. 1442 PPC::AddrMode getAddrModeForFlags(unsigned Flags) const; 1443 1444 /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute 1445 /// the address flags of the load/store instruction that is to be matched. 1446 /// The address flags are stored in a map, which is then searched 1447 /// through to determine the optimal load/store instruction format. 1448 unsigned computeMOFlags(const SDNode *Parent, SDValue N, 1449 SelectionDAG &DAG) const; 1450 }; // end class PPCTargetLowering 1451 1452 namespace PPC { 1453 1454 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1455 const TargetLibraryInfo *LibInfo); 1456 1457 } // end namespace PPC 1458 1459 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1460 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1461 bool isIntS34Immediate(SDNode *N, int64_t &Imm); 1462 bool isIntS34Immediate(SDValue Op, int64_t &Imm); 1463 1464 bool convertToNonDenormSingle(APInt &ArgAPInt); 1465 bool convertToNonDenormSingle(APFloat &ArgAPFloat); 1466 bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat); 1467 1468 } // end namespace llvm 1469 1470 #endif // LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 1471