1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/SelectionDAGNodes.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/Metadata.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/MachineValueType.h" 32 #include <utility> 33 34 namespace llvm { 35 36 namespace PPCISD { 37 38 // When adding a NEW PPCISD node please add it to the correct position in 39 // the enum. The order of elements in this enum matters! 40 // Values that are added after this entry: 41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 42 // are considered memory opcodes and are treated differently than entries 43 // that come before it. For example, ADD or MUL should be placed before 44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 45 // after it. 46 enum NodeType : unsigned { 47 // Start the numbering where the builtin ops and target ops leave off. 48 FIRST_NUMBER = ISD::BUILTIN_OP_END, 49 50 /// FSEL - Traditional three-operand fsel node. 51 /// 52 FSEL, 53 54 /// XSMAXCDP, XSMINCDP - C-type min/max instructions. 55 XSMAXCDP, 56 XSMINCDP, 57 58 /// FCFID - The FCFID instruction, taking an f64 operand and producing 59 /// and f64 value containing the FP representation of the integer that 60 /// was temporarily in the f64 operand. 61 FCFID, 62 63 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 64 /// unsigned integers and single-precision outputs. 65 FCFIDU, 66 FCFIDS, 67 FCFIDUS, 68 69 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 70 /// operand, producing an f64 value containing the integer representation 71 /// of that FP value. 72 FCTIDZ, 73 FCTIWZ, 74 75 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 76 /// unsigned integers with round toward zero. 77 FCTIDUZ, 78 FCTIWUZ, 79 80 /// Floating-point-to-interger conversion instructions 81 FP_TO_UINT_IN_VSR, 82 FP_TO_SINT_IN_VSR, 83 84 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 85 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 86 VEXTS, 87 88 /// SExtVElems, takes an input vector of a smaller type and sign 89 /// extends to an output vector of a larger type. 90 SExtVElems, 91 92 /// Reciprocal estimate instructions (unary FP ops). 93 FRE, 94 FRSQRTE, 95 96 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 97 // three v4f32 operands and producing a v4f32 result. 98 VMADDFP, 99 VNMSUBFP, 100 101 /// VPERM - The PPC VPERM Instruction. 102 /// 103 VPERM, 104 105 /// XXSPLT - The PPC VSX splat instructions 106 /// 107 XXSPLT, 108 109 /// VECINSERT - The PPC vector insert instruction 110 /// 111 VECINSERT, 112 113 /// VECSHL - The PPC vector shift left instruction 114 /// 115 VECSHL, 116 117 /// XXPERMDI - The PPC XXPERMDI instruction 118 /// 119 XXPERMDI, 120 121 /// The CMPB instruction (takes two operands of i32 or i64). 122 CMPB, 123 124 /// Hi/Lo - These represent the high and low 16-bit parts of a global 125 /// address respectively. These nodes have two operands, the first of 126 /// which must be a TargetGlobalAddress, and the second of which must be a 127 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 128 /// though these are usually folded into other nodes. 129 Hi, 130 Lo, 131 132 /// The following two target-specific nodes are used for calls through 133 /// function pointers in the 64-bit SVR4 ABI. 134 135 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 136 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 137 /// compute an allocation on the stack. 138 DYNALLOC, 139 140 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 141 /// compute an offset from native SP to the address of the most recent 142 /// dynamic alloca. 143 DYNAREAOFFSET, 144 145 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 146 /// at function entry, used for PIC code. 147 GlobalBaseReg, 148 149 /// These nodes represent PPC shifts. 150 /// 151 /// For scalar types, only the last `n + 1` bits of the shift amounts 152 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 153 /// for exact behaviors. 154 /// 155 /// For vector types, only the last n bits are used. See vsld. 156 SRL, 157 SRA, 158 SHL, 159 160 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 161 /// word and shift left immediate. 162 EXTSWSLI, 163 164 /// The combination of sra[wd]i and addze used to implemented signed 165 /// integer division by a power of 2. The first operand is the dividend, 166 /// and the second is the constant shift amount (representing the 167 /// divisor). 168 SRA_ADDZE, 169 170 /// CALL - A direct function call. 171 /// CALL_NOP is a call with the special NOP which follows 64-bit 172 /// SVR4 calls and 32-bit/64-bit AIX calls. 173 CALL, 174 CALL_NOP, 175 176 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 177 /// MTCTR instruction. 178 MTCTR, 179 180 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 181 /// BCTRL instruction. 182 BCTRL, 183 184 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 185 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 186 /// and 64-bit AIX. 187 BCTRL_LOAD_TOC, 188 189 /// Return with a flag operand, matched by 'blr' 190 RET_FLAG, 191 192 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 193 /// This copies the bits corresponding to the specified CRREG into the 194 /// resultant GPR. Bits corresponding to other CR regs are undefined. 195 MFOCRF, 196 197 /// Direct move from a VSX register to a GPR 198 MFVSR, 199 200 /// Direct move from a GPR to a VSX register (algebraic) 201 MTVSRA, 202 203 /// Direct move from a GPR to a VSX register (zero) 204 MTVSRZ, 205 206 /// Direct move of 2 consecutive GPR to a VSX register. 207 BUILD_FP128, 208 209 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 210 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 211 /// unsupported for this target. 212 /// Merge 2 GPRs to a single SPE register. 213 BUILD_SPE64, 214 215 /// Extract SPE register component, second argument is high or low. 216 EXTRACT_SPE, 217 218 /// Extract a subvector from signed integer vector and convert to FP. 219 /// It is primarily used to convert a (widened) illegal integer vector 220 /// type to a legal floating point vector type. 221 /// For example v2i32 -> widened to v4i32 -> v2f64 222 SINT_VEC_TO_FP, 223 224 /// Extract a subvector from unsigned integer vector and convert to FP. 225 /// As with SINT_VEC_TO_FP, used for converting illegal types. 226 UINT_VEC_TO_FP, 227 228 // FIXME: Remove these once the ANDI glue bug is fixed: 229 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 230 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 231 /// implement truncation of i32 or i64 to i1. 232 ANDI_rec_1_EQ_BIT, 233 ANDI_rec_1_GT_BIT, 234 235 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 236 // target (returns (Lo, Hi)). It takes a chain operand. 237 READ_TIME_BASE, 238 239 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 240 EH_SJLJ_SETJMP, 241 242 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 243 EH_SJLJ_LONGJMP, 244 245 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 246 /// instructions. For lack of better number, we use the opcode number 247 /// encoding for the OPC field to identify the compare. For example, 838 248 /// is VCMPGTSH. 249 VCMP, 250 251 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 252 /// altivec VCMP*o instructions. For lack of better number, we use the 253 /// opcode number encoding for the OPC field to identify the compare. For 254 /// example, 838 is VCMPGTSH. 255 VCMPo, 256 257 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 258 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 259 /// condition register to branch on, OPC is the branch opcode to use (e.g. 260 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 261 /// an optional input flag argument. 262 COND_BRANCH, 263 264 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 265 /// loops. 266 BDNZ, 267 BDZ, 268 269 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 270 /// towards zero. Used only as part of the long double-to-int 271 /// conversion sequence. 272 FADDRTZ, 273 274 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 275 MFFS, 276 277 /// TC_RETURN - A tail call return. 278 /// operand #0 chain 279 /// operand #1 callee (register or absolute) 280 /// operand #2 stack adjustment 281 /// operand #3 optional in flag 282 TC_RETURN, 283 284 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 285 CR6SET, 286 CR6UNSET, 287 288 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 289 /// for non-position independent code on PPC32. 290 PPC32_GOT, 291 292 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 293 /// local dynamic TLS and position indendepent code on PPC32. 294 PPC32_PICGOT, 295 296 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 297 /// TLS model, produces an ADDIS8 instruction that adds the GOT 298 /// base to sym\@got\@tprel\@ha. 299 ADDIS_GOT_TPREL_HA, 300 301 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 302 /// TLS model, produces a LD instruction with base register G8RReg 303 /// and offset sym\@got\@tprel\@l. This completes the addition that 304 /// finds the offset of "sym" relative to the thread pointer. 305 LD_GOT_TPREL_L, 306 307 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 308 /// model, produces an ADD instruction that adds the contents of 309 /// G8RReg to the thread pointer. Symbol contains a relocation 310 /// sym\@tls which is to be replaced by the thread pointer and 311 /// identifies to the linker that the instruction is part of a 312 /// TLS sequence. 313 ADD_TLS, 314 315 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 316 /// model, produces an ADDIS8 instruction that adds the GOT base 317 /// register to sym\@got\@tlsgd\@ha. 318 ADDIS_TLSGD_HA, 319 320 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 321 /// model, produces an ADDI8 instruction that adds G8RReg to 322 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 323 /// ADDIS_TLSGD_L_ADDR until after register assignment. 324 ADDI_TLSGD_L, 325 326 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 327 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 328 /// ADDIS_TLSGD_L_ADDR until after register assignment. 329 GET_TLS_ADDR, 330 331 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 332 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 333 /// register assignment. 334 ADDI_TLSGD_L_ADDR, 335 336 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 337 /// model, produces an ADDIS8 instruction that adds the GOT base 338 /// register to sym\@got\@tlsld\@ha. 339 ADDIS_TLSLD_HA, 340 341 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 342 /// model, produces an ADDI8 instruction that adds G8RReg to 343 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 344 /// ADDIS_TLSLD_L_ADDR until after register assignment. 345 ADDI_TLSLD_L, 346 347 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 348 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 349 /// ADDIS_TLSLD_L_ADDR until after register assignment. 350 GET_TLSLD_ADDR, 351 352 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 353 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 354 /// following register assignment. 355 ADDI_TLSLD_L_ADDR, 356 357 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 358 /// model, produces an ADDIS8 instruction that adds X3 to 359 /// sym\@dtprel\@ha. 360 ADDIS_DTPREL_HA, 361 362 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 363 /// model, produces an ADDI8 instruction that adds G8RReg to 364 /// sym\@got\@dtprel\@l. 365 ADDI_DTPREL_L, 366 367 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 368 /// during instruction selection to optimize a BUILD_VECTOR into 369 /// operations on splats. This is necessary to avoid losing these 370 /// optimizations due to constant folding. 371 VADD_SPLAT, 372 373 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 374 /// operand identifies the operating system entry point. 375 SC, 376 377 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 378 CLRBHRB, 379 380 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 381 /// history rolling buffer entry. 382 MFBHRBE, 383 384 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 385 RFEBB, 386 387 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 388 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 389 /// or stxvd2x instruction. The chain is necessary because the 390 /// sequence replaces a load and needs to provide the same number 391 /// of outputs. 392 XXSWAPD, 393 394 /// An SDNode for swaps that are not associated with any loads/stores 395 /// and thereby have no chain. 396 SWAP_NO_CHAIN, 397 398 /// An SDNode for Power9 vector absolute value difference. 399 /// operand #0 vector 400 /// operand #1 vector 401 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 402 /// the most significant bit for signed i32 403 /// 404 /// Power9 VABSD* instructions are designed to support unsigned integer 405 /// vectors (byte/halfword/word), if we want to make use of them for signed 406 /// integer vectors, we have to flip their sign bits first. To flip sign bit 407 /// for byte/halfword integer vector would become inefficient, but for word 408 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: 409 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 410 /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) 411 VABSD, 412 413 /// QVFPERM = This corresponds to the QPX qvfperm instruction. 414 QVFPERM, 415 416 /// QVGPCI = This corresponds to the QPX qvgpci instruction. 417 QVGPCI, 418 419 /// QVALIGNI = This corresponds to the QPX qvaligni instruction. 420 QVALIGNI, 421 422 /// QVESPLATI = This corresponds to the QPX qvesplati instruction. 423 QVESPLATI, 424 425 /// QBFLT = Access the underlying QPX floating-point boolean 426 /// representation. 427 QBFLT, 428 429 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 430 /// lower (IDX=1) half of v4f32 to v2f64. 431 FP_EXTEND_HALF, 432 433 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 434 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 435 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 436 /// i32. 437 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 438 439 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 440 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 441 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 442 /// or i32. 443 LBRX, 444 445 /// STFIWX - The STFIWX instruction. The first operand is an input token 446 /// chain, then an f64 value to store, then an address to store it to. 447 STFIWX, 448 449 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 450 /// load which sign-extends from a 32-bit integer value into the 451 /// destination 64-bit register. 452 LFIWAX, 453 454 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 455 /// load which zero-extends from a 32-bit integer value into the 456 /// destination 64-bit register. 457 LFIWZX, 458 459 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 460 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 461 /// This can be used for converting loaded integers to floating point. 462 LXSIZX, 463 464 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 465 /// chain, then an f64 value to store, then an address to store it to, 466 /// followed by a byte-width for the store. 467 STXSIX, 468 469 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 470 /// Maps directly to an lxvd2x instruction that will be followed by 471 /// an xxswapd. 472 LXVD2X, 473 474 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 475 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 476 /// the vector type to load vector in big-endian element order. 477 LOAD_VEC_BE, 478 479 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 480 /// v2f32 value into the lower half of a VSR register. 481 LD_VSX_LH, 482 483 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 484 /// instructions such as LXVDSX, LXVWSX. 485 LD_SPLAT, 486 487 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 488 /// Maps directly to an stxvd2x instruction that will be preceded by 489 /// an xxswapd. 490 STXVD2X, 491 492 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 493 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 494 /// the vector type to store vector in big-endian element order. 495 STORE_VEC_BE, 496 497 /// Store scalar integers from VSR. 498 ST_VSR_SCAL_INT, 499 500 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr 501 /// The 4xf32 load used for v4i1 constants. 502 QVLFSb, 503 504 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 505 /// except they ensure that the compare input is zero-extended for 506 /// sub-word versions because the atomic loads zero-extend. 507 ATOMIC_CMP_SWAP_8, 508 ATOMIC_CMP_SWAP_16, 509 510 /// GPRC = TOC_ENTRY GA, TOC 511 /// Loads the entry for GA from the TOC, where the TOC base is given by 512 /// the last operand. 513 TOC_ENTRY 514 }; 515 516 } // end namespace PPCISD 517 518 /// Define some predicates that are used for node matching. 519 namespace PPC { 520 521 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 522 /// VPKUHUM instruction. 523 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 524 SelectionDAG &DAG); 525 526 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 527 /// VPKUWUM instruction. 528 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 529 SelectionDAG &DAG); 530 531 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 532 /// VPKUDUM instruction. 533 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 534 SelectionDAG &DAG); 535 536 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 537 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 538 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 539 unsigned ShuffleKind, SelectionDAG &DAG); 540 541 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 542 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 543 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 544 unsigned ShuffleKind, SelectionDAG &DAG); 545 546 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 547 /// a VMRGEW or VMRGOW instruction 548 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 549 unsigned ShuffleKind, SelectionDAG &DAG); 550 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 551 /// for a XXSLDWI instruction. 552 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 553 bool &Swap, bool IsLE); 554 555 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 556 /// for a XXBRH instruction. 557 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 558 559 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 560 /// for a XXBRW instruction. 561 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 562 563 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 564 /// for a XXBRD instruction. 565 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 566 567 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 568 /// for a XXBRQ instruction. 569 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 570 571 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 572 /// for a XXPERMDI instruction. 573 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 574 bool &Swap, bool IsLE); 575 576 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 577 /// shift amount, otherwise return -1. 578 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 579 SelectionDAG &DAG); 580 581 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 582 /// specifies a splat of a single element that is suitable for input to 583 /// VSPLTB/VSPLTH/VSPLTW. 584 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 585 586 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 587 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 588 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 589 /// vector into the other. This function will also set a couple of 590 /// output parameters for how much the source vector needs to be shifted and 591 /// what byte number needs to be specified for the instruction to put the 592 /// element in the desired location of the target vector. 593 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 594 unsigned &InsertAtByte, bool &Swap, bool IsLE); 595 596 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 597 /// appropriate for PPC mnemonics (which have a big endian bias - namely 598 /// elements are counted from the left of the vector register). 599 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 600 SelectionDAG &DAG); 601 602 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 603 /// formed by using a vspltis[bhw] instruction of the specified element 604 /// size, return the constant being splatted. The ByteSize field indicates 605 /// the number of bytes of each element [124] -> [bhw]. 606 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 607 608 /// If this is a qvaligni shuffle mask, return the shift 609 /// amount, otherwise return -1. 610 int isQVALIGNIShuffleMask(SDNode *N); 611 612 } // end namespace PPC 613 614 class PPCTargetLowering : public TargetLowering { 615 const PPCSubtarget &Subtarget; 616 617 public: 618 explicit PPCTargetLowering(const PPCTargetMachine &TM, 619 const PPCSubtarget &STI); 620 621 /// getTargetNodeName() - This method returns the name of a target specific 622 /// DAG node. 623 const char *getTargetNodeName(unsigned Opcode) const override; 624 625 bool isSelectSupported(SelectSupportKind Kind) const override { 626 // PowerPC does not support scalar condition selects on vectors. 627 return (Kind != SelectSupportKind::ScalarCondVectorVal); 628 } 629 630 /// getPreferredVectorAction - The code we generate when vector types are 631 /// legalized by promoting the integer element type is often much worse 632 /// than code we generate if we widen the type for applicable vector types. 633 /// The issue with promoting is that the vector is scalaraized, individual 634 /// elements promoted and then the vector is rebuilt. So say we load a pair 635 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 636 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 637 /// then the VPERM for the shuffle. All in all a very slow sequence. 638 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 639 const override { 640 if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0) 641 return TypeWidenVector; 642 return TargetLoweringBase::getPreferredVectorAction(VT); 643 } 644 645 bool useSoftFloat() const override; 646 647 bool hasSPE() const; 648 649 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 650 return MVT::i32; 651 } 652 653 bool isCheapToSpeculateCttz() const override { 654 return true; 655 } 656 657 bool isCheapToSpeculateCtlz() const override { 658 return true; 659 } 660 661 bool isCtlzFast() const override { 662 return true; 663 } 664 665 bool isEqualityCmpFoldedWithSignedCmp() const override { 666 return false; 667 } 668 669 bool hasAndNotCompare(SDValue) const override { 670 return true; 671 } 672 673 bool preferIncOfAddToSubOfNot(EVT VT) const override; 674 675 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 676 return VT.isScalarInteger(); 677 } 678 679 bool supportSplitCSR(MachineFunction *MF) const override { 680 return 681 MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 682 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 683 } 684 685 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 686 687 void insertCopiesSplitCSR( 688 MachineBasicBlock *Entry, 689 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 690 691 /// getSetCCResultType - Return the ISD::SETCC ValueType 692 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 693 EVT VT) const override; 694 695 /// Return true if target always beneficiates from combining into FMA for a 696 /// given value type. This must typically return false on targets where FMA 697 /// takes more cycles to execute than FADD. 698 bool enableAggressiveFMAFusion(EVT VT) const override; 699 700 /// getPreIndexedAddressParts - returns true by value, base pointer and 701 /// offset pointer and addressing mode by reference if the node's address 702 /// can be legally represented as pre-indexed load / store address. 703 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 704 SDValue &Offset, 705 ISD::MemIndexedMode &AM, 706 SelectionDAG &DAG) const override; 707 708 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 709 /// it can be more efficiently represented as [r+imm]. 710 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 711 SelectionDAG &DAG) const; 712 713 /// SelectAddressRegReg - Given the specified addressed, check to see if it 714 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 715 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 716 /// Returns false if it can be represented by [r+imm], which are preferred. 717 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 718 SelectionDAG &DAG, 719 unsigned EncodingAlignment = 0) const; 720 721 /// SelectAddressRegImm - Returns true if the address N can be represented 722 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 723 /// is not better represented as reg+reg. If \p EncodingAlignment is 724 /// non-zero, only accept displacements suitable for instruction encoding 725 /// requirement, i.e. multiples of 4 for DS form. 726 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 727 SelectionDAG &DAG, 728 unsigned EncodingAlignment) const; 729 730 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 731 /// represented as an indexed [r+r] operation. 732 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 733 SelectionDAG &DAG) const; 734 735 Sched::Preference getSchedulingPreference(SDNode *N) const override; 736 737 /// LowerOperation - Provide custom lowering hooks for some operations. 738 /// 739 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 740 741 /// ReplaceNodeResults - Replace the results of node with an illegal result 742 /// type with new values built out of custom code. 743 /// 744 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 745 SelectionDAG &DAG) const override; 746 747 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 748 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 749 750 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 751 752 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 753 SmallVectorImpl<SDNode *> &Created) const override; 754 755 Register getRegisterByName(const char* RegName, LLT VT, 756 const MachineFunction &MF) const override; 757 758 void computeKnownBitsForTargetNode(const SDValue Op, 759 KnownBits &Known, 760 const APInt &DemandedElts, 761 const SelectionDAG &DAG, 762 unsigned Depth = 0) const override; 763 764 Align getPrefLoopAlignment(MachineLoop *ML) const override; 765 766 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 767 return true; 768 } 769 770 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 771 AtomicOrdering Ord) const override; 772 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 773 AtomicOrdering Ord) const override; 774 775 MachineBasicBlock * 776 EmitInstrWithCustomInserter(MachineInstr &MI, 777 MachineBasicBlock *MBB) const override; 778 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 779 MachineBasicBlock *MBB, 780 unsigned AtomicSize, 781 unsigned BinOpcode, 782 unsigned CmpOpcode = 0, 783 unsigned CmpPred = 0) const; 784 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 785 MachineBasicBlock *MBB, 786 bool is8bit, 787 unsigned Opcode, 788 unsigned CmpOpcode = 0, 789 unsigned CmpPred = 0) const; 790 791 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 792 MachineBasicBlock *MBB) const; 793 794 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 795 MachineBasicBlock *MBB) const; 796 797 ConstraintType getConstraintType(StringRef Constraint) const override; 798 799 /// Examine constraint string and operand type and determine a weight value. 800 /// The operand object must already have been set up with the operand type. 801 ConstraintWeight getSingleConstraintMatchWeight( 802 AsmOperandInfo &info, const char *constraint) const override; 803 804 std::pair<unsigned, const TargetRegisterClass *> 805 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 806 StringRef Constraint, MVT VT) const override; 807 808 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 809 /// function arguments in the caller parameter area. This is the actual 810 /// alignment, not its logarithm. 811 unsigned getByValTypeAlignment(Type *Ty, 812 const DataLayout &DL) const override; 813 814 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 815 /// vector. If it is invalid, don't add anything to Ops. 816 void LowerAsmOperandForConstraint(SDValue Op, 817 std::string &Constraint, 818 std::vector<SDValue> &Ops, 819 SelectionDAG &DAG) const override; 820 821 unsigned 822 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 823 if (ConstraintCode == "es") 824 return InlineAsm::Constraint_es; 825 else if (ConstraintCode == "o") 826 return InlineAsm::Constraint_o; 827 else if (ConstraintCode == "Q") 828 return InlineAsm::Constraint_Q; 829 else if (ConstraintCode == "Z") 830 return InlineAsm::Constraint_Z; 831 else if (ConstraintCode == "Zy") 832 return InlineAsm::Constraint_Zy; 833 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 834 } 835 836 /// isLegalAddressingMode - Return true if the addressing mode represented 837 /// by AM is legal for this target, for a load/store of the specified type. 838 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 839 Type *Ty, unsigned AS, 840 Instruction *I = nullptr) const override; 841 842 /// isLegalICmpImmediate - Return true if the specified immediate is legal 843 /// icmp immediate, that is the target has icmp instructions which can 844 /// compare a register against the immediate without having to materialize 845 /// the immediate into a register. 846 bool isLegalICmpImmediate(int64_t Imm) const override; 847 848 /// isLegalAddImmediate - Return true if the specified immediate is legal 849 /// add immediate, that is the target has add instructions which can 850 /// add a register and the immediate without having to materialize 851 /// the immediate into a register. 852 bool isLegalAddImmediate(int64_t Imm) const override; 853 854 /// isTruncateFree - Return true if it's free to truncate a value of 855 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 856 /// register X1 to i32 by referencing its sub-register R1. 857 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 858 bool isTruncateFree(EVT VT1, EVT VT2) const override; 859 860 bool isZExtFree(SDValue Val, EVT VT2) const override; 861 862 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 863 864 /// Returns true if it is beneficial to convert a load of a constant 865 /// to just the constant itself. 866 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 867 Type *Ty) const override; 868 869 bool convertSelectOfConstantsToMath(EVT VT) const override { 870 return true; 871 } 872 873 bool isDesirableToTransformToIntegerOp(unsigned Opc, 874 EVT VT) const override { 875 // Only handle float load/store pair because float(fpr) load/store 876 // instruction has more cycles than integer(gpr) load/store in PPC. 877 if (Opc != ISD::LOAD && Opc != ISD::STORE) 878 return false; 879 if (VT != MVT::f32 && VT != MVT::f64) 880 return false; 881 882 return true; 883 } 884 885 // Returns true if the address of the global is stored in TOC entry. 886 bool isAccessedAsGotIndirect(SDValue N) const; 887 888 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 889 890 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 891 const CallInst &I, 892 MachineFunction &MF, 893 unsigned Intrinsic) const override; 894 895 /// getOptimalMemOpType - Returns the target specific optimal type for load 896 /// and store operations as a result of memset, memcpy, and memmove 897 /// lowering. If DstAlign is zero that means it's safe to destination 898 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 899 /// means there isn't a need to check it against alignment requirement, 900 /// probably because the source does not need to be loaded. If 'IsMemset' is 901 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 902 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 903 /// source is constant so it does not need to be loaded. 904 /// It returns EVT::Other if the type should be determined using generic 905 /// target-independent logic. 906 EVT 907 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 908 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 909 const AttributeList &FuncAttributes) const override; 910 911 /// Is unaligned memory access allowed for the given type, and is it fast 912 /// relative to software emulation. 913 bool allowsMisalignedMemoryAccesses( 914 EVT VT, unsigned AddrSpace, unsigned Align = 1, 915 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 916 bool *Fast = nullptr) const override; 917 918 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 919 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 920 /// expanded to FMAs when this method returns true, otherwise fmuladd is 921 /// expanded to fmul + fadd. 922 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 923 EVT VT) const override; 924 925 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 926 927 // Should we expand the build vector with shuffles? 928 bool 929 shouldExpandBuildVectorWithShuffles(EVT VT, 930 unsigned DefinedValues) const override; 931 932 /// createFastISel - This method returns a target-specific FastISel object, 933 /// or null if the target does not support "fast" instruction selection. 934 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 935 const TargetLibraryInfo *LibInfo) const override; 936 937 /// Returns true if an argument of type Ty needs to be passed in a 938 /// contiguous block of registers in calling convention CallConv. 939 bool functionArgumentNeedsConsecutiveRegisters( 940 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 941 // We support any array type as "consecutive" block in the parameter 942 // save area. The element type defines the alignment requirement and 943 // whether the argument should go in GPRs, FPRs, or VRs if available. 944 // 945 // Note that clang uses this capability both to implement the ELFv2 946 // homogeneous float/vector aggregate ABI, and to avoid having to use 947 // "byval" when passing aggregates that might fully fit in registers. 948 return Ty->isArrayTy(); 949 } 950 951 /// If a physical register, this returns the register that receives the 952 /// exception address on entry to an EH pad. 953 unsigned 954 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 955 956 /// If a physical register, this returns the register that receives the 957 /// exception typeid on entry to a landing pad. 958 unsigned 959 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 960 961 /// Override to support customized stack guard loading. 962 bool useLoadStackGuardNode() const override; 963 void insertSSPDeclarations(Module &M) const override; 964 965 bool isFPImmLegal(const APFloat &Imm, EVT VT, 966 bool ForCodeSize) const override; 967 968 unsigned getJumpTableEncoding() const override; 969 bool isJumpTableRelative() const override; 970 SDValue getPICJumpTableRelocBase(SDValue Table, 971 SelectionDAG &DAG) const override; 972 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 973 unsigned JTI, 974 MCContext &Ctx) const override; 975 976 private: 977 struct ReuseLoadInfo { 978 SDValue Ptr; 979 SDValue Chain; 980 SDValue ResChain; 981 MachinePointerInfo MPI; 982 bool IsDereferenceable = false; 983 bool IsInvariant = false; 984 unsigned Alignment = 0; 985 AAMDNodes AAInfo; 986 const MDNode *Ranges = nullptr; 987 988 ReuseLoadInfo() = default; 989 990 MachineMemOperand::Flags MMOFlags() const { 991 MachineMemOperand::Flags F = MachineMemOperand::MONone; 992 if (IsDereferenceable) 993 F |= MachineMemOperand::MODereferenceable; 994 if (IsInvariant) 995 F |= MachineMemOperand::MOInvariant; 996 return F; 997 } 998 }; 999 1000 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 1001 // Addrspacecasts are always noops. 1002 return true; 1003 } 1004 1005 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1006 SelectionDAG &DAG, 1007 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1008 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1009 SelectionDAG &DAG) const; 1010 1011 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1012 SelectionDAG &DAG, const SDLoc &dl) const; 1013 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1014 const SDLoc &dl) const; 1015 1016 bool directMoveIsProfitable(const SDValue &Op) const; 1017 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1018 const SDLoc &dl) const; 1019 1020 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1021 const SDLoc &dl) const; 1022 1023 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1024 1025 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1026 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1027 1028 bool 1029 IsEligibleForTailCallOptimization(SDValue Callee, 1030 CallingConv::ID CalleeCC, 1031 bool isVarArg, 1032 const SmallVectorImpl<ISD::InputArg> &Ins, 1033 SelectionDAG& DAG) const; 1034 1035 bool 1036 IsEligibleForTailCallOptimization_64SVR4( 1037 SDValue Callee, 1038 CallingConv::ID CalleeCC, 1039 ImmutableCallSite CS, 1040 bool isVarArg, 1041 const SmallVectorImpl<ISD::OutputArg> &Outs, 1042 const SmallVectorImpl<ISD::InputArg> &Ins, 1043 SelectionDAG& DAG) const; 1044 1045 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1046 SDValue Chain, SDValue &LROpOut, 1047 SDValue &FPOpOut, 1048 const SDLoc &dl) const; 1049 1050 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1051 1052 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1053 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1054 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1055 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1056 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1057 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1058 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1059 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1060 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1061 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1062 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1063 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1064 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1065 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1066 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1067 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1068 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1069 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1070 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1071 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1072 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1073 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1074 const SDLoc &dl) const; 1075 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1076 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1077 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1078 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1079 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1080 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1081 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1082 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1083 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1084 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1085 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1086 SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const; 1087 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1088 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1089 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1090 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 1091 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1092 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1093 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1094 1095 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1096 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1097 1098 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1099 CallingConv::ID CallConv, bool isVarArg, 1100 const SmallVectorImpl<ISD::InputArg> &Ins, 1101 const SDLoc &dl, SelectionDAG &DAG, 1102 SmallVectorImpl<SDValue> &InVals) const; 1103 SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl, 1104 bool isTailCall, bool isVarArg, bool isPatchPoint, 1105 bool hasNest, SelectionDAG &DAG, 1106 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1107 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1108 SDValue &Callee, int SPDiff, unsigned NumBytes, 1109 const SmallVectorImpl<ISD::InputArg> &Ins, 1110 SmallVectorImpl<SDValue> &InVals, 1111 ImmutableCallSite CS) const; 1112 1113 SDValue 1114 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1115 const SmallVectorImpl<ISD::InputArg> &Ins, 1116 const SDLoc &dl, SelectionDAG &DAG, 1117 SmallVectorImpl<SDValue> &InVals) const override; 1118 1119 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1120 SmallVectorImpl<SDValue> &InVals) const override; 1121 1122 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1123 bool isVarArg, 1124 const SmallVectorImpl<ISD::OutputArg> &Outs, 1125 LLVMContext &Context) const override; 1126 1127 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1128 const SmallVectorImpl<ISD::OutputArg> &Outs, 1129 const SmallVectorImpl<SDValue> &OutVals, 1130 const SDLoc &dl, SelectionDAG &DAG) const override; 1131 1132 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1133 SelectionDAG &DAG, SDValue ArgVal, 1134 const SDLoc &dl) const; 1135 1136 SDValue LowerFormalArguments_AIX( 1137 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1138 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1139 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1140 SDValue LowerFormalArguments_Darwin( 1141 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1142 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1143 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1144 SDValue LowerFormalArguments_64SVR4( 1145 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1146 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1147 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1148 SDValue LowerFormalArguments_32SVR4( 1149 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1150 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1151 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1152 1153 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1154 SDValue CallSeqStart, 1155 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1156 const SDLoc &dl) const; 1157 1158 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, 1159 CallingConv::ID CallConv, bool isVarArg, 1160 bool isTailCall, bool isPatchPoint, 1161 const SmallVectorImpl<ISD::OutputArg> &Outs, 1162 const SmallVectorImpl<SDValue> &OutVals, 1163 const SmallVectorImpl<ISD::InputArg> &Ins, 1164 const SDLoc &dl, SelectionDAG &DAG, 1165 SmallVectorImpl<SDValue> &InVals, 1166 ImmutableCallSite CS) const; 1167 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, 1168 CallingConv::ID CallConv, bool isVarArg, 1169 bool isTailCall, bool isPatchPoint, 1170 const SmallVectorImpl<ISD::OutputArg> &Outs, 1171 const SmallVectorImpl<SDValue> &OutVals, 1172 const SmallVectorImpl<ISD::InputArg> &Ins, 1173 const SDLoc &dl, SelectionDAG &DAG, 1174 SmallVectorImpl<SDValue> &InVals, 1175 ImmutableCallSite CS) const; 1176 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, 1177 CallingConv::ID CallConv, bool isVarArg, 1178 bool isTailCall, bool isPatchPoint, 1179 const SmallVectorImpl<ISD::OutputArg> &Outs, 1180 const SmallVectorImpl<SDValue> &OutVals, 1181 const SmallVectorImpl<ISD::InputArg> &Ins, 1182 const SDLoc &dl, SelectionDAG &DAG, 1183 SmallVectorImpl<SDValue> &InVals, 1184 ImmutableCallSite CS) const; 1185 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, 1186 CallingConv::ID CallConv, bool isVarArg, 1187 bool isTailCall, bool isPatchPoint, 1188 const SmallVectorImpl<ISD::OutputArg> &Outs, 1189 const SmallVectorImpl<SDValue> &OutVals, 1190 const SmallVectorImpl<ISD::InputArg> &Ins, 1191 const SDLoc &dl, SelectionDAG &DAG, 1192 SmallVectorImpl<SDValue> &InVals, 1193 ImmutableCallSite CS) const; 1194 1195 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1196 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1197 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1198 1199 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1200 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1201 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1202 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1203 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1204 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1205 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1206 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1207 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1208 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1209 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1210 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1211 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const; 1212 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const; 1213 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1214 DAGCombinerInfo &DCI) const; 1215 1216 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1217 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1218 /// (2) keeping the result of comparison in GPR has performance benefit. 1219 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1220 1221 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1222 int &RefinementSteps, bool &UseOneConstNR, 1223 bool Reciprocal) const override; 1224 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1225 int &RefinementSteps) const override; 1226 unsigned combineRepeatedFPDivisors() const override; 1227 1228 SDValue 1229 combineElementTruncationToVectorTruncation(SDNode *N, 1230 DAGCombinerInfo &DCI) const; 1231 1232 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1233 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1234 /// essentially any shuffle of v8i16 vectors that just inserts one element 1235 /// from one vector into the other. 1236 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1237 1238 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1239 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1240 /// essentially v16i8 vector version of VINSERTH. 1241 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1242 1243 // Return whether the call instruction can potentially be optimized to a 1244 // tail call. This will cause the optimizers to attempt to move, or 1245 // duplicate return instructions to help enable tail call optimizations. 1246 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1247 bool hasBitPreservingFPLogic(EVT VT) const override; 1248 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1249 }; // end class PPCTargetLowering 1250 1251 namespace PPC { 1252 1253 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1254 const TargetLibraryInfo *LibInfo); 1255 1256 } // end namespace PPC 1257 1258 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1259 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1260 1261 } // end namespace llvm 1262 1263 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1264