1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/MachineValueType.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/CodeGen/SelectionDAGNodes.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/IR/Attributes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/IR/InlineAsm.h" 30 #include "llvm/IR/Metadata.h" 31 #include "llvm/IR/Type.h" 32 #include <optional> 33 #include <utility> 34 35 namespace llvm { 36 37 namespace PPCISD { 38 39 // When adding a NEW PPCISD node please add it to the correct position in 40 // the enum. The order of elements in this enum matters! 41 // Values that are added after this entry: 42 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 43 // are considered memory opcodes and are treated differently than entries 44 // that come before it. For example, ADD or MUL should be placed before 45 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 46 // after it. 47 enum NodeType : unsigned { 48 // Start the numbering where the builtin ops and target ops leave off. 49 FIRST_NUMBER = ISD::BUILTIN_OP_END, 50 51 /// FSEL - Traditional three-operand fsel node. 52 /// 53 FSEL, 54 55 /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions. 56 XSMAXC, 57 XSMINC, 58 59 /// FCFID - The FCFID instruction, taking an f64 operand and producing 60 /// and f64 value containing the FP representation of the integer that 61 /// was temporarily in the f64 operand. 62 FCFID, 63 64 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 65 /// unsigned integers and single-precision outputs. 66 FCFIDU, 67 FCFIDS, 68 FCFIDUS, 69 70 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 71 /// operand, producing an f64 value containing the integer representation 72 /// of that FP value. 73 FCTIDZ, 74 FCTIWZ, 75 76 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 77 /// unsigned integers with round toward zero. 78 FCTIDUZ, 79 FCTIWUZ, 80 81 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 82 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 83 VEXTS, 84 85 /// Reciprocal estimate instructions (unary FP ops). 86 FRE, 87 FRSQRTE, 88 89 /// Test instruction for software square root. 90 FTSQRT, 91 92 /// Square root instruction. 93 FSQRT, 94 95 /// VPERM - The PPC VPERM Instruction. 96 /// 97 VPERM, 98 99 /// XXSPLT - The PPC VSX splat instructions 100 /// 101 XXSPLT, 102 103 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for 104 /// converting immediate single precision numbers to double precision 105 /// vector or scalar. 106 XXSPLTI_SP_TO_DP, 107 108 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. 109 /// 110 XXSPLTI32DX, 111 112 /// VECINSERT - The PPC vector insert instruction 113 /// 114 VECINSERT, 115 116 /// VECSHL - The PPC vector shift left instruction 117 /// 118 VECSHL, 119 120 /// XXPERMDI - The PPC XXPERMDI instruction 121 /// 122 XXPERMDI, 123 XXPERM, 124 125 /// The CMPB instruction (takes two operands of i32 or i64). 126 CMPB, 127 128 /// Hi/Lo - These represent the high and low 16-bit parts of a global 129 /// address respectively. These nodes have two operands, the first of 130 /// which must be a TargetGlobalAddress, and the second of which must be a 131 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 132 /// though these are usually folded into other nodes. 133 Hi, 134 Lo, 135 136 /// The following two target-specific nodes are used for calls through 137 /// function pointers in the 64-bit SVR4 ABI. 138 139 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 140 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 141 /// compute an allocation on the stack. 142 DYNALLOC, 143 144 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 145 /// compute an offset from native SP to the address of the most recent 146 /// dynamic alloca. 147 DYNAREAOFFSET, 148 149 /// To avoid stack clash, allocation is performed by block and each block is 150 /// probed. 151 PROBED_ALLOCA, 152 153 /// The result of the mflr at function entry, used for PIC code. 154 GlobalBaseReg, 155 156 /// These nodes represent PPC shifts. 157 /// 158 /// For scalar types, only the last `n + 1` bits of the shift amounts 159 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 160 /// for exact behaviors. 161 /// 162 /// For vector types, only the last n bits are used. See vsld. 163 SRL, 164 SRA, 165 SHL, 166 167 /// FNMSUB - Negated multiply-subtract instruction. 168 FNMSUB, 169 170 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 171 /// word and shift left immediate. 172 EXTSWSLI, 173 174 /// The combination of sra[wd]i and addze used to implemented signed 175 /// integer division by a power of 2. The first operand is the dividend, 176 /// and the second is the constant shift amount (representing the 177 /// divisor). 178 SRA_ADDZE, 179 180 /// CALL - A direct function call. 181 /// CALL_NOP is a call with the special NOP which follows 64-bit 182 /// CALL_NOTOC the caller does not use the TOC. 183 /// SVR4 calls and 32-bit/64-bit AIX calls. 184 CALL, 185 CALL_NOP, 186 CALL_NOTOC, 187 188 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 189 /// MTCTR instruction. 190 MTCTR, 191 192 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 193 /// BCTRL instruction. 194 BCTRL, 195 196 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 197 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 198 /// and 64-bit AIX. 199 BCTRL_LOAD_TOC, 200 201 /// The variants that implicitly define rounding mode for calls with 202 /// strictfp semantics. 203 CALL_RM, 204 CALL_NOP_RM, 205 CALL_NOTOC_RM, 206 BCTRL_RM, 207 BCTRL_LOAD_TOC_RM, 208 209 /// Return with a glue operand, matched by 'blr' 210 RET_GLUE, 211 212 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 213 /// This copies the bits corresponding to the specified CRREG into the 214 /// resultant GPR. Bits corresponding to other CR regs are undefined. 215 MFOCRF, 216 217 /// Direct move from a VSX register to a GPR 218 MFVSR, 219 220 /// Direct move from a GPR to a VSX register (algebraic) 221 MTVSRA, 222 223 /// Direct move from a GPR to a VSX register (zero) 224 MTVSRZ, 225 226 /// Direct move of 2 consecutive GPR to a VSX register. 227 BUILD_FP128, 228 229 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 230 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 231 /// unsupported for this target. 232 /// Merge 2 GPRs to a single SPE register. 233 BUILD_SPE64, 234 235 /// Extract SPE register component, second argument is high or low. 236 EXTRACT_SPE, 237 238 /// Extract a subvector from signed integer vector and convert to FP. 239 /// It is primarily used to convert a (widened) illegal integer vector 240 /// type to a legal floating point vector type. 241 /// For example v2i32 -> widened to v4i32 -> v2f64 242 SINT_VEC_TO_FP, 243 244 /// Extract a subvector from unsigned integer vector and convert to FP. 245 /// As with SINT_VEC_TO_FP, used for converting illegal types. 246 UINT_VEC_TO_FP, 247 248 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to 249 /// place the value into the least significant element of the most 250 /// significant doubleword in the vector. This is not element zero for 251 /// anything smaller than a doubleword on either endianness. This node has 252 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in 253 /// the aforementioned location in the vector register. 254 SCALAR_TO_VECTOR_PERMUTED, 255 256 // FIXME: Remove these once the ANDI glue bug is fixed: 257 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 258 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 259 /// implement truncation of i32 or i64 to i1. 260 ANDI_rec_1_EQ_BIT, 261 ANDI_rec_1_GT_BIT, 262 263 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 264 // target (returns (Lo, Hi)). It takes a chain operand. 265 READ_TIME_BASE, 266 267 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 268 EH_SJLJ_SETJMP, 269 270 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 271 EH_SJLJ_LONGJMP, 272 273 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 274 /// instructions. For lack of better number, we use the opcode number 275 /// encoding for the OPC field to identify the compare. For example, 838 276 /// is VCMPGTSH. 277 VCMP, 278 279 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the 280 /// altivec VCMP*_rec instructions. For lack of better number, we use the 281 /// opcode number encoding for the OPC field to identify the compare. For 282 /// example, 838 is VCMPGTSH. 283 VCMP_rec, 284 285 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 286 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 287 /// condition register to branch on, OPC is the branch opcode to use (e.g. 288 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 289 /// an optional input flag argument. 290 COND_BRANCH, 291 292 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 293 /// loops. 294 BDNZ, 295 BDZ, 296 297 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 298 /// towards zero. Used only as part of the long double-to-int 299 /// conversion sequence. 300 FADDRTZ, 301 302 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 303 MFFS, 304 305 /// TC_RETURN - A tail call return. 306 /// operand #0 chain 307 /// operand #1 callee (register or absolute) 308 /// operand #2 stack adjustment 309 /// operand #3 optional in flag 310 TC_RETURN, 311 312 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 313 CR6SET, 314 CR6UNSET, 315 316 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 317 /// for non-position independent code on PPC32. 318 PPC32_GOT, 319 320 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 321 /// local dynamic TLS and position indendepent code on PPC32. 322 PPC32_PICGOT, 323 324 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 325 /// TLS model, produces an ADDIS8 instruction that adds the GOT 326 /// base to sym\@got\@tprel\@ha. 327 ADDIS_GOT_TPREL_HA, 328 329 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 330 /// TLS model, produces a LD instruction with base register G8RReg 331 /// and offset sym\@got\@tprel\@l. This completes the addition that 332 /// finds the offset of "sym" relative to the thread pointer. 333 LD_GOT_TPREL_L, 334 335 /// G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec 336 /// and local-exec TLS models, produces an ADD instruction that adds 337 /// the contents of G8RReg to the thread pointer. Symbol contains a 338 /// relocation sym\@tls which is to be replaced by the thread pointer 339 /// and identifies to the linker that the instruction is part of a 340 /// TLS sequence. 341 ADD_TLS, 342 343 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 344 /// model, produces an ADDIS8 instruction that adds the GOT base 345 /// register to sym\@got\@tlsgd\@ha. 346 ADDIS_TLSGD_HA, 347 348 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 349 /// model, produces an ADDI8 instruction that adds G8RReg to 350 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 351 /// ADDIS_TLSGD_L_ADDR until after register assignment. 352 ADDI_TLSGD_L, 353 354 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 355 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 356 /// ADDIS_TLSGD_L_ADDR until after register assignment. 357 GET_TLS_ADDR, 358 359 /// %x3 = GET_TPOINTER - Used for the local-exec TLS model on 32-bit AIX, 360 /// produces a call to .__get_tpointer to retrieve the thread pointer 361 /// At the end of the call, the thread pointer is found in R3. 362 GET_TPOINTER, 363 364 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 365 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 366 /// register assignment. 367 ADDI_TLSGD_L_ADDR, 368 369 /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY 370 /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY 371 /// Op that combines two register copies of TOC entries 372 /// (region handle into R3 and variable offset into R4) followed by a 373 /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr. 374 /// This node is used in 64-bit mode as well (in which case the result is 375 /// G8RC and inputs are X3/X4). 376 TLSGD_AIX, 377 378 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 379 /// model, produces an ADDIS8 instruction that adds the GOT base 380 /// register to sym\@got\@tlsld\@ha. 381 ADDIS_TLSLD_HA, 382 383 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 384 /// model, produces an ADDI8 instruction that adds G8RReg to 385 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 386 /// ADDIS_TLSLD_L_ADDR until after register assignment. 387 ADDI_TLSLD_L, 388 389 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 390 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 391 /// ADDIS_TLSLD_L_ADDR until after register assignment. 392 GET_TLSLD_ADDR, 393 394 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 395 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 396 /// following register assignment. 397 ADDI_TLSLD_L_ADDR, 398 399 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 400 /// model, produces an ADDIS8 instruction that adds X3 to 401 /// sym\@dtprel\@ha. 402 ADDIS_DTPREL_HA, 403 404 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 405 /// model, produces an ADDI8 instruction that adds G8RReg to 406 /// sym\@got\@dtprel\@l. 407 ADDI_DTPREL_L, 408 409 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS 410 /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. 411 PADDI_DTPREL, 412 413 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 414 /// during instruction selection to optimize a BUILD_VECTOR into 415 /// operations on splats. This is necessary to avoid losing these 416 /// optimizations due to constant folding. 417 VADD_SPLAT, 418 419 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 420 /// operand identifies the operating system entry point. 421 SC, 422 423 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 424 CLRBHRB, 425 426 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 427 /// history rolling buffer entry. 428 MFBHRBE, 429 430 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 431 RFEBB, 432 433 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 434 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 435 /// or stxvd2x instruction. The chain is necessary because the 436 /// sequence replaces a load and needs to provide the same number 437 /// of outputs. 438 XXSWAPD, 439 440 /// An SDNode for swaps that are not associated with any loads/stores 441 /// and thereby have no chain. 442 SWAP_NO_CHAIN, 443 444 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 445 /// lower (IDX=1) half of v4f32 to v2f64. 446 FP_EXTEND_HALF, 447 448 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done 449 /// either through an add like PADDI or through a PC Relative load like 450 /// PLD. 451 MAT_PCREL_ADDR, 452 453 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for 454 /// TLS global address when using dynamic access models. This can be done 455 /// through an add like PADDI. 456 TLS_DYNAMIC_MAT_PCREL_ADDR, 457 458 /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address 459 /// when using local exec access models, and when prefixed instructions are 460 /// available. This is used with ADD_TLS to produce an add like PADDI. 461 TLS_LOCAL_EXEC_MAT_ADDR, 462 463 /// ACC_BUILD = Build an accumulator register from 4 VSX registers. 464 ACC_BUILD, 465 466 /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. 467 PAIR_BUILD, 468 469 /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of 470 /// an accumulator or pair register. This node is needed because 471 /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same 472 /// element type. 473 EXTRACT_VSX_REG, 474 475 /// XXMFACC = This corresponds to the xxmfacc instruction. 476 XXMFACC, 477 478 // Constrained conversion from floating point to int 479 STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, 480 STRICT_FCTIWZ, 481 STRICT_FCTIDUZ, 482 STRICT_FCTIWUZ, 483 484 /// Constrained integer-to-floating-point conversion instructions. 485 STRICT_FCFID, 486 STRICT_FCFIDU, 487 STRICT_FCFIDS, 488 STRICT_FCFIDUS, 489 490 /// Constrained floating point add in round-to-zero mode. 491 STRICT_FADDRTZ, 492 493 // NOTE: The nodes below may require PC-Rel specific patterns if the 494 // address could be PC-Relative. When adding new nodes below, consider 495 // whether or not the address can be PC-Relative and add the corresponding 496 // PC-relative patterns and tests. 497 498 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 499 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 500 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 501 /// i32. 502 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 503 504 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 505 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 506 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 507 /// or i32. 508 LBRX, 509 510 /// STFIWX - The STFIWX instruction. The first operand is an input token 511 /// chain, then an f64 value to store, then an address to store it to. 512 STFIWX, 513 514 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 515 /// load which sign-extends from a 32-bit integer value into the 516 /// destination 64-bit register. 517 LFIWAX, 518 519 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 520 /// load which zero-extends from a 32-bit integer value into the 521 /// destination 64-bit register. 522 LFIWZX, 523 524 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 525 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 526 /// This can be used for converting loaded integers to floating point. 527 LXSIZX, 528 529 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 530 /// chain, then an f64 value to store, then an address to store it to, 531 /// followed by a byte-width for the store. 532 STXSIX, 533 534 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 535 /// Maps directly to an lxvd2x instruction that will be followed by 536 /// an xxswapd. 537 LXVD2X, 538 539 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend 540 /// This node represents v1i128 BUILD_VECTOR of a zero extending load 541 /// instruction from <byte, halfword, word, or doubleword> to i128. 542 /// Allows utilization of the Load VSX Vector Rightmost Instructions. 543 LXVRZX, 544 545 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 546 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 547 /// the vector type to load vector in big-endian element order. 548 LOAD_VEC_BE, 549 550 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 551 /// v2f32 value into the lower half of a VSR register. 552 LD_VSX_LH, 553 554 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 555 /// instructions such as LXVDSX, LXVWSX. 556 LD_SPLAT, 557 558 /// VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory 559 /// that zero-extends. 560 ZEXT_LD_SPLAT, 561 562 /// VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory 563 /// that sign-extends. 564 SEXT_LD_SPLAT, 565 566 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 567 /// Maps directly to an stxvd2x instruction that will be preceded by 568 /// an xxswapd. 569 STXVD2X, 570 571 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 572 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 573 /// the vector type to store vector in big-endian element order. 574 STORE_VEC_BE, 575 576 /// Store scalar integers from VSR. 577 ST_VSR_SCAL_INT, 578 579 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 580 /// except they ensure that the compare input is zero-extended for 581 /// sub-word versions because the atomic loads zero-extend. 582 ATOMIC_CMP_SWAP_8, 583 ATOMIC_CMP_SWAP_16, 584 585 /// CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr 586 /// The store conditional instruction ST[BHWD]ARX that produces a glue 587 /// result to attach it to a conditional branch. 588 STORE_COND, 589 590 /// GPRC = TOC_ENTRY GA, TOC 591 /// Loads the entry for GA from the TOC, where the TOC base is given by 592 /// the last operand. 593 TOC_ENTRY 594 }; 595 596 } // end namespace PPCISD 597 598 /// Define some predicates that are used for node matching. 599 namespace PPC { 600 601 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 602 /// VPKUHUM instruction. 603 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 604 SelectionDAG &DAG); 605 606 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 607 /// VPKUWUM instruction. 608 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 609 SelectionDAG &DAG); 610 611 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 612 /// VPKUDUM instruction. 613 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 614 SelectionDAG &DAG); 615 616 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 617 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 618 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 619 unsigned ShuffleKind, SelectionDAG &DAG); 620 621 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 622 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 623 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 624 unsigned ShuffleKind, SelectionDAG &DAG); 625 626 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 627 /// a VMRGEW or VMRGOW instruction 628 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 629 unsigned ShuffleKind, SelectionDAG &DAG); 630 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 631 /// for a XXSLDWI instruction. 632 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 633 bool &Swap, bool IsLE); 634 635 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 636 /// for a XXBRH instruction. 637 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 638 639 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 640 /// for a XXBRW instruction. 641 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 642 643 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 644 /// for a XXBRD instruction. 645 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 646 647 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 648 /// for a XXBRQ instruction. 649 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 650 651 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 652 /// for a XXPERMDI instruction. 653 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 654 bool &Swap, bool IsLE); 655 656 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 657 /// shift amount, otherwise return -1. 658 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 659 SelectionDAG &DAG); 660 661 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 662 /// specifies a splat of a single element that is suitable for input to 663 /// VSPLTB/VSPLTH/VSPLTW. 664 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 665 666 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 667 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 668 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 669 /// vector into the other. This function will also set a couple of 670 /// output parameters for how much the source vector needs to be shifted and 671 /// what byte number needs to be specified for the instruction to put the 672 /// element in the desired location of the target vector. 673 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 674 unsigned &InsertAtByte, bool &Swap, bool IsLE); 675 676 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 677 /// appropriate for PPC mnemonics (which have a big endian bias - namely 678 /// elements are counted from the left of the vector register). 679 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 680 SelectionDAG &DAG); 681 682 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 683 /// formed by using a vspltis[bhw] instruction of the specified element 684 /// size, return the constant being splatted. The ByteSize field indicates 685 /// the number of bytes of each element [124] -> [bhw]. 686 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 687 688 // Flags for computing the optimal addressing mode for loads and stores. 689 enum MemOpFlags { 690 MOF_None = 0, 691 692 // Extension mode for integer loads. 693 MOF_SExt = 1, 694 MOF_ZExt = 1 << 1, 695 MOF_NoExt = 1 << 2, 696 697 // Address computation flags. 698 MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar. 699 MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant. 700 MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation 701 MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4. 702 MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16. 703 MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant. 704 MOF_RPlusR = 1 << 11, // Sum of two variables. 705 MOF_PCRel = 1 << 12, // PC-Relative relocation. 706 MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant. 707 708 // The in-memory type. 709 MOF_SubWordInt = 1 << 15, 710 MOF_WordInt = 1 << 16, 711 MOF_DoubleWordInt = 1 << 17, 712 MOF_ScalarFloat = 1 << 18, // Scalar single or double precision. 713 MOF_Vector = 1 << 19, // Vector types and quad precision scalars. 714 MOF_Vector256 = 1 << 20, 715 716 // Subtarget features. 717 MOF_SubtargetBeforeP9 = 1 << 22, 718 MOF_SubtargetP9 = 1 << 23, 719 MOF_SubtargetP10 = 1 << 24, 720 MOF_SubtargetSPE = 1 << 25 721 }; 722 723 // The addressing modes for loads and stores. 724 enum AddrMode { 725 AM_None, 726 AM_DForm, 727 AM_DSForm, 728 AM_DQForm, 729 AM_PrefixDForm, 730 AM_XForm, 731 AM_PCRel 732 }; 733 } // end namespace PPC 734 735 class PPCTargetLowering : public TargetLowering { 736 const PPCSubtarget &Subtarget; 737 738 public: 739 explicit PPCTargetLowering(const PPCTargetMachine &TM, 740 const PPCSubtarget &STI); 741 742 /// getTargetNodeName() - This method returns the name of a target specific 743 /// DAG node. 744 const char *getTargetNodeName(unsigned Opcode) const override; 745 746 bool isSelectSupported(SelectSupportKind Kind) const override { 747 // PowerPC does not support scalar condition selects on vectors. 748 return (Kind != SelectSupportKind::ScalarCondVectorVal); 749 } 750 751 /// getPreferredVectorAction - The code we generate when vector types are 752 /// legalized by promoting the integer element type is often much worse 753 /// than code we generate if we widen the type for applicable vector types. 754 /// The issue with promoting is that the vector is scalaraized, individual 755 /// elements promoted and then the vector is rebuilt. So say we load a pair 756 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 757 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 758 /// then the VPERM for the shuffle. All in all a very slow sequence. 759 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 760 const override { 761 // Default handling for scalable and single-element vectors. 762 if (VT.isScalableVector() || VT.getVectorNumElements() == 1) 763 return TargetLoweringBase::getPreferredVectorAction(VT); 764 765 // Split and promote vNi1 vectors so we don't produce v256i1/v512i1 766 // types as those are only for MMA instructions. 767 if (VT.getScalarSizeInBits() == 1 && VT.getSizeInBits() > 16) 768 return TypeSplitVector; 769 if (VT.getScalarSizeInBits() == 1) 770 return TypePromoteInteger; 771 772 // Widen vectors that have reasonably sized elements. 773 if (VT.getScalarSizeInBits() % 8 == 0) 774 return TypeWidenVector; 775 return TargetLoweringBase::getPreferredVectorAction(VT); 776 } 777 778 bool useSoftFloat() const override; 779 780 bool hasSPE() const; 781 782 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 783 return MVT::i32; 784 } 785 786 bool isCheapToSpeculateCttz(Type *Ty) const override { 787 return true; 788 } 789 790 bool isCheapToSpeculateCtlz(Type *Ty) const override { 791 return true; 792 } 793 794 bool isCtlzFast() const override { 795 return true; 796 } 797 798 bool isEqualityCmpFoldedWithSignedCmp() const override { 799 return false; 800 } 801 802 bool hasAndNotCompare(SDValue) const override { 803 return true; 804 } 805 806 bool preferIncOfAddToSubOfNot(EVT VT) const override; 807 808 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 809 return VT.isScalarInteger(); 810 } 811 812 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, 813 bool OptForSize, NegatibleCost &Cost, 814 unsigned Depth = 0) const override; 815 816 /// getSetCCResultType - Return the ISD::SETCC ValueType 817 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 818 EVT VT) const override; 819 820 /// Return true if target always benefits from combining into FMA for a 821 /// given value type. This must typically return false on targets where FMA 822 /// takes more cycles to execute than FADD. 823 bool enableAggressiveFMAFusion(EVT VT) const override; 824 825 /// getPreIndexedAddressParts - returns true by value, base pointer and 826 /// offset pointer and addressing mode by reference if the node's address 827 /// can be legally represented as pre-indexed load / store address. 828 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 829 SDValue &Offset, 830 ISD::MemIndexedMode &AM, 831 SelectionDAG &DAG) const override; 832 833 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 834 /// it can be more efficiently represented as [r+imm]. 835 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 836 SelectionDAG &DAG) const; 837 838 /// SelectAddressRegReg - Given the specified addressed, check to see if it 839 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 840 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 841 /// Returns false if it can be represented by [r+imm], which are preferred. 842 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 843 SelectionDAG &DAG, 844 MaybeAlign EncodingAlignment = std::nullopt) const; 845 846 /// SelectAddressRegImm - Returns true if the address N can be represented 847 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 848 /// is not better represented as reg+reg. If \p EncodingAlignment is 849 /// non-zero, only accept displacements suitable for instruction encoding 850 /// requirement, i.e. multiples of 4 for DS form. 851 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 852 SelectionDAG &DAG, 853 MaybeAlign EncodingAlignment) const; 854 bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, 855 SelectionDAG &DAG) const; 856 857 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 858 /// represented as an indexed [r+r] operation. 859 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 860 SelectionDAG &DAG) const; 861 862 /// SelectAddressPCRel - Represent the specified address as pc relative to 863 /// be represented as [pc+imm] 864 bool SelectAddressPCRel(SDValue N, SDValue &Base) const; 865 866 Sched::Preference getSchedulingPreference(SDNode *N) const override; 867 868 /// LowerOperation - Provide custom lowering hooks for some operations. 869 /// 870 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 871 872 /// ReplaceNodeResults - Replace the results of node with an illegal result 873 /// type with new values built out of custom code. 874 /// 875 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 876 SelectionDAG &DAG) const override; 877 878 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 879 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 880 881 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 882 883 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 884 SmallVectorImpl<SDNode *> &Created) const override; 885 886 Register getRegisterByName(const char* RegName, LLT VT, 887 const MachineFunction &MF) const override; 888 889 void computeKnownBitsForTargetNode(const SDValue Op, 890 KnownBits &Known, 891 const APInt &DemandedElts, 892 const SelectionDAG &DAG, 893 unsigned Depth = 0) const override; 894 895 Align getPrefLoopAlignment(MachineLoop *ML) const override; 896 897 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 898 return true; 899 } 900 901 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 902 AtomicOrdering Ord) const override; 903 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 904 AtomicOrdering Ord) const override; 905 906 bool shouldInlineQuadwordAtomics() const; 907 908 TargetLowering::AtomicExpansionKind 909 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 910 911 TargetLowering::AtomicExpansionKind 912 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 913 914 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, 915 AtomicRMWInst *AI, Value *AlignedAddr, 916 Value *Incr, Value *Mask, 917 Value *ShiftAmt, 918 AtomicOrdering Ord) const override; 919 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 920 AtomicCmpXchgInst *CI, 921 Value *AlignedAddr, Value *CmpVal, 922 Value *NewVal, Value *Mask, 923 AtomicOrdering Ord) const override; 924 925 MachineBasicBlock * 926 EmitInstrWithCustomInserter(MachineInstr &MI, 927 MachineBasicBlock *MBB) const override; 928 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 929 MachineBasicBlock *MBB, 930 unsigned AtomicSize, 931 unsigned BinOpcode, 932 unsigned CmpOpcode = 0, 933 unsigned CmpPred = 0) const; 934 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 935 MachineBasicBlock *MBB, 936 bool is8bit, 937 unsigned Opcode, 938 unsigned CmpOpcode = 0, 939 unsigned CmpPred = 0) const; 940 941 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 942 MachineBasicBlock *MBB) const; 943 944 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 945 MachineBasicBlock *MBB) const; 946 947 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 948 MachineBasicBlock *MBB) const; 949 950 bool hasInlineStackProbe(const MachineFunction &MF) const override; 951 952 unsigned getStackProbeSize(const MachineFunction &MF) const; 953 954 ConstraintType getConstraintType(StringRef Constraint) const override; 955 956 /// Examine constraint string and operand type and determine a weight value. 957 /// The operand object must already have been set up with the operand type. 958 ConstraintWeight getSingleConstraintMatchWeight( 959 AsmOperandInfo &info, const char *constraint) const override; 960 961 std::pair<unsigned, const TargetRegisterClass *> 962 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 963 StringRef Constraint, MVT VT) const override; 964 965 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 966 /// function arguments in the caller parameter area. This is the actual 967 /// alignment, not its logarithm. 968 uint64_t getByValTypeAlignment(Type *Ty, 969 const DataLayout &DL) const override; 970 971 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 972 /// vector. If it is invalid, don't add anything to Ops. 973 void LowerAsmOperandForConstraint(SDValue Op, 974 std::string &Constraint, 975 std::vector<SDValue> &Ops, 976 SelectionDAG &DAG) const override; 977 978 unsigned 979 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 980 if (ConstraintCode == "es") 981 return InlineAsm::Constraint_es; 982 else if (ConstraintCode == "Q") 983 return InlineAsm::Constraint_Q; 984 else if (ConstraintCode == "Z") 985 return InlineAsm::Constraint_Z; 986 else if (ConstraintCode == "Zy") 987 return InlineAsm::Constraint_Zy; 988 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 989 } 990 991 void CollectTargetIntrinsicOperands(const CallInst &I, 992 SmallVectorImpl<SDValue> &Ops, 993 SelectionDAG &DAG) const override; 994 995 /// isLegalAddressingMode - Return true if the addressing mode represented 996 /// by AM is legal for this target, for a load/store of the specified type. 997 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 998 Type *Ty, unsigned AS, 999 Instruction *I = nullptr) const override; 1000 1001 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1002 /// icmp immediate, that is the target has icmp instructions which can 1003 /// compare a register against the immediate without having to materialize 1004 /// the immediate into a register. 1005 bool isLegalICmpImmediate(int64_t Imm) const override; 1006 1007 /// isLegalAddImmediate - Return true if the specified immediate is legal 1008 /// add immediate, that is the target has add instructions which can 1009 /// add a register and the immediate without having to materialize 1010 /// the immediate into a register. 1011 bool isLegalAddImmediate(int64_t Imm) const override; 1012 1013 /// isTruncateFree - Return true if it's free to truncate a value of 1014 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 1015 /// register X1 to i32 by referencing its sub-register R1. 1016 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 1017 bool isTruncateFree(EVT VT1, EVT VT2) const override; 1018 1019 bool isZExtFree(SDValue Val, EVT VT2) const override; 1020 1021 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 1022 1023 /// Returns true if it is beneficial to convert a load of a constant 1024 /// to just the constant itself. 1025 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 1026 Type *Ty) const override; 1027 1028 bool convertSelectOfConstantsToMath(EVT VT) const override { 1029 return true; 1030 } 1031 1032 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 1033 SDValue C) const override; 1034 1035 bool isDesirableToTransformToIntegerOp(unsigned Opc, 1036 EVT VT) const override { 1037 // Only handle float load/store pair because float(fpr) load/store 1038 // instruction has more cycles than integer(gpr) load/store in PPC. 1039 if (Opc != ISD::LOAD && Opc != ISD::STORE) 1040 return false; 1041 if (VT != MVT::f32 && VT != MVT::f64) 1042 return false; 1043 1044 return true; 1045 } 1046 1047 // Returns true if the address of the global is stored in TOC entry. 1048 bool isAccessedAsGotIndirect(SDValue N) const; 1049 1050 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 1051 1052 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 1053 const CallInst &I, 1054 MachineFunction &MF, 1055 unsigned Intrinsic) const override; 1056 1057 /// It returns EVT::Other if the type should be determined using generic 1058 /// target-independent logic. 1059 EVT getOptimalMemOpType(const MemOp &Op, 1060 const AttributeList &FuncAttributes) const override; 1061 1062 /// Is unaligned memory access allowed for the given type, and is it fast 1063 /// relative to software emulation. 1064 bool allowsMisalignedMemoryAccesses( 1065 EVT VT, unsigned AddrSpace, Align Alignment = Align(1), 1066 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1067 unsigned *Fast = nullptr) const override; 1068 1069 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 1070 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 1071 /// expanded to FMAs when this method returns true, otherwise fmuladd is 1072 /// expanded to fmul + fadd. 1073 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 1074 EVT VT) const override; 1075 1076 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 1077 1078 /// isProfitableToHoist - Check if it is profitable to hoist instruction 1079 /// \p I to its dominator block. 1080 /// For example, it is not profitable if \p I and it's only user can form a 1081 /// FMA instruction, because Powerpc prefers FMADD. 1082 bool isProfitableToHoist(Instruction *I) const override; 1083 1084 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 1085 1086 // Should we expand the build vector with shuffles? 1087 bool 1088 shouldExpandBuildVectorWithShuffles(EVT VT, 1089 unsigned DefinedValues) const override; 1090 1091 // Keep the zero-extensions for arguments to libcalls. 1092 bool shouldKeepZExtForFP16Conv() const override { return true; } 1093 1094 /// createFastISel - This method returns a target-specific FastISel object, 1095 /// or null if the target does not support "fast" instruction selection. 1096 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1097 const TargetLibraryInfo *LibInfo) const override; 1098 1099 /// Returns true if an argument of type Ty needs to be passed in a 1100 /// contiguous block of registers in calling convention CallConv. 1101 bool functionArgumentNeedsConsecutiveRegisters( 1102 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 1103 const DataLayout &DL) const override { 1104 // We support any array type as "consecutive" block in the parameter 1105 // save area. The element type defines the alignment requirement and 1106 // whether the argument should go in GPRs, FPRs, or VRs if available. 1107 // 1108 // Note that clang uses this capability both to implement the ELFv2 1109 // homogeneous float/vector aggregate ABI, and to avoid having to use 1110 // "byval" when passing aggregates that might fully fit in registers. 1111 return Ty->isArrayTy(); 1112 } 1113 1114 /// If a physical register, this returns the register that receives the 1115 /// exception address on entry to an EH pad. 1116 Register 1117 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 1118 1119 /// If a physical register, this returns the register that receives the 1120 /// exception typeid on entry to a landing pad. 1121 Register 1122 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 1123 1124 /// Override to support customized stack guard loading. 1125 bool useLoadStackGuardNode() const override; 1126 void insertSSPDeclarations(Module &M) const override; 1127 Value *getSDagStackGuard(const Module &M) const override; 1128 1129 bool isFPImmLegal(const APFloat &Imm, EVT VT, 1130 bool ForCodeSize) const override; 1131 1132 unsigned getJumpTableEncoding() const override; 1133 bool isJumpTableRelative() const override; 1134 SDValue getPICJumpTableRelocBase(SDValue Table, 1135 SelectionDAG &DAG) const override; 1136 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1137 unsigned JTI, 1138 MCContext &Ctx) const override; 1139 1140 /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), 1141 /// compute the address flags of the node, get the optimal address mode 1142 /// based on the flags, and set the Base and Disp based on the address mode. 1143 PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, 1144 SDValue &Disp, SDValue &Base, 1145 SelectionDAG &DAG, 1146 MaybeAlign Align) const; 1147 /// SelectForceXFormMode - Given the specified address, force it to be 1148 /// represented as an indexed [r+r] operation (an XForm instruction). 1149 PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, 1150 SelectionDAG &DAG) const; 1151 1152 bool splitValueIntoRegisterParts( 1153 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, 1154 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) 1155 const override; 1156 /// Structure that collects some common arguments that get passed around 1157 /// between the functions for call lowering. 1158 struct CallFlags { 1159 const CallingConv::ID CallConv; 1160 const bool IsTailCall : 1; 1161 const bool IsVarArg : 1; 1162 const bool IsPatchPoint : 1; 1163 const bool IsIndirect : 1; 1164 const bool HasNest : 1; 1165 const bool NoMerge : 1; 1166 1167 CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, 1168 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge) 1169 : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg), 1170 IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect), 1171 HasNest(HasNest), NoMerge(NoMerge) {} 1172 }; 1173 1174 CCAssignFn *ccAssignFnForCall(CallingConv::ID CC, bool Return, 1175 bool IsVarArg) const; 1176 bool supportsTailCallFor(const CallBase *CB) const; 1177 1178 private: 1179 struct ReuseLoadInfo { 1180 SDValue Ptr; 1181 SDValue Chain; 1182 SDValue ResChain; 1183 MachinePointerInfo MPI; 1184 bool IsDereferenceable = false; 1185 bool IsInvariant = false; 1186 Align Alignment; 1187 AAMDNodes AAInfo; 1188 const MDNode *Ranges = nullptr; 1189 1190 ReuseLoadInfo() = default; 1191 1192 MachineMemOperand::Flags MMOFlags() const { 1193 MachineMemOperand::Flags F = MachineMemOperand::MONone; 1194 if (IsDereferenceable) 1195 F |= MachineMemOperand::MODereferenceable; 1196 if (IsInvariant) 1197 F |= MachineMemOperand::MOInvariant; 1198 return F; 1199 } 1200 }; 1201 1202 // Map that relates a set of common address flags to PPC addressing modes. 1203 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap; 1204 void initializeAddrModeMap(); 1205 1206 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1207 SelectionDAG &DAG, 1208 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1209 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1210 SelectionDAG &DAG) const; 1211 1212 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1213 SelectionDAG &DAG, const SDLoc &dl) const; 1214 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1215 const SDLoc &dl) const; 1216 1217 bool directMoveIsProfitable(const SDValue &Op) const; 1218 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1219 const SDLoc &dl) const; 1220 1221 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1222 const SDLoc &dl) const; 1223 1224 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1225 1226 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1227 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1228 1229 bool IsEligibleForTailCallOptimization( 1230 const GlobalValue *CalleeGV, CallingConv::ID CalleeCC, 1231 CallingConv::ID CallerCC, bool isVarArg, 1232 const SmallVectorImpl<ISD::InputArg> &Ins) const; 1233 1234 bool IsEligibleForTailCallOptimization_64SVR4( 1235 const GlobalValue *CalleeGV, CallingConv::ID CalleeCC, 1236 CallingConv::ID CallerCC, const CallBase *CB, bool isVarArg, 1237 const SmallVectorImpl<ISD::OutputArg> &Outs, 1238 const SmallVectorImpl<ISD::InputArg> &Ins, const Function *CallerFunc, 1239 bool isCalleeExternalSymbol) const; 1240 1241 bool isEligibleForTCO(const GlobalValue *CalleeGV, CallingConv::ID CalleeCC, 1242 CallingConv::ID CallerCC, const CallBase *CB, 1243 bool isVarArg, 1244 const SmallVectorImpl<ISD::OutputArg> &Outs, 1245 const SmallVectorImpl<ISD::InputArg> &Ins, 1246 const Function *CallerFunc, 1247 bool isCalleeExternalSymbol) const; 1248 1249 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1250 SDValue Chain, SDValue &LROpOut, 1251 SDValue &FPOpOut, 1252 const SDLoc &dl) const; 1253 1254 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1255 1256 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1257 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1258 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1259 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1260 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1261 SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const; 1262 SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const; 1263 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1264 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1265 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1266 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1267 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1268 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 1269 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1270 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1271 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1272 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1273 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1274 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1275 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1276 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1277 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1278 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1279 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1280 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1281 const SDLoc &dl) const; 1282 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1283 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 1284 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1285 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1286 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1287 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; 1288 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1289 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1290 SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef<int> PermMask, 1291 EVT VT, SDValue V1, SDValue V2) const; 1292 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1293 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1294 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1295 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1296 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1297 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const; 1298 SDValue lowerToLibCall(const char *LibCallName, SDValue Op, 1299 SelectionDAG &DAG) const; 1300 SDValue lowerLibCallBasedOnType(const char *LibCallFloatName, 1301 const char *LibCallDoubleName, SDValue Op, 1302 SelectionDAG &DAG) const; 1303 bool isLowringToMASSFiniteSafe(SDValue Op) const; 1304 bool isLowringToMASSSafe(SDValue Op) const; 1305 bool isScalarMASSConversionEnabled() const; 1306 SDValue lowerLibCallBase(const char *LibCallDoubleName, 1307 const char *LibCallFloatName, 1308 const char *LibCallDoubleNameFinite, 1309 const char *LibCallFloatNameFinite, SDValue Op, 1310 SelectionDAG &DAG) const; 1311 SDValue lowerPow(SDValue Op, SelectionDAG &DAG) const; 1312 SDValue lowerSin(SDValue Op, SelectionDAG &DAG) const; 1313 SDValue lowerCos(SDValue Op, SelectionDAG &DAG) const; 1314 SDValue lowerLog(SDValue Op, SelectionDAG &DAG) const; 1315 SDValue lowerLog10(SDValue Op, SelectionDAG &DAG) const; 1316 SDValue lowerExp(SDValue Op, SelectionDAG &DAG) const; 1317 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const; 1318 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1319 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1320 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1321 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 1322 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 1323 1324 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1325 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1326 1327 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 1328 CallingConv::ID CallConv, bool isVarArg, 1329 const SmallVectorImpl<ISD::InputArg> &Ins, 1330 const SDLoc &dl, SelectionDAG &DAG, 1331 SmallVectorImpl<SDValue> &InVals) const; 1332 1333 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, 1334 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1335 SDValue InGlue, SDValue Chain, SDValue CallSeqStart, 1336 SDValue &Callee, int SPDiff, unsigned NumBytes, 1337 const SmallVectorImpl<ISD::InputArg> &Ins, 1338 SmallVectorImpl<SDValue> &InVals, 1339 const CallBase *CB) const; 1340 1341 SDValue 1342 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1343 const SmallVectorImpl<ISD::InputArg> &Ins, 1344 const SDLoc &dl, SelectionDAG &DAG, 1345 SmallVectorImpl<SDValue> &InVals) const override; 1346 1347 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1348 SmallVectorImpl<SDValue> &InVals) const override; 1349 1350 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1351 bool isVarArg, 1352 const SmallVectorImpl<ISD::OutputArg> &Outs, 1353 LLVMContext &Context) const override; 1354 1355 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1356 const SmallVectorImpl<ISD::OutputArg> &Outs, 1357 const SmallVectorImpl<SDValue> &OutVals, 1358 const SDLoc &dl, SelectionDAG &DAG) const override; 1359 1360 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1361 SelectionDAG &DAG, SDValue ArgVal, 1362 const SDLoc &dl) const; 1363 1364 SDValue LowerFormalArguments_AIX( 1365 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1366 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1367 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1368 SDValue LowerFormalArguments_64SVR4( 1369 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1370 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1371 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1372 SDValue LowerFormalArguments_32SVR4( 1373 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1374 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1375 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1376 1377 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1378 SDValue CallSeqStart, 1379 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1380 const SDLoc &dl) const; 1381 1382 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1383 const SmallVectorImpl<ISD::OutputArg> &Outs, 1384 const SmallVectorImpl<SDValue> &OutVals, 1385 const SmallVectorImpl<ISD::InputArg> &Ins, 1386 const SDLoc &dl, SelectionDAG &DAG, 1387 SmallVectorImpl<SDValue> &InVals, 1388 const CallBase *CB) const; 1389 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1390 const SmallVectorImpl<ISD::OutputArg> &Outs, 1391 const SmallVectorImpl<SDValue> &OutVals, 1392 const SmallVectorImpl<ISD::InputArg> &Ins, 1393 const SDLoc &dl, SelectionDAG &DAG, 1394 SmallVectorImpl<SDValue> &InVals, 1395 const CallBase *CB) const; 1396 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, 1397 const SmallVectorImpl<ISD::OutputArg> &Outs, 1398 const SmallVectorImpl<SDValue> &OutVals, 1399 const SmallVectorImpl<ISD::InputArg> &Ins, 1400 const SDLoc &dl, SelectionDAG &DAG, 1401 SmallVectorImpl<SDValue> &InVals, 1402 const CallBase *CB) const; 1403 1404 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1405 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1406 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1407 1408 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1409 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1410 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1411 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1412 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1413 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1414 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1415 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1416 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1417 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1418 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const; 1419 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1420 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1421 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN, 1422 SelectionDAG &DAG) const; 1423 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1424 DAGCombinerInfo &DCI) const; 1425 1426 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1427 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1428 /// (2) keeping the result of comparison in GPR has performance benefit. 1429 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1430 1431 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1432 int &RefinementSteps, bool &UseOneConstNR, 1433 bool Reciprocal) const override; 1434 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1435 int &RefinementSteps) const override; 1436 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1437 const DenormalMode &Mode) const override; 1438 SDValue getSqrtResultForDenormInput(SDValue Operand, 1439 SelectionDAG &DAG) const override; 1440 unsigned combineRepeatedFPDivisors() const override; 1441 1442 SDValue 1443 combineElementTruncationToVectorTruncation(SDNode *N, 1444 DAGCombinerInfo &DCI) const; 1445 1446 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1447 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1448 /// essentially any shuffle of v8i16 vectors that just inserts one element 1449 /// from one vector into the other. 1450 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1451 1452 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1453 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1454 /// essentially v16i8 vector version of VINSERTH. 1455 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1456 1457 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be 1458 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1. 1459 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1460 1461 // Return whether the call instruction can potentially be optimized to a 1462 // tail call. This will cause the optimizers to attempt to move, or 1463 // duplicate return instructions to help enable tail call optimizations. 1464 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1465 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1466 1467 /// getAddrModeForFlags - Based on the set of address flags, select the most 1468 /// optimal instruction format to match by. 1469 PPC::AddrMode getAddrModeForFlags(unsigned Flags) const; 1470 1471 /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute 1472 /// the address flags of the load/store instruction that is to be matched. 1473 /// The address flags are stored in a map, which is then searched 1474 /// through to determine the optimal load/store instruction format. 1475 unsigned computeMOFlags(const SDNode *Parent, SDValue N, 1476 SelectionDAG &DAG) const; 1477 }; // end class PPCTargetLowering 1478 1479 namespace PPC { 1480 1481 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1482 const TargetLibraryInfo *LibInfo); 1483 1484 } // end namespace PPC 1485 1486 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1487 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1488 bool isIntS34Immediate(SDNode *N, int64_t &Imm); 1489 bool isIntS34Immediate(SDValue Op, int64_t &Imm); 1490 1491 bool convertToNonDenormSingle(APInt &ArgAPInt); 1492 bool convertToNonDenormSingle(APFloat &ArgAPFloat); 1493 bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat); 1494 1495 } // end namespace llvm 1496 1497 #endif // LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 1498