1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the PowerPC 32- and 64-bit 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const PPCSubtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", 18 F), 19 A>; 20class CCIfNotSubtarget<string F, CCAction A> 21 : CCIf<!strconcat("!static_cast<const PPCSubtarget&>" 22 "(State.getMachineFunction().getSubtarget()).", 23 F), 24 A>; 25class CCIfOrigArgWasNotPPCF128<CCAction A> 26 : CCIf<"!static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)", 27 A>; 28class CCIfOrigArgWasPPCF128<CCAction A> 29 : CCIf<"static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)", 30 A>; 31 32//===----------------------------------------------------------------------===// 33// Return Value Calling Convention 34//===----------------------------------------------------------------------===// 35 36// PPC64 AnyReg return-value convention. No explicit register is specified for 37// the return-value. The register allocator is allowed and expected to choose 38// any free register. 39// 40// This calling convention is currently only supported by the stackmap and 41// patchpoint intrinsics. All other uses will result in an assert on Debug 42// builds. On Release builds we fallback to the PPC C calling convention. 43def RetCC_PPC64_AnyReg : CallingConv<[ 44 CCCustom<"CC_PPC_AnyReg_Error"> 45]>; 46 47// Return-value convention for PowerPC coldcc. 48let Entry = 1 in 49def RetCC_PPC_Cold : CallingConv<[ 50 // Use the same return registers as RetCC_PPC, but limited to only 51 // one return value. The remaining return values will be saved to 52 // the stack. 53 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 54 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>, 55 56 CCIfType<[i32], CCAssignToReg<[R3]>>, 57 CCIfType<[i64], CCAssignToReg<[X3]>>, 58 CCIfType<[i128], CCAssignToReg<[X3]>>, 59 60 CCIfType<[f32], CCAssignToReg<[F1]>>, 61 CCIfType<[f64], CCAssignToReg<[F1]>>, 62 CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2]>>>, 63 64 CCIfType<[v4f64, v4f32, v4i1], 65 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1]>>>, 66 67 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 68 CCIfSubtarget<"hasAltivec()", 69 CCAssignToReg<[V2]>>> 70]>; 71 72// Return-value convention for PowerPC 73let Entry = 1 in 74def RetCC_PPC : CallingConv<[ 75 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, 76 77 // On PPC64, integer return values are always promoted to i64 78 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 79 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>, 80 81 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 82 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 83 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 84 85 // Floating point types returned as "direct" go into F1 .. F8; note that 86 // only the ELFv2 ABI fully utilizes all these registers. 87 CCIfNotSubtarget<"hasSPE()", 88 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, 89 CCIfNotSubtarget<"hasSPE()", 90 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, 91 CCIfSubtarget<"hasSPE()", 92 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>, 93 CCIfSubtarget<"hasSPE()", 94 CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>, 95 96 // For P9, f128 are passed in vector registers. 97 CCIfType<[f128], 98 CCIfSubtarget<"hasP9Vector()", 99 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, 100 101 // QPX vectors are returned in QF1 and QF2. 102 CCIfType<[v4f64, v4f32, v4i1], 103 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>, 104 105 // Vector types returned as "direct" go into V2 .. V9; note that only the 106 // ELFv2 ABI fully utilizes all these registers. 107 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 108 CCIfSubtarget<"hasAltivec()", 109 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>> 110]>; 111 112// No explicit register is specified for the AnyReg calling convention. The 113// register allocator may assign the arguments to any free register. 114// 115// This calling convention is currently only supported by the stackmap and 116// patchpoint intrinsics. All other uses will result in an assert on Debug 117// builds. On Release builds we fallback to the PPC C calling convention. 118def CC_PPC64_AnyReg : CallingConv<[ 119 CCCustom<"CC_PPC_AnyReg_Error"> 120]>; 121 122// Note that we don't currently have calling conventions for 64-bit 123// PowerPC, but handle all the complexities of the ABI in the lowering 124// logic. FIXME: See if the logic can be simplified with use of CCs. 125// This may require some extensions to current table generation. 126 127// Simple calling convention for 64-bit ELF PowerPC fast isel. 128// Only handle ints and floats. All ints are promoted to i64. 129// Vector types and quadword ints are not handled. 130let Entry = 1 in 131def CC_PPC64_ELF_FIS : CallingConv<[ 132 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>, 133 134 CCIfType<[i1], CCPromoteToType<i64>>, 135 CCIfType<[i8], CCPromoteToType<i64>>, 136 CCIfType<[i16], CCPromoteToType<i64>>, 137 CCIfType<[i32], CCPromoteToType<i64>>, 138 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>, 139 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>> 140]>; 141 142// Simple return-value convention for 64-bit ELF PowerPC fast isel. 143// All small ints are promoted to i64. Vector types, quadword ints, 144// and multiple register returns are "supported" to avoid compile 145// errors, but none are handled by the fast selector. 146let Entry = 1 in 147def RetCC_PPC64_ELF_FIS : CallingConv<[ 148 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>, 149 150 CCIfType<[i1], CCPromoteToType<i64>>, 151 CCIfType<[i8], CCPromoteToType<i64>>, 152 CCIfType<[i16], CCPromoteToType<i64>>, 153 CCIfType<[i32], CCPromoteToType<i64>>, 154 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 155 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 156 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 157 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 158 CCIfType<[f128], 159 CCIfSubtarget<"hasP9Vector()", 160 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, 161 CCIfType<[v4f64, v4f32, v4i1], 162 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>, 163 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 164 CCIfSubtarget<"hasAltivec()", 165 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>> 166]>; 167 168//===----------------------------------------------------------------------===// 169// PowerPC System V Release 4 32-bit ABI 170//===----------------------------------------------------------------------===// 171 172def CC_PPC32_SVR4_Common : CallingConv<[ 173 CCIfType<[i1], CCPromoteToType<i32>>, 174 175 // The ABI requires i64 to be passed in two adjacent registers with the first 176 // register having an odd register number. 177 CCIfType<[i32], 178 CCIfSplit<CCIfSubtarget<"useSoftFloat()", 179 CCIfOrigArgWasNotPPCF128< 180 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>>, 181 182 CCIfType<[i32], 183 CCIfSplit<CCIfNotSubtarget<"useSoftFloat()", 184 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>, 185 CCIfType<[f64], 186 CCIfSubtarget<"hasSPE()", 187 CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>, 188 CCIfSplit<CCIfSubtarget<"useSoftFloat()", 189 CCIfOrigArgWasPPCF128<CCCustom< 190 "CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>, 191 192 // The 'nest' parameter, if any, is passed in R11. 193 CCIfNest<CCAssignToReg<[R11]>>, 194 195 // The first 8 integer arguments are passed in integer registers. 196 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 197 198 // Make sure the i64 words from a long double are either both passed in 199 // registers or both passed on the stack. 200 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>, 201 202 // FP values are passed in F1 - F8. 203 CCIfType<[f32, f64], 204 CCIfNotSubtarget<"hasSPE()", 205 CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>, 206 CCIfType<[f64], 207 CCIfSubtarget<"hasSPE()", 208 CCCustom<"CC_PPC32_SPE_CustomSplitFP64">>>, 209 CCIfType<[f32], 210 CCIfSubtarget<"hasSPE()", 211 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>, 212 213 // Split arguments have an alignment of 8 bytes on the stack. 214 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, 215 216 CCIfType<[i32], CCAssignToStack<4, 4>>, 217 218 // Floats are stored in double precision format, thus they have the same 219 // alignment and size as doubles. 220 // With SPE floats are stored as single precision, so have alignment and 221 // size of int. 222 CCIfType<[f32,f64], CCIfNotSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>, 223 CCIfType<[f32], CCIfSubtarget<"hasSPE()", CCAssignToStack<4, 4>>>, 224 CCIfType<[f64], CCIfSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>, 225 226 // QPX vectors that are stored in double precision need 32-byte alignment. 227 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>, 228 229 // Vectors and float128 get 16-byte stack slots that are 16-byte aligned. 230 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>, 231 CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToStack<16, 16>>> 232]>; 233 234// This calling convention puts vector arguments always on the stack. It is used 235// to assign vector arguments which belong to the variable portion of the 236// parameter list of a variable argument function. 237let Entry = 1 in 238def CC_PPC32_SVR4_VarArg : CallingConv<[ 239 CCDelegateTo<CC_PPC32_SVR4_Common> 240]>; 241 242// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to 243// put vector arguments in vector registers before putting them on the stack. 244let Entry = 1 in 245def CC_PPC32_SVR4 : CallingConv<[ 246 // QPX vectors mirror the scalar FP convention. 247 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()", 248 CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>, 249 250 // The first 12 Vector arguments are passed in AltiVec registers. 251 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], 252 CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, 253 V8, V9, V10, V11, V12, V13]>>>, 254 255 // Float128 types treated as vector arguments. 256 CCIfType<[f128], 257 CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, 258 V8, V9, V10, V11, V12, V13]>>>, 259 260 CCDelegateTo<CC_PPC32_SVR4_Common> 261]>; 262 263// Helper "calling convention" to handle aggregate by value arguments. 264// Aggregate by value arguments are always placed in the local variable space 265// of the caller. This calling convention is only used to assign those stack 266// offsets in the callers stack frame. 267// 268// Still, the address of the aggregate copy in the callers stack frame is passed 269// in a GPR (or in the parameter list area if all GPRs are allocated) from the 270// caller to the callee. The location for the address argument is assigned by 271// the CC_PPC32_SVR4 calling convention. 272// 273// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are 274// not passed by value. 275 276let Entry = 1 in 277def CC_PPC32_SVR4_ByVal : CallingConv<[ 278 CCIfByVal<CCPassByVal<4, 4>>, 279 280 CCCustom<"CC_PPC32_SVR4_Custom_Dummy"> 281]>; 282 283def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27, 284 V28, V29, V30, V31)>; 285 286// SPE does not use FPRs, so break out the common register set as base. 287def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, 288 R21, R22, R23, R24, R25, R26, R27, 289 R28, R29, R30, R31, CR2, CR3, CR4 290 )>; 291def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18, 292 F19, F20, F21, F22, F23, F24, F25, F26, 293 F27, F28, F29, F30, F31 294 )>; 295def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22, 296 S23, S24, S25, S26, S27, S28, S29, S30, S31 297 )>; 298 299def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; 300 301def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>; 302 303def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, 304 R21, R22, R23, R24, R25, R26, R27, R28, 305 R29, R30, R31, F14, F15, F16, F17, F18, 306 F19, F20, F21, F22, F23, F24, F25, F26, 307 F27, F28, F29, F30, F31, CR2, CR3, CR4 308 )>; 309 310// Common CalleeSavedRegs for SVR4 and AIX. 311def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, 312 X21, X22, X23, X24, X25, X26, X27, X28, 313 X29, X30, X31, F14, F15, F16, F17, F18, 314 F19, F20, F21, F22, F23, F24, F25, F26, 315 F27, F28, F29, F30, F31, CR2, CR3, CR4 316 )>; 317 318 319def CSR_PPC64_Altivec : CalleeSavedRegs<(add CSR_PPC64, CSR_Altivec)>; 320 321def CSR_PPC64_R2 : CalleeSavedRegs<(add CSR_PPC64, X2)>; 322 323def CSR_PPC64_R2_Altivec : CalleeSavedRegs<(add CSR_PPC64_Altivec, X2)>; 324 325def CSR_NoRegs : CalleeSavedRegs<(add)>; 326 327// coldcc calling convection marks most registers as non-volatile. 328// Do not include r1 since the stack pointer is never considered a CSR. 329// Do not include r2, since it is the TOC register and is added depending 330// on whether or not the function uses the TOC and is a non-leaf. 331// Do not include r0,r11,r13 as they are optional in functional linkage 332// and value may be altered by inter-library calls. 333// Do not include r12 as it is used as a scratch register. 334// Do not include return registers r3, f1, v2. 335def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10), 336 (sequence "R%u", 14, 31), 337 (sequence "CR%u", 0, 7))>; 338 339def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common, 340 F0, (sequence "F%u", 2, 31))>; 341 342 343def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC, 344 (sequence "V%u", 0, 1), 345 (sequence "V%u", 3, 31))>; 346 347def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common, 348 (sequence "S%u", 4, 10), 349 (sequence "S%u", 14, 31))>; 350 351def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10), 352 (sequence "X%u", 14, 31), 353 F0, (sequence "F%u", 2, 31), 354 (sequence "CR%u", 0, 7))>; 355 356def CSR_SVR64_ColdCC_R2: CalleeSavedRegs<(add CSR_SVR64_ColdCC, X2)>; 357 358def CSR_SVR64_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC, 359 (sequence "V%u", 0, 1), 360 (sequence "V%u", 3, 31))>; 361 362def CSR_SVR64_ColdCC_R2_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC_Altivec, X2)>; 363 364def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10), 365 (sequence "X%u", 14, 31), 366 (sequence "F%u", 0, 31), 367 (sequence "CR%u", 0, 7))>; 368 369def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs, 370 (sequence "V%u", 0, 31))>; 371 372def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec, 373 (sequence "VSL%u", 0, 31))>; 374 375