1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 61def FeatureModernAIXAs 62 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 63 "AIX system assembler is modern enough to support new mnes">; 64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 65 "Enable floating-point instructions">; 66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 67 "Enable 64-bit registers usage for ppc32 [beta]">; 68def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 69 "Use condition-register bits individually">; 70def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 71 "Enable classic FPU instructions", 72 [FeatureHardFloat]>; 73def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 74 "Enable Altivec instructions", 75 [FeatureFPU]>; 76def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 77 "Enable SPE instructions", 78 [FeatureHardFloat]>; 79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 80 "Enable Embedded Floating-Point APU 2 instructions", 81 [FeatureSPE]>; 82def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 83 "Enable the MFOCRF instruction">; 84def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 85 "Enable the fsqrt instruction", 86 [FeatureFPU]>; 87def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 88 "Enable the fcpsgn instruction", 89 [FeatureFPU]>; 90def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 91 "Enable the fre instruction", 92 [FeatureFPU]>; 93def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 94 "Enable the fres instruction", 95 [FeatureFPU]>; 96def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 97 "Enable the frsqrte instruction", 98 [FeatureFPU]>; 99def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 100 "Enable the frsqrtes instruction", 101 [FeatureFPU]>; 102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 103 "Assume higher precision reciprocal estimates">; 104def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 105 "Enable the stfiwx instruction", 106 [FeatureFPU]>; 107def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 108 "Enable the lfiwax instruction", 109 [FeatureFPU]>; 110def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 111 "Enable the fri[mnpz] instructions", 112 [FeatureFPU]>; 113def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 115 [FeatureFPU]>; 116def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 117 "Enable the isel instruction">; 118def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 119 "Enable the bpermd instruction">; 120def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 121 "Enable extended divide instructions">; 122def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 123 "Enable the ldbrx instruction">; 124def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 125 "Enable the cmpb instruction">; 126def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 127 "Enable icbt instruction">; 128def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 129 "Enable Book E instructions", 130 [FeatureICBT]>; 131def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 132 "Has only the msync instruction instead of sync", 133 [FeatureBookE]>; 134def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 135 "Enable E500/E500mc instructions">; 136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 137 "Enable secure plt mode">; 138def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 139 "Enable PPC 4xx instructions">; 140def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 141 "Enable PPC 6xx instructions">; 142def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 143 "Enable VSX instructions", 144 [FeatureAltivec]>; 145def FeatureTwoConstNR : 146 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 147 "Requires two constant Newton-Raphson computation">; 148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 149 "Enable POWER8 Altivec instructions", 150 [FeatureAltivec]>; 151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 152 "Enable POWER8 Crypto instructions", 153 [FeatureP8Altivec]>; 154def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 155 "Enable POWER8 vector instructions", 156 [FeatureVSX, FeatureP8Altivec]>; 157def FeatureDirectMove : 158 SubtargetFeature<"direct-move", "HasDirectMove", "true", 159 "Enable Power8 direct move instructions", 160 [FeatureVSX]>; 161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 162 "HasPartwordAtomics", "true", 163 "Enable l[bh]arx and st[bh]cx.">; 164def FeatureInvariantFunctionDescriptors : 165 SubtargetFeature<"invariant-function-descriptors", 166 "HasInvariantFunctionDescriptors", "true", 167 "Assume function descriptors are invariant">; 168def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 169 "Always use indirect calls">; 170def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 171 "Enable Hardware Transactional Memory instructions">; 172def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 173 "Implement mftb using the mfspr instruction">; 174def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 175 "Target supports instruction fusion">; 176def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 177 "HasAddiLoadFusion", "true", 178 "Power8 Addi-Load fusion", 179 [FeatureFusion]>; 180def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 181 "HasAddisLoadFusion", "true", 182 "Power8 Addis-Load fusion", 183 [FeatureFusion]>; 184def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 185 "Target supports store clustering", 186 [FeatureFusion]>; 187def FeatureUnalignedFloats : 188 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 189 "true", "CPU does not trap on unaligned FP access">; 190def FeaturePPCPreRASched: 191 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 192 "Use PowerPC pre-RA scheduling strategy">; 193def FeaturePPCPostRASched: 194 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 195 "Use PowerPC post-RA scheduling strategy">; 196def FeatureFloat128 : 197 SubtargetFeature<"float128", "HasFloat128", "true", 198 "Enable the __float128 data type for IEEE-754R Binary128.", 199 [FeatureVSX]>; 200def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 201 "POPCNTD_Fast", 202 "Enable the popcnt[dw] instructions">; 203// Note that for the a2 processor models we should not use popcnt[dw] by 204// default. These processors do support the instructions, but they're 205// microcoded, and the software emulation is about twice as fast. 206def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 207 "POPCNTD_Slow", 208 "Has slow popcnt[dw] instructions">; 209 210def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 211 "Treat vector data stream cache control instructions as deprecated">; 212 213def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 214 "true", 215 "Enable instructions in ISA 3.0.">; 216def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 217 "true", 218 "Enable instructions in ISA 3.1.", 219 [FeatureISA3_0]>; 220def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 221 "Enable POWER9 Altivec instructions", 222 [FeatureISA3_0, FeatureP8Altivec]>; 223def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 224 "Enable POWER9 vector instructions", 225 [FeatureISA3_0, FeatureP8Vector, 226 FeatureP9Altivec]>; 227def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 228 "true", 229 "Enable POWER10 vector instructions", 230 [FeatureISA3_1, FeatureP9Vector]>; 231// A separate feature for this even though it is equivalent to P9Vector 232// because this is a feature of the implementation rather than the architecture 233// and may go away with future CPU's. 234def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 235 "VectorsUseTwoUnits", 236 "true", 237 "Vectors use two units">; 238def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 239 "true", 240 "Enable prefixed instructions", 241 [FeatureISA3_0, FeatureP8Vector, 242 FeatureP9Altivec]>; 243def FeaturePCRelativeMemops : 244 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 245 "Enable PC relative Memory Ops", 246 [FeatureISA3_0, FeaturePrefixInstrs]>; 247def FeaturePairedVectorMemops: 248 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 249 "32Byte load and store instructions", 250 [FeatureISA3_0]>; 251def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 252 "Enable MMA instructions", 253 [FeatureP8Vector, FeatureP9Altivec, 254 FeaturePairedVectorMemops]>; 255 256def FeaturePredictableSelectIsExpensive : 257 SubtargetFeature<"predictable-select-expensive", 258 "PredictableSelectIsExpensive", 259 "true", 260 "Prefer likely predicted branches over selects">; 261 262// Since new processors generally contain a superset of features of those that 263// came before them, the idea is to make implementations of new processors 264// less error prone and easier to read. 265// Namely: 266// list<SubtargetFeature> P8InheritableFeatures = ... 267// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 268// [ features that Power8 does not support but inheritable ] 269// list<SubtargetFeature> FutureProcessorSpecificFeatures = 270// [ features that Power8 does not support and not inheritable ] 271// list<SubtargetFeature> FutureProcessorInheritableFeatures = 272// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 273// list<SubtargetFeature> FutureProcessorFeatures = 274// !listconcat(FutureProcessorInheritableFeatures, 275// FutureProcessorSpecificFeatures) 276 277// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 278// well as providing a single point of definition if the feature set will be 279// used elsewhere. 280def ProcessorFeatures { 281 // Power7 282 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 283 FeatureAltivec, 284 FeatureVSX, 285 FeatureMFOCRF, 286 FeatureFCPSGN, 287 FeatureFSqrt, 288 FeatureFRE, 289 FeatureFRES, 290 FeatureFRSQRTE, 291 FeatureFRSQRTES, 292 FeatureRecipPrec, 293 FeatureSTFIWX, 294 FeatureLFIWAX, 295 FeatureFPRND, 296 FeatureFPCVT, 297 FeatureISEL, 298 FeaturePOPCNTD, 299 FeatureCMPB, 300 FeatureLDBRX, 301 Feature64Bit, 302 /* Feature64BitRegs, */ 303 FeatureBPERMD, 304 FeatureExtDiv, 305 FeatureMFTB, 306 DeprecatedDST, 307 FeatureTwoConstNR, 308 FeatureUnalignedFloats]; 309 list<SubtargetFeature> P7SpecificFeatures = []; 310 list<SubtargetFeature> P7Features = 311 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 312 313 // Power8 314 list<SubtargetFeature> P8AdditionalFeatures = 315 [DirectivePwr8, 316 FeatureP8Altivec, 317 FeatureP8Vector, 318 FeatureP8Crypto, 319 FeatureHTM, 320 FeatureDirectMove, 321 FeatureICBT, 322 FeaturePartwordAtomic, 323 FeaturePredictableSelectIsExpensive 324 ]; 325 326 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 327 FeatureAddisLoadFusion]; 328 list<SubtargetFeature> P8InheritableFeatures = 329 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 330 list<SubtargetFeature> P8Features = 331 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 332 333 // Power9 334 list<SubtargetFeature> P9AdditionalFeatures = 335 [DirectivePwr9, 336 FeatureP9Altivec, 337 FeatureP9Vector, 338 FeaturePPCPreRASched, 339 FeaturePPCPostRASched, 340 FeatureISA3_0, 341 FeaturePredictableSelectIsExpensive 342 ]; 343 344 // Some features are unique to Power9 and there is no reason to assume 345 // they will be part of any future CPUs. One example is the narrower 346 // dispatch for vector operations than scalar ones. For the time being, 347 // this list also includes scheduling-related features since we do not have 348 // enough info to create custom scheduling strategies for future CPUs. 349 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 350 list<SubtargetFeature> P9InheritableFeatures = 351 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 352 list<SubtargetFeature> P9Features = 353 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 354 355 // Power10 356 // For P10 CPU we assume that all of the existing features from Power9 357 // still exist with the exception of those we know are Power9 specific. 358 list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion]; 359 list<SubtargetFeature> P10AdditionalFeatures = 360 !listconcat(FusionFeatures, [ 361 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 362 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 363 FeaturePairedVectorMemops]); 364 list<SubtargetFeature> P10SpecificFeatures = []; 365 list<SubtargetFeature> P10InheritableFeatures = 366 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 367 list<SubtargetFeature> P10Features = 368 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 369 370 // Future 371 // For future CPU we assume that all of the existing features from Power10 372 // still exist with the exception of those we know are Power10 specific. 373 list<SubtargetFeature> FutureAdditionalFeatures = []; 374 list<SubtargetFeature> FutureSpecificFeatures = []; 375 list<SubtargetFeature> FutureInheritableFeatures = 376 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 377 list<SubtargetFeature> FutureFeatures = 378 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 379} 380 381// Note: Future features to add when support is extended to more 382// recent ISA levels: 383// 384// DFP p6, p6x, p7 decimal floating-point instructions 385// POPCNTB p5 through p7 popcntb and related instructions 386 387//===----------------------------------------------------------------------===// 388// Classes used for relation maps. 389//===----------------------------------------------------------------------===// 390// RecFormRel - Filter class used to relate non-record-form instructions with 391// their record-form variants. 392class RecFormRel; 393 394// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 395// FMA instruction forms with their corresponding factor-killing forms. 396class AltVSXFMARel { 397 bit IsVSXFMAAlt = 0; 398} 399 400//===----------------------------------------------------------------------===// 401// Relation Map Definitions. 402//===----------------------------------------------------------------------===// 403 404def getRecordFormOpcode : InstrMapping { 405 let FilterClass = "RecFormRel"; 406 // Instructions with the same BaseName and Interpretation64Bit values 407 // form a row. 408 let RowFields = ["BaseName", "Interpretation64Bit"]; 409 // Instructions with the same RC value form a column. 410 let ColFields = ["RC"]; 411 // The key column are the non-record-form instructions. 412 let KeyCol = ["0"]; 413 // Value columns RC=1 414 let ValueCols = [["1"]]; 415} 416 417def getNonRecordFormOpcode : InstrMapping { 418 let FilterClass = "RecFormRel"; 419 // Instructions with the same BaseName and Interpretation64Bit values 420 // form a row. 421 let RowFields = ["BaseName", "Interpretation64Bit"]; 422 // Instructions with the same RC value form a column. 423 let ColFields = ["RC"]; 424 // The key column are the record-form instructions. 425 let KeyCol = ["1"]; 426 // Value columns are RC=0 427 let ValueCols = [["0"]]; 428} 429 430def getAltVSXFMAOpcode : InstrMapping { 431 let FilterClass = "AltVSXFMARel"; 432 // Instructions with the same BaseName value form a row. 433 let RowFields = ["BaseName"]; 434 // Instructions with the same IsVSXFMAAlt value form a column. 435 let ColFields = ["IsVSXFMAAlt"]; 436 // The key column are the (default) addend-killing instructions. 437 let KeyCol = ["0"]; 438 // Value columns IsVSXFMAAlt=1 439 let ValueCols = [["1"]]; 440} 441 442//===----------------------------------------------------------------------===// 443// Register File Description 444//===----------------------------------------------------------------------===// 445 446include "PPCRegisterInfo.td" 447include "PPCSchedule.td" 448include "GISel/PPCRegisterBanks.td" 449 450//===----------------------------------------------------------------------===// 451// PowerPC processors supported. 452// 453 454def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 455 FeatureMFTB]>; 456def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 457 FeatureFRES, FeatureFRSQRTE, 458 FeatureICBT, FeatureBookE, 459 FeatureMSYNC, FeatureMFTB]>; 460def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 461 FeatureFRES, FeatureFRSQRTE, 462 FeatureICBT, FeatureBookE, 463 FeatureMSYNC, FeatureMFTB]>; 464def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 465def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 466 FeatureMFTB]>; 467def : Processor<"603", G3Itineraries, [Directive603, 468 FeatureFRES, FeatureFRSQRTE, 469 FeatureMFTB]>; 470def : Processor<"603e", G3Itineraries, [Directive603, 471 FeatureFRES, FeatureFRSQRTE, 472 FeatureMFTB]>; 473def : Processor<"603ev", G3Itineraries, [Directive603, 474 FeatureFRES, FeatureFRSQRTE, 475 FeatureMFTB]>; 476def : Processor<"604", G3Itineraries, [Directive604, 477 FeatureFRES, FeatureFRSQRTE, 478 FeatureMFTB]>; 479def : Processor<"604e", G3Itineraries, [Directive604, 480 FeatureFRES, FeatureFRSQRTE, 481 FeatureMFTB]>; 482def : Processor<"620", G3Itineraries, [Directive620, 483 FeatureFRES, FeatureFRSQRTE, 484 FeatureMFTB]>; 485def : Processor<"750", G4Itineraries, [Directive750, 486 FeatureFRES, FeatureFRSQRTE, 487 FeatureMFTB]>; 488def : Processor<"g3", G3Itineraries, [Directive750, 489 FeatureFRES, FeatureFRSQRTE, 490 FeatureMFTB]>; 491def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 492 FeatureFRES, FeatureFRSQRTE, 493 FeatureMFTB]>; 494def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 495 FeatureFRES, FeatureFRSQRTE, 496 FeatureMFTB]>; 497def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 498 FeatureFRES, FeatureFRSQRTE, 499 FeatureMFTB]>; 500def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 501 FeatureFRES, FeatureFRSQRTE, 502 FeatureMFTB]>; 503 504def : ProcessorModel<"970", G5Model, 505 [Directive970, FeatureAltivec, 506 FeatureMFOCRF, FeatureFSqrt, 507 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 508 Feature64Bit /*, Feature64BitRegs */, 509 FeatureMFTB]>; 510def : ProcessorModel<"g5", G5Model, 511 [Directive970, FeatureAltivec, 512 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 513 FeatureFRES, FeatureFRSQRTE, 514 Feature64Bit /*, Feature64BitRegs */, 515 FeatureMFTB, DeprecatedDST]>; 516def : ProcessorModel<"e500", PPCE500Model, 517 [DirectiveE500, 518 FeatureICBT, FeatureBookE, 519 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 520def : ProcessorModel<"e500mc", PPCE500mcModel, 521 [DirectiveE500mc, 522 FeatureSTFIWX, FeatureICBT, FeatureBookE, 523 FeatureISEL, FeatureMFTB]>; 524def : ProcessorModel<"e5500", PPCE5500Model, 525 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 526 FeatureSTFIWX, FeatureICBT, FeatureBookE, 527 FeatureISEL, FeatureMFTB]>; 528def : ProcessorModel<"a2", PPCA2Model, 529 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 530 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 531 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 532 FeatureSTFIWX, FeatureLFIWAX, 533 FeatureFPRND, FeatureFPCVT, FeatureISEL, 534 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 535 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 536def : ProcessorModel<"pwr3", G5Model, 537 [DirectivePwr3, FeatureAltivec, 538 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 539 FeatureSTFIWX, Feature64Bit]>; 540def : ProcessorModel<"pwr4", G5Model, 541 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 542 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 543 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 544def : ProcessorModel<"pwr5", G5Model, 545 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 546 FeatureFSqrt, FeatureFRE, FeatureFRES, 547 FeatureFRSQRTE, FeatureFRSQRTES, 548 FeatureSTFIWX, Feature64Bit, 549 FeatureMFTB, DeprecatedDST]>; 550def : ProcessorModel<"pwr5x", G5Model, 551 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 552 FeatureFSqrt, FeatureFRE, FeatureFRES, 553 FeatureFRSQRTE, FeatureFRSQRTES, 554 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 555 FeatureMFTB, DeprecatedDST]>; 556def : ProcessorModel<"pwr6", G5Model, 557 [DirectivePwr6, FeatureAltivec, 558 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 559 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 560 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 561 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 562 FeatureMFTB, DeprecatedDST]>; 563def : ProcessorModel<"pwr6x", G5Model, 564 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 565 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 566 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 567 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 568 FeatureFPRND, Feature64Bit, 569 FeatureMFTB, DeprecatedDST]>; 570def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 571def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 572def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 573// No scheduler model yet. 574def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>; 575// No scheduler model for future CPU. 576def : ProcessorModel<"future", NoSchedModel, 577 ProcessorFeatures.FutureFeatures>; 578def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 579 FeatureMFTB]>; 580def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 581 FeatureMFTB]>; 582def : ProcessorModel<"ppc64", G5Model, 583 [Directive64, FeatureAltivec, 584 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 585 FeatureFRSQRTE, FeatureSTFIWX, 586 Feature64Bit /*, Feature64BitRegs */, 587 FeatureMFTB]>; 588def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 589 590//===----------------------------------------------------------------------===// 591// Calling Conventions 592//===----------------------------------------------------------------------===// 593 594include "PPCCallingConv.td" 595 596def PPCInstrInfo : InstrInfo { 597 let isLittleEndianEncoding = 1; 598 599 // FIXME: Unset this when no longer needed! 600 let decodePositionallyEncodedOperands = 1; 601 602 let noNamedPositionallyEncodedOperands = 1; 603} 604 605def PPCAsmWriter : AsmWriter { 606 string AsmWriterClassName = "InstPrinter"; 607 int PassSubtarget = 1; 608 int Variant = 0; 609 bit isMCAsmWriter = 1; 610} 611 612def PPCAsmParser : AsmParser { 613 let ShouldEmitMatchRegisterName = 0; 614} 615 616def PPCAsmParserVariant : AsmParserVariant { 617 int Variant = 0; 618 619 // We do not use hard coded registers in asm strings. However, some 620 // InstAlias definitions use immediate literals. Set RegisterPrefix 621 // so that those are not misinterpreted as registers. 622 string RegisterPrefix = "%"; 623 string BreakCharacters = "."; 624} 625 626def PPC : Target { 627 // Information about the instructions. 628 let InstructionSet = PPCInstrInfo; 629 630 let AssemblyWriters = [PPCAsmWriter]; 631 let AssemblyParsers = [PPCAsmParser]; 632 let AssemblyParserVariants = [PPCAsmParserVariant]; 633 let AllowRegisterRenaming = 1; 634} 635 636//===----------------------------------------------------------------------===// 637// Pfm Counters 638//===----------------------------------------------------------------------===// 639 640include "PPCPfmCounters.td" 641