1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 61def FeatureModernAIXAs 62 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 63 "AIX system assembler is modern enough to support new mnes">; 64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 65 "Enable floating-point instructions">; 66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 67 "Enable 64-bit registers usage for ppc32 [beta]">; 68def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 69 "Use condition-register bits individually">; 70def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 71 "Enable classic FPU instructions", 72 [FeatureHardFloat]>; 73def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 74 "Enable Altivec instructions", 75 [FeatureFPU]>; 76def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 77 "Enable SPE instructions", 78 [FeatureHardFloat]>; 79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 80 "Enable Embedded Floating-Point APU 2 instructions", 81 [FeatureSPE]>; 82def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 83 "Enable the MFOCRF instruction">; 84def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 85 "Enable the fsqrt instruction", 86 [FeatureFPU]>; 87def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 88 "Enable the fcpsgn instruction", 89 [FeatureFPU]>; 90def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 91 "Enable the fre instruction", 92 [FeatureFPU]>; 93def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 94 "Enable the fres instruction", 95 [FeatureFPU]>; 96def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 97 "Enable the frsqrte instruction", 98 [FeatureFPU]>; 99def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 100 "Enable the frsqrtes instruction", 101 [FeatureFPU]>; 102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 103 "Assume higher precision reciprocal estimates">; 104def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 105 "Enable the stfiwx instruction", 106 [FeatureFPU]>; 107def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 108 "Enable the lfiwax instruction", 109 [FeatureFPU]>; 110def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 111 "Enable the fri[mnpz] instructions", 112 [FeatureFPU]>; 113def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 115 [FeatureFPU]>; 116def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 117 "Enable the isel instruction">; 118def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 119 "Enable the bpermd instruction">; 120def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 121 "Enable extended divide instructions">; 122def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 123 "Enable the ldbrx instruction">; 124def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 125 "Enable the cmpb instruction">; 126def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 127 "Enable icbt instruction">; 128def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 129 "Enable Book E instructions", 130 [FeatureICBT]>; 131def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 132 "Has only the msync instruction instead of sync", 133 [FeatureBookE]>; 134def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 135 "Enable E500/E500mc instructions">; 136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 137 "Enable secure plt mode">; 138def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 139 "Enable PPC 4xx instructions">; 140def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 141 "Enable PPC 6xx instructions">; 142def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 143 "Enable VSX instructions", 144 [FeatureAltivec]>; 145def FeatureTwoConstNR : 146 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 147 "Requires two constant Newton-Raphson computation">; 148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 149 "Enable POWER8 Altivec instructions", 150 [FeatureAltivec]>; 151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 152 "Enable POWER8 Crypto instructions", 153 [FeatureP8Altivec]>; 154def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 155 "Enable POWER8 vector instructions", 156 [FeatureVSX, FeatureP8Altivec]>; 157def FeatureDirectMove : 158 SubtargetFeature<"direct-move", "HasDirectMove", "true", 159 "Enable Power8 direct move instructions", 160 [FeatureVSX]>; 161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 162 "HasPartwordAtomics", "true", 163 "Enable l[bh]arx and st[bh]cx.">; 164def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics", 165 "HasQuadwordAtomics", "true", 166 "Enable lqarx and stqcx.">; 167def FeatureInvariantFunctionDescriptors : 168 SubtargetFeature<"invariant-function-descriptors", 169 "HasInvariantFunctionDescriptors", "true", 170 "Assume function descriptors are invariant">; 171def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 172 "Always use indirect calls">; 173def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 174 "Enable Hardware Transactional Memory instructions">; 175def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 176 "Implement mftb using the mfspr instruction">; 177def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 178 "Target supports instruction fusion">; 179def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 180 "HasAddiLoadFusion", "true", 181 "Power8 Addi-Load fusion", 182 [FeatureFusion]>; 183def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 184 "HasAddisLoadFusion", "true", 185 "Power8 Addis-Load fusion", 186 [FeatureFusion]>; 187def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 188 "Target supports store clustering", 189 [FeatureFusion]>; 190def FeatureArithAddFusion : 191 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true", 192 "Target supports Arithmetic Operations with Add fusion", 193 [FeatureFusion]>; 194def FeatureAddLogicalFusion : 195 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true", 196 "Target supports Add with Logical Operations fusion", 197 [FeatureFusion]>; 198def FeatureLogicalAddFusion : 199 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true", 200 "Target supports Logical with Add Operations fusion", 201 [FeatureFusion]>; 202def FeatureLogicalFusion : 203 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true", 204 "Target supports Logical Operations fusion", 205 [FeatureFusion]>; 206def FeatureUnalignedFloats : 207 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 208 "true", "CPU does not trap on unaligned FP access">; 209def FeaturePPCPreRASched: 210 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 211 "Use PowerPC pre-RA scheduling strategy">; 212def FeaturePPCPostRASched: 213 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 214 "Use PowerPC post-RA scheduling strategy">; 215def FeatureFloat128 : 216 SubtargetFeature<"float128", "HasFloat128", "true", 217 "Enable the __float128 data type for IEEE-754R Binary128.", 218 [FeatureVSX]>; 219def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 220 "POPCNTD_Fast", 221 "Enable the popcnt[dw] instructions">; 222// Note that for the a2 processor models we should not use popcnt[dw] by 223// default. These processors do support the instructions, but they're 224// microcoded, and the software emulation is about twice as fast. 225def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 226 "POPCNTD_Slow", 227 "Has slow popcnt[dw] instructions">; 228 229def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 230 "Treat vector data stream cache control instructions as deprecated">; 231 232def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06", 233 "true", 234 "Enable instructions in ISA 2.06.">; 235def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", 236 "true", 237 "Enable instructions in ISA 2.07.">; 238def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 239 "true", 240 "Enable instructions in ISA 3.0.", 241 [FeatureISA2_07]>; 242def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 243 "true", 244 "Enable instructions in ISA 3.1.", 245 [FeatureISA3_0]>; 246def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 247 "Enable POWER9 Altivec instructions", 248 [FeatureISA3_0, FeatureP8Altivec]>; 249def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 250 "Enable POWER9 vector instructions", 251 [FeatureISA3_0, FeatureP8Vector, 252 FeatureP9Altivec]>; 253def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 254 "true", 255 "Enable POWER10 vector instructions", 256 [FeatureISA3_1, FeatureP9Vector]>; 257// A separate feature for this even though it is equivalent to P9Vector 258// because this is a feature of the implementation rather than the architecture 259// and may go away with future CPU's. 260def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 261 "VectorsUseTwoUnits", 262 "true", 263 "Vectors use two units">; 264def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 265 "true", 266 "Enable prefixed instructions", 267 [FeatureISA3_0, FeatureP8Vector, 268 FeatureP9Altivec]>; 269def FeaturePCRelativeMemops : 270 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 271 "Enable PC relative Memory Ops", 272 [FeatureISA3_0, FeaturePrefixInstrs]>; 273def FeaturePairedVectorMemops: 274 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 275 "32Byte load and store instructions", 276 [FeatureISA3_0]>; 277def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 278 "Enable MMA instructions", 279 [FeatureP8Vector, FeatureP9Altivec, 280 FeaturePairedVectorMemops]>; 281def FeatureROPProtect : 282 SubtargetFeature<"rop-protect", "HasROPProtect", "true", 283 "Add ROP protect">; 284 285def FeaturePrivileged : 286 SubtargetFeature<"privileged", "HasPrivileged", "true", 287 "Add privileged instructions">; 288 289def FeaturePredictableSelectIsExpensive : 290 SubtargetFeature<"predictable-select-expensive", 291 "PredictableSelectIsExpensive", 292 "true", 293 "Prefer likely predicted branches over selects">; 294 295// Since new processors generally contain a superset of features of those that 296// came before them, the idea is to make implementations of new processors 297// less error prone and easier to read. 298// Namely: 299// list<SubtargetFeature> P8InheritableFeatures = ... 300// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 301// [ features that Power8 does not support but inheritable ] 302// list<SubtargetFeature> FutureProcessorSpecificFeatures = 303// [ features that Power8 does not support and not inheritable ] 304// list<SubtargetFeature> FutureProcessorInheritableFeatures = 305// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 306// list<SubtargetFeature> FutureProcessorFeatures = 307// !listconcat(FutureProcessorInheritableFeatures, 308// FutureProcessorSpecificFeatures) 309 310// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 311// well as providing a single point of definition if the feature set will be 312// used elsewhere. 313def ProcessorFeatures { 314 // Power7 315 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 316 FeatureAltivec, 317 FeatureVSX, 318 FeatureMFOCRF, 319 FeatureFCPSGN, 320 FeatureFSqrt, 321 FeatureFRE, 322 FeatureFRES, 323 FeatureFRSQRTE, 324 FeatureFRSQRTES, 325 FeatureRecipPrec, 326 FeatureSTFIWX, 327 FeatureLFIWAX, 328 FeatureFPRND, 329 FeatureFPCVT, 330 FeatureISEL, 331 FeaturePOPCNTD, 332 FeatureCMPB, 333 FeatureLDBRX, 334 Feature64Bit, 335 /* Feature64BitRegs, */ 336 FeatureBPERMD, 337 FeatureExtDiv, 338 FeatureMFTB, 339 DeprecatedDST, 340 FeatureTwoConstNR, 341 FeatureUnalignedFloats, 342 FeatureISA2_06]; 343 list<SubtargetFeature> P7SpecificFeatures = []; 344 list<SubtargetFeature> P7Features = 345 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 346 347 // Power8 348 list<SubtargetFeature> P8AdditionalFeatures = 349 [DirectivePwr8, 350 FeatureP8Altivec, 351 FeatureP8Vector, 352 FeatureP8Crypto, 353 FeatureHTM, 354 FeatureDirectMove, 355 FeatureICBT, 356 FeaturePartwordAtomic, 357 FeatureQuadwordAtomic, 358 FeaturePredictableSelectIsExpensive, 359 FeatureISA2_07 360 ]; 361 362 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 363 FeatureAddisLoadFusion]; 364 list<SubtargetFeature> P8InheritableFeatures = 365 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 366 list<SubtargetFeature> P8Features = 367 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 368 369 // Power9 370 list<SubtargetFeature> P9AdditionalFeatures = 371 [DirectivePwr9, 372 FeatureP9Altivec, 373 FeatureP9Vector, 374 FeaturePPCPreRASched, 375 FeaturePPCPostRASched, 376 FeatureISA3_0, 377 FeaturePredictableSelectIsExpensive 378 ]; 379 380 // Some features are unique to Power9 and there is no reason to assume 381 // they will be part of any future CPUs. One example is the narrower 382 // dispatch for vector operations than scalar ones. For the time being, 383 // this list also includes scheduling-related features since we do not have 384 // enough info to create custom scheduling strategies for future CPUs. 385 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 386 list<SubtargetFeature> P9InheritableFeatures = 387 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 388 list<SubtargetFeature> P9Features = 389 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 390 391 // Power10 392 // For P10 CPU we assume that all of the existing features from Power9 393 // still exist with the exception of those we know are Power9 specific. 394 list<SubtargetFeature> FusionFeatures = [ 395 FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion, 396 FeatureLogicalFusion, FeatureArithAddFusion 397 ]; 398 list<SubtargetFeature> P10AdditionalFeatures = 399 !listconcat(FusionFeatures, [ 400 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 401 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 402 FeaturePairedVectorMemops]); 403 list<SubtargetFeature> P10SpecificFeatures = []; 404 list<SubtargetFeature> P10InheritableFeatures = 405 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 406 list<SubtargetFeature> P10Features = 407 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 408 409 // Future 410 // For future CPU we assume that all of the existing features from Power10 411 // still exist with the exception of those we know are Power10 specific. 412 list<SubtargetFeature> FutureAdditionalFeatures = []; 413 list<SubtargetFeature> FutureSpecificFeatures = []; 414 list<SubtargetFeature> FutureInheritableFeatures = 415 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 416 list<SubtargetFeature> FutureFeatures = 417 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 418} 419 420// Note: Future features to add when support is extended to more 421// recent ISA levels: 422// 423// DFP p6, p6x, p7 decimal floating-point instructions 424// POPCNTB p5 through p7 popcntb and related instructions 425 426//===----------------------------------------------------------------------===// 427// Classes used for relation maps. 428//===----------------------------------------------------------------------===// 429// RecFormRel - Filter class used to relate non-record-form instructions with 430// their record-form variants. 431class RecFormRel; 432 433// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 434// FMA instruction forms with their corresponding factor-killing forms. 435class AltVSXFMARel { 436 bit IsVSXFMAAlt = 0; 437} 438 439//===----------------------------------------------------------------------===// 440// Relation Map Definitions. 441//===----------------------------------------------------------------------===// 442 443def getRecordFormOpcode : InstrMapping { 444 let FilterClass = "RecFormRel"; 445 // Instructions with the same BaseName and Interpretation64Bit values 446 // form a row. 447 let RowFields = ["BaseName", "Interpretation64Bit"]; 448 // Instructions with the same RC value form a column. 449 let ColFields = ["RC"]; 450 // The key column are the non-record-form instructions. 451 let KeyCol = ["0"]; 452 // Value columns RC=1 453 let ValueCols = [["1"]]; 454} 455 456def getNonRecordFormOpcode : InstrMapping { 457 let FilterClass = "RecFormRel"; 458 // Instructions with the same BaseName and Interpretation64Bit values 459 // form a row. 460 let RowFields = ["BaseName", "Interpretation64Bit"]; 461 // Instructions with the same RC value form a column. 462 let ColFields = ["RC"]; 463 // The key column are the record-form instructions. 464 let KeyCol = ["1"]; 465 // Value columns are RC=0 466 let ValueCols = [["0"]]; 467} 468 469def getAltVSXFMAOpcode : InstrMapping { 470 let FilterClass = "AltVSXFMARel"; 471 // Instructions with the same BaseName value form a row. 472 let RowFields = ["BaseName"]; 473 // Instructions with the same IsVSXFMAAlt value form a column. 474 let ColFields = ["IsVSXFMAAlt"]; 475 // The key column are the (default) addend-killing instructions. 476 let KeyCol = ["0"]; 477 // Value columns IsVSXFMAAlt=1 478 let ValueCols = [["1"]]; 479} 480 481//===----------------------------------------------------------------------===// 482// Register File Description 483//===----------------------------------------------------------------------===// 484 485include "PPCRegisterInfo.td" 486include "PPCSchedule.td" 487include "GISel/PPCRegisterBanks.td" 488 489//===----------------------------------------------------------------------===// 490// PowerPC processors supported. 491// 492 493def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 494 FeatureMFTB]>; 495def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 496 FeatureFRES, FeatureFRSQRTE, 497 FeatureICBT, FeatureBookE, 498 FeatureMSYNC, FeatureMFTB]>; 499def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 500 FeatureFRES, FeatureFRSQRTE, 501 FeatureICBT, FeatureBookE, 502 FeatureMSYNC, FeatureMFTB]>; 503def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 504def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 505 FeatureMFTB]>; 506def : Processor<"603", G3Itineraries, [Directive603, 507 FeatureFRES, FeatureFRSQRTE, 508 FeatureMFTB]>; 509def : Processor<"603e", G3Itineraries, [Directive603, 510 FeatureFRES, FeatureFRSQRTE, 511 FeatureMFTB]>; 512def : Processor<"603ev", G3Itineraries, [Directive603, 513 FeatureFRES, FeatureFRSQRTE, 514 FeatureMFTB]>; 515def : Processor<"604", G3Itineraries, [Directive604, 516 FeatureFRES, FeatureFRSQRTE, 517 FeatureMFTB]>; 518def : Processor<"604e", G3Itineraries, [Directive604, 519 FeatureFRES, FeatureFRSQRTE, 520 FeatureMFTB]>; 521def : Processor<"620", G3Itineraries, [Directive620, 522 FeatureFRES, FeatureFRSQRTE, 523 FeatureMFTB]>; 524def : Processor<"750", G4Itineraries, [Directive750, 525 FeatureFRES, FeatureFRSQRTE, 526 FeatureMFTB]>; 527def : Processor<"g3", G3Itineraries, [Directive750, 528 FeatureFRES, FeatureFRSQRTE, 529 FeatureMFTB]>; 530def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 531 FeatureFRES, FeatureFRSQRTE, 532 FeatureMFTB]>; 533def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 534 FeatureFRES, FeatureFRSQRTE, 535 FeatureMFTB]>; 536def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 537 FeatureFRES, FeatureFRSQRTE, 538 FeatureMFTB]>; 539def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 540 FeatureFRES, FeatureFRSQRTE, 541 FeatureMFTB]>; 542 543def : ProcessorModel<"970", G5Model, 544 [Directive970, FeatureAltivec, 545 FeatureMFOCRF, FeatureFSqrt, 546 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 547 Feature64Bit /*, Feature64BitRegs */, 548 FeatureMFTB]>; 549def : ProcessorModel<"g5", G5Model, 550 [Directive970, FeatureAltivec, 551 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 552 FeatureFRES, FeatureFRSQRTE, 553 Feature64Bit /*, Feature64BitRegs */, 554 FeatureMFTB, DeprecatedDST]>; 555def : ProcessorModel<"e500", PPCE500Model, 556 [DirectiveE500, 557 FeatureICBT, FeatureBookE, 558 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 559def : ProcessorModel<"e500mc", PPCE500mcModel, 560 [DirectiveE500mc, 561 FeatureSTFIWX, FeatureICBT, FeatureBookE, 562 FeatureISEL, FeatureMFTB]>; 563def : ProcessorModel<"e5500", PPCE5500Model, 564 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 565 FeatureSTFIWX, FeatureICBT, FeatureBookE, 566 FeatureISEL, FeatureMFTB]>; 567def : ProcessorModel<"a2", PPCA2Model, 568 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 569 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 570 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 571 FeatureSTFIWX, FeatureLFIWAX, 572 FeatureFPRND, FeatureFPCVT, FeatureISEL, 573 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 574 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 575def : ProcessorModel<"pwr3", G5Model, 576 [DirectivePwr3, FeatureAltivec, 577 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 578 FeatureSTFIWX, Feature64Bit]>; 579def : ProcessorModel<"pwr4", G5Model, 580 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 581 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 582 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 583def : ProcessorModel<"pwr5", G5Model, 584 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 585 FeatureFSqrt, FeatureFRE, FeatureFRES, 586 FeatureFRSQRTE, FeatureFRSQRTES, 587 FeatureSTFIWX, Feature64Bit, 588 FeatureMFTB, DeprecatedDST]>; 589def : ProcessorModel<"pwr5x", G5Model, 590 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 591 FeatureFSqrt, FeatureFRE, FeatureFRES, 592 FeatureFRSQRTE, FeatureFRSQRTES, 593 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 594 FeatureMFTB, DeprecatedDST]>; 595def : ProcessorModel<"pwr6", G5Model, 596 [DirectivePwr6, FeatureAltivec, 597 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 598 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 599 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 600 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 601 FeatureMFTB, DeprecatedDST]>; 602def : ProcessorModel<"pwr6x", G5Model, 603 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 604 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 605 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 606 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 607 FeatureFPRND, Feature64Bit, 608 FeatureMFTB, DeprecatedDST]>; 609def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 610def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 611def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 612def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>; 613// No scheduler model for future CPU. 614def : ProcessorModel<"future", NoSchedModel, 615 ProcessorFeatures.FutureFeatures>; 616def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 617 FeatureMFTB]>; 618def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 619 FeatureMFTB]>; 620def : ProcessorModel<"ppc64", G5Model, 621 [Directive64, FeatureAltivec, 622 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 623 FeatureFRSQRTE, FeatureSTFIWX, 624 Feature64Bit /*, Feature64BitRegs */, 625 FeatureMFTB]>; 626def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 627 628//===----------------------------------------------------------------------===// 629// Calling Conventions 630//===----------------------------------------------------------------------===// 631 632include "PPCCallingConv.td" 633 634def PPCInstrInfo : InstrInfo { 635 let isLittleEndianEncoding = 1; 636 637 // FIXME: Unset this when no longer needed! 638 let decodePositionallyEncodedOperands = 1; 639 640 let noNamedPositionallyEncodedOperands = 1; 641} 642 643def PPCAsmWriter : AsmWriter { 644 string AsmWriterClassName = "InstPrinter"; 645 int PassSubtarget = 1; 646 int Variant = 0; 647 bit isMCAsmWriter = 1; 648} 649 650def PPCAsmParser : AsmParser { 651 let ShouldEmitMatchRegisterName = 0; 652} 653 654def PPCAsmParserVariant : AsmParserVariant { 655 int Variant = 0; 656 657 // We do not use hard coded registers in asm strings. However, some 658 // InstAlias definitions use immediate literals. Set RegisterPrefix 659 // so that those are not misinterpreted as registers. 660 string RegisterPrefix = "%"; 661 string BreakCharacters = "."; 662} 663 664def PPC : Target { 665 // Information about the instructions. 666 let InstructionSet = PPCInstrInfo; 667 668 let AssemblyWriters = [PPCAsmWriter]; 669 let AssemblyParsers = [PPCAsmParser]; 670 let AssemblyParserVariants = [PPCAsmParserVariant]; 671 let AllowRegisterRenaming = 1; 672} 673 674//===----------------------------------------------------------------------===// 675// Pfm Counters 676//===----------------------------------------------------------------------===// 677 678include "PPCPfmCounters.td" 679