1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 61def FeatureModernAIXAs 62 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 63 "AIX system assembler is modern enough to support new mnes">; 64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 65 "Enable floating-point instructions">; 66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 67 "Enable 64-bit registers usage for ppc32 [beta]">; 68def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 69 "Use condition-register bits individually">; 70def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 71 "Enable classic FPU instructions", 72 [FeatureHardFloat]>; 73def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 74 "Enable Altivec instructions", 75 [FeatureFPU]>; 76def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 77 "Enable SPE instructions", 78 [FeatureHardFloat]>; 79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 80 "Enable Embedded Floating-Point APU 2 instructions", 81 [FeatureSPE]>; 82def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 83 "Enable the MFOCRF instruction">; 84def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 85 "Enable the fsqrt instruction", 86 [FeatureFPU]>; 87def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 88 "Enable the fcpsgn instruction", 89 [FeatureFPU]>; 90def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 91 "Enable the fre instruction", 92 [FeatureFPU]>; 93def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 94 "Enable the fres instruction", 95 [FeatureFPU]>; 96def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 97 "Enable the frsqrte instruction", 98 [FeatureFPU]>; 99def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 100 "Enable the frsqrtes instruction", 101 [FeatureFPU]>; 102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 103 "Assume higher precision reciprocal estimates">; 104def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 105 "Enable the stfiwx instruction", 106 [FeatureFPU]>; 107def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 108 "Enable the lfiwax instruction", 109 [FeatureFPU]>; 110def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 111 "Enable the fri[mnpz] instructions", 112 [FeatureFPU]>; 113def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 115 [FeatureFPU]>; 116def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 117 "Enable the isel instruction">; 118def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 119 "Enable the bpermd instruction">; 120def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 121 "Enable extended divide instructions">; 122def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 123 "Enable the ldbrx instruction">; 124def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 125 "Enable the cmpb instruction">; 126def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 127 "Enable icbt instruction">; 128def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 129 "Enable Book E instructions", 130 [FeatureICBT]>; 131def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 132 "Has only the msync instruction instead of sync", 133 [FeatureBookE]>; 134def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 135 "Enable E500/E500mc instructions">; 136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 137 "Enable secure plt mode">; 138def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 139 "Enable PPC 4xx instructions">; 140def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 141 "Enable PPC 6xx instructions">; 142def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 143 "Enable VSX instructions", 144 [FeatureAltivec]>; 145def FeatureTwoConstNR : 146 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 147 "Requires two constant Newton-Raphson computation">; 148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 149 "Enable POWER8 Altivec instructions", 150 [FeatureAltivec]>; 151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 152 "Enable POWER8 Crypto instructions", 153 [FeatureP8Altivec]>; 154def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 155 "Enable POWER8 vector instructions", 156 [FeatureVSX, FeatureP8Altivec]>; 157def FeatureDirectMove : 158 SubtargetFeature<"direct-move", "HasDirectMove", "true", 159 "Enable Power8 direct move instructions", 160 [FeatureVSX]>; 161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 162 "HasPartwordAtomics", "true", 163 "Enable l[bh]arx and st[bh]cx.">; 164def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics", 165 "HasQuadwordAtomics", "true", 166 "Enable lqarx and stqcx.">; 167def FeatureInvariantFunctionDescriptors : 168 SubtargetFeature<"invariant-function-descriptors", 169 "HasInvariantFunctionDescriptors", "true", 170 "Assume function descriptors are invariant">; 171def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 172 "Always use indirect calls">; 173def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 174 "Enable Hardware Transactional Memory instructions">; 175def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 176 "Implement mftb using the mfspr instruction">; 177def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 178 "Target supports instruction fusion">; 179def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 180 "HasAddiLoadFusion", "true", 181 "Power8 Addi-Load fusion", 182 [FeatureFusion]>; 183def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 184 "HasAddisLoadFusion", "true", 185 "Power8 Addis-Load fusion", 186 [FeatureFusion]>; 187def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 188 "Target supports store clustering", 189 [FeatureFusion]>; 190def FeatureArithAddFusion : 191 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true", 192 "Target supports Arithmetic Operations with Add fusion", 193 [FeatureFusion]>; 194def FeatureAddLogicalFusion : 195 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true", 196 "Target supports Add with Logical Operations fusion", 197 [FeatureFusion]>; 198def FeatureLogicalAddFusion : 199 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true", 200 "Target supports Logical with Add Operations fusion", 201 [FeatureFusion]>; 202def FeatureLogicalFusion : 203 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true", 204 "Target supports Logical Operations fusion", 205 [FeatureFusion]>; 206def FeatureSha3Fusion : 207 SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true", 208 "Target supports SHA3 assist fusion", 209 [FeatureFusion]>; 210def FeatureCompareFusion: 211 SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true", 212 "Target supports Comparison Operations fusion", 213 [FeatureFusion]>; 214def FeatureWideImmFusion: 215 SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true", 216 "Target supports Wide-Immediate fusion", 217 [FeatureFusion]>; 218def FeatureZeroMoveFusion: 219 SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true", 220 "Target supports move to SPR with branch fusion", 221 [FeatureFusion]>; 222def FeatureBack2BackFusion: 223 SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true", 224 "Target supports general back to back fusion", 225 [FeatureFusion]>; 226def FeatureUnalignedFloats : 227 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 228 "true", "CPU does not trap on unaligned FP access">; 229def FeaturePPCPreRASched: 230 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 231 "Use PowerPC pre-RA scheduling strategy">; 232def FeaturePPCPostRASched: 233 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 234 "Use PowerPC post-RA scheduling strategy">; 235def FeatureFloat128 : 236 SubtargetFeature<"float128", "HasFloat128", "true", 237 "Enable the __float128 data type for IEEE-754R Binary128.", 238 [FeatureVSX]>; 239def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 240 "POPCNTD_Fast", 241 "Enable the popcnt[dw] instructions">; 242// Note that for the a2 processor models we should not use popcnt[dw] by 243// default. These processors do support the instructions, but they're 244// microcoded, and the software emulation is about twice as fast. 245def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 246 "POPCNTD_Slow", 247 "Has slow popcnt[dw] instructions">; 248 249def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 250 "Treat vector data stream cache control instructions as deprecated">; 251 252def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06", 253 "true", 254 "Enable instructions in ISA 2.06.">; 255def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", 256 "true", 257 "Enable instructions in ISA 2.07.">; 258def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 259 "true", 260 "Enable instructions in ISA 3.0.", 261 [FeatureISA2_07]>; 262def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 263 "true", 264 "Enable instructions in ISA 3.1.", 265 [FeatureISA3_0]>; 266def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 267 "Enable POWER9 Altivec instructions", 268 [FeatureISA3_0, FeatureP8Altivec]>; 269def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 270 "Enable POWER9 vector instructions", 271 [FeatureISA3_0, FeatureP8Vector, 272 FeatureP9Altivec]>; 273def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 274 "true", 275 "Enable POWER10 vector instructions", 276 [FeatureISA3_1, FeatureP9Vector]>; 277// A separate feature for this even though it is equivalent to P9Vector 278// because this is a feature of the implementation rather than the architecture 279// and may go away with future CPU's. 280def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 281 "VectorsUseTwoUnits", 282 "true", 283 "Vectors use two units">; 284def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 285 "true", 286 "Enable prefixed instructions", 287 [FeatureISA3_0, FeatureP8Vector, 288 FeatureP9Altivec]>; 289def FeaturePCRelativeMemops : 290 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 291 "Enable PC relative Memory Ops", 292 [FeatureISA3_0, FeaturePrefixInstrs]>; 293def FeaturePairedVectorMemops: 294 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 295 "32Byte load and store instructions", 296 [FeatureISA3_0]>; 297def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 298 "Enable MMA instructions", 299 [FeatureP8Vector, FeatureP9Altivec, 300 FeaturePairedVectorMemops]>; 301def FeatureROPProtect : 302 SubtargetFeature<"rop-protect", "HasROPProtect", "true", 303 "Add ROP protect">; 304 305def FeaturePrivileged : 306 SubtargetFeature<"privileged", "HasPrivileged", "true", 307 "Add privileged instructions">; 308 309def FeaturePredictableSelectIsExpensive : 310 SubtargetFeature<"predictable-select-expensive", 311 "PredictableSelectIsExpensive", 312 "true", 313 "Prefer likely predicted branches over selects">; 314 315// Since new processors generally contain a superset of features of those that 316// came before them, the idea is to make implementations of new processors 317// less error prone and easier to read. 318// Namely: 319// list<SubtargetFeature> P8InheritableFeatures = ... 320// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 321// [ features that Power8 does not support but inheritable ] 322// list<SubtargetFeature> FutureProcessorSpecificFeatures = 323// [ features that Power8 does not support and not inheritable ] 324// list<SubtargetFeature> FutureProcessorInheritableFeatures = 325// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 326// list<SubtargetFeature> FutureProcessorFeatures = 327// !listconcat(FutureProcessorInheritableFeatures, 328// FutureProcessorSpecificFeatures) 329 330// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 331// well as providing a single point of definition if the feature set will be 332// used elsewhere. 333def ProcessorFeatures { 334 // Power7 335 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 336 FeatureAltivec, 337 FeatureVSX, 338 FeatureMFOCRF, 339 FeatureFCPSGN, 340 FeatureFSqrt, 341 FeatureFRE, 342 FeatureFRES, 343 FeatureFRSQRTE, 344 FeatureFRSQRTES, 345 FeatureRecipPrec, 346 FeatureSTFIWX, 347 FeatureLFIWAX, 348 FeatureFPRND, 349 FeatureFPCVT, 350 FeatureISEL, 351 FeaturePOPCNTD, 352 FeatureCMPB, 353 FeatureLDBRX, 354 Feature64Bit, 355 /* Feature64BitRegs, */ 356 FeatureBPERMD, 357 FeatureExtDiv, 358 FeatureMFTB, 359 DeprecatedDST, 360 FeatureTwoConstNR, 361 FeatureUnalignedFloats, 362 FeatureISA2_06]; 363 list<SubtargetFeature> P7SpecificFeatures = []; 364 list<SubtargetFeature> P7Features = 365 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 366 367 // Power8 368 list<SubtargetFeature> P8AdditionalFeatures = 369 [DirectivePwr8, 370 FeatureP8Altivec, 371 FeatureP8Vector, 372 FeatureP8Crypto, 373 FeatureHTM, 374 FeatureDirectMove, 375 FeatureICBT, 376 FeaturePartwordAtomic, 377 FeatureQuadwordAtomic, 378 FeaturePredictableSelectIsExpensive, 379 FeatureISA2_07 380 ]; 381 382 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 383 FeatureAddisLoadFusion]; 384 list<SubtargetFeature> P8InheritableFeatures = 385 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 386 list<SubtargetFeature> P8Features = 387 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 388 389 // Power9 390 list<SubtargetFeature> P9AdditionalFeatures = 391 [DirectivePwr9, 392 FeatureP9Altivec, 393 FeatureP9Vector, 394 FeaturePPCPreRASched, 395 FeaturePPCPostRASched, 396 FeatureISA3_0, 397 FeaturePredictableSelectIsExpensive 398 ]; 399 400 // Some features are unique to Power9 and there is no reason to assume 401 // they will be part of any future CPUs. One example is the narrower 402 // dispatch for vector operations than scalar ones. For the time being, 403 // this list also includes scheduling-related features since we do not have 404 // enough info to create custom scheduling strategies for future CPUs. 405 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 406 list<SubtargetFeature> P9InheritableFeatures = 407 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 408 list<SubtargetFeature> P9Features = 409 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 410 411 // Power10 412 // For P10 CPU we assume that all of the existing features from Power9 413 // still exist with the exception of those we know are Power9 specific. 414 list<SubtargetFeature> FusionFeatures = [ 415 FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion, 416 FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion, 417 ]; 418 list<SubtargetFeature> P10AdditionalFeatures = 419 !listconcat(FusionFeatures, [ 420 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 421 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 422 FeaturePairedVectorMemops]); 423 list<SubtargetFeature> P10SpecificFeatures = []; 424 list<SubtargetFeature> P10InheritableFeatures = 425 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 426 list<SubtargetFeature> P10Features = 427 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 428 429 // Future 430 // For future CPU we assume that all of the existing features from Power10 431 // still exist with the exception of those we know are Power10 specific. 432 list<SubtargetFeature> FutureAdditionalFeatures = []; 433 list<SubtargetFeature> FutureSpecificFeatures = []; 434 list<SubtargetFeature> FutureInheritableFeatures = 435 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 436 list<SubtargetFeature> FutureFeatures = 437 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 438} 439 440// Note: Future features to add when support is extended to more 441// recent ISA levels: 442// 443// DFP p6, p6x, p7 decimal floating-point instructions 444// POPCNTB p5 through p7 popcntb and related instructions 445 446//===----------------------------------------------------------------------===// 447// Classes used for relation maps. 448//===----------------------------------------------------------------------===// 449// RecFormRel - Filter class used to relate non-record-form instructions with 450// their record-form variants. 451class RecFormRel; 452 453// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 454// FMA instruction forms with their corresponding factor-killing forms. 455class AltVSXFMARel { 456 bit IsVSXFMAAlt = 0; 457} 458 459//===----------------------------------------------------------------------===// 460// Relation Map Definitions. 461//===----------------------------------------------------------------------===// 462 463def getRecordFormOpcode : InstrMapping { 464 let FilterClass = "RecFormRel"; 465 // Instructions with the same BaseName and Interpretation64Bit values 466 // form a row. 467 let RowFields = ["BaseName", "Interpretation64Bit"]; 468 // Instructions with the same RC value form a column. 469 let ColFields = ["RC"]; 470 // The key column are the non-record-form instructions. 471 let KeyCol = ["0"]; 472 // Value columns RC=1 473 let ValueCols = [["1"]]; 474} 475 476def getNonRecordFormOpcode : InstrMapping { 477 let FilterClass = "RecFormRel"; 478 // Instructions with the same BaseName and Interpretation64Bit values 479 // form a row. 480 let RowFields = ["BaseName", "Interpretation64Bit"]; 481 // Instructions with the same RC value form a column. 482 let ColFields = ["RC"]; 483 // The key column are the record-form instructions. 484 let KeyCol = ["1"]; 485 // Value columns are RC=0 486 let ValueCols = [["0"]]; 487} 488 489def getAltVSXFMAOpcode : InstrMapping { 490 let FilterClass = "AltVSXFMARel"; 491 // Instructions with the same BaseName value form a row. 492 let RowFields = ["BaseName"]; 493 // Instructions with the same IsVSXFMAAlt value form a column. 494 let ColFields = ["IsVSXFMAAlt"]; 495 // The key column are the (default) addend-killing instructions. 496 let KeyCol = ["0"]; 497 // Value columns IsVSXFMAAlt=1 498 let ValueCols = [["1"]]; 499} 500 501//===----------------------------------------------------------------------===// 502// Register File Description 503//===----------------------------------------------------------------------===// 504 505include "PPCRegisterInfo.td" 506include "PPCSchedule.td" 507include "GISel/PPCRegisterBanks.td" 508 509//===----------------------------------------------------------------------===// 510// PowerPC processors supported. 511// 512 513def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 514 FeatureMFTB]>; 515def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 516 FeatureFRES, FeatureFRSQRTE, 517 FeatureICBT, FeatureBookE, 518 FeatureMSYNC, FeatureMFTB]>; 519def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 520 FeatureFRES, FeatureFRSQRTE, 521 FeatureICBT, FeatureBookE, 522 FeatureMSYNC, FeatureMFTB]>; 523def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 524def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 525 FeatureMFTB]>; 526def : Processor<"603", G3Itineraries, [Directive603, 527 FeatureFRES, FeatureFRSQRTE, 528 FeatureMFTB]>; 529def : Processor<"603e", G3Itineraries, [Directive603, 530 FeatureFRES, FeatureFRSQRTE, 531 FeatureMFTB]>; 532def : Processor<"603ev", G3Itineraries, [Directive603, 533 FeatureFRES, FeatureFRSQRTE, 534 FeatureMFTB]>; 535def : Processor<"604", G3Itineraries, [Directive604, 536 FeatureFRES, FeatureFRSQRTE, 537 FeatureMFTB]>; 538def : Processor<"604e", G3Itineraries, [Directive604, 539 FeatureFRES, FeatureFRSQRTE, 540 FeatureMFTB]>; 541def : Processor<"620", G3Itineraries, [Directive620, 542 FeatureFRES, FeatureFRSQRTE, 543 FeatureMFTB]>; 544def : Processor<"750", G4Itineraries, [Directive750, 545 FeatureFRES, FeatureFRSQRTE, 546 FeatureMFTB]>; 547def : Processor<"g3", G3Itineraries, [Directive750, 548 FeatureFRES, FeatureFRSQRTE, 549 FeatureMFTB]>; 550def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 551 FeatureFRES, FeatureFRSQRTE, 552 FeatureMFTB]>; 553def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 554 FeatureFRES, FeatureFRSQRTE, 555 FeatureMFTB]>; 556def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 557 FeatureFRES, FeatureFRSQRTE, 558 FeatureMFTB]>; 559def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 560 FeatureFRES, FeatureFRSQRTE, 561 FeatureMFTB]>; 562 563def : ProcessorModel<"970", G5Model, 564 [Directive970, FeatureAltivec, 565 FeatureMFOCRF, FeatureFSqrt, 566 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 567 Feature64Bit /*, Feature64BitRegs */, 568 FeatureMFTB]>; 569def : ProcessorModel<"g5", G5Model, 570 [Directive970, FeatureAltivec, 571 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 572 FeatureFRES, FeatureFRSQRTE, 573 Feature64Bit /*, Feature64BitRegs */, 574 FeatureMFTB, DeprecatedDST]>; 575def : ProcessorModel<"e500", PPCE500Model, 576 [DirectiveE500, 577 FeatureICBT, FeatureBookE, 578 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 579def : ProcessorModel<"e500mc", PPCE500mcModel, 580 [DirectiveE500mc, 581 FeatureSTFIWX, FeatureICBT, FeatureBookE, 582 FeatureISEL, FeatureMFTB]>; 583def : ProcessorModel<"e5500", PPCE5500Model, 584 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 585 FeatureSTFIWX, FeatureICBT, FeatureBookE, 586 FeatureISEL, FeatureMFTB]>; 587def : ProcessorModel<"a2", PPCA2Model, 588 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 589 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 590 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 591 FeatureSTFIWX, FeatureLFIWAX, 592 FeatureFPRND, FeatureFPCVT, FeatureISEL, 593 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 594 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 595def : ProcessorModel<"pwr3", G5Model, 596 [DirectivePwr3, FeatureAltivec, 597 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 598 FeatureSTFIWX, Feature64Bit]>; 599def : ProcessorModel<"pwr4", G5Model, 600 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 601 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 602 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 603def : ProcessorModel<"pwr5", G5Model, 604 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 605 FeatureFSqrt, FeatureFRE, FeatureFRES, 606 FeatureFRSQRTE, FeatureFRSQRTES, 607 FeatureSTFIWX, Feature64Bit, 608 FeatureMFTB, DeprecatedDST]>; 609def : ProcessorModel<"pwr5x", G5Model, 610 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 611 FeatureFSqrt, FeatureFRE, FeatureFRES, 612 FeatureFRSQRTE, FeatureFRSQRTES, 613 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 614 FeatureMFTB, DeprecatedDST]>; 615def : ProcessorModel<"pwr6", G5Model, 616 [DirectivePwr6, FeatureAltivec, 617 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 618 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 619 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 620 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 621 FeatureMFTB, DeprecatedDST]>; 622def : ProcessorModel<"pwr6x", G5Model, 623 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 624 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 625 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 626 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 627 FeatureFPRND, Feature64Bit, 628 FeatureMFTB, DeprecatedDST]>; 629def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 630def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 631def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 632def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>; 633// No scheduler model for future CPU. 634def : ProcessorModel<"future", NoSchedModel, 635 ProcessorFeatures.FutureFeatures>; 636def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 637 FeatureMFTB]>; 638def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 639 FeatureMFTB]>; 640def : ProcessorModel<"ppc64", G5Model, 641 [Directive64, FeatureAltivec, 642 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 643 FeatureFRSQRTE, FeatureSTFIWX, 644 Feature64Bit /*, Feature64BitRegs */, 645 FeatureMFTB]>; 646def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 647 648//===----------------------------------------------------------------------===// 649// Calling Conventions 650//===----------------------------------------------------------------------===// 651 652include "PPCCallingConv.td" 653 654def PPCInstrInfo : InstrInfo { 655 let isLittleEndianEncoding = 1; 656 657 // FIXME: Unset this when no longer needed! 658 let decodePositionallyEncodedOperands = 1; 659 660 let noNamedPositionallyEncodedOperands = 1; 661} 662 663def PPCAsmWriter : AsmWriter { 664 string AsmWriterClassName = "InstPrinter"; 665 int PassSubtarget = 1; 666 int Variant = 0; 667 bit isMCAsmWriter = 1; 668} 669 670def PPCAsmParser : AsmParser { 671 let ShouldEmitMatchRegisterName = 0; 672} 673 674def PPCAsmParserVariant : AsmParserVariant { 675 int Variant = 0; 676 677 // We do not use hard coded registers in asm strings. However, some 678 // InstAlias definitions use immediate literals. Set RegisterPrefix 679 // so that those are not misinterpreted as registers. 680 string RegisterPrefix = "%"; 681 string BreakCharacters = "."; 682} 683 684def PPC : Target { 685 // Information about the instructions. 686 let InstructionSet = PPCInstrInfo; 687 688 let AssemblyWriters = [PPCAsmWriter]; 689 let AssemblyParsers = [PPCAsmParser]; 690 let AssemblyParserVariants = [PPCAsmParserVariant]; 691 let AllowRegisterRenaming = 1; 692} 693 694//===----------------------------------------------------------------------===// 695// Pfm Counters 696//===----------------------------------------------------------------------===// 697 698include "PPCPfmCounters.td" 699