1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 61def FeatureModernAIXAs 62 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 63 "AIX system assembler is modern enough to support new mnes">; 64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 65 "Enable floating-point instructions">; 66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 67 "Enable 64-bit registers usage for ppc32 [beta]">; 68def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 69 "Use condition-register bits individually">; 70def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 71 "Enable classic FPU instructions", 72 [FeatureHardFloat]>; 73def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 74 "Enable Altivec instructions", 75 [FeatureFPU]>; 76def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 77 "Enable SPE instructions", 78 [FeatureHardFloat]>; 79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 80 "Enable Embedded Floating-Point APU 2 instructions", 81 [FeatureSPE]>; 82def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 83 "Enable the MFOCRF instruction">; 84def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 85 "Enable the fsqrt instruction", 86 [FeatureFPU]>; 87def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 88 "Enable the fcpsgn instruction", 89 [FeatureFPU]>; 90def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 91 "Enable the fre instruction", 92 [FeatureFPU]>; 93def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 94 "Enable the fres instruction", 95 [FeatureFPU]>; 96def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 97 "Enable the frsqrte instruction", 98 [FeatureFPU]>; 99def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 100 "Enable the frsqrtes instruction", 101 [FeatureFPU]>; 102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 103 "Assume higher precision reciprocal estimates">; 104def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 105 "Enable the stfiwx instruction", 106 [FeatureFPU]>; 107def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 108 "Enable the lfiwax instruction", 109 [FeatureFPU]>; 110def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 111 "Enable the fri[mnpz] instructions", 112 [FeatureFPU]>; 113def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 115 [FeatureFPU]>; 116def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 117 "Enable the isel instruction">; 118def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 119 "Enable the bpermd instruction">; 120def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 121 "Enable extended divide instructions">; 122def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 123 "Enable the ldbrx instruction">; 124def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 125 "Enable the cmpb instruction">; 126def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 127 "Enable icbt instruction">; 128def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 129 "Enable Book E instructions", 130 [FeatureICBT]>; 131def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 132 "Has only the msync instruction instead of sync", 133 [FeatureBookE]>; 134def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 135 "Enable E500/E500mc instructions">; 136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 137 "Enable secure plt mode">; 138def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 139 "Enable PPC 4xx instructions">; 140def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 141 "Enable PPC 6xx instructions">; 142def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 143 "Enable VSX instructions", 144 [FeatureAltivec]>; 145def FeatureTwoConstNR : 146 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 147 "Requires two constant Newton-Raphson computation">; 148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 149 "Enable POWER8 Altivec instructions", 150 [FeatureAltivec]>; 151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 152 "Enable POWER8 Crypto instructions", 153 [FeatureP8Altivec]>; 154def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 155 "Enable POWER8 vector instructions", 156 [FeatureVSX, FeatureP8Altivec]>; 157def FeatureDirectMove : 158 SubtargetFeature<"direct-move", "HasDirectMove", "true", 159 "Enable Power8 direct move instructions", 160 [FeatureVSX]>; 161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 162 "HasPartwordAtomics", "true", 163 "Enable l[bh]arx and st[bh]cx.">; 164def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics", 165 "HasQuadwordAtomics", "true", 166 "Enable lqarx and stqcx.">; 167def FeatureInvariantFunctionDescriptors : 168 SubtargetFeature<"invariant-function-descriptors", 169 "HasInvariantFunctionDescriptors", "true", 170 "Assume function descriptors are invariant">; 171def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 172 "Always use indirect calls">; 173def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 174 "Enable Hardware Transactional Memory instructions">; 175def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 176 "Implement mftb using the mfspr instruction">; 177def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 178 "Target supports instruction fusion">; 179def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 180 "HasAddiLoadFusion", "true", 181 "Power8 Addi-Load fusion", 182 [FeatureFusion]>; 183def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 184 "HasAddisLoadFusion", "true", 185 "Power8 Addis-Load fusion", 186 [FeatureFusion]>; 187def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 188 "Target supports store clustering", 189 [FeatureFusion]>; 190def FeatureArithAddFusion : 191 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true", 192 "Target supports Arithmetic Operations with Add fusion", 193 [FeatureFusion]>; 194def FeatureAddLogicalFusion : 195 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true", 196 "Target supports Add with Logical Operations fusion", 197 [FeatureFusion]>; 198def FeatureLogicalAddFusion : 199 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true", 200 "Target supports Logical with Add Operations fusion", 201 [FeatureFusion]>; 202def FeatureLogicalFusion : 203 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true", 204 "Target supports Logical Operations fusion", 205 [FeatureFusion]>; 206def FeatureSha3Fusion : 207 SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true", 208 "Target supports SHA3 assist fusion", 209 [FeatureFusion]>; 210def FeatureCompareFusion: 211 SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true", 212 "Target supports Comparison Operations fusion", 213 [FeatureFusion]>; 214def FeatureWideImmFusion: 215 SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true", 216 "Target supports Wide-Immediate fusion", 217 [FeatureFusion]>; 218def FeatureZeroMoveFusion: 219 SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true", 220 "Target supports move to SPR with branch fusion", 221 [FeatureFusion]>; 222def FeatureBack2BackFusion: 223 SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true", 224 "Target supports general back to back fusion", 225 [FeatureFusion]>; 226def FeatureUnalignedFloats : 227 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 228 "true", "CPU does not trap on unaligned FP access">; 229def FeaturePPCPreRASched: 230 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 231 "Use PowerPC pre-RA scheduling strategy">; 232def FeaturePPCPostRASched: 233 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 234 "Use PowerPC post-RA scheduling strategy">; 235def FeatureFloat128 : 236 SubtargetFeature<"float128", "HasFloat128", "true", 237 "Enable the __float128 data type for IEEE-754R Binary128.", 238 [FeatureVSX]>; 239def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 240 "POPCNTD_Fast", 241 "Enable the popcnt[dw] instructions">; 242// Note that for the a2 processor models we should not use popcnt[dw] by 243// default. These processors do support the instructions, but they're 244// microcoded, and the software emulation is about twice as fast. 245def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 246 "POPCNTD_Slow", 247 "Has slow popcnt[dw] instructions">; 248 249def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 250 "Treat vector data stream cache control instructions as deprecated">; 251 252def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06", 253 "true", 254 "Enable instructions in ISA 2.06.">; 255def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", 256 "true", 257 "Enable instructions in ISA 2.07.">; 258def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 259 "true", 260 "Enable instructions in ISA 3.0.", 261 [FeatureISA2_07]>; 262def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 263 "true", 264 "Enable instructions in ISA 3.1.", 265 [FeatureISA3_0]>; 266def FeatureISAFuture : SubtargetFeature<"isa-future-instructions", 267 "IsISAFuture", "true", 268 "Enable instructions for Future ISA.", 269 [FeatureISA3_1]>; 270def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 271 "Enable POWER9 Altivec instructions", 272 [FeatureISA3_0, FeatureP8Altivec]>; 273def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 274 "Enable POWER9 vector instructions", 275 [FeatureISA3_0, FeatureP8Vector, 276 FeatureP9Altivec]>; 277def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 278 "true", 279 "Enable POWER10 vector instructions", 280 [FeatureISA3_1, FeatureP9Vector]>; 281// A separate feature for this even though it is equivalent to P9Vector 282// because this is a feature of the implementation rather than the architecture 283// and may go away with future CPU's. 284def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 285 "VectorsUseTwoUnits", 286 "true", 287 "Vectors use two units">; 288def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 289 "true", 290 "Enable prefixed instructions", 291 [FeatureISA3_0, FeatureP8Vector, 292 FeatureP9Altivec]>; 293def FeaturePCRelativeMemops : 294 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 295 "Enable PC relative Memory Ops", 296 [FeatureISA3_0, FeaturePrefixInstrs]>; 297def FeaturePairedVectorMemops: 298 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 299 "32Byte load and store instructions", 300 [FeatureISA3_0]>; 301def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 302 "Enable MMA instructions", 303 [FeatureP8Vector, FeatureP9Altivec, 304 FeaturePairedVectorMemops]>; 305def FeatureROPProtect : 306 SubtargetFeature<"rop-protect", "HasROPProtect", "true", 307 "Add ROP protect">; 308 309def FeaturePrivileged : 310 SubtargetFeature<"privileged", "HasPrivileged", "true", 311 "Add privileged instructions">; 312 313def FeaturePredictableSelectIsExpensive : 314 SubtargetFeature<"predictable-select-expensive", 315 "PredictableSelectIsExpensive", 316 "true", 317 "Prefer likely predicted branches over selects">; 318 319// Since new processors generally contain a superset of features of those that 320// came before them, the idea is to make implementations of new processors 321// less error prone and easier to read. 322// Namely: 323// list<SubtargetFeature> P8InheritableFeatures = ... 324// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 325// [ features that Power8 does not support but inheritable ] 326// list<SubtargetFeature> FutureProcessorSpecificFeatures = 327// [ features that Power8 does not support and not inheritable ] 328// list<SubtargetFeature> FutureProcessorInheritableFeatures = 329// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 330// list<SubtargetFeature> FutureProcessorFeatures = 331// !listconcat(FutureProcessorInheritableFeatures, 332// FutureProcessorSpecificFeatures) 333 334// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 335// well as providing a single point of definition if the feature set will be 336// used elsewhere. 337def ProcessorFeatures { 338 // Power7 339 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 340 FeatureAltivec, 341 FeatureVSX, 342 FeatureMFOCRF, 343 FeatureFCPSGN, 344 FeatureFSqrt, 345 FeatureFRE, 346 FeatureFRES, 347 FeatureFRSQRTE, 348 FeatureFRSQRTES, 349 FeatureRecipPrec, 350 FeatureSTFIWX, 351 FeatureLFIWAX, 352 FeatureFPRND, 353 FeatureFPCVT, 354 FeatureISEL, 355 FeaturePOPCNTD, 356 FeatureCMPB, 357 FeatureLDBRX, 358 Feature64Bit, 359 /* Feature64BitRegs, */ 360 FeatureBPERMD, 361 FeatureExtDiv, 362 FeatureMFTB, 363 DeprecatedDST, 364 FeatureTwoConstNR, 365 FeatureUnalignedFloats, 366 FeatureISA2_06]; 367 list<SubtargetFeature> P7SpecificFeatures = []; 368 list<SubtargetFeature> P7Features = 369 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 370 371 // Power8 372 list<SubtargetFeature> P8AdditionalFeatures = 373 [DirectivePwr8, 374 FeatureP8Altivec, 375 FeatureP8Vector, 376 FeatureP8Crypto, 377 FeatureHTM, 378 FeatureDirectMove, 379 FeatureICBT, 380 FeaturePartwordAtomic, 381 FeatureQuadwordAtomic, 382 FeaturePredictableSelectIsExpensive, 383 FeatureISA2_07, 384 FeatureCRBits 385 ]; 386 387 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 388 FeatureAddisLoadFusion]; 389 list<SubtargetFeature> P8InheritableFeatures = 390 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 391 list<SubtargetFeature> P8Features = 392 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 393 394 // Power9 395 list<SubtargetFeature> P9AdditionalFeatures = 396 [DirectivePwr9, 397 FeatureP9Altivec, 398 FeatureP9Vector, 399 FeaturePPCPreRASched, 400 FeaturePPCPostRASched, 401 FeatureISA3_0, 402 FeaturePredictableSelectIsExpensive 403 ]; 404 405 // Some features are unique to Power9 and there is no reason to assume 406 // they will be part of any future CPUs. One example is the narrower 407 // dispatch for vector operations than scalar ones. For the time being, 408 // this list also includes scheduling-related features since we do not have 409 // enough info to create custom scheduling strategies for future CPUs. 410 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 411 list<SubtargetFeature> P9InheritableFeatures = 412 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 413 list<SubtargetFeature> P9Features = 414 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 415 416 // Power10 417 // For P10 CPU we assume that all of the existing features from Power9 418 // still exist with the exception of those we know are Power9 specific. 419 list<SubtargetFeature> FusionFeatures = [ 420 FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion, 421 FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion, 422 ]; 423 list<SubtargetFeature> P10AdditionalFeatures = 424 !listconcat(FusionFeatures, [ 425 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 426 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 427 FeaturePairedVectorMemops]); 428 list<SubtargetFeature> P10SpecificFeatures = []; 429 list<SubtargetFeature> P10InheritableFeatures = 430 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 431 list<SubtargetFeature> P10Features = 432 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 433 434 // Future 435 // For future CPU we assume that all of the existing features from Power10 436 // still exist with the exception of those we know are Power10 specific. 437 list<SubtargetFeature> FutureAdditionalFeatures = [FeatureISAFuture]; 438 list<SubtargetFeature> FutureSpecificFeatures = []; 439 list<SubtargetFeature> FutureInheritableFeatures = 440 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 441 list<SubtargetFeature> FutureFeatures = 442 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 443} 444 445// Note: Future features to add when support is extended to more 446// recent ISA levels: 447// 448// DFP p6, p6x, p7 decimal floating-point instructions 449// POPCNTB p5 through p7 popcntb and related instructions 450 451//===----------------------------------------------------------------------===// 452// Classes used for relation maps. 453//===----------------------------------------------------------------------===// 454// RecFormRel - Filter class used to relate non-record-form instructions with 455// their record-form variants. 456class RecFormRel; 457 458// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 459// FMA instruction forms with their corresponding factor-killing forms. 460class AltVSXFMARel { 461 bit IsVSXFMAAlt = 0; 462} 463 464//===----------------------------------------------------------------------===// 465// Relation Map Definitions. 466//===----------------------------------------------------------------------===// 467 468def getRecordFormOpcode : InstrMapping { 469 let FilterClass = "RecFormRel"; 470 // Instructions with the same BaseName and Interpretation64Bit values 471 // form a row. 472 let RowFields = ["BaseName", "Interpretation64Bit"]; 473 // Instructions with the same RC value form a column. 474 let ColFields = ["RC"]; 475 // The key column are the non-record-form instructions. 476 let KeyCol = ["0"]; 477 // Value columns RC=1 478 let ValueCols = [["1"]]; 479} 480 481def getNonRecordFormOpcode : InstrMapping { 482 let FilterClass = "RecFormRel"; 483 // Instructions with the same BaseName and Interpretation64Bit values 484 // form a row. 485 let RowFields = ["BaseName", "Interpretation64Bit"]; 486 // Instructions with the same RC value form a column. 487 let ColFields = ["RC"]; 488 // The key column are the record-form instructions. 489 let KeyCol = ["1"]; 490 // Value columns are RC=0 491 let ValueCols = [["0"]]; 492} 493 494def getAltVSXFMAOpcode : InstrMapping { 495 let FilterClass = "AltVSXFMARel"; 496 // Instructions with the same BaseName value form a row. 497 let RowFields = ["BaseName"]; 498 // Instructions with the same IsVSXFMAAlt value form a column. 499 let ColFields = ["IsVSXFMAAlt"]; 500 // The key column are the (default) addend-killing instructions. 501 let KeyCol = ["0"]; 502 // Value columns IsVSXFMAAlt=1 503 let ValueCols = [["1"]]; 504} 505 506//===----------------------------------------------------------------------===// 507// Register File Description 508//===----------------------------------------------------------------------===// 509 510include "PPCRegisterInfo.td" 511include "PPCSchedule.td" 512include "GISel/PPCRegisterBanks.td" 513 514//===----------------------------------------------------------------------===// 515// PowerPC processors supported. 516// 517 518def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 519 FeatureMFTB]>; 520def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 521 FeatureFRES, FeatureFRSQRTE, 522 FeatureICBT, FeatureBookE, 523 FeatureMSYNC, FeatureMFTB]>; 524def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 525 FeatureFRES, FeatureFRSQRTE, 526 FeatureICBT, FeatureBookE, 527 FeatureMSYNC, FeatureMFTB]>; 528def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 529def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 530 FeatureMFTB]>; 531def : Processor<"603", G3Itineraries, [Directive603, 532 FeatureFRES, FeatureFRSQRTE, 533 FeatureMFTB]>; 534def : Processor<"603e", G3Itineraries, [Directive603, 535 FeatureFRES, FeatureFRSQRTE, 536 FeatureMFTB]>; 537def : Processor<"603ev", G3Itineraries, [Directive603, 538 FeatureFRES, FeatureFRSQRTE, 539 FeatureMFTB]>; 540def : Processor<"604", G3Itineraries, [Directive604, 541 FeatureFRES, FeatureFRSQRTE, 542 FeatureMFTB]>; 543def : Processor<"604e", G3Itineraries, [Directive604, 544 FeatureFRES, FeatureFRSQRTE, 545 FeatureMFTB]>; 546def : Processor<"620", G3Itineraries, [Directive620, 547 FeatureFRES, FeatureFRSQRTE, 548 FeatureMFTB]>; 549def : Processor<"750", G4Itineraries, [Directive750, 550 FeatureFRES, FeatureFRSQRTE, 551 FeatureMFTB]>; 552def : Processor<"g3", G3Itineraries, [Directive750, 553 FeatureFRES, FeatureFRSQRTE, 554 FeatureMFTB]>; 555def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 556 FeatureFRES, FeatureFRSQRTE, 557 FeatureMFTB]>; 558def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 559 FeatureFRES, FeatureFRSQRTE, 560 FeatureMFTB]>; 561def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 562 FeatureFRES, FeatureFRSQRTE, 563 FeatureMFTB]>; 564def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 565 FeatureFRES, FeatureFRSQRTE, 566 FeatureMFTB]>; 567 568def : ProcessorModel<"970", G5Model, 569 [Directive970, FeatureAltivec, 570 FeatureMFOCRF, FeatureFSqrt, 571 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 572 Feature64Bit /*, Feature64BitRegs */, 573 FeatureMFTB]>; 574def : ProcessorModel<"g5", G5Model, 575 [Directive970, FeatureAltivec, 576 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 577 FeatureFRES, FeatureFRSQRTE, 578 Feature64Bit /*, Feature64BitRegs */, 579 FeatureMFTB, DeprecatedDST]>; 580def : ProcessorModel<"e500", PPCE500Model, 581 [DirectiveE500, 582 FeatureICBT, FeatureBookE, 583 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 584def : ProcessorModel<"e500mc", PPCE500mcModel, 585 [DirectiveE500mc, 586 FeatureSTFIWX, FeatureICBT, FeatureBookE, 587 FeatureISEL, FeatureMFTB]>; 588def : ProcessorModel<"e5500", PPCE5500Model, 589 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 590 FeatureSTFIWX, FeatureICBT, FeatureBookE, 591 FeatureISEL, FeatureMFTB]>; 592def : ProcessorModel<"a2", PPCA2Model, 593 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 594 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 595 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 596 FeatureSTFIWX, FeatureLFIWAX, 597 FeatureFPRND, FeatureFPCVT, FeatureISEL, 598 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 599 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB, 600 FeatureISA2_06]>; 601def : ProcessorModel<"pwr3", G5Model, 602 [DirectivePwr3, FeatureAltivec, 603 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 604 FeatureSTFIWX, Feature64Bit]>; 605def : ProcessorModel<"pwr4", G5Model, 606 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 607 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 608 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 609def : ProcessorModel<"pwr5", G5Model, 610 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 611 FeatureFSqrt, FeatureFRE, FeatureFRES, 612 FeatureFRSQRTE, FeatureFRSQRTES, 613 FeatureSTFIWX, Feature64Bit, 614 FeatureMFTB, DeprecatedDST]>; 615def : ProcessorModel<"pwr5x", G5Model, 616 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 617 FeatureFSqrt, FeatureFRE, FeatureFRES, 618 FeatureFRSQRTE, FeatureFRSQRTES, 619 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 620 FeatureMFTB, DeprecatedDST]>; 621def : ProcessorModel<"pwr6", G5Model, 622 [DirectivePwr6, FeatureAltivec, 623 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 624 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 625 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 626 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 627 FeatureMFTB, DeprecatedDST]>; 628def : ProcessorModel<"pwr6x", G5Model, 629 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 630 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 631 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 632 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 633 FeatureFPRND, Feature64Bit, 634 FeatureMFTB, DeprecatedDST]>; 635def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 636def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 637def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 638def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>; 639// No scheduler model for future CPU. 640def : ProcessorModel<"future", NoSchedModel, 641 ProcessorFeatures.FutureFeatures>; 642def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 643 FeatureMFTB]>; 644def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 645 FeatureMFTB]>; 646def : ProcessorModel<"ppc64", G5Model, 647 [Directive64, FeatureAltivec, 648 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 649 FeatureFRSQRTE, FeatureSTFIWX, 650 Feature64Bit /*, Feature64BitRegs */, 651 FeatureMFTB]>; 652def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 653 654//===----------------------------------------------------------------------===// 655// Calling Conventions 656//===----------------------------------------------------------------------===// 657 658include "PPCCallingConv.td" 659 660def PPCInstrInfo : InstrInfo { 661 let isLittleEndianEncoding = 1; 662 663 // FIXME: Unset this when no longer needed! 664 let decodePositionallyEncodedOperands = 1; 665 666 let noNamedPositionallyEncodedOperands = 1; 667} 668 669def PPCAsmWriter : AsmWriter { 670 string AsmWriterClassName = "InstPrinter"; 671 int PassSubtarget = 1; 672 int Variant = 0; 673 bit isMCAsmWriter = 1; 674} 675 676def PPCAsmParser : AsmParser { 677 let ShouldEmitMatchRegisterName = 0; 678} 679 680def PPCAsmParserVariant : AsmParserVariant { 681 int Variant = 0; 682 683 // We do not use hard coded registers in asm strings. However, some 684 // InstAlias definitions use immediate literals. Set RegisterPrefix 685 // so that those are not misinterpreted as registers. 686 string RegisterPrefix = "%"; 687 string BreakCharacters = "."; 688} 689 690def PPC : Target { 691 // Information about the instructions. 692 let InstructionSet = PPCInstrInfo; 693 694 let AssemblyWriters = [PPCAsmWriter]; 695 let AssemblyParsers = [PPCAsmParser]; 696 let AssemblyParserVariants = [PPCAsmParserVariant]; 697 let AllowRegisterRenaming = 1; 698} 699 700//===----------------------------------------------------------------------===// 701// Pfm Counters 702//===----------------------------------------------------------------------===// 703 704include "PPCPfmCounters.td" 705