1*0b57cec5SDimitry Andric //===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file describes the PowerPC branch predicates. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCPREDICATES_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCPREDICATES_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric // GCC #defines PPC on Linux but we use it as our namespace name 17*0b57cec5SDimitry Andric #undef PPC 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric // Generated files will use "namespace PPC". To avoid symbol clash, 20*0b57cec5SDimitry Andric // undefine PPC here. PPC may be predefined on some hosts. 21*0b57cec5SDimitry Andric #undef PPC 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric namespace llvm { 24*0b57cec5SDimitry Andric namespace PPC { 25*0b57cec5SDimitry Andric /// Predicate - These are "(BI << 5) | BO" for various predicates. 26*0b57cec5SDimitry Andric enum Predicate { 27*0b57cec5SDimitry Andric PRED_LT = (0 << 5) | 12, 28*0b57cec5SDimitry Andric PRED_LE = (1 << 5) | 4, 29*0b57cec5SDimitry Andric PRED_EQ = (2 << 5) | 12, 30*0b57cec5SDimitry Andric PRED_GE = (0 << 5) | 4, 31*0b57cec5SDimitry Andric PRED_GT = (1 << 5) | 12, 32*0b57cec5SDimitry Andric PRED_NE = (2 << 5) | 4, 33*0b57cec5SDimitry Andric PRED_UN = (3 << 5) | 12, 34*0b57cec5SDimitry Andric PRED_NU = (3 << 5) | 4, 35*0b57cec5SDimitry Andric PRED_LT_MINUS = (0 << 5) | 14, 36*0b57cec5SDimitry Andric PRED_LE_MINUS = (1 << 5) | 6, 37*0b57cec5SDimitry Andric PRED_EQ_MINUS = (2 << 5) | 14, 38*0b57cec5SDimitry Andric PRED_GE_MINUS = (0 << 5) | 6, 39*0b57cec5SDimitry Andric PRED_GT_MINUS = (1 << 5) | 14, 40*0b57cec5SDimitry Andric PRED_NE_MINUS = (2 << 5) | 6, 41*0b57cec5SDimitry Andric PRED_UN_MINUS = (3 << 5) | 14, 42*0b57cec5SDimitry Andric PRED_NU_MINUS = (3 << 5) | 6, 43*0b57cec5SDimitry Andric PRED_LT_PLUS = (0 << 5) | 15, 44*0b57cec5SDimitry Andric PRED_LE_PLUS = (1 << 5) | 7, 45*0b57cec5SDimitry Andric PRED_EQ_PLUS = (2 << 5) | 15, 46*0b57cec5SDimitry Andric PRED_GE_PLUS = (0 << 5) | 7, 47*0b57cec5SDimitry Andric PRED_GT_PLUS = (1 << 5) | 15, 48*0b57cec5SDimitry Andric PRED_NE_PLUS = (2 << 5) | 7, 49*0b57cec5SDimitry Andric PRED_UN_PLUS = (3 << 5) | 15, 50*0b57cec5SDimitry Andric PRED_NU_PLUS = (3 << 5) | 7, 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric // SPE scalar compare instructions always set the GT bit. 53*0b57cec5SDimitry Andric PRED_SPE = PRED_GT, 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric // When dealing with individual condition-register bits, we have simple set 56*0b57cec5SDimitry Andric // and unset predicates. 57*0b57cec5SDimitry Andric PRED_BIT_SET = 1024, 58*0b57cec5SDimitry Andric PRED_BIT_UNSET = 1025 59*0b57cec5SDimitry Andric }; 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andric // Bit for branch taken (plus) or not-taken (minus) hint 62*0b57cec5SDimitry Andric enum BranchHintBit { 63*0b57cec5SDimitry Andric BR_NO_HINT = 0x0, 64*0b57cec5SDimitry Andric BR_NONTAKEN_HINT = 0x2, 65*0b57cec5SDimitry Andric BR_TAKEN_HINT = 0x3, 66*0b57cec5SDimitry Andric BR_HINT_MASK = 0X3 67*0b57cec5SDimitry Andric }; 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric /// Invert the specified predicate. != -> ==, < -> >=. 70*0b57cec5SDimitry Andric Predicate InvertPredicate(Predicate Opcode); 71*0b57cec5SDimitry Andric 72*0b57cec5SDimitry Andric /// Assume the condition register is set by MI(a,b), return the predicate if 73*0b57cec5SDimitry Andric /// we modify the instructions such that condition register is set by MI(b,a). 74*0b57cec5SDimitry Andric Predicate getSwappedPredicate(Predicate Opcode); 75*0b57cec5SDimitry Andric 76*0b57cec5SDimitry Andric /// Return the condition without hint bits. getPredicateCondition(Predicate Opcode)77*0b57cec5SDimitry Andric inline unsigned getPredicateCondition(Predicate Opcode) { 78*0b57cec5SDimitry Andric return (unsigned)(Opcode & ~BR_HINT_MASK); 79*0b57cec5SDimitry Andric } 80*0b57cec5SDimitry Andric 81*0b57cec5SDimitry Andric /// Return the hint bits of the predicate. getPredicateHint(Predicate Opcode)82*0b57cec5SDimitry Andric inline unsigned getPredicateHint(Predicate Opcode) { 83*0b57cec5SDimitry Andric return (unsigned)(Opcode & BR_HINT_MASK); 84*0b57cec5SDimitry Andric } 85*0b57cec5SDimitry Andric 86*0b57cec5SDimitry Andric /// Return predicate consisting of specified condition and hint bits. getPredicate(unsigned Condition,unsigned Hint)87*0b57cec5SDimitry Andric inline Predicate getPredicate(unsigned Condition, unsigned Hint) { 88*0b57cec5SDimitry Andric return (Predicate)((Condition & ~BR_HINT_MASK) | 89*0b57cec5SDimitry Andric (Hint & BR_HINT_MASK)); 90*0b57cec5SDimitry Andric } 91*0b57cec5SDimitry Andric } 92*0b57cec5SDimitry Andric } 93*0b57cec5SDimitry Andric 94*0b57cec5SDimitry Andric #endif 95