1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPCMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/PPCFixupKinds.h" 14 #include "PPCInstrInfo.h" 15 #include "PPCMCCodeEmitter.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCFixup.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/Support/Endian.h" 23 #include "llvm/Support/EndianStream.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <cassert> 28 #include <cstdint> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "mccodeemitter" 33 34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 35 36 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 37 MCContext &Ctx) { 38 return new PPCMCCodeEmitter(MCII, Ctx); 39 } 40 41 unsigned PPCMCCodeEmitter:: 42 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 43 SmallVectorImpl<MCFixup> &Fixups, 44 const MCSubtargetInfo &STI) const { 45 const MCOperand &MO = MI.getOperand(OpNo); 46 47 if (MO.isReg() || MO.isImm()) 48 return getMachineOpValue(MI, MO, Fixups, STI); 49 50 const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo *>(&MCII); 51 unsigned Opcode = MI.getOpcode(); 52 // Add a fixup for the branch target. 53 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 54 (InstrInfo->isNoTOCCallInstr(Opcode) 55 ? (MCFixupKind)PPC::fixup_ppc_br24_notoc 56 : (MCFixupKind)PPC::fixup_ppc_br24))); 57 return 0; 58 } 59 60 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const { 63 const MCOperand &MO = MI.getOperand(OpNo); 64 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 65 66 // Add a fixup for the branch target. 67 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 68 (MCFixupKind)PPC::fixup_ppc_brcond14)); 69 return 0; 70 } 71 72 unsigned PPCMCCodeEmitter:: 73 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 74 SmallVectorImpl<MCFixup> &Fixups, 75 const MCSubtargetInfo &STI) const { 76 const MCOperand &MO = MI.getOperand(OpNo); 77 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 78 79 // Add a fixup for the branch target. 80 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 81 (MCFixupKind)PPC::fixup_ppc_br24abs)); 82 return 0; 83 } 84 85 unsigned PPCMCCodeEmitter:: 86 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const { 89 const MCOperand &MO = MI.getOperand(OpNo); 90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 91 92 // Add a fixup for the branch target. 93 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 94 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 95 return 0; 96 } 97 98 unsigned 99 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, 100 SmallVectorImpl<MCFixup> &Fixups, 101 const MCSubtargetInfo &STI) const { 102 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); 103 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) 104 << 1; 105 return RegBits; 106 } 107 108 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const { 111 const MCOperand &MO = MI.getOperand(OpNo); 112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 113 114 // Add a fixup for the immediate field. 115 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 116 (MCFixupKind)PPC::fixup_ppc_half16)); 117 return 0; 118 } 119 120 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo, 121 SmallVectorImpl<MCFixup> &Fixups, 122 const MCSubtargetInfo &STI, 123 MCFixupKind Fixup) const { 124 const MCOperand &MO = MI.getOperand(OpNo); 125 assert(!MO.isReg() && "Not expecting a register for this operand."); 126 if (MO.isImm()) 127 return getMachineOpValue(MI, MO, Fixups, STI); 128 129 // Add a fixup for the immediate field. 130 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup)); 131 return 0; 132 } 133 134 uint64_t 135 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, 136 SmallVectorImpl<MCFixup> &Fixups, 137 const MCSubtargetInfo &STI) const { 138 return getImm34Encoding(MI, OpNo, Fixups, STI, 139 (MCFixupKind)PPC::fixup_ppc_imm34); 140 } 141 142 uint64_t 143 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, 144 SmallVectorImpl<MCFixup> &Fixups, 145 const MCSubtargetInfo &STI) const { 146 return getImm34Encoding(MI, OpNo, Fixups, STI, 147 (MCFixupKind)PPC::fixup_ppc_pcrel34); 148 } 149 150 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 151 SmallVectorImpl<MCFixup> &Fixups, 152 const MCSubtargetInfo &STI) const { 153 // Encode (imm, reg) as a memri, which has the low 16-bits as the 154 // displacement and the next 5 bits as the register #. 155 assert(MI.getOperand(OpNo+1).isReg()); 156 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 157 158 const MCOperand &MO = MI.getOperand(OpNo); 159 if (MO.isImm()) 160 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 161 162 // Add a fixup for the displacement field. 163 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 164 (MCFixupKind)PPC::fixup_ppc_half16)); 165 return RegBits; 166 } 167 168 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 169 SmallVectorImpl<MCFixup> &Fixups, 170 const MCSubtargetInfo &STI) const { 171 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 172 // displacement and the next 5 bits as the register #. 173 assert(MI.getOperand(OpNo+1).isReg()); 174 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; 175 176 const MCOperand &MO = MI.getOperand(OpNo); 177 if (MO.isImm()) 178 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; 179 180 // Add a fixup for the displacement field. 181 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 182 (MCFixupKind)PPC::fixup_ppc_half16ds)); 183 return RegBits; 184 } 185 186 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 187 SmallVectorImpl<MCFixup> &Fixups, 188 const MCSubtargetInfo &STI) const { 189 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the 190 // displacement and the next 5 bits as the register #. 191 assert(MI.getOperand(OpNo+1).isReg()); 192 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; 193 194 const MCOperand &MO = MI.getOperand(OpNo); 195 if (MO.isImm()) { 196 assert(!(MO.getImm() % 16) && 197 "Expecting an immediate that is a multiple of 16"); 198 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; 199 } 200 201 // Otherwise add a fixup for the displacement field. 202 Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(), 203 (MCFixupKind)PPC::fixup_ppc_half16dq)); 204 return RegBits; 205 } 206 207 unsigned 208 PPCMCCodeEmitter::getMemRIHashEncoding(const MCInst &MI, unsigned OpNo, 209 SmallVectorImpl<MCFixup> &Fixups, 210 const MCSubtargetInfo &STI) const { 211 // Encode (imm, reg) for the hash load/store to stack for the ROP Protection 212 // instructions. 213 const MCOperand &RegMO = MI.getOperand(OpNo + 1); 214 const MCOperand &MO = MI.getOperand(OpNo); 215 216 assert(RegMO.isReg() && "Base address must be a register."); 217 assert(MO.isImm() && "Expecting an immediate operand."); 218 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned."); 219 220 unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6; 221 unsigned DX = (MO.getImm() >> 3) & 0x3F; 222 return RegBits | DX; 223 } 224 225 uint64_t 226 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, 227 SmallVectorImpl<MCFixup> &Fixups, 228 const MCSubtargetInfo &STI) const { 229 // Encode the PCRelative version of memri34: imm34(r0). 230 // In the PC relative version the register for the address must be zero. 231 // The 34 bit immediate can fall into one of three cases: 232 // 1) It is a relocation to be filled in by the linker represented as: 233 // (MCExpr::SymbolRef) 234 // 2) It is a relocation + SignedOffset represented as: 235 // (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant)) 236 // 3) It is a known value at compile time. 237 238 // Make sure that the register is a zero as expected. 239 assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate."); 240 uint64_t RegBits = 241 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34; 242 assert(RegBits == 0 && "Operand must be 0."); 243 244 // If this is not a MCExpr then we are in case 3) and we are dealing with 245 // a value known at compile time, not a relocation. 246 const MCOperand &MO = MI.getOperand(OpNo); 247 if (!MO.isExpr()) 248 return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; 249 250 // At this point in the function it is known that MO is of type MCExpr. 251 // Therefore we are dealing with either case 1) a symbol ref or 252 // case 2) a symbol ref plus a constant. 253 const MCExpr *Expr = MO.getExpr(); 254 switch (Expr->getKind()) { 255 default: 256 llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding."); 257 case MCExpr::SymbolRef: { 258 // Relocation alone. 259 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr); 260 (void)SRE; 261 // Currently these are the only valid PCRelative Relocations. 262 assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL || 263 SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL || 264 SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL || 265 SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL || 266 SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) && 267 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or " 268 "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or " 269 "VK_PPC_GOT_TPREL_PCREL."); 270 // Generate the fixup for the relocation. 271 Fixups.push_back( 272 MCFixup::create(0, Expr, 273 static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34))); 274 // Put zero in the location of the immediate. The linker will fill in the 275 // correct value based on the relocation. 276 return 0; 277 } 278 case MCExpr::Binary: { 279 // Relocation plus some offset. 280 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr); 281 assert(BE->getOpcode() == MCBinaryExpr::Add && 282 "Binary expression opcode must be an add."); 283 284 const MCExpr *LHS = BE->getLHS(); 285 const MCExpr *RHS = BE->getRHS(); 286 287 // Need to check in both directions. Reloc+Offset and Offset+Reloc. 288 if (LHS->getKind() != MCExpr::SymbolRef) 289 std::swap(LHS, RHS); 290 291 if (LHS->getKind() != MCExpr::SymbolRef || 292 RHS->getKind() != MCExpr::Constant) 293 llvm_unreachable("Expecting to have one constant and one relocation."); 294 295 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS); 296 (void)SRE; 297 assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) && 298 "Value must fit in 34 bits."); 299 300 // Currently these are the only valid PCRelative Relocations. 301 assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL || 302 SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) && 303 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL"); 304 // Generate the fixup for the relocation. 305 Fixups.push_back( 306 MCFixup::create(0, Expr, 307 static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34))); 308 // Put zero in the location of the immediate. The linker will fill in the 309 // correct value based on the relocation. 310 return 0; 311 } 312 } 313 } 314 315 uint64_t 316 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo, 317 SmallVectorImpl<MCFixup> &Fixups, 318 const MCSubtargetInfo &STI) const { 319 // Encode (imm, reg) as a memri34, which has the low 34-bits as the 320 // displacement and the next 5 bits as the register #. 321 assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register."); 322 uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) 323 << 34; 324 const MCOperand &MO = MI.getOperand(OpNo); 325 return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; 326 } 327 328 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 329 SmallVectorImpl<MCFixup> &Fixups, 330 const MCSubtargetInfo &STI) 331 const { 332 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8) 333 // as the displacement and the next 5 bits as the register #. 334 assert(MI.getOperand(OpNo+1).isReg()); 335 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 336 337 const MCOperand &MO = MI.getOperand(OpNo); 338 assert(MO.isImm()); 339 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; 340 return reverseBits(Imm | RegBits) >> 22; 341 } 342 343 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 344 SmallVectorImpl<MCFixup> &Fixups, 345 const MCSubtargetInfo &STI) 346 const { 347 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4) 348 // as the displacement and the next 5 bits as the register #. 349 assert(MI.getOperand(OpNo+1).isReg()); 350 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 351 352 const MCOperand &MO = MI.getOperand(OpNo); 353 assert(MO.isImm()); 354 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; 355 return reverseBits(Imm | RegBits) >> 22; 356 } 357 358 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 359 SmallVectorImpl<MCFixup> &Fixups, 360 const MCSubtargetInfo &STI) 361 const { 362 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2) 363 // as the displacement and the next 5 bits as the register #. 364 assert(MI.getOperand(OpNo+1).isReg()); 365 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 366 367 const MCOperand &MO = MI.getOperand(OpNo); 368 assert(MO.isImm()); 369 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; 370 return reverseBits(Imm | RegBits) >> 22; 371 } 372 373 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 374 SmallVectorImpl<MCFixup> &Fixups, 375 const MCSubtargetInfo &STI) const { 376 const MCOperand &MO = MI.getOperand(OpNo); 377 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 378 379 // Add a fixup for the TLS register, which simply provides a relocation 380 // hint to the linker that this statement is part of a relocation sequence. 381 // Return the thread-pointer register's encoding. Add a one byte displacement 382 // if using PC relative memops. 383 const MCExpr *Expr = MO.getExpr(); 384 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr); 385 bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL; 386 Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr, 387 (MCFixupKind)PPC::fixup_ppc_nofixup)); 388 const Triple &TT = STI.getTargetTriple(); 389 bool isPPC64 = TT.isPPC64(); 390 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 391 } 392 393 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 394 SmallVectorImpl<MCFixup> &Fixups, 395 const MCSubtargetInfo &STI) const { 396 // For special TLS calls, we need two fixups; one for the branch target 397 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 398 // and one for the TLSGD or TLSLD symbol, which is emitted here. 399 const MCOperand &MO = MI.getOperand(OpNo+1); 400 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 401 (MCFixupKind)PPC::fixup_ppc_nofixup)); 402 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 403 } 404 405 unsigned PPCMCCodeEmitter:: 406 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 407 SmallVectorImpl<MCFixup> &Fixups, 408 const MCSubtargetInfo &STI) const { 409 const MCOperand &MO = MI.getOperand(OpNo); 410 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 411 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 412 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 413 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 414 } 415 416 // Get the index for this operand in this instruction. This is needed for 417 // computing the register number in PPCInstrInfo::getRegNumForOperand() for 418 // any instructions that use a different numbering scheme for registers in 419 // different operands. 420 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) { 421 for (unsigned i = 0; i < MI.getNumOperands(); i++) { 422 const MCOperand &Op = MI.getOperand(i); 423 if (&Op == &MO) 424 return i; 425 } 426 llvm_unreachable("This operand is not part of this instruction"); 427 return ~0U; // Silence any warnings about no return. 428 } 429 430 uint64_t PPCMCCodeEmitter:: 431 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 432 SmallVectorImpl<MCFixup> &Fixups, 433 const MCSubtargetInfo &STI) const { 434 if (MO.isReg()) { 435 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 436 // The GPR operand should come through here though. 437 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 438 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 439 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 440 unsigned OpNo = getOpIdxForMO(MI, MO); 441 unsigned Reg = 442 PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()), 443 MO.getReg(), OpNo); 444 return CTX.getRegisterInfo()->getEncodingValue(Reg); 445 } 446 447 assert(MO.isImm() && 448 "Relocation required in an instruction that we cannot encode!"); 449 return MO.getImm(); 450 } 451 452 void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 453 SmallVectorImpl<MCFixup> &Fixups, 454 const MCSubtargetInfo &STI) const { 455 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 456 457 // Output the constant in big/little endian byte order. 458 unsigned Size = getInstSizeInBytes(MI); 459 support::endianness E = IsLittleEndian ? support::little : support::big; 460 switch (Size) { 461 case 0: 462 break; 463 case 4: 464 support::endian::write<uint32_t>(OS, Bits, E); 465 break; 466 case 8: 467 // If we emit a pair of instructions, the first one is 468 // always in the top 32 bits, even on little-endian. 469 support::endian::write<uint32_t>(OS, Bits >> 32, E); 470 support::endian::write<uint32_t>(OS, Bits, E); 471 break; 472 default: 473 llvm_unreachable("Invalid instruction size"); 474 } 475 476 ++MCNumEmitted; // Keep track of the # of mi's emitted. 477 } 478 479 // Get the number of bytes used to encode the given MCInst. 480 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const { 481 unsigned Opcode = MI.getOpcode(); 482 const MCInstrDesc &Desc = MCII.get(Opcode); 483 return Desc.getSize(); 484 } 485 486 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const { 487 unsigned Opcode = MI.getOpcode(); 488 const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII); 489 return InstrInfo->isPrefixed(Opcode); 490 } 491 492 #include "PPCGenMCCodeEmitter.inc" 493