1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPCMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCMCCodeEmitter.h" 14 #include "MCTargetDesc/PPCFixupKinds.h" 15 #include "PPCMCAsmInfo.h" 16 #include "PPCMCTargetDesc.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCFixup.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/Support/Casting.h" 24 #include "llvm/Support/EndianStream.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/TargetParser/Triple.h" 28 #include <cassert> 29 #include <cstdint> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "mccodeemitter" 34 35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 36 37 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 38 MCContext &Ctx) { 39 return new PPCMCCodeEmitter(MCII, Ctx); 40 } 41 42 static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset, 43 const MCExpr *Value, uint16_t Kind) { 44 bool PCRel = false; 45 switch (Kind) { 46 case PPC::fixup_ppc_br24: 47 case PPC::fixup_ppc_br24_notoc: 48 case PPC::fixup_ppc_brcond14: 49 case PPC::fixup_ppc_pcrel34: 50 PCRel = true; 51 } 52 Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel)); 53 } 54 55 unsigned PPCMCCodeEmitter:: 56 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const { 59 const MCOperand &MO = MI.getOperand(OpNo); 60 61 if (MO.isReg() || MO.isImm()) 62 return getMachineOpValue(MI, MO, Fixups, STI); 63 64 // Add a fixup for the branch target. 65 addFixup( 66 Fixups, 0, MO.getExpr(), 67 (isNoTOCCallInstr(MI) ? PPC::fixup_ppc_br24_notoc : PPC::fixup_ppc_br24)); 68 return 0; 69 } 70 71 /// Check if Opcode corresponds to a call instruction that should be marked 72 /// with the NOTOC relocation. 73 bool PPCMCCodeEmitter::isNoTOCCallInstr(const MCInst &MI) const { 74 unsigned Opcode = MI.getOpcode(); 75 if (!MCII.get(Opcode).isCall()) 76 return false; 77 78 switch (Opcode) { 79 default: 80 #ifndef NDEBUG 81 llvm_unreachable("Unknown call opcode"); 82 #endif 83 return false; 84 case PPC::BL8_NOTOC: 85 case PPC::BL8_NOTOC_TLS: 86 case PPC::BL8_NOTOC_RM: 87 return true; 88 #ifndef NDEBUG 89 case PPC::BL8: 90 case PPC::BL: 91 case PPC::BL8_TLS: 92 case PPC::BL_TLS: 93 case PPC::BLA8: 94 case PPC::BLA: 95 case PPC::BCCL: 96 case PPC::BCCLA: 97 case PPC::BCL: 98 case PPC::BCLn: 99 case PPC::BL8_NOP: 100 case PPC::BL_NOP: 101 case PPC::BL8_NOP_TLS: 102 case PPC::BLA8_NOP: 103 case PPC::BCTRL8: 104 case PPC::BCTRL: 105 case PPC::BCCCTRL8: 106 case PPC::BCCCTRL: 107 case PPC::BCCTRL8: 108 case PPC::BCCTRL: 109 case PPC::BCCTRL8n: 110 case PPC::BCCTRLn: 111 case PPC::BL8_RM: 112 case PPC::BLA8_RM: 113 case PPC::BL8_NOP_RM: 114 case PPC::BLA8_NOP_RM: 115 case PPC::BCTRL8_RM: 116 case PPC::BCTRL8_LDinto_toc: 117 case PPC::BCTRL8_LDinto_toc_RM: 118 case PPC::BL8_TLS_: 119 case PPC::TCRETURNdi8: 120 case PPC::TCRETURNai8: 121 case PPC::TCRETURNri8: 122 case PPC::TAILBCTR8: 123 case PPC::TAILB8: 124 case PPC::TAILBA8: 125 case PPC::BCLalways: 126 case PPC::BLRL: 127 case PPC::BCCLRL: 128 case PPC::BCLRL: 129 case PPC::BCLRLn: 130 case PPC::BDZL: 131 case PPC::BDNZL: 132 case PPC::BDZLA: 133 case PPC::BDNZLA: 134 case PPC::BDZLp: 135 case PPC::BDNZLp: 136 case PPC::BDZLAp: 137 case PPC::BDNZLAp: 138 case PPC::BDZLm: 139 case PPC::BDNZLm: 140 case PPC::BDZLAm: 141 case PPC::BDNZLAm: 142 case PPC::BDZLRL: 143 case PPC::BDNZLRL: 144 case PPC::BDZLRLp: 145 case PPC::BDNZLRLp: 146 case PPC::BDZLRLm: 147 case PPC::BDNZLRLm: 148 case PPC::BL_RM: 149 case PPC::BLA_RM: 150 case PPC::BL_NOP_RM: 151 case PPC::BCTRL_RM: 152 case PPC::TCRETURNdi: 153 case PPC::TCRETURNai: 154 case PPC::TCRETURNri: 155 case PPC::BCTRL_LWZinto_toc: 156 case PPC::BCTRL_LWZinto_toc_RM: 157 case PPC::TAILBCTR: 158 case PPC::TAILB: 159 case PPC::TAILBA: 160 return false; 161 #endif 162 } 163 } 164 165 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 166 SmallVectorImpl<MCFixup> &Fixups, 167 const MCSubtargetInfo &STI) const { 168 const MCOperand &MO = MI.getOperand(OpNo); 169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 170 171 // Add a fixup for the branch target. 172 addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_brcond14); 173 return 0; 174 } 175 176 unsigned PPCMCCodeEmitter:: 177 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 178 SmallVectorImpl<MCFixup> &Fixups, 179 const MCSubtargetInfo &STI) const { 180 const MCOperand &MO = MI.getOperand(OpNo); 181 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 182 183 // Add a fixup for the branch target. 184 addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_br24abs); 185 return 0; 186 } 187 188 unsigned PPCMCCodeEmitter:: 189 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 190 SmallVectorImpl<MCFixup> &Fixups, 191 const MCSubtargetInfo &STI) const { 192 const MCOperand &MO = MI.getOperand(OpNo); 193 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 194 195 // Add a fixup for the branch target. 196 addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_brcond14abs); 197 return 0; 198 } 199 200 unsigned 201 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, 202 SmallVectorImpl<MCFixup> &Fixups, 203 const MCSubtargetInfo &STI) const { 204 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); 205 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) 206 << 1; 207 return RegBits; 208 } 209 210 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 211 SmallVectorImpl<MCFixup> &Fixups, 212 const MCSubtargetInfo &STI) const { 213 const MCOperand &MO = MI.getOperand(OpNo); 214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 215 216 // Add a fixup for the immediate field. 217 addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16); 218 return 0; 219 } 220 221 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo, 222 SmallVectorImpl<MCFixup> &Fixups, 223 const MCSubtargetInfo &STI, 224 MCFixupKind Fixup) const { 225 const MCOperand &MO = MI.getOperand(OpNo); 226 assert(!MO.isReg() && "Not expecting a register for this operand."); 227 if (MO.isImm()) 228 return getMachineOpValue(MI, MO, Fixups, STI); 229 230 // Add a fixup for the immediate field. 231 addFixup(Fixups, 0, MO.getExpr(), Fixup); 232 return 0; 233 } 234 235 uint64_t 236 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, 237 SmallVectorImpl<MCFixup> &Fixups, 238 const MCSubtargetInfo &STI) const { 239 return getImm34Encoding(MI, OpNo, Fixups, STI, PPC::fixup_ppc_imm34); 240 } 241 242 uint64_t 243 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, 244 SmallVectorImpl<MCFixup> &Fixups, 245 const MCSubtargetInfo &STI) const { 246 return getImm34Encoding(MI, OpNo, Fixups, STI, PPC::fixup_ppc_pcrel34); 247 } 248 249 unsigned PPCMCCodeEmitter::getDispRIEncoding(const MCInst &MI, unsigned OpNo, 250 SmallVectorImpl<MCFixup> &Fixups, 251 const MCSubtargetInfo &STI) const { 252 const MCOperand &MO = MI.getOperand(OpNo); 253 if (MO.isImm()) 254 return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF; 255 256 // Add a fixup for the displacement field. 257 addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), PPC::fixup_ppc_half16); 258 return 0; 259 } 260 261 unsigned 262 PPCMCCodeEmitter::getDispRIXEncoding(const MCInst &MI, unsigned OpNo, 263 SmallVectorImpl<MCFixup> &Fixups, 264 const MCSubtargetInfo &STI) const { 265 const MCOperand &MO = MI.getOperand(OpNo); 266 if (MO.isImm()) 267 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF); 268 269 // Add a fixup for the displacement field. 270 addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), 271 PPC::fixup_ppc_half16ds); 272 return 0; 273 } 274 275 unsigned 276 PPCMCCodeEmitter::getDispRIX16Encoding(const MCInst &MI, unsigned OpNo, 277 SmallVectorImpl<MCFixup> &Fixups, 278 const MCSubtargetInfo &STI) const { 279 const MCOperand &MO = MI.getOperand(OpNo); 280 if (MO.isImm()) { 281 assert(!(MO.getImm() % 16) && 282 "Expecting an immediate that is a multiple of 16"); 283 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF); 284 } 285 286 // Otherwise add a fixup for the displacement field. 287 addFixup(Fixups, IsLittleEndian ? 0 : 2, MO.getExpr(), 288 PPC::fixup_ppc_half16dq); 289 return 0; 290 } 291 292 unsigned 293 PPCMCCodeEmitter::getDispRIHashEncoding(const MCInst &MI, unsigned OpNo, 294 SmallVectorImpl<MCFixup> &Fixups, 295 const MCSubtargetInfo &STI) const { 296 // Encode imm for the hash load/store to stack for the ROP Protection 297 // instructions. 298 const MCOperand &MO = MI.getOperand(OpNo); 299 300 assert(MO.isImm() && "Expecting an immediate operand."); 301 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned."); 302 303 unsigned DX = (MO.getImm() >> 3) & 0x3F; 304 return DX; 305 } 306 307 uint64_t 308 PPCMCCodeEmitter::getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, 309 SmallVectorImpl<MCFixup> &Fixups, 310 const MCSubtargetInfo &STI) const { 311 // Encode the displacement part of pc-relative memri34, which is an imm34. 312 // The 34 bit immediate can fall into one of three cases: 313 // 1) It is a relocation to be filled in by the linker represented as: 314 // (MCExpr::SymbolRef) 315 // 2) It is a relocation + SignedOffset represented as: 316 // (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant)) 317 // 3) It is a known value at compile time. 318 319 // If this is not a MCExpr then we are in case 3) and we are dealing with 320 // a value known at compile time, not a relocation. 321 const MCOperand &MO = MI.getOperand(OpNo); 322 if (!MO.isExpr()) 323 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL; 324 325 // At this point in the function it is known that MO is of type MCExpr. 326 // Therefore we are dealing with either case 1) a symbol ref or 327 // case 2) a symbol ref plus a constant. 328 const MCExpr *Expr = MO.getExpr(); 329 switch (Expr->getKind()) { 330 default: 331 llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding."); 332 case MCExpr::SymbolRef: { 333 // Relocation alone. 334 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr); 335 (void)SRE; 336 // Currently these are the only valid PCRelative Relocations. 337 assert(is_contained({PPC::S_PCREL, PPC::S_GOT_PCREL, PPC::S_GOT_TLSGD_PCREL, 338 PPC::S_GOT_TLSLD_PCREL, PPC::S_GOT_TPREL_PCREL}, 339 SRE->getSpecifier()) && 340 "specifier must be S_PCREL, S_GOT_PCREL, S_GOT_TLSGD_PCREL, " 341 "S_GOT_TLSLD_PCREL, or S_GOT_TPREL_PCREL"); 342 // Generate the fixup for the relocation. 343 addFixup(Fixups, 0, Expr, PPC::fixup_ppc_pcrel34); 344 // Put zero in the location of the immediate. The linker will fill in the 345 // correct value based on the relocation. 346 return 0; 347 } 348 case MCExpr::Binary: { 349 // Relocation plus some offset. 350 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr); 351 assert(BE->getOpcode() == MCBinaryExpr::Add && 352 "Binary expression opcode must be an add."); 353 354 const MCExpr *LHS = BE->getLHS(); 355 const MCExpr *RHS = BE->getRHS(); 356 357 // Need to check in both directions. Reloc+Offset and Offset+Reloc. 358 if (LHS->getKind() != MCExpr::SymbolRef) 359 std::swap(LHS, RHS); 360 361 if (LHS->getKind() != MCExpr::SymbolRef || 362 RHS->getKind() != MCExpr::Constant) 363 llvm_unreachable("Expecting to have one constant and one relocation."); 364 365 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS); 366 (void)SRE; 367 assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) && 368 "Value must fit in 34 bits."); 369 370 // Currently these are the only valid PCRelative Relocations. 371 assert((getSpecifier(SRE) == PPC::S_PCREL || 372 getSpecifier(SRE) == PPC::S_GOT_PCREL) && 373 "VariantKind must be VK_PCREL or VK_GOT_PCREL"); 374 // Generate the fixup for the relocation. 375 addFixup(Fixups, 0, Expr, PPC::fixup_ppc_pcrel34); 376 // Put zero in the location of the immediate. The linker will fill in the 377 // correct value based on the relocation. 378 return 0; 379 } 380 } 381 } 382 383 uint64_t 384 PPCMCCodeEmitter::getDispRI34Encoding(const MCInst &MI, unsigned OpNo, 385 SmallVectorImpl<MCFixup> &Fixups, 386 const MCSubtargetInfo &STI) const { 387 // Encode the displacement part of a memri34. 388 const MCOperand &MO = MI.getOperand(OpNo); 389 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL; 390 } 391 392 unsigned 393 PPCMCCodeEmitter::getDispSPE8Encoding(const MCInst &MI, unsigned OpNo, 394 SmallVectorImpl<MCFixup> &Fixups, 395 const MCSubtargetInfo &STI) const { 396 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 8). 397 const MCOperand &MO = MI.getOperand(OpNo); 398 assert(MO.isImm()); 399 return getMachineOpValue(MI, MO, Fixups, STI) >> 3; 400 } 401 402 unsigned 403 PPCMCCodeEmitter::getDispSPE4Encoding(const MCInst &MI, unsigned OpNo, 404 SmallVectorImpl<MCFixup> &Fixups, 405 const MCSubtargetInfo &STI) const { 406 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 4). 407 const MCOperand &MO = MI.getOperand(OpNo); 408 assert(MO.isImm()); 409 return getMachineOpValue(MI, MO, Fixups, STI) >> 2; 410 } 411 412 unsigned 413 PPCMCCodeEmitter::getDispSPE2Encoding(const MCInst &MI, unsigned OpNo, 414 SmallVectorImpl<MCFixup> &Fixups, 415 const MCSubtargetInfo &STI) const { 416 // Encode imm as a dispSPE8, which has the low 5-bits of (imm / 2). 417 const MCOperand &MO = MI.getOperand(OpNo); 418 assert(MO.isImm()); 419 return getMachineOpValue(MI, MO, Fixups, STI) >> 1; 420 } 421 422 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 423 SmallVectorImpl<MCFixup> &Fixups, 424 const MCSubtargetInfo &STI) const { 425 const MCOperand &MO = MI.getOperand(OpNo); 426 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 427 428 // Add a fixup for the TLS register, which simply provides a relocation 429 // hint to the linker that this statement is part of a relocation sequence. 430 // Return the thread-pointer register's encoding. Add a one byte displacement 431 // if using PC relative memops. 432 const MCExpr *Expr = MO.getExpr(); 433 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr); 434 bool IsPCRel = getSpecifier(SRE) == PPC::S_TLS_PCREL; 435 addFixup(Fixups, IsPCRel ? 1 : 0, Expr, PPC::fixup_ppc_nofixup); 436 const Triple &TT = STI.getTargetTriple(); 437 bool isPPC64 = TT.isPPC64(); 438 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 439 } 440 441 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 442 SmallVectorImpl<MCFixup> &Fixups, 443 const MCSubtargetInfo &STI) const { 444 // For special TLS calls, we need two fixups; one for the branch target 445 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 446 // and one for the TLSGD or TLSLD symbol, which is emitted here. 447 const MCOperand &MO = MI.getOperand(OpNo+1); 448 addFixup(Fixups, 0, MO.getExpr(), PPC::fixup_ppc_nofixup); 449 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 450 } 451 452 unsigned PPCMCCodeEmitter:: 453 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 454 SmallVectorImpl<MCFixup> &Fixups, 455 const MCSubtargetInfo &STI) const { 456 const MCOperand &MO = MI.getOperand(OpNo); 457 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 458 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 459 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 460 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 461 } 462 463 // Get the index for this operand in this instruction. This is needed for 464 // computing the register number in PPC::getRegNumForOperand() for 465 // any instructions that use a different numbering scheme for registers in 466 // different operands. 467 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) { 468 for (unsigned i = 0; i < MI.getNumOperands(); i++) { 469 const MCOperand &Op = MI.getOperand(i); 470 if (&Op == &MO) 471 return i; 472 } 473 llvm_unreachable("This operand is not part of this instruction"); 474 return ~0U; // Silence any warnings about no return. 475 } 476 477 uint64_t PPCMCCodeEmitter:: 478 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 479 SmallVectorImpl<MCFixup> &Fixups, 480 const MCSubtargetInfo &STI) const { 481 if (MO.isReg()) { 482 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 483 // The GPR operand should come through here though. 484 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 485 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 486 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 487 unsigned OpNo = getOpIdxForMO(MI, MO); 488 MCRegister Reg = 489 PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo); 490 return CTX.getRegisterInfo()->getEncodingValue(Reg); 491 } 492 493 assert(MO.isImm() && 494 "Relocation required in an instruction that we cannot encode!"); 495 return MO.getImm(); 496 } 497 498 void PPCMCCodeEmitter::encodeInstruction(const MCInst &MI, 499 SmallVectorImpl<char> &CB, 500 SmallVectorImpl<MCFixup> &Fixups, 501 const MCSubtargetInfo &STI) const { 502 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 503 504 // Output the constant in big/little endian byte order. 505 unsigned Size = getInstSizeInBytes(MI); 506 llvm::endianness E = 507 IsLittleEndian ? llvm::endianness::little : llvm::endianness::big; 508 switch (Size) { 509 case 0: 510 break; 511 case 4: 512 support::endian::write<uint32_t>(CB, Bits, E); 513 break; 514 case 8: 515 // If we emit a pair of instructions, the first one is 516 // always in the top 32 bits, even on little-endian. 517 support::endian::write<uint32_t>(CB, Bits >> 32, E); 518 support::endian::write<uint32_t>(CB, Bits, E); 519 break; 520 default: 521 llvm_unreachable("Invalid instruction size"); 522 } 523 524 ++MCNumEmitted; // Keep track of the # of mi's emitted. 525 } 526 527 // Get the number of bytes used to encode the given MCInst. 528 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const { 529 unsigned Opcode = MI.getOpcode(); 530 const MCInstrDesc &Desc = MCII.get(Opcode); 531 return Desc.getSize(); 532 } 533 534 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const { 535 return MCII.get(MI.getOpcode()).TSFlags & PPCII::Prefixed; 536 } 537 538 #include "PPCGenMCCodeEmitter.inc" 539