xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34              cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44                         cl::init(false),
45                         cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51   const char *RegName = getRegisterName(RegNo);
52   if (RegName[0] == 'q' /* QPX */) {
53     // The system toolchain on the BG/Q does not understand QPX register names
54     // in .cfi_* directives, so print the name of the floating-point
55     // subregister instead.
56     std::string RN(RegName);
57 
58     RN[0] = 'f';
59     OS << RN;
60 
61     return;
62   }
63 
64   OS << RegName;
65 }
66 
67 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
68                                StringRef Annot, const MCSubtargetInfo &STI,
69                                raw_ostream &O) {
70   // Customize printing of the addis instruction on AIX. When an operand is a
71   // symbol reference, the instruction syntax is changed to look like a load
72   // operation, i.e:
73   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
74   if (TT.isOSAIX() &&
75       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
76       MI->getOperand(2).isExpr()) {
77     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
78            "The first and the second operand of an addis instruction"
79            " should be registers.");
80 
81     assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
82            "The third operand of an addis instruction should be a symbol "
83            "reference expression if it is an expression at all.");
84 
85     O << "\taddis ";
86     printOperand(MI, 0, O);
87     O << ", ";
88     printOperand(MI, 2, O);
89     O << "(";
90     printOperand(MI, 1, O);
91     O << ")";
92     return;
93   }
94 
95   // Check for slwi/srwi mnemonics.
96   if (MI->getOpcode() == PPC::RLWINM) {
97     unsigned char SH = MI->getOperand(2).getImm();
98     unsigned char MB = MI->getOperand(3).getImm();
99     unsigned char ME = MI->getOperand(4).getImm();
100     bool useSubstituteMnemonic = false;
101     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
102       O << "\tslwi "; useSubstituteMnemonic = true;
103     }
104     if (SH <= 31 && MB == (32-SH) && ME == 31) {
105       O << "\tsrwi "; useSubstituteMnemonic = true;
106       SH = 32-SH;
107     }
108     if (useSubstituteMnemonic) {
109       printOperand(MI, 0, O);
110       O << ", ";
111       printOperand(MI, 1, O);
112       O << ", " << (unsigned int)SH;
113 
114       printAnnotation(O, Annot);
115       return;
116     }
117   }
118 
119   if (MI->getOpcode() == PPC::RLDICR ||
120       MI->getOpcode() == PPC::RLDICR_32) {
121     unsigned char SH = MI->getOperand(2).getImm();
122     unsigned char ME = MI->getOperand(3).getImm();
123     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
124     if (63-SH == ME) {
125       O << "\tsldi ";
126       printOperand(MI, 0, O);
127       O << ", ";
128       printOperand(MI, 1, O);
129       O << ", " << (unsigned int)SH;
130       printAnnotation(O, Annot);
131       return;
132     }
133   }
134 
135   // dcbt[st] is printed manually here because:
136   //  1. The assembly syntax is different between embedded and server targets
137   //  2. We must print the short mnemonics for TH == 0 because the
138   //     embedded/server syntax default will not be stable across assemblers
139   //  The syntax for dcbt is:
140   //    dcbt ra, rb, th [server]
141   //    dcbt th, ra, rb [embedded]
142   //  where th can be omitted when it is 0. dcbtst is the same.
143   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
144     unsigned char TH = MI->getOperand(0).getImm();
145     O << "\tdcbt";
146     if (MI->getOpcode() == PPC::DCBTST)
147       O << "st";
148     if (TH == 16)
149       O << "t";
150     O << " ";
151 
152     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
153     if (IsBookE && TH != 0 && TH != 16)
154       O << (unsigned int) TH << ", ";
155 
156     printOperand(MI, 1, O);
157     O << ", ";
158     printOperand(MI, 2, O);
159 
160     if (!IsBookE && TH != 0 && TH != 16)
161       O << ", " << (unsigned int) TH;
162 
163     printAnnotation(O, Annot);
164     return;
165   }
166 
167   if (MI->getOpcode() == PPC::DCBF) {
168     unsigned char L = MI->getOperand(0).getImm();
169     if (!L || L == 1 || L == 3) {
170       O << "\tdcbf";
171       if (L == 1 || L == 3)
172         O << "l";
173       if (L == 3)
174         O << "p";
175       O << " ";
176 
177       printOperand(MI, 1, O);
178       O << ", ";
179       printOperand(MI, 2, O);
180 
181       printAnnotation(O, Annot);
182       return;
183     }
184   }
185 
186   if (!printAliasInstr(MI, Address, O))
187     printInstruction(MI, Address, O);
188   printAnnotation(O, Annot);
189 }
190 
191 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
192                                            raw_ostream &O,
193                                            const char *Modifier) {
194   unsigned Code = MI->getOperand(OpNo).getImm();
195 
196   if (StringRef(Modifier) == "cc") {
197     switch ((PPC::Predicate)Code) {
198     case PPC::PRED_LT_MINUS:
199     case PPC::PRED_LT_PLUS:
200     case PPC::PRED_LT:
201       O << "lt";
202       return;
203     case PPC::PRED_LE_MINUS:
204     case PPC::PRED_LE_PLUS:
205     case PPC::PRED_LE:
206       O << "le";
207       return;
208     case PPC::PRED_EQ_MINUS:
209     case PPC::PRED_EQ_PLUS:
210     case PPC::PRED_EQ:
211       O << "eq";
212       return;
213     case PPC::PRED_GE_MINUS:
214     case PPC::PRED_GE_PLUS:
215     case PPC::PRED_GE:
216       O << "ge";
217       return;
218     case PPC::PRED_GT_MINUS:
219     case PPC::PRED_GT_PLUS:
220     case PPC::PRED_GT:
221       O << "gt";
222       return;
223     case PPC::PRED_NE_MINUS:
224     case PPC::PRED_NE_PLUS:
225     case PPC::PRED_NE:
226       O << "ne";
227       return;
228     case PPC::PRED_UN_MINUS:
229     case PPC::PRED_UN_PLUS:
230     case PPC::PRED_UN:
231       O << "un";
232       return;
233     case PPC::PRED_NU_MINUS:
234     case PPC::PRED_NU_PLUS:
235     case PPC::PRED_NU:
236       O << "nu";
237       return;
238     case PPC::PRED_BIT_SET:
239     case PPC::PRED_BIT_UNSET:
240       llvm_unreachable("Invalid use of bit predicate code");
241     }
242     llvm_unreachable("Invalid predicate code");
243   }
244 
245   if (StringRef(Modifier) == "pm") {
246     switch ((PPC::Predicate)Code) {
247     case PPC::PRED_LT:
248     case PPC::PRED_LE:
249     case PPC::PRED_EQ:
250     case PPC::PRED_GE:
251     case PPC::PRED_GT:
252     case PPC::PRED_NE:
253     case PPC::PRED_UN:
254     case PPC::PRED_NU:
255       return;
256     case PPC::PRED_LT_MINUS:
257     case PPC::PRED_LE_MINUS:
258     case PPC::PRED_EQ_MINUS:
259     case PPC::PRED_GE_MINUS:
260     case PPC::PRED_GT_MINUS:
261     case PPC::PRED_NE_MINUS:
262     case PPC::PRED_UN_MINUS:
263     case PPC::PRED_NU_MINUS:
264       O << "-";
265       return;
266     case PPC::PRED_LT_PLUS:
267     case PPC::PRED_LE_PLUS:
268     case PPC::PRED_EQ_PLUS:
269     case PPC::PRED_GE_PLUS:
270     case PPC::PRED_GT_PLUS:
271     case PPC::PRED_NE_PLUS:
272     case PPC::PRED_UN_PLUS:
273     case PPC::PRED_NU_PLUS:
274       O << "+";
275       return;
276     case PPC::PRED_BIT_SET:
277     case PPC::PRED_BIT_UNSET:
278       llvm_unreachable("Invalid use of bit predicate code");
279     }
280     llvm_unreachable("Invalid predicate code");
281   }
282 
283   assert(StringRef(Modifier) == "reg" &&
284          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
285   printOperand(MI, OpNo+1, O);
286 }
287 
288 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
289                                        raw_ostream &O) {
290   unsigned Code = MI->getOperand(OpNo).getImm();
291   if (Code == 2)
292     O << "-";
293   else if (Code == 3)
294     O << "+";
295 }
296 
297 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
298                                        raw_ostream &O) {
299   unsigned int Value = MI->getOperand(OpNo).getImm();
300   assert(Value <= 1 && "Invalid u1imm argument!");
301   O << (unsigned int)Value;
302 }
303 
304 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
305                                        raw_ostream &O) {
306   unsigned int Value = MI->getOperand(OpNo).getImm();
307   assert(Value <= 3 && "Invalid u2imm argument!");
308   O << (unsigned int)Value;
309 }
310 
311 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
312                                        raw_ostream &O) {
313   unsigned int Value = MI->getOperand(OpNo).getImm();
314   assert(Value <= 8 && "Invalid u3imm argument!");
315   O << (unsigned int)Value;
316 }
317 
318 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
319                                        raw_ostream &O) {
320   unsigned int Value = MI->getOperand(OpNo).getImm();
321   assert(Value <= 15 && "Invalid u4imm argument!");
322   O << (unsigned int)Value;
323 }
324 
325 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
326                                        raw_ostream &O) {
327   int Value = MI->getOperand(OpNo).getImm();
328   Value = SignExtend32<5>(Value);
329   O << (int)Value;
330 }
331 
332 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
333                                          raw_ostream &O) {
334   unsigned int Value = MI->getOperand(OpNo).getImm();
335   assert(Value == 0 && "Operand must be zero");
336   O << (unsigned int)Value;
337 }
338 
339 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
340                                        raw_ostream &O) {
341   unsigned int Value = MI->getOperand(OpNo).getImm();
342   assert(Value <= 31 && "Invalid u5imm argument!");
343   O << (unsigned int)Value;
344 }
345 
346 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
347                                        raw_ostream &O) {
348   unsigned int Value = MI->getOperand(OpNo).getImm();
349   assert(Value <= 63 && "Invalid u6imm argument!");
350   O << (unsigned int)Value;
351 }
352 
353 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
354                                        raw_ostream &O) {
355   unsigned int Value = MI->getOperand(OpNo).getImm();
356   assert(Value <= 127 && "Invalid u7imm argument!");
357   O << (unsigned int)Value;
358 }
359 
360 // Operands of BUILD_VECTOR are signed and we use this to print operands
361 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
362 // print as unsigned.
363 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
364                                        raw_ostream &O) {
365   unsigned char Value = MI->getOperand(OpNo).getImm();
366   O << (unsigned int)Value;
367 }
368 
369 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
370                                         raw_ostream &O) {
371   unsigned short Value = MI->getOperand(OpNo).getImm();
372   assert(Value <= 1023 && "Invalid u10imm argument!");
373   O << (unsigned short)Value;
374 }
375 
376 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
377                                         raw_ostream &O) {
378   unsigned short Value = MI->getOperand(OpNo).getImm();
379   assert(Value <= 4095 && "Invalid u12imm argument!");
380   O << (unsigned short)Value;
381 }
382 
383 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
384                                         raw_ostream &O) {
385   if (MI->getOperand(OpNo).isImm())
386     O << (short)MI->getOperand(OpNo).getImm();
387   else
388     printOperand(MI, OpNo, O);
389 }
390 
391 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
392                                         raw_ostream &O) {
393   if (MI->getOperand(OpNo).isImm()) {
394     long long Value = MI->getOperand(OpNo).getImm();
395     assert(isInt<34>(Value) && "Invalid s34imm argument!");
396     O << (long long)Value;
397   }
398   else
399     printOperand(MI, OpNo, O);
400 }
401 
402 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
403                                         raw_ostream &O) {
404   if (MI->getOperand(OpNo).isImm())
405     O << (unsigned short)MI->getOperand(OpNo).getImm();
406   else
407     printOperand(MI, OpNo, O);
408 }
409 
410 void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
411                                         unsigned OpNo, raw_ostream &O) {
412   if (!MI->getOperand(OpNo).isImm())
413     return printOperand(MI, OpNo, O);
414   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
415   if (PrintBranchImmAsAddress) {
416     uint64_t Target = Address + Imm;
417     if (!TT.isPPC64())
418       Target &= 0xffffffff;
419     O << formatHex(Target);
420   } else {
421     // Branches can take an immediate operand. This is used by the branch
422     // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
423     // to express an eight byte displacement from the program counter.
424     if (!TT.isOSAIX())
425       O << ".";
426     else
427       O << "$";
428 
429     if (Imm >= 0)
430       O << "+";
431     O << Imm;
432   }
433 }
434 
435 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
436                                            raw_ostream &O) {
437   if (!MI->getOperand(OpNo).isImm())
438     return printOperand(MI, OpNo, O);
439 
440   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
441 }
442 
443 
444 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
445                                  raw_ostream &O) {
446   unsigned CCReg = MI->getOperand(OpNo).getReg();
447   unsigned RegNo;
448   switch (CCReg) {
449   default: llvm_unreachable("Unknown CR register");
450   case PPC::CR0: RegNo = 0; break;
451   case PPC::CR1: RegNo = 1; break;
452   case PPC::CR2: RegNo = 2; break;
453   case PPC::CR3: RegNo = 3; break;
454   case PPC::CR4: RegNo = 4; break;
455   case PPC::CR5: RegNo = 5; break;
456   case PPC::CR6: RegNo = 6; break;
457   case PPC::CR7: RegNo = 7; break;
458   }
459   O << (0x80 >> RegNo);
460 }
461 
462 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
463                                     raw_ostream &O) {
464   printS16ImmOperand(MI, OpNo, O);
465   O << '(';
466   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
467     O << "0";
468   else
469     printOperand(MI, OpNo+1, O);
470   O << ')';
471 }
472 
473 void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
474                                            raw_ostream &O) {
475   printS34ImmOperand(MI, OpNo, O);
476   O << '(';
477   printImmZeroOperand(MI, OpNo + 1, O);
478   O << ')';
479 }
480 
481 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
482                                         raw_ostream &O) {
483   printS34ImmOperand(MI, OpNo, O);
484   O << '(';
485   printOperand(MI, OpNo + 1, O);
486   O << ')';
487 }
488 
489 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
490                                     raw_ostream &O) {
491   // When used as the base register, r0 reads constant zero rather than
492   // the value contained in the register.  For this reason, the darwin
493   // assembler requires that we print r0 as 0 (no r) when used as the base.
494   if (MI->getOperand(OpNo).getReg() == PPC::R0)
495     O << "0";
496   else
497     printOperand(MI, OpNo, O);
498   O << ", ";
499   printOperand(MI, OpNo+1, O);
500 }
501 
502 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
503                                   raw_ostream &O) {
504   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
505   // come at the _end_ of the expression.
506   const MCOperand &Op = MI->getOperand(OpNo);
507   const MCSymbolRefExpr *RefExp = nullptr;
508   const MCConstantExpr *ConstExp = nullptr;
509   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
510     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
511     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
512   } else
513     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
514 
515   O << RefExp->getSymbol().getName();
516   O << '(';
517   printOperand(MI, OpNo+1, O);
518   O << ')';
519   if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
520     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
521   if (ConstExp != nullptr)
522     O << '+' << ConstExp->getValue();
523 }
524 
525 /// showRegistersWithPercentPrefix - Check if this register name should be
526 /// printed with a percentage symbol as prefix.
527 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
528   if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
529     return false;
530 
531   switch (RegName[0]) {
532   default:
533     return false;
534   case 'r':
535   case 'f':
536   case 'q':
537   case 'v':
538   case 'c':
539     return true;
540   }
541 }
542 
543 /// getVerboseConditionalRegName - This method expands the condition register
544 /// when requested explicitly or targetting Darwin.
545 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
546                                                        unsigned RegEncoding)
547                                                        const {
548   if (!TT.isOSDarwin() && !FullRegNames)
549     return nullptr;
550   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
551     return nullptr;
552   const char *CRBits[] = {
553     "lt", "gt", "eq", "un",
554     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
555     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
556     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
557     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
558     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
559     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
560     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
561   };
562   return CRBits[RegEncoding];
563 }
564 
565 // showRegistersWithPrefix - This method determines whether registers
566 // should be number-only or include the prefix.
567 bool PPCInstPrinter::showRegistersWithPrefix() const {
568   if (TT.getOS() == Triple::AIX)
569     return false;
570   return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
571 }
572 
573 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
574                                   raw_ostream &O) {
575   const MCOperand &Op = MI->getOperand(OpNo);
576   if (Op.isReg()) {
577     unsigned Reg = Op.getReg();
578     if (!ShowVSRNumsAsVR)
579       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
580                                               Reg, OpNo);
581 
582     const char *RegName;
583     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
584     if (RegName == nullptr)
585      RegName = getRegisterName(Reg);
586     if (showRegistersWithPercentPrefix(RegName))
587       O << "%";
588     if (!showRegistersWithPrefix())
589       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
590 
591     O << RegName;
592     return;
593   }
594 
595   if (Op.isImm()) {
596     O << Op.getImm();
597     return;
598   }
599 
600   assert(Op.isExpr() && "unknown operand kind in printOperand");
601   Op.getExpr()->print(O, &MAI);
602 }
603 
604