1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class prints an PPC MCInst to a .s file. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/PPCInstPrinter.h" 14 #include "MCTargetDesc/PPCMCTargetDesc.h" 15 #include "MCTargetDesc/PPCPredicates.h" 16 #include "PPCInstrInfo.h" 17 #include "llvm/CodeGen/TargetOpcodes.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/MC/MCSymbol.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/raw_ostream.h" 26 using namespace llvm; 27 28 #define DEBUG_TYPE "asm-printer" 29 30 // FIXME: Once the integrated assembler supports full register names, tie this 31 // to the verbose-asm setting. 32 static cl::opt<bool> 33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), 34 cl::desc("Use full register names when printing assembly")); 35 36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively. 37 static cl::opt<bool> 38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), 39 cl::desc("Prints full register names with vs{31-63} as v{0-31}")); 40 41 // Prints full register names with percent symbol. 42 static cl::opt<bool> 43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, 44 cl::init(false), 45 cl::desc("Prints full register names with percent")); 46 47 #define PRINT_ALIAS_INSTR 48 #include "PPCGenAsmWriter.inc" 49 50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 51 const char *RegName = getRegisterName(RegNo); 52 OS << RegName; 53 } 54 55 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address, 56 StringRef Annot, const MCSubtargetInfo &STI, 57 raw_ostream &O) { 58 // Customize printing of the addis instruction on AIX. When an operand is a 59 // symbol reference, the instruction syntax is changed to look like a load 60 // operation, i.e: 61 // Transform: addis $rD, $rA, $src --> addis $rD, $src($rA). 62 if (TT.isOSAIX() && 63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && 64 MI->getOperand(2).isExpr()) { 65 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) && 66 "The first and the second operand of an addis instruction" 67 " should be registers."); 68 69 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && 70 "The third operand of an addis instruction should be a symbol " 71 "reference expression if it is an expression at all."); 72 73 O << "\taddis "; 74 printOperand(MI, 0, STI, O); 75 O << ", "; 76 printOperand(MI, 2, STI, O); 77 O << "("; 78 printOperand(MI, 1, STI, O); 79 O << ")"; 80 return; 81 } 82 83 // Check if the last operand is an expression with the variant kind 84 // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization 85 // relocation and the .reloc directive needs to be added. 86 unsigned LastOp = MI->getNumOperands() - 1; 87 if (MI->getNumOperands() > 1) { 88 const MCOperand &Operand = MI->getOperand(LastOp); 89 if (Operand.isExpr()) { 90 const MCExpr *Expr = Operand.getExpr(); 91 const MCSymbolRefExpr *SymExpr = 92 static_cast<const MCSymbolRefExpr *>(Expr); 93 94 if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) { 95 const MCSymbol &Symbol = SymExpr->getSymbol(); 96 if (MI->getOpcode() == PPC::PLDpc) { 97 printInstruction(MI, Address, STI, O); 98 O << "\n"; 99 Symbol.print(O, &MAI); 100 O << ":"; 101 return; 102 } else { 103 O << "\t.reloc "; 104 Symbol.print(O, &MAI); 105 O << "-8,R_PPC64_PCREL_OPT,.-("; 106 Symbol.print(O, &MAI); 107 O << "-8)\n"; 108 } 109 } 110 } 111 } 112 113 // Check for slwi/srwi mnemonics. 114 if (MI->getOpcode() == PPC::RLWINM) { 115 unsigned char SH = MI->getOperand(2).getImm(); 116 unsigned char MB = MI->getOperand(3).getImm(); 117 unsigned char ME = MI->getOperand(4).getImm(); 118 bool useSubstituteMnemonic = false; 119 if (SH <= 31 && MB == 0 && ME == (31-SH)) { 120 O << "\tslwi "; useSubstituteMnemonic = true; 121 } 122 if (SH <= 31 && MB == (32-SH) && ME == 31) { 123 O << "\tsrwi "; useSubstituteMnemonic = true; 124 SH = 32-SH; 125 } 126 if (useSubstituteMnemonic) { 127 printOperand(MI, 0, STI, O); 128 O << ", "; 129 printOperand(MI, 1, STI, O); 130 O << ", " << (unsigned int)SH; 131 132 printAnnotation(O, Annot); 133 return; 134 } 135 } 136 137 if (MI->getOpcode() == PPC::RLDICR || 138 MI->getOpcode() == PPC::RLDICR_32) { 139 unsigned char SH = MI->getOperand(2).getImm(); 140 unsigned char ME = MI->getOperand(3).getImm(); 141 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH 142 if (63-SH == ME) { 143 O << "\tsldi "; 144 printOperand(MI, 0, STI, O); 145 O << ", "; 146 printOperand(MI, 1, STI, O); 147 O << ", " << (unsigned int)SH; 148 printAnnotation(O, Annot); 149 return; 150 } 151 } 152 153 // dcbt[st] is printed manually here because: 154 // 1. The assembly syntax is different between embedded and server targets 155 // 2. We must print the short mnemonics for TH == 0 because the 156 // embedded/server syntax default will not be stable across assemblers 157 // The syntax for dcbt is: 158 // dcbt ra, rb, th [server] 159 // dcbt th, ra, rb [embedded] 160 // where th can be omitted when it is 0. dcbtst is the same. 161 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) { 162 unsigned char TH = MI->getOperand(0).getImm(); 163 O << "\tdcbt"; 164 if (MI->getOpcode() == PPC::DCBTST) 165 O << "st"; 166 if (TH == 16) 167 O << "t"; 168 O << " "; 169 170 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; 171 if (IsBookE && TH != 0 && TH != 16) 172 O << (unsigned int) TH << ", "; 173 174 printOperand(MI, 1, STI, O); 175 O << ", "; 176 printOperand(MI, 2, STI, O); 177 178 if (!IsBookE && TH != 0 && TH != 16) 179 O << ", " << (unsigned int) TH; 180 181 printAnnotation(O, Annot); 182 return; 183 } 184 185 if (MI->getOpcode() == PPC::DCBF) { 186 unsigned char L = MI->getOperand(0).getImm(); 187 if (!L || L == 1 || L == 3 || L == 4 || L == 6) { 188 O << "\tdcb"; 189 if (L != 6) 190 O << "f"; 191 if (L == 1) 192 O << "l"; 193 if (L == 3) 194 O << "lp"; 195 if (L == 4) 196 O << "ps"; 197 if (L == 6) 198 O << "stps"; 199 O << " "; 200 201 printOperand(MI, 1, STI, O); 202 O << ", "; 203 printOperand(MI, 2, STI, O); 204 205 printAnnotation(O, Annot); 206 return; 207 } 208 } 209 210 if (!printAliasInstr(MI, Address, STI, O)) 211 printInstruction(MI, Address, STI, O); 212 printAnnotation(O, Annot); 213 } 214 215 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, 216 const MCSubtargetInfo &STI, 217 raw_ostream &O, 218 const char *Modifier) { 219 unsigned Code = MI->getOperand(OpNo).getImm(); 220 221 if (StringRef(Modifier) == "cc") { 222 switch ((PPC::Predicate)Code) { 223 case PPC::PRED_LT_MINUS: 224 case PPC::PRED_LT_PLUS: 225 case PPC::PRED_LT: 226 O << "lt"; 227 return; 228 case PPC::PRED_LE_MINUS: 229 case PPC::PRED_LE_PLUS: 230 case PPC::PRED_LE: 231 O << "le"; 232 return; 233 case PPC::PRED_EQ_MINUS: 234 case PPC::PRED_EQ_PLUS: 235 case PPC::PRED_EQ: 236 O << "eq"; 237 return; 238 case PPC::PRED_GE_MINUS: 239 case PPC::PRED_GE_PLUS: 240 case PPC::PRED_GE: 241 O << "ge"; 242 return; 243 case PPC::PRED_GT_MINUS: 244 case PPC::PRED_GT_PLUS: 245 case PPC::PRED_GT: 246 O << "gt"; 247 return; 248 case PPC::PRED_NE_MINUS: 249 case PPC::PRED_NE_PLUS: 250 case PPC::PRED_NE: 251 O << "ne"; 252 return; 253 case PPC::PRED_UN_MINUS: 254 case PPC::PRED_UN_PLUS: 255 case PPC::PRED_UN: 256 O << "un"; 257 return; 258 case PPC::PRED_NU_MINUS: 259 case PPC::PRED_NU_PLUS: 260 case PPC::PRED_NU: 261 O << "nu"; 262 return; 263 case PPC::PRED_BIT_SET: 264 case PPC::PRED_BIT_UNSET: 265 llvm_unreachable("Invalid use of bit predicate code"); 266 } 267 llvm_unreachable("Invalid predicate code"); 268 } 269 270 if (StringRef(Modifier) == "pm") { 271 switch ((PPC::Predicate)Code) { 272 case PPC::PRED_LT: 273 case PPC::PRED_LE: 274 case PPC::PRED_EQ: 275 case PPC::PRED_GE: 276 case PPC::PRED_GT: 277 case PPC::PRED_NE: 278 case PPC::PRED_UN: 279 case PPC::PRED_NU: 280 return; 281 case PPC::PRED_LT_MINUS: 282 case PPC::PRED_LE_MINUS: 283 case PPC::PRED_EQ_MINUS: 284 case PPC::PRED_GE_MINUS: 285 case PPC::PRED_GT_MINUS: 286 case PPC::PRED_NE_MINUS: 287 case PPC::PRED_UN_MINUS: 288 case PPC::PRED_NU_MINUS: 289 O << "-"; 290 return; 291 case PPC::PRED_LT_PLUS: 292 case PPC::PRED_LE_PLUS: 293 case PPC::PRED_EQ_PLUS: 294 case PPC::PRED_GE_PLUS: 295 case PPC::PRED_GT_PLUS: 296 case PPC::PRED_NE_PLUS: 297 case PPC::PRED_UN_PLUS: 298 case PPC::PRED_NU_PLUS: 299 O << "+"; 300 return; 301 case PPC::PRED_BIT_SET: 302 case PPC::PRED_BIT_UNSET: 303 llvm_unreachable("Invalid use of bit predicate code"); 304 } 305 llvm_unreachable("Invalid predicate code"); 306 } 307 308 assert(StringRef(Modifier) == "reg" && 309 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!"); 310 printOperand(MI, OpNo + 1, STI, O); 311 } 312 313 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo, 314 const MCSubtargetInfo &STI, 315 raw_ostream &O) { 316 unsigned Code = MI->getOperand(OpNo).getImm(); 317 if (Code == 2) 318 O << "-"; 319 else if (Code == 3) 320 O << "+"; 321 } 322 323 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo, 324 const MCSubtargetInfo &STI, 325 raw_ostream &O) { 326 unsigned int Value = MI->getOperand(OpNo).getImm(); 327 assert(Value <= 1 && "Invalid u1imm argument!"); 328 O << (unsigned int)Value; 329 } 330 331 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, 332 const MCSubtargetInfo &STI, 333 raw_ostream &O) { 334 unsigned int Value = MI->getOperand(OpNo).getImm(); 335 assert(Value <= 3 && "Invalid u2imm argument!"); 336 O << (unsigned int)Value; 337 } 338 339 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo, 340 const MCSubtargetInfo &STI, 341 raw_ostream &O) { 342 unsigned int Value = MI->getOperand(OpNo).getImm(); 343 assert(Value <= 8 && "Invalid u3imm argument!"); 344 O << (unsigned int)Value; 345 } 346 347 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, 348 const MCSubtargetInfo &STI, 349 raw_ostream &O) { 350 unsigned int Value = MI->getOperand(OpNo).getImm(); 351 assert(Value <= 15 && "Invalid u4imm argument!"); 352 O << (unsigned int)Value; 353 } 354 355 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, 356 const MCSubtargetInfo &STI, 357 raw_ostream &O) { 358 int Value = MI->getOperand(OpNo).getImm(); 359 Value = SignExtend32<5>(Value); 360 O << (int)Value; 361 } 362 363 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo, 364 const MCSubtargetInfo &STI, 365 raw_ostream &O) { 366 unsigned int Value = MI->getOperand(OpNo).getImm(); 367 assert(Value == 0 && "Operand must be zero"); 368 O << (unsigned int)Value; 369 } 370 371 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo, 372 const MCSubtargetInfo &STI, 373 raw_ostream &O) { 374 unsigned int Value = MI->getOperand(OpNo).getImm(); 375 assert(Value <= 31 && "Invalid u5imm argument!"); 376 O << (unsigned int)Value; 377 } 378 379 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo, 380 const MCSubtargetInfo &STI, 381 raw_ostream &O) { 382 unsigned int Value = MI->getOperand(OpNo).getImm(); 383 assert(Value <= 63 && "Invalid u6imm argument!"); 384 O << (unsigned int)Value; 385 } 386 387 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo, 388 const MCSubtargetInfo &STI, 389 raw_ostream &O) { 390 unsigned int Value = MI->getOperand(OpNo).getImm(); 391 assert(Value <= 127 && "Invalid u7imm argument!"); 392 O << (unsigned int)Value; 393 } 394 395 // Operands of BUILD_VECTOR are signed and we use this to print operands 396 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and 397 // print as unsigned. 398 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, 399 const MCSubtargetInfo &STI, 400 raw_ostream &O) { 401 unsigned char Value = MI->getOperand(OpNo).getImm(); 402 O << (unsigned int)Value; 403 } 404 405 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo, 406 const MCSubtargetInfo &STI, 407 raw_ostream &O) { 408 unsigned short Value = MI->getOperand(OpNo).getImm(); 409 assert(Value <= 1023 && "Invalid u10imm argument!"); 410 O << (unsigned short)Value; 411 } 412 413 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo, 414 const MCSubtargetInfo &STI, 415 raw_ostream &O) { 416 unsigned short Value = MI->getOperand(OpNo).getImm(); 417 assert(Value <= 4095 && "Invalid u12imm argument!"); 418 O << (unsigned short)Value; 419 } 420 421 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, 422 const MCSubtargetInfo &STI, 423 raw_ostream &O) { 424 if (MI->getOperand(OpNo).isImm()) 425 O << (short)MI->getOperand(OpNo).getImm(); 426 else 427 printOperand(MI, OpNo, STI, O); 428 } 429 430 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo, 431 const MCSubtargetInfo &STI, 432 raw_ostream &O) { 433 if (MI->getOperand(OpNo).isImm()) { 434 long long Value = MI->getOperand(OpNo).getImm(); 435 assert(isInt<34>(Value) && "Invalid s34imm argument!"); 436 O << (long long)Value; 437 } 438 else 439 printOperand(MI, OpNo, STI, O); 440 } 441 442 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, 443 const MCSubtargetInfo &STI, 444 raw_ostream &O) { 445 if (MI->getOperand(OpNo).isImm()) 446 O << (unsigned short)MI->getOperand(OpNo).getImm(); 447 else 448 printOperand(MI, OpNo, STI, O); 449 } 450 451 void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, 452 unsigned OpNo, 453 const MCSubtargetInfo &STI, 454 raw_ostream &O) { 455 if (!MI->getOperand(OpNo).isImm()) 456 return printOperand(MI, OpNo, STI, O); 457 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2); 458 if (PrintBranchImmAsAddress) { 459 uint64_t Target = Address + Imm; 460 if (!TT.isPPC64()) 461 Target &= 0xffffffff; 462 O << formatHex(Target); 463 } else { 464 // Branches can take an immediate operand. This is used by the branch 465 // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX) 466 // to express an eight byte displacement from the program counter. 467 if (!TT.isOSAIX()) 468 O << "."; 469 else 470 O << "$"; 471 472 if (Imm >= 0) 473 O << "+"; 474 O << Imm; 475 } 476 } 477 478 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo, 479 const MCSubtargetInfo &STI, 480 raw_ostream &O) { 481 if (!MI->getOperand(OpNo).isImm()) 482 return printOperand(MI, OpNo, STI, O); 483 484 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2); 485 } 486 487 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo, 488 const MCSubtargetInfo &STI, raw_ostream &O) { 489 unsigned CCReg = MI->getOperand(OpNo).getReg(); 490 unsigned RegNo; 491 switch (CCReg) { 492 default: llvm_unreachable("Unknown CR register"); 493 case PPC::CR0: RegNo = 0; break; 494 case PPC::CR1: RegNo = 1; break; 495 case PPC::CR2: RegNo = 2; break; 496 case PPC::CR3: RegNo = 3; break; 497 case PPC::CR4: RegNo = 4; break; 498 case PPC::CR5: RegNo = 5; break; 499 case PPC::CR6: RegNo = 6; break; 500 case PPC::CR7: RegNo = 7; break; 501 } 502 O << (0x80 >> RegNo); 503 } 504 505 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo, 506 const MCSubtargetInfo &STI, 507 raw_ostream &O) { 508 printS16ImmOperand(MI, OpNo, STI, O); 509 O << '('; 510 if (MI->getOperand(OpNo+1).getReg() == PPC::R0) 511 O << "0"; 512 else 513 printOperand(MI, OpNo + 1, STI, O); 514 O << ')'; 515 } 516 517 void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, 518 const MCSubtargetInfo &STI, 519 raw_ostream &O) { 520 printS34ImmOperand(MI, OpNo, STI, O); 521 O << '('; 522 printImmZeroOperand(MI, OpNo + 1, STI, O); 523 O << ')'; 524 } 525 526 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo, 527 const MCSubtargetInfo &STI, 528 raw_ostream &O) { 529 printS34ImmOperand(MI, OpNo, STI, O); 530 O << '('; 531 printOperand(MI, OpNo + 1, STI, O); 532 O << ')'; 533 } 534 535 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo, 536 const MCSubtargetInfo &STI, 537 raw_ostream &O) { 538 // When used as the base register, r0 reads constant zero rather than 539 // the value contained in the register. For this reason, the darwin 540 // assembler requires that we print r0 as 0 (no r) when used as the base. 541 if (MI->getOperand(OpNo).getReg() == PPC::R0) 542 O << "0"; 543 else 544 printOperand(MI, OpNo, STI, O); 545 O << ", "; 546 printOperand(MI, OpNo + 1, STI, O); 547 } 548 549 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo, 550 const MCSubtargetInfo &STI, raw_ostream &O) { 551 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must 552 // come at the _end_ of the expression. 553 const MCOperand &Op = MI->getOperand(OpNo); 554 const MCSymbolRefExpr *RefExp = nullptr; 555 const MCConstantExpr *ConstExp = nullptr; 556 if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) { 557 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS()); 558 ConstExp = cast<MCConstantExpr>(BinExpr->getRHS()); 559 } else 560 RefExp = cast<MCSymbolRefExpr>(Op.getExpr()); 561 562 O << RefExp->getSymbol().getName(); 563 // The variant kind VK_PPC_NOTOC needs to be handled as a special case 564 // because we do not want the assembly to print out the @notoc at the 565 // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look 566 // like __tls_get_addr@notoc(x@tlsgd). 567 if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC) 568 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind()); 569 O << '('; 570 printOperand(MI, OpNo + 1, STI, O); 571 O << ')'; 572 if (RefExp->getKind() != MCSymbolRefExpr::VK_None && 573 RefExp->getKind() != MCSymbolRefExpr::VK_PPC_NOTOC) 574 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind()); 575 if (ConstExp != nullptr) 576 O << '+' << ConstExp->getValue(); 577 } 578 579 /// showRegistersWithPercentPrefix - Check if this register name should be 580 /// printed with a percentage symbol as prefix. 581 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { 582 if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX) 583 return false; 584 585 switch (RegName[0]) { 586 default: 587 return false; 588 case 'r': 589 case 'f': 590 case 'q': 591 case 'v': 592 case 'c': 593 return true; 594 } 595 } 596 597 /// getVerboseConditionalRegName - This method expands the condition register 598 /// when requested explicitly or targetting Darwin. 599 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, 600 unsigned RegEncoding) 601 const { 602 if (!FullRegNames) 603 return nullptr; 604 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN) 605 return nullptr; 606 const char *CRBits[] = { 607 "lt", "gt", "eq", "un", 608 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un", 609 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un", 610 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un", 611 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un", 612 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un", 613 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un", 614 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un" 615 }; 616 return CRBits[RegEncoding]; 617 } 618 619 // showRegistersWithPrefix - This method determines whether registers 620 // should be number-only or include the prefix. 621 bool PPCInstPrinter::showRegistersWithPrefix() const { 622 if (TT.getOS() == Triple::AIX) 623 return false; 624 return FullRegNamesWithPercent || FullRegNames; 625 } 626 627 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 628 const MCSubtargetInfo &STI, raw_ostream &O) { 629 const MCOperand &Op = MI->getOperand(OpNo); 630 if (Op.isReg()) { 631 unsigned Reg = Op.getReg(); 632 if (!ShowVSRNumsAsVR) 633 Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()), 634 Reg, OpNo); 635 636 const char *RegName; 637 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); 638 if (RegName == nullptr) 639 RegName = getRegisterName(Reg); 640 if (showRegistersWithPercentPrefix(RegName)) 641 O << "%"; 642 if (!showRegistersWithPrefix()) 643 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); 644 645 O << RegName; 646 return; 647 } 648 649 if (Op.isImm()) { 650 O << Op.getImm(); 651 return; 652 } 653 654 assert(Op.isExpr() && "unknown operand kind in printOperand"); 655 Op.getExpr()->print(O, &MAI); 656 } 657