xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp (revision 162ae9c834f6d9f9cb443bd62cceb23e0b5fef48)
1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34              cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44                         cl::init(false),
45                         cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51   const char *RegName = getRegisterName(RegNo);
52   if (RegName[0] == 'q' /* QPX */) {
53     // The system toolchain on the BG/Q does not understand QPX register names
54     // in .cfi_* directives, so print the name of the floating-point
55     // subregister instead.
56     std::string RN(RegName);
57 
58     RN[0] = 'f';
59     OS << RN;
60 
61     return;
62   }
63 
64   OS << RegName;
65 }
66 
67 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
68                                StringRef Annot, const MCSubtargetInfo &STI) {
69   // Check for slwi/srwi mnemonics.
70   if (MI->getOpcode() == PPC::RLWINM) {
71     unsigned char SH = MI->getOperand(2).getImm();
72     unsigned char MB = MI->getOperand(3).getImm();
73     unsigned char ME = MI->getOperand(4).getImm();
74     bool useSubstituteMnemonic = false;
75     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
76       O << "\tslwi "; useSubstituteMnemonic = true;
77     }
78     if (SH <= 31 && MB == (32-SH) && ME == 31) {
79       O << "\tsrwi "; useSubstituteMnemonic = true;
80       SH = 32-SH;
81     }
82     if (useSubstituteMnemonic) {
83       printOperand(MI, 0, O);
84       O << ", ";
85       printOperand(MI, 1, O);
86       O << ", " << (unsigned int)SH;
87 
88       printAnnotation(O, Annot);
89       return;
90     }
91   }
92 
93   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
94       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
95     O << "\tmr ";
96     printOperand(MI, 0, O);
97     O << ", ";
98     printOperand(MI, 1, O);
99     printAnnotation(O, Annot);
100     return;
101   }
102 
103   if (MI->getOpcode() == PPC::RLDICR ||
104       MI->getOpcode() == PPC::RLDICR_32) {
105     unsigned char SH = MI->getOperand(2).getImm();
106     unsigned char ME = MI->getOperand(3).getImm();
107     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
108     if (63-SH == ME) {
109       O << "\tsldi ";
110       printOperand(MI, 0, O);
111       O << ", ";
112       printOperand(MI, 1, O);
113       O << ", " << (unsigned int)SH;
114       printAnnotation(O, Annot);
115       return;
116     }
117   }
118 
119   // dcbt[st] is printed manually here because:
120   //  1. The assembly syntax is different between embedded and server targets
121   //  2. We must print the short mnemonics for TH == 0 because the
122   //     embedded/server syntax default will not be stable across assemblers
123   //  The syntax for dcbt is:
124   //    dcbt ra, rb, th [server]
125   //    dcbt th, ra, rb [embedded]
126   //  where th can be omitted when it is 0. dcbtst is the same.
127   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
128     unsigned char TH = MI->getOperand(0).getImm();
129     O << "\tdcbt";
130     if (MI->getOpcode() == PPC::DCBTST)
131       O << "st";
132     if (TH == 16)
133       O << "t";
134     O << " ";
135 
136     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
137     if (IsBookE && TH != 0 && TH != 16)
138       O << (unsigned int) TH << ", ";
139 
140     printOperand(MI, 1, O);
141     O << ", ";
142     printOperand(MI, 2, O);
143 
144     if (!IsBookE && TH != 0 && TH != 16)
145       O << ", " << (unsigned int) TH;
146 
147     printAnnotation(O, Annot);
148     return;
149   }
150 
151   if (MI->getOpcode() == PPC::DCBF) {
152     unsigned char L = MI->getOperand(0).getImm();
153     if (!L || L == 1 || L == 3) {
154       O << "\tdcbf";
155       if (L == 1 || L == 3)
156         O << "l";
157       if (L == 3)
158         O << "p";
159       O << " ";
160 
161       printOperand(MI, 1, O);
162       O << ", ";
163       printOperand(MI, 2, O);
164 
165       printAnnotation(O, Annot);
166       return;
167     }
168   }
169 
170   if (!printAliasInstr(MI, O))
171     printInstruction(MI, O);
172   printAnnotation(O, Annot);
173 }
174 
175 
176 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
177                                            raw_ostream &O,
178                                            const char *Modifier) {
179   unsigned Code = MI->getOperand(OpNo).getImm();
180 
181   if (StringRef(Modifier) == "cc") {
182     switch ((PPC::Predicate)Code) {
183     case PPC::PRED_LT_MINUS:
184     case PPC::PRED_LT_PLUS:
185     case PPC::PRED_LT:
186       O << "lt";
187       return;
188     case PPC::PRED_LE_MINUS:
189     case PPC::PRED_LE_PLUS:
190     case PPC::PRED_LE:
191       O << "le";
192       return;
193     case PPC::PRED_EQ_MINUS:
194     case PPC::PRED_EQ_PLUS:
195     case PPC::PRED_EQ:
196       O << "eq";
197       return;
198     case PPC::PRED_GE_MINUS:
199     case PPC::PRED_GE_PLUS:
200     case PPC::PRED_GE:
201       O << "ge";
202       return;
203     case PPC::PRED_GT_MINUS:
204     case PPC::PRED_GT_PLUS:
205     case PPC::PRED_GT:
206       O << "gt";
207       return;
208     case PPC::PRED_NE_MINUS:
209     case PPC::PRED_NE_PLUS:
210     case PPC::PRED_NE:
211       O << "ne";
212       return;
213     case PPC::PRED_UN_MINUS:
214     case PPC::PRED_UN_PLUS:
215     case PPC::PRED_UN:
216       O << "un";
217       return;
218     case PPC::PRED_NU_MINUS:
219     case PPC::PRED_NU_PLUS:
220     case PPC::PRED_NU:
221       O << "nu";
222       return;
223     case PPC::PRED_BIT_SET:
224     case PPC::PRED_BIT_UNSET:
225       llvm_unreachable("Invalid use of bit predicate code");
226     }
227     llvm_unreachable("Invalid predicate code");
228   }
229 
230   if (StringRef(Modifier) == "pm") {
231     switch ((PPC::Predicate)Code) {
232     case PPC::PRED_LT:
233     case PPC::PRED_LE:
234     case PPC::PRED_EQ:
235     case PPC::PRED_GE:
236     case PPC::PRED_GT:
237     case PPC::PRED_NE:
238     case PPC::PRED_UN:
239     case PPC::PRED_NU:
240       return;
241     case PPC::PRED_LT_MINUS:
242     case PPC::PRED_LE_MINUS:
243     case PPC::PRED_EQ_MINUS:
244     case PPC::PRED_GE_MINUS:
245     case PPC::PRED_GT_MINUS:
246     case PPC::PRED_NE_MINUS:
247     case PPC::PRED_UN_MINUS:
248     case PPC::PRED_NU_MINUS:
249       O << "-";
250       return;
251     case PPC::PRED_LT_PLUS:
252     case PPC::PRED_LE_PLUS:
253     case PPC::PRED_EQ_PLUS:
254     case PPC::PRED_GE_PLUS:
255     case PPC::PRED_GT_PLUS:
256     case PPC::PRED_NE_PLUS:
257     case PPC::PRED_UN_PLUS:
258     case PPC::PRED_NU_PLUS:
259       O << "+";
260       return;
261     case PPC::PRED_BIT_SET:
262     case PPC::PRED_BIT_UNSET:
263       llvm_unreachable("Invalid use of bit predicate code");
264     }
265     llvm_unreachable("Invalid predicate code");
266   }
267 
268   assert(StringRef(Modifier) == "reg" &&
269          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
270   printOperand(MI, OpNo+1, O);
271 }
272 
273 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
274                                        raw_ostream &O) {
275   unsigned Code = MI->getOperand(OpNo).getImm();
276   if (Code == 2)
277     O << "-";
278   else if (Code == 3)
279     O << "+";
280 }
281 
282 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
283                                        raw_ostream &O) {
284   unsigned int Value = MI->getOperand(OpNo).getImm();
285   assert(Value <= 1 && "Invalid u1imm argument!");
286   O << (unsigned int)Value;
287 }
288 
289 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
290                                        raw_ostream &O) {
291   unsigned int Value = MI->getOperand(OpNo).getImm();
292   assert(Value <= 3 && "Invalid u2imm argument!");
293   O << (unsigned int)Value;
294 }
295 
296 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
297                                        raw_ostream &O) {
298   unsigned int Value = MI->getOperand(OpNo).getImm();
299   assert(Value <= 8 && "Invalid u3imm argument!");
300   O << (unsigned int)Value;
301 }
302 
303 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
304                                        raw_ostream &O) {
305   unsigned int Value = MI->getOperand(OpNo).getImm();
306   assert(Value <= 15 && "Invalid u4imm argument!");
307   O << (unsigned int)Value;
308 }
309 
310 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
311                                        raw_ostream &O) {
312   int Value = MI->getOperand(OpNo).getImm();
313   Value = SignExtend32<5>(Value);
314   O << (int)Value;
315 }
316 
317 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
318                                        raw_ostream &O) {
319   unsigned int Value = MI->getOperand(OpNo).getImm();
320   assert(Value <= 31 && "Invalid u5imm argument!");
321   O << (unsigned int)Value;
322 }
323 
324 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
325                                        raw_ostream &O) {
326   unsigned int Value = MI->getOperand(OpNo).getImm();
327   assert(Value <= 63 && "Invalid u6imm argument!");
328   O << (unsigned int)Value;
329 }
330 
331 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
332                                        raw_ostream &O) {
333   unsigned int Value = MI->getOperand(OpNo).getImm();
334   assert(Value <= 127 && "Invalid u7imm argument!");
335   O << (unsigned int)Value;
336 }
337 
338 // Operands of BUILD_VECTOR are signed and we use this to print operands
339 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
340 // print as unsigned.
341 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
342                                        raw_ostream &O) {
343   unsigned char Value = MI->getOperand(OpNo).getImm();
344   O << (unsigned int)Value;
345 }
346 
347 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
348                                         raw_ostream &O) {
349   unsigned short Value = MI->getOperand(OpNo).getImm();
350   assert(Value <= 1023 && "Invalid u10imm argument!");
351   O << (unsigned short)Value;
352 }
353 
354 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
355                                         raw_ostream &O) {
356   unsigned short Value = MI->getOperand(OpNo).getImm();
357   assert(Value <= 4095 && "Invalid u12imm argument!");
358   O << (unsigned short)Value;
359 }
360 
361 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
362                                         raw_ostream &O) {
363   if (MI->getOperand(OpNo).isImm())
364     O << (short)MI->getOperand(OpNo).getImm();
365   else
366     printOperand(MI, OpNo, O);
367 }
368 
369 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
370                                         raw_ostream &O) {
371   if (MI->getOperand(OpNo).isImm())
372     O << (unsigned short)MI->getOperand(OpNo).getImm();
373   else
374     printOperand(MI, OpNo, O);
375 }
376 
377 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
378                                         raw_ostream &O) {
379   if (!MI->getOperand(OpNo).isImm())
380     return printOperand(MI, OpNo, O);
381 
382   // Branches can take an immediate operand.  This is used by the branch
383   // selection pass to print .+8, an eight byte displacement from the PC.
384   O << ".";
385   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
386   if (Imm >= 0)
387     O << "+";
388   O << Imm;
389 }
390 
391 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
392                                            raw_ostream &O) {
393   if (!MI->getOperand(OpNo).isImm())
394     return printOperand(MI, OpNo, O);
395 
396   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
397 }
398 
399 
400 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
401                                  raw_ostream &O) {
402   unsigned CCReg = MI->getOperand(OpNo).getReg();
403   unsigned RegNo;
404   switch (CCReg) {
405   default: llvm_unreachable("Unknown CR register");
406   case PPC::CR0: RegNo = 0; break;
407   case PPC::CR1: RegNo = 1; break;
408   case PPC::CR2: RegNo = 2; break;
409   case PPC::CR3: RegNo = 3; break;
410   case PPC::CR4: RegNo = 4; break;
411   case PPC::CR5: RegNo = 5; break;
412   case PPC::CR6: RegNo = 6; break;
413   case PPC::CR7: RegNo = 7; break;
414   }
415   O << (0x80 >> RegNo);
416 }
417 
418 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
419                                     raw_ostream &O) {
420   printS16ImmOperand(MI, OpNo, O);
421   O << '(';
422   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
423     O << "0";
424   else
425     printOperand(MI, OpNo+1, O);
426   O << ')';
427 }
428 
429 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
430                                     raw_ostream &O) {
431   // When used as the base register, r0 reads constant zero rather than
432   // the value contained in the register.  For this reason, the darwin
433   // assembler requires that we print r0 as 0 (no r) when used as the base.
434   if (MI->getOperand(OpNo).getReg() == PPC::R0)
435     O << "0";
436   else
437     printOperand(MI, OpNo, O);
438   O << ", ";
439   printOperand(MI, OpNo+1, O);
440 }
441 
442 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
443                                   raw_ostream &O) {
444   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
445   // come at the _end_ of the expression.
446   const MCOperand &Op = MI->getOperand(OpNo);
447   const MCSymbolRefExpr *RefExp = nullptr;
448   const MCConstantExpr *ConstExp = nullptr;
449   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
450     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
451     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
452   } else
453     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
454 
455   O << RefExp->getSymbol().getName();
456   O << '(';
457   printOperand(MI, OpNo+1, O);
458   O << ')';
459   if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
460     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
461   if (ConstExp != nullptr)
462     O << '+' << ConstExp->getValue();
463 }
464 
465 /// showRegistersWithPercentPrefix - Check if this register name should be
466 /// printed with a percentage symbol as prefix.
467 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
468   if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
469     return false;
470 
471   switch (RegName[0]) {
472   default:
473     return false;
474   case 'r':
475   case 'f':
476   case 'q':
477   case 'v':
478   case 'c':
479     return true;
480   }
481 }
482 
483 /// getVerboseConditionalRegName - This method expands the condition register
484 /// when requested explicitly or targetting Darwin.
485 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
486                                                        unsigned RegEncoding)
487                                                        const {
488   if (!TT.isOSDarwin() && !FullRegNames)
489     return nullptr;
490   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
491     return nullptr;
492   const char *CRBits[] = {
493     "lt", "gt", "eq", "un",
494     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
495     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
496     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
497     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
498     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
499     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
500     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
501   };
502   return CRBits[RegEncoding];
503 }
504 
505 // showRegistersWithPrefix - This method determines whether registers
506 // should be number-only or include the prefix.
507 bool PPCInstPrinter::showRegistersWithPrefix() const {
508   if (TT.getOS() == Triple::AIX)
509     return false;
510   return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
511 }
512 
513 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
514                                   raw_ostream &O) {
515   const MCOperand &Op = MI->getOperand(OpNo);
516   if (Op.isReg()) {
517     unsigned Reg = Op.getReg();
518     if (!ShowVSRNumsAsVR)
519       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
520                                               Reg, OpNo);
521 
522     const char *RegName;
523     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
524     if (RegName == nullptr)
525      RegName = getRegisterName(Reg);
526     if (showRegistersWithPercentPrefix(RegName))
527       O << "%";
528     if (!showRegistersWithPrefix())
529       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
530 
531     O << RegName;
532     return;
533   }
534 
535   if (Op.isImm()) {
536     O << Op.getImm();
537     return;
538   }
539 
540   assert(Op.isExpr() && "unknown operand kind in printOperand");
541   Op.getExpr()->print(O, &MAI);
542 }
543 
544