xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h (revision 911f0260390e18cf85f3dbf2c719b593efdc1e3c)
1 //===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCFIXUPKINDS_H
10 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCFIXUPKINDS_H
11 
12 #include "llvm/MC/MCFixup.h"
13 
14 #undef PPC
15 
16 namespace llvm {
17 namespace PPC {
18 enum Fixups {
19   // 24-bit PC relative relocation for direct branches like 'b' and 'bl'.
20   fixup_ppc_br24 = FirstTargetFixupKind,
21 
22   // 24-bit PC relative relocation for direct branches like 'b' and 'bl' where
23   // the caller does not use the TOC.
24   fixup_ppc_br24_notoc,
25 
26   /// 14-bit PC relative relocation for conditional branches.
27   fixup_ppc_brcond14,
28 
29   /// 24-bit absolute relocation for direct branches like 'ba' and 'bla'.
30   fixup_ppc_br24abs,
31 
32   /// 14-bit absolute relocation for conditional branches.
33   fixup_ppc_brcond14abs,
34 
35   /// A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like
36   /// 'li' or 'addis'.
37   fixup_ppc_half16,
38 
39   /// A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for
40   /// instrs like 'std'.
41   fixup_ppc_half16ds,
42 
43   // A 34-bit fixup corresponding to PC-relative paddi.
44   fixup_ppc_pcrel34,
45 
46   // A 34-bit fixup corresponding to Non-PC-relative paddi.
47   fixup_ppc_imm34,
48 
49   /// Not a true fixup, but ties a symbol to a call to __tls_get_addr for the
50   /// TLS general and local dynamic models, or inserts the thread-pointer
51   /// register number.
52   fixup_ppc_nofixup,
53 
54   /// A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for
55   /// instrs like 'lxv'. Produces the same relocation as fixup_ppc_half16ds.
56   fixup_ppc_half16dq,
57 
58   // Marker
59   LastTargetFixupKind,
60   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
61 };
62 }
63 }
64 
65 #endif
66