1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES; 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 58 createPPCDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 60 createPPCLEDisassembler); 61 } 62 63 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, 64 uint64_t /*Address*/, 65 const void * /*Decoder*/) { 66 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); 67 return MCDisassembler::Success; 68 } 69 70 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, 71 uint64_t /*Address*/, 72 const void * /*Decoder*/) { 73 int32_t Offset = SignExtend32<24>(Imm); 74 Inst.addOperand(MCOperand::createImm(Offset)); 75 return MCDisassembler::Success; 76 } 77 78 // FIXME: These can be generated by TableGen from the existing register 79 // encoding values! 80 81 template <std::size_t N> 82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 83 const MCPhysReg (&Regs)[N]) { 84 assert(RegNo < N && "Invalid register number"); 85 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 86 return MCDisassembler::Success; 87 } 88 89 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 90 uint64_t Address, 91 const void *Decoder) { 92 return decodeRegisterClass(Inst, RegNo, CRRegs); 93 } 94 95 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 96 uint64_t Address, 97 const void *Decoder) { 98 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 99 } 100 101 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 102 uint64_t Address, 103 const void *Decoder) { 104 return decodeRegisterClass(Inst, RegNo, FRegs); 105 } 106 107 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 108 uint64_t Address, 109 const void *Decoder) { 110 return decodeRegisterClass(Inst, RegNo, FRegs); 111 } 112 113 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 114 uint64_t Address, 115 const void *Decoder) { 116 return decodeRegisterClass(Inst, RegNo, VFRegs); 117 } 118 119 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 120 uint64_t Address, 121 const void *Decoder) { 122 return decodeRegisterClass(Inst, RegNo, VRegs); 123 } 124 125 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 126 uint64_t Address, 127 const void *Decoder) { 128 return decodeRegisterClass(Inst, RegNo, VSRegs); 129 } 130 131 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 132 uint64_t Address, 133 const void *Decoder) { 134 return decodeRegisterClass(Inst, RegNo, VSFRegs); 135 } 136 137 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 138 uint64_t Address, 139 const void *Decoder) { 140 return decodeRegisterClass(Inst, RegNo, VSSRegs); 141 } 142 143 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 144 uint64_t Address, 145 const void *Decoder) { 146 return decodeRegisterClass(Inst, RegNo, RRegs); 147 } 148 149 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 150 uint64_t Address, 151 const void *Decoder) { 152 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 153 } 154 155 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 156 uint64_t Address, 157 const void *Decoder) { 158 return decodeRegisterClass(Inst, RegNo, XRegs); 159 } 160 161 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 162 uint64_t Address, 163 const void *Decoder) { 164 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 165 } 166 167 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 168 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 169 170 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 171 uint64_t Address, 172 const void *Decoder) { 173 return decodeRegisterClass(Inst, RegNo, QFRegs); 174 } 175 176 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 177 uint64_t Address, 178 const void *Decoder) { 179 return decodeRegisterClass(Inst, RegNo, SPERegs); 180 } 181 182 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 183 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 184 185 template<unsigned N> 186 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 187 int64_t Address, const void *Decoder) { 188 assert(isUInt<N>(Imm) && "Invalid immediate"); 189 Inst.addOperand(MCOperand::createImm(Imm)); 190 return MCDisassembler::Success; 191 } 192 193 template<unsigned N> 194 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 195 int64_t Address, const void *Decoder) { 196 assert(isUInt<N>(Imm) && "Invalid immediate"); 197 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 198 return MCDisassembler::Success; 199 } 200 201 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, 202 int64_t Address, const void *Decoder) { 203 if (Imm != 0) 204 return MCDisassembler::Fail; 205 Inst.addOperand(MCOperand::createImm(Imm)); 206 return MCDisassembler::Success; 207 } 208 209 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 210 int64_t Address, const void *Decoder) { 211 // Decode the memri field (imm, reg), which has the low 16-bits as the 212 // displacement and the next 5 bits as the register #. 213 214 uint64_t Base = Imm >> 16; 215 uint64_t Disp = Imm & 0xFFFF; 216 217 assert(Base < 32 && "Invalid base register"); 218 219 switch (Inst.getOpcode()) { 220 default: break; 221 case PPC::LBZU: 222 case PPC::LHAU: 223 case PPC::LHZU: 224 case PPC::LWZU: 225 case PPC::LFSU: 226 case PPC::LFDU: 227 // Add the tied output operand. 228 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 229 break; 230 case PPC::STBU: 231 case PPC::STHU: 232 case PPC::STWU: 233 case PPC::STFSU: 234 case PPC::STFDU: 235 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 236 break; 237 } 238 239 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 240 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 241 return MCDisassembler::Success; 242 } 243 244 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 245 int64_t Address, const void *Decoder) { 246 // Decode the memrix field (imm, reg), which has the low 14-bits as the 247 // displacement and the next 5 bits as the register #. 248 249 uint64_t Base = Imm >> 14; 250 uint64_t Disp = Imm & 0x3FFF; 251 252 assert(Base < 32 && "Invalid base register"); 253 254 if (Inst.getOpcode() == PPC::LDU) 255 // Add the tied output operand. 256 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 257 else if (Inst.getOpcode() == PPC::STDU) 258 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 259 260 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 261 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 262 return MCDisassembler::Success; 263 } 264 265 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 266 int64_t Address, const void *Decoder) { 267 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 268 // displacement with 16-byte aligned, and the next 5 bits as the register #. 269 270 uint64_t Base = Imm >> 12; 271 uint64_t Disp = Imm & 0xFFF; 272 273 assert(Base < 32 && "Invalid base register"); 274 275 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 276 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 277 return MCDisassembler::Success; 278 } 279 280 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, 281 int64_t Address, 282 const void *Decoder) { 283 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the 284 // displacement, and the next 5 bits as an immediate 0. 285 uint64_t Base = Imm >> 34; 286 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 287 288 assert(Base < 32 && "Invalid base register"); 289 290 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 291 return decodeImmZeroOperand(Inst, Base, Address, Decoder); 292 } 293 294 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, 295 int64_t Address, 296 const void *Decoder) { 297 // Decode the memri34 field (imm, reg), which has the low 34-bits as the 298 // displacement, and the next 5 bits as the register #. 299 uint64_t Base = Imm >> 34; 300 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 301 302 assert(Base < 32 && "Invalid base register"); 303 304 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 305 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 306 return MCDisassembler::Success; 307 } 308 309 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 310 int64_t Address, const void *Decoder) { 311 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 312 // displacement with 8-byte aligned, and the next 5 bits as the register #. 313 314 uint64_t Base = Imm >> 5; 315 uint64_t Disp = Imm & 0x1F; 316 317 assert(Base < 32 && "Invalid base register"); 318 319 Inst.addOperand(MCOperand::createImm(Disp << 3)); 320 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 321 return MCDisassembler::Success; 322 } 323 324 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 325 int64_t Address, const void *Decoder) { 326 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 327 // displacement with 4-byte aligned, and the next 5 bits as the register #. 328 329 uint64_t Base = Imm >> 5; 330 uint64_t Disp = Imm & 0x1F; 331 332 assert(Base < 32 && "Invalid base register"); 333 334 Inst.addOperand(MCOperand::createImm(Disp << 2)); 335 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 336 return MCDisassembler::Success; 337 } 338 339 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 340 int64_t Address, const void *Decoder) { 341 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 342 // displacement with 2-byte aligned, and the next 5 bits as the register #. 343 344 uint64_t Base = Imm >> 5; 345 uint64_t Disp = Imm & 0x1F; 346 347 assert(Base < 32 && "Invalid base register"); 348 349 Inst.addOperand(MCOperand::createImm(Disp << 1)); 350 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 351 return MCDisassembler::Success; 352 } 353 354 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 355 int64_t Address, const void *Decoder) { 356 // The cr bit encoding is 0x80 >> cr_reg_num. 357 358 unsigned Zeros = countTrailingZeros(Imm); 359 assert(Zeros < 8 && "Invalid CR bit value"); 360 361 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 362 return MCDisassembler::Success; 363 } 364 365 #include "PPCGenDisassemblerTables.inc" 366 367 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 368 ArrayRef<uint8_t> Bytes, 369 uint64_t Address, 370 raw_ostream &CS) const { 371 auto *ReadFunc = IsLittleEndian ? support::endian::read32le 372 : support::endian::read32be; 373 374 // If this is an 8-byte prefixed instruction, handle it here. 375 // Note: prefixed instructions aren't technically 8-byte entities - the prefix 376 // appears in memory at an address 4 bytes prior to that of the base 377 // instruction regardless of endianness. So we read the two pieces and 378 // rebuild the 8-byte instruction. 379 // TODO: In this function we call decodeInstruction several times with 380 // different decoder tables. It may be possible to only call once by 381 // looking at the top 6 bits of the instruction. 382 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) { 383 uint32_t Prefix = ReadFunc(Bytes.data()); 384 uint32_t BaseInst = ReadFunc(Bytes.data() + 4); 385 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32; 386 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address, 387 this, STI); 388 if (result != MCDisassembler::Fail) { 389 Size = 8; 390 return result; 391 } 392 } 393 394 // Get the four bytes of the instruction. 395 Size = 4; 396 if (Bytes.size() < 4) { 397 Size = 0; 398 return MCDisassembler::Fail; 399 } 400 401 // Read the instruction in the proper endianness. 402 uint64_t Inst = ReadFunc(Bytes.data()); 403 404 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 405 DecodeStatus result = 406 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 407 if (result != MCDisassembler::Fail) 408 return result; 409 } else if (STI.getFeatureBits()[PPC::FeatureSPE]) { 410 DecodeStatus result = 411 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 412 if (result != MCDisassembler::Fail) 413 return result; 414 } 415 416 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 417 } 418