1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES; 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(), 58 createPPCLEDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 60 createPPCDisassembler); 61 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 62 createPPCLEDisassembler); 63 } 64 65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, 66 uint64_t /*Address*/, 67 const void * /*Decoder*/) { 68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); 69 return MCDisassembler::Success; 70 } 71 72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, 73 uint64_t /*Address*/, 74 const void * /*Decoder*/) { 75 int32_t Offset = SignExtend32<24>(Imm); 76 Inst.addOperand(MCOperand::createImm(Offset)); 77 return MCDisassembler::Success; 78 } 79 80 // FIXME: These can be generated by TableGen from the existing register 81 // encoding values! 82 83 template <std::size_t N> 84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 85 const MCPhysReg (&Regs)[N]) { 86 assert(RegNo < N && "Invalid register number"); 87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 88 return MCDisassembler::Success; 89 } 90 91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 92 uint64_t Address, 93 const void *Decoder) { 94 return decodeRegisterClass(Inst, RegNo, CRRegs); 95 } 96 97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 98 uint64_t Address, 99 const void *Decoder) { 100 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 101 } 102 103 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 104 uint64_t Address, 105 const void *Decoder) { 106 return decodeRegisterClass(Inst, RegNo, FRegs); 107 } 108 109 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 110 uint64_t Address, 111 const void *Decoder) { 112 return decodeRegisterClass(Inst, RegNo, FRegs); 113 } 114 115 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 116 uint64_t Address, 117 const void *Decoder) { 118 return decodeRegisterClass(Inst, RegNo, VFRegs); 119 } 120 121 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 122 uint64_t Address, 123 const void *Decoder) { 124 return decodeRegisterClass(Inst, RegNo, VRegs); 125 } 126 127 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 128 uint64_t Address, 129 const void *Decoder) { 130 return decodeRegisterClass(Inst, RegNo, VSRegs); 131 } 132 133 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 134 uint64_t Address, 135 const void *Decoder) { 136 return decodeRegisterClass(Inst, RegNo, VSFRegs); 137 } 138 139 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 140 uint64_t Address, 141 const void *Decoder) { 142 return decodeRegisterClass(Inst, RegNo, VSSRegs); 143 } 144 145 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 146 uint64_t Address, 147 const void *Decoder) { 148 return decodeRegisterClass(Inst, RegNo, RRegs); 149 } 150 151 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 152 uint64_t Address, 153 const void *Decoder) { 154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 155 } 156 157 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 158 uint64_t Address, 159 const void *Decoder) { 160 return decodeRegisterClass(Inst, RegNo, XRegs); 161 } 162 163 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 164 uint64_t Address, 165 const void *Decoder) { 166 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 167 } 168 169 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 170 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 171 172 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 173 uint64_t Address, 174 const void *Decoder) { 175 return decodeRegisterClass(Inst, RegNo, SPERegs); 176 } 177 178 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, 179 uint64_t Address, 180 const void *Decoder) { 181 return decodeRegisterClass(Inst, RegNo, ACCRegs); 182 } 183 184 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 185 uint64_t Address, 186 const void *Decoder) { 187 return decodeRegisterClass(Inst, RegNo, VSRpRegs); 188 } 189 190 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 191 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 192 193 template<unsigned N> 194 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 195 int64_t Address, const void *Decoder) { 196 assert(isUInt<N>(Imm) && "Invalid immediate"); 197 Inst.addOperand(MCOperand::createImm(Imm)); 198 return MCDisassembler::Success; 199 } 200 201 template<unsigned N> 202 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 203 int64_t Address, const void *Decoder) { 204 assert(isUInt<N>(Imm) && "Invalid immediate"); 205 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 206 return MCDisassembler::Success; 207 } 208 209 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, 210 int64_t Address, const void *Decoder) { 211 if (Imm != 0) 212 return MCDisassembler::Fail; 213 Inst.addOperand(MCOperand::createImm(Imm)); 214 return MCDisassembler::Success; 215 } 216 217 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, 218 uint64_t Address, 219 const void *Decoder) { 220 if (RegNo & 1) 221 return MCDisassembler::Fail; 222 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); 223 return MCDisassembler::Success; 224 } 225 226 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 227 int64_t Address, const void *Decoder) { 228 // Decode the memri field (imm, reg), which has the low 16-bits as the 229 // displacement and the next 5 bits as the register #. 230 231 uint64_t Base = Imm >> 16; 232 uint64_t Disp = Imm & 0xFFFF; 233 234 assert(Base < 32 && "Invalid base register"); 235 236 switch (Inst.getOpcode()) { 237 default: break; 238 case PPC::LBZU: 239 case PPC::LHAU: 240 case PPC::LHZU: 241 case PPC::LWZU: 242 case PPC::LFSU: 243 case PPC::LFDU: 244 // Add the tied output operand. 245 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 246 break; 247 case PPC::STBU: 248 case PPC::STHU: 249 case PPC::STWU: 250 case PPC::STFSU: 251 case PPC::STFDU: 252 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 253 break; 254 } 255 256 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 257 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 258 return MCDisassembler::Success; 259 } 260 261 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 262 int64_t Address, const void *Decoder) { 263 // Decode the memrix field (imm, reg), which has the low 14-bits as the 264 // displacement and the next 5 bits as the register #. 265 266 uint64_t Base = Imm >> 14; 267 uint64_t Disp = Imm & 0x3FFF; 268 269 assert(Base < 32 && "Invalid base register"); 270 271 if (Inst.getOpcode() == PPC::LDU) 272 // Add the tied output operand. 273 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 274 else if (Inst.getOpcode() == PPC::STDU) 275 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 276 277 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 278 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 279 return MCDisassembler::Success; 280 } 281 282 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 283 int64_t Address, const void *Decoder) { 284 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 285 // displacement with 16-byte aligned, and the next 5 bits as the register #. 286 287 uint64_t Base = Imm >> 12; 288 uint64_t Disp = Imm & 0xFFF; 289 290 assert(Base < 32 && "Invalid base register"); 291 292 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 293 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 294 return MCDisassembler::Success; 295 } 296 297 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, 298 int64_t Address, 299 const void *Decoder) { 300 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the 301 // displacement, and the next 5 bits as an immediate 0. 302 uint64_t Base = Imm >> 34; 303 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 304 305 assert(Base < 32 && "Invalid base register"); 306 307 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 308 return decodeImmZeroOperand(Inst, Base, Address, Decoder); 309 } 310 311 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, 312 int64_t Address, 313 const void *Decoder) { 314 // Decode the memri34 field (imm, reg), which has the low 34-bits as the 315 // displacement, and the next 5 bits as the register #. 316 uint64_t Base = Imm >> 34; 317 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 318 319 assert(Base < 32 && "Invalid base register"); 320 321 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 322 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 323 return MCDisassembler::Success; 324 } 325 326 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 327 int64_t Address, const void *Decoder) { 328 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 329 // displacement with 8-byte aligned, and the next 5 bits as the register #. 330 331 uint64_t Base = Imm >> 5; 332 uint64_t Disp = Imm & 0x1F; 333 334 assert(Base < 32 && "Invalid base register"); 335 336 Inst.addOperand(MCOperand::createImm(Disp << 3)); 337 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 338 return MCDisassembler::Success; 339 } 340 341 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 342 int64_t Address, const void *Decoder) { 343 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 344 // displacement with 4-byte aligned, and the next 5 bits as the register #. 345 346 uint64_t Base = Imm >> 5; 347 uint64_t Disp = Imm & 0x1F; 348 349 assert(Base < 32 && "Invalid base register"); 350 351 Inst.addOperand(MCOperand::createImm(Disp << 2)); 352 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 353 return MCDisassembler::Success; 354 } 355 356 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 357 int64_t Address, const void *Decoder) { 358 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 359 // displacement with 2-byte aligned, and the next 5 bits as the register #. 360 361 uint64_t Base = Imm >> 5; 362 uint64_t Disp = Imm & 0x1F; 363 364 assert(Base < 32 && "Invalid base register"); 365 366 Inst.addOperand(MCOperand::createImm(Disp << 1)); 367 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 368 return MCDisassembler::Success; 369 } 370 371 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 372 int64_t Address, const void *Decoder) { 373 // The cr bit encoding is 0x80 >> cr_reg_num. 374 375 unsigned Zeros = countTrailingZeros(Imm); 376 assert(Zeros < 8 && "Invalid CR bit value"); 377 378 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 379 return MCDisassembler::Success; 380 } 381 382 #include "PPCGenDisassemblerTables.inc" 383 384 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 385 ArrayRef<uint8_t> Bytes, 386 uint64_t Address, 387 raw_ostream &CS) const { 388 auto *ReadFunc = IsLittleEndian ? support::endian::read32le 389 : support::endian::read32be; 390 391 // If this is an 8-byte prefixed instruction, handle it here. 392 // Note: prefixed instructions aren't technically 8-byte entities - the prefix 393 // appears in memory at an address 4 bytes prior to that of the base 394 // instruction regardless of endianness. So we read the two pieces and 395 // rebuild the 8-byte instruction. 396 // TODO: In this function we call decodeInstruction several times with 397 // different decoder tables. It may be possible to only call once by 398 // looking at the top 6 bits of the instruction. 399 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) { 400 uint32_t Prefix = ReadFunc(Bytes.data()); 401 uint32_t BaseInst = ReadFunc(Bytes.data() + 4); 402 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32; 403 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address, 404 this, STI); 405 if (result != MCDisassembler::Fail) { 406 Size = 8; 407 return result; 408 } 409 } 410 411 // Get the four bytes of the instruction. 412 Size = 4; 413 if (Bytes.size() < 4) { 414 Size = 0; 415 return MCDisassembler::Fail; 416 } 417 418 // Read the instruction in the proper endianness. 419 uint64_t Inst = ReadFunc(Bytes.data()); 420 421 if (STI.getFeatureBits()[PPC::FeatureSPE]) { 422 DecodeStatus result = 423 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 424 if (result != MCDisassembler::Fail) 425 return result; 426 } 427 428 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 429 } 430