1 //=====-- NVPTXSubtarget.h - Define Subtarget for the NVPTX ---*- C++ -*--====// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the NVPTX specific subclass of TargetSubtarget. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXSUBTARGET_H 14 #define LLVM_LIB_TARGET_NVPTX_NVPTXSUBTARGET_H 15 16 #include "NVPTX.h" 17 #include "NVPTXFrameLowering.h" 18 #include "NVPTXISelLowering.h" 19 #include "NVPTXInstrInfo.h" 20 #include "NVPTXRegisterInfo.h" 21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 22 #include "llvm/CodeGen/TargetSubtargetInfo.h" 23 #include "llvm/IR/DataLayout.h" 24 #include <string> 25 26 #define GET_SUBTARGETINFO_HEADER 27 #include "NVPTXGenSubtargetInfo.inc" 28 29 namespace llvm { 30 31 class NVPTXSubtarget : public NVPTXGenSubtargetInfo { 32 virtual void anchor(); 33 std::string TargetName; 34 35 // PTX version x.y is represented as 10*x+y, e.g. 3.1 == 31 36 unsigned PTXVersion; 37 38 // Full SM version x.y is represented as 100*x+10*y+feature, e.g. 3.1 == 310 39 // sm_90a == 901 40 unsigned int FullSmVersion; 41 42 // SM version x.y is represented as 10*x+y, e.g. 3.1 == 31. Derived from 43 // FullSmVersion. 44 unsigned int SmVersion; 45 46 const NVPTXTargetMachine &TM; 47 NVPTXInstrInfo InstrInfo; 48 NVPTXTargetLowering TLInfo; 49 SelectionDAGTargetInfo TSInfo; 50 51 // NVPTX does not have any call stack frame, but need a NVPTX specific 52 // FrameLowering class because TargetFrameLowering is abstract. 53 NVPTXFrameLowering FrameLowering; 54 55 public: 56 /// This constructor initializes the data members to match that 57 /// of the specified module. 58 /// 59 NVPTXSubtarget(const Triple &TT, const std::string &CPU, 60 const std::string &FS, const NVPTXTargetMachine &TM); 61 62 const TargetFrameLowering *getFrameLowering() const override { 63 return &FrameLowering; 64 } 65 const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; } 66 const NVPTXRegisterInfo *getRegisterInfo() const override { 67 return &InstrInfo.getRegisterInfo(); 68 } 69 const NVPTXTargetLowering *getTargetLowering() const override { 70 return &TLInfo; 71 } 72 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 73 return &TSInfo; 74 } 75 76 bool hasAtomAddF64() const { return SmVersion >= 60; } 77 bool hasAtomScope() const { return SmVersion >= 60; } 78 bool hasAtomBitwise64() const { return SmVersion >= 32; } 79 bool hasAtomMinMax64() const { return SmVersion >= 32; } 80 bool hasLDG() const { return SmVersion >= 32; } 81 inline bool hasHWROT32() const { return SmVersion >= 32; } 82 bool hasImageHandles() const; 83 bool hasFP16Math() const { return SmVersion >= 53; } 84 bool hasBF16Math() const { return SmVersion >= 80; } 85 bool allowFP16Math() const; 86 bool hasMaskOperator() const { return PTXVersion >= 71; } 87 bool hasNoReturn() const { return SmVersion >= 30 && PTXVersion >= 64; } 88 unsigned int getFullSmVersion() const { return FullSmVersion; } 89 unsigned int getSmVersion() const { return getFullSmVersion() / 10; } 90 // GPUs with "a" suffix have include architecture-accelerated features that 91 // are supported on the specified architecture only, hence such targets do not 92 // follow the onion layer model. hasAAFeatures() allows distinguishing such 93 // GPU variants from the base GPU architecture. 94 // - 0 represents base GPU model, 95 // - non-zero value identifies particular architecture-accelerated variant. 96 bool hasAAFeatures() const { return getFullSmVersion() % 10; } 97 std::string getTargetName() const { return TargetName; } 98 99 // Get maximum value of required alignments among the supported data types. 100 // From the PTX ISA doc, section 8.2.3: 101 // The memory consistency model relates operations executed on memory 102 // locations with scalar data-types, which have a maximum size and alignment 103 // of 64 bits. Memory operations with a vector data-type are modelled as a 104 // set of equivalent memory operations with a scalar data-type, executed in 105 // an unspecified order on the elements in the vector. 106 unsigned getMaxRequiredAlignment() const { return 8; } 107 108 unsigned getPTXVersion() const { return PTXVersion; } 109 110 NVPTXSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 111 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 112 }; 113 114 } // End llvm namespace 115 116 #endif 117